diff --git a/targets/TARGET_RENESAS/TARGET_RZ_A1XX/TARGET_GR_LYCHEE/PeripheralNames.h b/targets/TARGET_RENESAS/TARGET_RZ_A1XX/TARGET_GR_LYCHEE/PeripheralNames.h new file mode 100644 index 0000000..5d8eb3f --- /dev/null +++ b/targets/TARGET_RENESAS/TARGET_RZ_A1XX/TARGET_GR_LYCHEE/PeripheralNames.h @@ -0,0 +1,103 @@ +/* mbed Microcontroller Library + * Copyright (c) 2006-2013 ARM Limited + * + * Licensed under the Apache License, Version 2.0 (the "License"); + * you may not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, + * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ +#ifndef MBED_PERIPHERALNAMES_H +#define MBED_PERIPHERALNAMES_H + +#include "cmsis.h" +#include "PinNames.h" + +#ifdef __cplusplus +extern "C" { +#endif + +typedef enum { + UART0, + UART1, + UART2, + UART3, + UART4, +} UARTName; + +typedef enum { + PWM_PWM1A = 0, + PWM_PWM1B, + PWM_PWM1C, + PWM_PWM1D, + PWM_PWM1E, + PWM_PWM1F, + PWM_PWM1G, + PWM_PWM1H, + PWM_PWM2A, + PWM_PWM2B, + PWM_PWM2C, + PWM_PWM2D, + PWM_PWM2E, + PWM_PWM2F, + PWM_PWM2G, + PWM_PWM2H, + PWM_TIOC0A = 0x20, + PWM_TIOC0C, + PWM_TIOC1A, + PWM_TIOC2A, + PWM_TIOC3A, + PWM_TIOC3C, + PWM_TIOC4A, + PWM_TIOC4C, +} PWMName; + +typedef enum { + AN0= 0, + AN1= 1, + AN2= 2, + AN3= 3, + AN4= 4, + AN5= 5, + AN6= 6, + AN7= 7, +} ADCName; + +typedef enum { + SPI_0 = 0, + SPI_1, + SPI_2, + SPI_3, + SPI_4, +} SPIName; + +typedef enum { + I2C_0 = 0, + I2C_1, + I2C_2, + I2C_3, +} I2CName; + +typedef enum { + CAN_0 = 0, + CAN_1, +} CANName; + + +#define STDIO_UART_TX USBTX +#define STDIO_UART_RX USBRX +#define STDIO_UART UART1 + + + +#ifdef __cplusplus +} +#endif + +#endif diff --git a/targets/TARGET_RENESAS/TARGET_RZ_A1XX/TARGET_GR_LYCHEE/PeripheralPins.c b/targets/TARGET_RENESAS/TARGET_RZ_A1XX/TARGET_GR_LYCHEE/PeripheralPins.c new file mode 100644 index 0000000..c94ebdf --- /dev/null +++ b/targets/TARGET_RENESAS/TARGET_RZ_A1XX/TARGET_GR_LYCHEE/PeripheralPins.c @@ -0,0 +1,282 @@ + +/* mbed Microcontroller Library + * Copyright (c) 2006-2015 ARM Limited + * + * Licensed under the Apache License, Version 2.0 (the "License"); + * you may not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, + * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ + +#include "PeripheralPins.h" + +/************IRQ***************/ +enum { + IRQ0,IRQ1, + IRQ2,IRQ3, + IRQ4,IRQ5, + IRQ6,IRQ7, +} IRQNo; +const PinMap PinMap_IRQ[] = { + {P6_7, IRQ0, 4}, + {P1_8, IRQ0, 2}, + {P1_4, IRQ0, 2}, + {P6_8, IRQ1, 4}, + {P1_9, IRQ1, 2}, + {P1_5, IRQ1, 2}, + {P2_9, IRQ1, 4}, + {P6_9, IRQ2, 4}, + {P1_10, IRQ2, 2}, + {P1_6, IRQ2, 2}, + {P2_7, IRQ2, 4}, + {P5_8, IRQ3, 4}, + {P6_10, IRQ3, 4}, + {P7_3, IRQ3, 4}, + {P7_8, IRQ3, 4}, + {P1_11, IRQ3, 2}, + {P1_7, IRQ3, 2}, + {P5_9, IRQ4, 4}, + {P7_2, IRQ4, 4}, + {P0_0, IRQ4, 3}, + {P1_12, IRQ4, 2}, + {P1_0, IRQ4, 2}, + {P5_10, IRQ5, 4}, + {P7_7, IRQ5, 4}, + {P7_9, IRQ5, 4}, + {P2_2, IRQ5, 4}, + {P1_13, IRQ5, 2}, + {P1_1, IRQ5, 2}, + {P5_11, IRQ6, 4}, + {P8_6, IRQ6, 3}, + {P7_6, IRQ6, 4}, + {P2_1, IRQ6, 4}, + {P1_14, IRQ6, 2}, + {P1_2, IRQ6, 2}, + {P8_7, IRQ7, 3}, + {P2_0, IRQ7, 4}, + {P0_2, IRQ7, 3}, + {P1_15, IRQ7, 2}, + {P1_3, IRQ7, 2}, + {NC, NC, 0} +}; + +/************PINMAP***************/ +const PinFunc PIPC_0_tbl[] = { +// pin func pm + {P2_8 , 3 , -1}, /* TIOC0A */ + {P8_4 , 5 , -1}, /* TIOC0A */ /* for 208QFP */ + {P8_5 , 5 , -1}, /* TIOC0B */ /* for 208QFP */ + {P8_6 , 5 , -1}, /* TIOC0C */ /* for 208QFP */ + {P2_2 , 3 , -1}, /* TIOC0C */ + {P8_7 , 5 , -1}, /* TIOC0D */ /* for 208QFP */ + {P2_3 , 3 , -1}, /* TIOC0D */ + {P7_9 , 6 , -1}, /* TIOC1A */ + {P9_2 , 5 , -1}, /* TIOC1A */ /* for 208QFP */ + {P2_7 , 3 , -1}, /* TIOC1A */ + {P9_3 , 5 , -1}, /* TIOC1B */ /* for 208QFP */ + {P4_0 , 3 , -1}, /* TIOC1B */ + {P5_14 , 4 , -1}, /* TIOC2A */ + {P7_0 , 5 , -1}, /* TIOC2A */ + {P9_4 , 5 , -1}, /* TIOC2A */ + {P2_6 , 3 , -1}, /* TIOC2A */ + {P9_5 , 5 , -1}, /* TIOC2B */ /* for 208QFP */ + {P4_1 , 3 , -1}, /* TIOC2B */ + {P6_7 , 5 , -1}, /* TIOC3A */ + {P2_5 , 3 , -1}, /* TIOC3A */ + {P3_11 , 3 , -1}, /* TIOC3A */ + {P6_8 , 5 , -1}, /* TIOC3B */ + {P3_10 , 3 , -1}, /* TIOC3B */ + {P6_9 , 5 , -1}, /* TIOC3C */ + {P3_12 , 3 , -1}, /* TIOC3C */ + {P6_10 , 5 , -1}, /* TIOC3D */ + {P3_13 , 3 , -1}, /* TIOC3D */ + {P5_8 , 3 , -1}, /* TIOC4A */ + {P2_4 , 3 , -1}, /* TIOC4A */ + {P5_9 , 3 , -1}, /* TIOC4B */ + {P5_10 , 3 , -1}, /* TIOC4C */ + {P5_11 , 3 , -1}, /* TIOC4D */ + {P6_10 , 3 , 0 }, /* SSITxD0 */ + {P5_6 , 3 , 0 }, /* SSITxD1 */ + {P7_10 , 2 , 0 }, /* SSITxD1 */ + {P8_2 , 3 , 0 }, /* SSITxD1 */ /* for 208QFP */ + {P6_6 , 3 , 0 }, /* SSITxD3 */ + {P2_8 , 2 , 0 }, /* SSITxD3 */ + {P6_0 , 5 , 0 }, /* WDTOVF */ + {NC , 0 , -1} +}; + +/************ADC***************/ +const PinMap PinMap_ADC[] = { + {P1_8, AN0, 1}, + {P1_9, AN1, 1}, + {P1_10, AN2, 1}, + {P1_11, AN3, 1}, + {P1_12, AN4, 1}, + {P1_13, AN5, 1}, + {P1_14, AN6, 1}, + {P1_15, AN7, 1}, + {NC , NC , 0} +}; + +/************I2C***************/ +const PinMap PinMap_I2C_SDA[] = { + {P1_1 , I2C_0, 1}, + {P1_3 , I2C_1, 1}, + {P1_5 , I2C_2, 1}, + {P1_7 , I2C_3, 1}, + {NC , NC , 0} +}; + +const PinMap PinMap_I2C_SCL[] = { + {P1_0 , I2C_0, 1}, + {P1_2 , I2C_1, 1}, + {P1_4 , I2C_2, 1}, + {P1_6 , I2C_3, 1}, + {NC , NC, 0} +}; + +/************UART***************/ +const PinMap PinMap_UART_TX[] = { + {P6_15 , UART0, 5}, + {P7_5 , UART0, 4}, + {P7_8 , UART0, 5}, + {P9_5 , UART0, 4}, /* for 208QFP */ + {P9_0 , UART1, 4}, /* for 208QFP */ + {P3_15 , UART1, 5}, + {P5_7 , UART2, 5}, + {P8_10 , UART2, 4}, /* for 208QFP */ + {P7_1 , UART2, 4}, + {P7_11 , UART3, 5}, + {P3_9 , UART3, 5}, + {P8_2 , UART3, 4}, + {P5_15 , UART4, 3}, + {P8_13 , UART4, 4}, + {NC , NC , 0} +}; + +const PinMap PinMap_UART_RX[] = { + {P2_15 , UART0, 6}, + {P0_0 , UART0, 2}, + {P1_8 , UART0, 3}, + {P9_4 , UART0, 4}, /* for 208QFP */ + {P8_15 , UART1, 4}, /* for 208QFP */ + {P0_2 , UART1, 2}, + {P1_9 , UART1, 3}, + {P8_9 , UART2, 4}, /* for 208QFP */ + {P0_1 , UART2, 2}, + {P1_10 , UART2, 3}, + {P1_7 , UART2, 3}, + {P7_10 , UART3, 5}, + {P0_3 , UART3, 2}, + {P1_11 , UART3, 3}, + {P3_10 , UART3, 5}, + {P8_1 , UART3, 4}, /* for 208QFP */ + {P5_14 , UART4, 3}, + {P8_12 , UART4, 4}, /* for 208QFP */ + {P8_12 , UART4, 4}, /* for 208QFP */ + {NC , NC , 0} +}; + +const PinMap PinMap_UART_CTS[] = { + {P6_13 , UART0, 5}, + {P9_1 , UART0, 4}, /* for 208QFP */ + {P8_6 , UART1, 4}, /* for 208QFP */ + {P4_0 , UART1, 5}, + {P7_6 , UART2, 5}, + {P8_4 , UART2, 4}, /* for 208QFP */ + {NC , NC , 0} +}; + +const PinMap PinMap_UART_RTS[] = { + {P6_12 , UART0, 5}, + {P9_2 , UART0, 4}, /* for 208QFP */ + {P8_7 , UART1, 4}, /* for 208QFP */ + {P4_1 , UART1, 5}, + {P7_7 , UART2, 5}, + {P8_5 , UART2, 4}, /* for 208QFP */ + {NC , NC , 0} +}; + +/************SPI***************/ +const PinMap PinMap_SPI_SCLK[] = { + {P6_0 , SPI_0, 3}, + {P6_12 , SPI_1, 3}, + {P5_4 , SPI_2, 2}, + {P9_2 , SPI_2, 1}, /* for 208QFP */ + {NC , NC , 0} +}; + +const PinMap PinMap_SPI_MOSI[] = { + {P6_2 , SPI_0, 3}, + {P6_14 , SPI_1, 3}, + {P5_6 , SPI_2, 2}, + {P9_4 , SPI_2, 1}, /* for 208QFP */ + {NC , NC , 0} +}; + +const PinMap PinMap_SPI_MISO[] = { + {P6_3 , SPI_0, 3}, + {P6_15 , SPI_1, 3}, + {P5_7 , SPI_2, 2}, + {P9_5 , SPI_2, 1}, /* for 208QFP */ + {NC , NC , 0} +}; + +const PinMap PinMap_SPI_SSEL[] = { + {P6_1 , SPI_0, 3}, + {P6_13 , SPI_1, 3}, + {P5_5 , SPI_2, 2}, + {P9_3 , SPI_2, 1}, /* for 208QFP */ + {NC , NC , 0} +}; + +/************PWM***************/ +const PinMap PinMap_PWM[] = { + {P2_8 , PWM_TIOC0A, 3}, + {P8_4 , PWM_TIOC0A, 5}, /* for 208QFP */ + {P8_6 , PWM_TIOC0C, 5}, /* for 208QFP */ + {P2_2 , PWM_TIOC0C, 3}, + {P7_9 , PWM_TIOC1A, 6}, + {P9_2 , PWM_TIOC1A, 5}, /* for 208QFP */ + {P2_7 , PWM_TIOC1A, 3}, + {P5_14 , PWM_TIOC2A, 4}, + {P7_0 , PWM_TIOC2A, 5}, + {P9_4 , PWM_TIOC2A, 5}, /* for 208QFP */ + {P2_6 , PWM_TIOC2A, 3}, + {P6_7 , PWM_TIOC3A, 5}, + {P2_5 , PWM_TIOC3A, 3}, + {P3_11 , PWM_TIOC3A, 3}, + {P6_9 , PWM_TIOC3C, 5}, + {P3_12 , PWM_TIOC3C, 3}, + {P5_8 , PWM_TIOC4A, 3}, + {P2_4 , PWM_TIOC4A, 3}, + {P5_10 , PWM_TIOC4C, 3}, + {NC , NC , 0} +}; + +/************CAN***************/ +const PinMap PinMap_CAN_RD[] = { + {P5_8 , CAN_0, 2}, + {P7_2 , CAN_0, 5}, + {P2_9 , CAN_0, 5}, + {P8_10 , CAN_1, 3}, + {P2_2 , CAN_1, 2}, + {NC , NC , 0} +}; + +const PinMap PinMap_CAN_TD[] = { + {P5_9 , CAN_0, 2}, + {P7_3 , CAN_0, 5}, + {P2_8 , CAN_0, 5}, + {P8_9 , CAN_1, 3}, + {P2_3 , CAN_1, 2}, + {NC , NC , 0} +}; + diff --git a/targets/TARGET_RENESAS/TARGET_RZ_A1XX/TARGET_GR_LYCHEE/PinNames.h b/targets/TARGET_RENESAS/TARGET_RZ_A1XX/TARGET_GR_LYCHEE/PinNames.h new file mode 100644 index 0000000..d60a4b5 --- /dev/null +++ b/targets/TARGET_RENESAS/TARGET_RZ_A1XX/TARGET_GR_LYCHEE/PinNames.h @@ -0,0 +1,111 @@ +/* mbed Microcontroller Library + * Copyright (c) 2006-2013 ARM Limited + * + * Licensed under the Apache License, Version 2.0 (the "License"); + * you may not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, + * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ +#ifndef MBED_PINNAMES_H +#define MBED_PINNAMES_H + +#include "cmsis.h" + +#ifdef __cplusplus +extern "C" { +#endif + +typedef enum { + PIN_INPUT, + PIN_OUTPUT +} PinDirection; + +#define PORT_SHIFT 4 + +typedef enum { + P0_0 = 0, + P0_1, P0_2, P0_3, P0_4, P0_5,_P0_6,_P0_7,_P0_8,_P0_9,_P0_10,_P0_11,_P0_12,_P0_13,_P0_14,_P0_15, + P1_0, P1_1, P1_2, P1_3, P1_4, P1_5, P1_6, P1_7, P1_8, P1_9, P1_10, P1_11, P1_12, P1_13, P1_14, P1_15, + P2_0, P2_1, P2_2, P2_3, P2_4, P2_5, P2_6, P2_7, P2_8, P2_9, P2_10, P2_11, P2_12, P2_13, P2_14, P2_15, + P3_0, P3_1, P3_2, P3_3, P3_4, P3_5, P3_6, P3_7, P3_8, P3_9, P3_10, P3_11, P3_12, P3_13, P3_14, P3_15, + P4_0, P4_1, P4_2, P4_3, P4_4, P4_5, P4_6, P4_7, P4_8, P4_9, P4_10, P4_11, P4_12, P4_13, P4_14, P4_15, + P5_0, P5_1, P5_2, P5_3, P5_4, P5_5, P5_6, P5_7, P5_8, P5_9, P5_10, P5_11, P5_12, P5_13, P5_14, P5_15, + P6_0, P6_1, P6_2, P6_3, P6_4, P6_5, P6_6, P6_7, P6_8, P6_9, P6_10, P6_11, P6_12, P6_13, P6_14, P6_15, + P7_0, P7_1, P7_2, P7_3, P7_4, P7_5, P7_6, P7_7, P7_8, P7_9, P7_10, P7_11, P7_12, P7_13, P7_14, P7_15, + P8_0, P8_1, P8_2, P8_3, P8_4, P8_5, P8_6, P8_7, P8_8, P8_9, P8_10, P8_11, P8_12, P8_13, P8_14, P8_15, + P9_0, P9_1, P9_2, P9_3, P9_4, P9_5, P9_6, P9_7, P9_8, P9_9, P9_10, P9_11, P9_12, P9_13, P9_14, P9_15, + + // mbed Pin Names + LED1 = P2_4, + LED2 = P2_5, + LED3 = P7_0, + LED4 = P2_2, + + LED_GREEN = LED1, + LED_YELLOW = LED2, + LED_ORANGE = LED3, + LED_RED = LED4, + + USBTX = P3_15, + USBRX = P0_2, + + // Arduiono Pin Names + D0 = P5_14, + D1 = P5_15, + D2 = P5_9, + D3 = P5_8, + D4 = P5_11, + D5 = P5_10, + D6 = P2_1, + D7 = P2_0, + D8 = P3_10, + D9 = P3_9, + D10 = P6_13, + D11 = P6_14, + D12 = P6_15, + D13 = P6_12, + D14 = P1_7, + D15 = P1_6, + + A0 = P1_15, + A1 = P1_14, + A2 = P1_13, + A3 = P1_12, + A4 = P1_11, + A5 = P1_10, + + I2C_SCL = D15, + I2C_SDA = D14, + + USER_BUTTON0 = P7_2, + USER_BUTTON1 = P7_3, + // Standardized button names + BUTTON1 = USER_BUTTON0, + + // Not connected + NC = (int)0xFFFFFFFF +} PinName; + +typedef enum { + PullUp = 0, + PullDown = 3, + PullNone = 2, + OpenDrain = 4, + PullDefault = PullDown +} PinMode; + +#define PINGROUP(pin) (((pin)>>PORT_SHIFT)&0x0f) +#define PINNO(pin) ((pin)&0x0f) + +#ifdef __cplusplus +} +#endif + +#endif diff --git a/targets/TARGET_RENESAS/TARGET_RZ_A1XX/TARGET_GR_LYCHEE/PortNames.h b/targets/TARGET_RENESAS/TARGET_RZ_A1XX/TARGET_GR_LYCHEE/PortNames.h new file mode 100644 index 0000000..1c2413c --- /dev/null +++ b/targets/TARGET_RENESAS/TARGET_RZ_A1XX/TARGET_GR_LYCHEE/PortNames.h @@ -0,0 +1,37 @@ +/* mbed Microcontroller Library + * Copyright (c) 2006-2013 ARM Limited + * + * Licensed under the Apache License, Version 2.0 (the "License"); + * you may not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, + * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ +#ifndef MBED_PORTNAMES_H +#define MBED_PORTNAMES_H + +#ifdef __cplusplus +extern "C" { +#endif + +typedef enum { + Port0 = 0, + Port1 = 1, + Port2 = 2, + Port3 = 3, + Port4 = 4, + Port5 = 5, + Port6 = 6, + Port7 = 7 +} PortName; + +#ifdef __cplusplus +} +#endif +#endif diff --git a/targets/TARGET_RENESAS/TARGET_RZ_A1XX/TARGET_GR_LYCHEE/TARGET_MBED_MBRZA1LU/reserved_pins.h b/targets/TARGET_RENESAS/TARGET_RZ_A1XX/TARGET_GR_LYCHEE/TARGET_MBED_MBRZA1LU/reserved_pins.h new file mode 100644 index 0000000..10d094c --- /dev/null +++ b/targets/TARGET_RENESAS/TARGET_RZ_A1XX/TARGET_GR_LYCHEE/TARGET_MBED_MBRZA1LU/reserved_pins.h @@ -0,0 +1,6 @@ +#ifndef RESERVED_PINS_H +#define RESERVED_PINS_H + +#define TARGET_RESERVED_PINS {} + +#endif diff --git a/targets/TARGET_RENESAS/TARGET_RZ_A1XX/TARGET_GR_LYCHEE/device.h b/targets/TARGET_RENESAS/TARGET_RZ_A1XX/TARGET_GR_LYCHEE/device.h new file mode 100644 index 0000000..ba7b411 --- /dev/null +++ b/targets/TARGET_RENESAS/TARGET_RZ_A1XX/TARGET_GR_LYCHEE/device.h @@ -0,0 +1,50 @@ +// The 'features' section in 'target.json' is now used to create the device's hardware preprocessor switches. +// Check the 'features' section of the target description in 'targets.json' for more details. +/* mbed Microcontroller Library + * Copyright (c) 2006-2013 ARM Limited + * + * Licensed under the Apache License, Version 2.0 (the "License"); + * you may not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, + * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ +#ifndef MBED_DEVICE_H +#define MBED_DEVICE_H + +/* ->Take measures about optimization problems of web compiler */ + /* Web compiler has problem that inlining code may not be generated correctly */ + /* when "-O3 -Otime" was specified. */ +#if defined(__CC_ARM) && (__ARMCC_VERSION <= 5040027) +#pragma Ospace +#endif +/* <-Take measures about optimization problems of web compiler */ + + + + + + +#define TRANSACTION_QUEUE_SIZE_SPI 16 + + + + + +#define DEVICE_ID_LENGTH 32 +#define DEVICE_MAC_OFFSET 20 + + + + + +#include "objects.h" +#include "dma_api.h" + +#endif diff --git a/targets/TARGET_RENESAS/TARGET_RZ_A1XX/TARGET_GR_LYCHEE/device/MBRZA1LU.h b/targets/TARGET_RENESAS/TARGET_RZ_A1XX/TARGET_GR_LYCHEE/device/MBRZA1LU.h new file mode 100644 index 0000000..c244663 --- /dev/null +++ b/targets/TARGET_RENESAS/TARGET_RZ_A1XX/TARGET_GR_LYCHEE/device/MBRZA1LU.h @@ -0,0 +1 @@ +#include "RZ_A1LU.h" diff --git a/targets/TARGET_RENESAS/TARGET_RZ_A1XX/TARGET_GR_LYCHEE/device/RZ_A1_Init.c b/targets/TARGET_RENESAS/TARGET_RZ_A1XX/TARGET_GR_LYCHEE/device/RZ_A1_Init.c new file mode 100644 index 0000000..9eb7dd5 --- /dev/null +++ b/targets/TARGET_RENESAS/TARGET_RZ_A1XX/TARGET_GR_LYCHEE/device/RZ_A1_Init.c @@ -0,0 +1,138 @@ +/******************************************************************************* +* DISCLAIMER +* This software is supplied by Renesas Electronics Corporation and is only +* intended for use with Renesas products. No other uses are authorized. This +* software is owned by Renesas Electronics Corporation and is protected under +* all applicable laws, including copyright laws. +* THIS SOFTWARE IS PROVIDED "AS IS" AND RENESAS MAKES NO WARRANTIES REGARDING +* THIS SOFTWARE, WHETHER EXPRESS, IMPLIED OR STATUTORY, INCLUDING BUT NOT +* LIMITED TO WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE +* AND NON-INFRINGEMENT. ALL SUCH WARRANTIES ARE EXPRESSLY DISCLAIMED. +* TO THE MAXIMUM EXTENT PERMITTED NOT PROHIBITED BY LAW, NEITHER RENESAS +* ELECTRONICS CORPORATION NOR ANY OF ITS AFFILIATED COMPANIES SHALL BE LIABLE +* FOR ANY DIRECT, INDIRECT, SPECIAL, INCIDENTAL OR CONSEQUENTIAL DAMAGES FOR +* ANY REASON RELATED TO THIS SOFTWARE, EVEN IF RENESAS OR ITS AFFILIATES HAVE +* BEEN ADVISED OF THE POSSIBILITY OF SUCH DAMAGES. +* Renesas reserves the right, without notice, to make changes to this software +* and to discontinue the availability of this software. By using this software, +* you agree to the additional terms and conditions found by accessing the +* following link: +* http://www.renesas.com/disclaimer +* Copyright (C) 2012 - 2014 Renesas Electronics Corporation. All rights reserved. +*******************************************************************************/ +/**************************************************************************//** +* @file RZ_A1_Init.c +* $Rev: 624 $ +* $Date:: 2013-04-24 13:37:48 +0900#$ +* @brief RZ_A1 Initialize +******************************************************************************/ + +/****************************************************************************** +Includes , "Project Includes" +******************************************************************************/ +#include "MBRZA1LU.h" +#include "RZ_A1_Init.h" + +/****************************************************************************** +Typedef definitions +******************************************************************************/ + +/****************************************************************************** +Macro definitions +******************************************************************************/ +#define CS2_SDRAM_MODE_16BIT_CAS2_BR_BW (*(volatile uint16_t*)0x3FFFD040) +#define CS3_SDRAM_MODE_16BIT_CAS2_BR_BW (*(volatile uint16_t*)0x3FFFE040) + +#define GPIO_PORT0_BOOTMODE_BITMASK (0x000fu) + +/****************************************************************************** +Imported global variables and functions (from other files) +******************************************************************************/ + +/****************************************************************************** +Exported global variables and functions (to be accessed by other files) +******************************************************************************/ + +/****************************************************************************** +Private global variables and functions +******************************************************************************/ + +/**************************************************************************//** +* Function Name: RZ_A1_SetSramWriteEnable +* @brief Initialize Board settings +* +* Description:
+* Set SRAM write enable +* @param none +* @retval none +******************************************************************************/ +void RZ_A1_SetSramWriteEnable(void) +{ + /* Enable SRAM write access */ + CPG.SYSCR3 = 0x0F; + + return; +} + +/**************************************************************************//** +* Function Name: RZ_A1_InitClock +* @brief Initialize Board settings +* +* Description:
+* Initialize Clock +* @param none +* @retval none +******************************************************************************/ +void RZ_A1_InitClock(void) +{ + /* Cancel L2C standby status before clock change */ + L2CREG15_POWER_CTRL = 0x00000001; + + /* Clock settings */ + /* ClockMode1 */ + CPG.FRQCR = 0x1035; /* CPU Clock =384.00MHz */ + + return; +} + +/**************************************************************************//** +* Function Name: RZ_A1_IsClockMode0 +* @brief Query Clock Mode +* +* Description:
+* Answer ClockMode0 or not +* @param none +* @retval true : clock mode 0 +* @retval false : clock mode 1 +******************************************************************************/ +int RZ_A1_IsClockMode0(void) +{ + /* ClockMode1 */ + return false; +} + +/**************************************************************************//** +* Function Name: RZ_A1_InitBus +* @brief Initialize Bus +* +* Description:
+* Initialize Pin Setting +* @param none +* @retval none +******************************************************************************/ +void RZ_A1_InitBus(void) +{ + /*************************************************************************/ + /* If need Pin Setting before run program, the setting will be wrote here*/ + /*************************************************************************/ + /* P5_3(ESP_EN) */ + GPIOP5 &= ~0x0008; /* Outputs low level */ + GPIOPMC5 &= ~0x0008; /* Port mode */ + GPIOPM5 &= ~0x0008; /* Output mode */ + + return; +} + +/****************************************************************************** +End of file +******************************************************************************/ diff --git a/targets/TARGET_RENESAS/TARGET_RZ_A1XX/TARGET_GR_LYCHEE/device/TOOLCHAIN_ARM_STD/MBRZA1LU.sct b/targets/TARGET_RENESAS/TARGET_RZ_A1XX/TARGET_GR_LYCHEE/device/TOOLCHAIN_ARM_STD/MBRZA1LU.sct new file mode 100644 index 0000000..6e7215d --- /dev/null +++ b/targets/TARGET_RENESAS/TARGET_RZ_A1XX/TARGET_GR_LYCHEE/device/TOOLCHAIN_ARM_STD/MBRZA1LU.sct @@ -0,0 +1,57 @@ +#! armcc -E +;************************************************** +; Copyright (c) 2017 ARM Ltd. All rights reserved. +;************************************************** + +; Scatter-file for RTX Example on Versatile Express + +; This scatter-file places application code, data, stack and heap at suitable addresses in the memory map. + +#include "mem_RZ_A1LU.h" + +LOAD_TTB __TTB_BASE __TTB_SIZE ; Page 0 of On-Chip Data Retention RAM +{ + TTB +0 EMPTY 0x4000 + { } ; Level-1 Translation Table for MMU +} + +SFLASH __ROM_BASE __ROM_SIZE ; load region size_region +{ + BOOT_LOADER_BEGIN __ROM_BASE FIXED + { + * (BOOT_LOADER) + } + + VECTORS __VECTOR_BASE FIXED + { + * (RESET, +FIRST) ; Vector table and other startup code + * (InRoot$$Sections) ; All (library) code that must be in a root region + * (+RO-CODE) ; Application RO code (.text) + } + + RO_DATA +0 + { * (+RO-DATA) } ; Application RO data (.constdata) + + RW_DATA 0x20020000 + { * (+RW) } ; Application RW data (.data) + + RW_IRAM1 +0 ALIGN 0x10 + { * (+ZI) } ; Application ZI data (.bss) + + ARM_LIB_HEAP +0 + { * (HEAP) } ; Application heap area (HEAP) + + ARM_LIB_STACK (__RAM_BASE + __NM_RAM_SIZE) EMPTY -__STACK_SIZE ; Stack region growing down + { } + + ;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;; + ; RAM-NC : Internal non-cached RAM region + ;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;; + + RW_DATA_NC __DATA_NC_BASE __NC_RAM_SIZE + { * (NC_DATA) } ; Application RW data Non cached area + + ZI_DATA_NC +0 + { * (NC_BSS) } ; Application ZI data Non cached area +} + diff --git a/targets/TARGET_RENESAS/TARGET_RZ_A1XX/TARGET_GR_LYCHEE/device/TOOLCHAIN_ARM_STD/mem_RZ_A1LU.h b/targets/TARGET_RENESAS/TARGET_RZ_A1XX/TARGET_GR_LYCHEE/device/TOOLCHAIN_ARM_STD/mem_RZ_A1LU.h new file mode 100644 index 0000000..46fb985 --- /dev/null +++ b/targets/TARGET_RENESAS/TARGET_RZ_A1XX/TARGET_GR_LYCHEE/device/TOOLCHAIN_ARM_STD/mem_RZ_A1LU.h @@ -0,0 +1,77 @@ +/**************************************************************************//** + * @file mem_RZ_A1LU.h + * @brief Memory base and size definitions (used in scatter file) + * @version V1.00 + * @date 10 Mar 2017 + * + * @note + * + ******************************************************************************/ +/* + * Copyright (c) 2009-2017 ARM Limited. All rights reserved. + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the License); you may + * not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an AS IS BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ + +#ifndef __MEM_RZ_A1LU_H +#define __MEM_RZ_A1LU_H + +/*---------------------------------------------------------------------------- + User Stack & Heap size definition + *----------------------------------------------------------------------------*/ +/* +//-------- <<< Use Configuration Wizard in Context Menu >>> ------------------ +*/ + +/*--------------------- ROM Configuration ------------------------------------ +// +// ROM Configuration +// ROM Base Address <0x0-0xFFFFFFFF:8> +// ROM Size (in Bytes) <0x0-0xFFFFFFFF:8> +// + *----------------------------------------------------------------------------*/ +#define __ROM_BASE 0x18000000 +#define __ROM_SIZE 0x08000000 + +#define __VECTOR_BASE 0x18004000 + +/*--------------------- RAM Configuration ----------------------------------- + *----------------------------------------------------------------------------*/ +#define __RAM_BASE 0x20000000 +#define __RAM_SIZE 0x00200000 +#define __NC_RAM_SIZE 0x00100000 +#define __NM_RAM_SIZE (__RAM_SIZE - __NC_RAM_SIZE) +#define __DATA_NC_BASE (__RAM_BASE + __NM_RAM_SIZE + 0x40000000) + +#define __UND_STACK_SIZE 0x00000100 +#define __SVC_STACK_SIZE 0x00008000 +#define __ABT_STACK_SIZE 0x00000100 +#define __FIQ_STACK_SIZE 0x00000100 +#define __IRQ_STACK_SIZE 0x0000F000 +#define __STACK_SIZE (__UND_STACK_SIZE + __SVC_STACK_SIZE + __ABT_STACK_SIZE + __FIQ_STACK_SIZE + __IRQ_STACK_SIZE) + +/*----------------------------------------------------------------------------*/ + +/*--------------------- TTB Configuration ------------------------------------ +// +// TTB Configuration +// TTB Base Address <0x0-0xFFFFFFFF:8> +// TTB Size (in Bytes) <0x0-0xFFFFFFFF:8> +// + *----------------------------------------------------------------------------*/ +#define __TTB_BASE 0x20000000 +#define __TTB_SIZE 0x00004000 + +#endif /* __MEM_RZ_A1H_H */ diff --git a/targets/TARGET_RENESAS/TARGET_RZ_A1XX/TARGET_GR_LYCHEE/device/TOOLCHAIN_ARM_STD/startup_RZ_A1LU.c b/targets/TARGET_RENESAS/TARGET_RZ_A1XX/TARGET_GR_LYCHEE/device/TOOLCHAIN_ARM_STD/startup_RZ_A1LU.c new file mode 100644 index 0000000..2592ad2 --- /dev/null +++ b/targets/TARGET_RENESAS/TARGET_RZ_A1XX/TARGET_GR_LYCHEE/device/TOOLCHAIN_ARM_STD/startup_RZ_A1LU.c @@ -0,0 +1,162 @@ +/****************************************************************************** + * @file startup_RZ_A1LU.c + * @brief CMSIS Device System Source File for ARM Cortex-A9 Device Series + * @version V1.00 + * @date 10 Mar 2017 + * + * @note + * + ******************************************************************************/ +/* + * Copyright (c) 2009-2017 ARM Limited. All rights reserved. + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the License); you may + * not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an AS IS BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ + +#include "MBRZA1LU.h" +#include "mem_RZ_A1LU.h" + +/*---------------------------------------------------------------------------- + Definitions + *----------------------------------------------------------------------------*/ +#define USR_MODE 0x10 // User mode +#define FIQ_MODE 0x11 // Fast Interrupt Request mode +#define IRQ_MODE 0x12 // Interrupt Request mode +#define SVC_MODE 0x13 // Supervisor mode +#define ABT_MODE 0x17 // Abort mode +#define UND_MODE 0x1B // Undefined Instruction mode +#define SYS_MODE 0x1F // System mode + +/*---------------------------------------------------------------------------- + Internal References + *----------------------------------------------------------------------------*/ +void Vectors (void) __attribute__ ((section("RESET"))); +void Reset_Handler(void); + +/*---------------------------------------------------------------------------- + Exception / Interrupt Handler + *----------------------------------------------------------------------------*/ +void Undef_Handler (void) __attribute__ ((weak, alias("Default_Handler"))); +void SVC_Handler (void) __attribute__ ((weak, alias("Default_Handler"))); +void PAbt_Handler (void) __attribute__ ((weak, alias("Default_Handler"))); +void DAbt_Handler (void) __attribute__ ((weak, alias("Default_Handler"))); +void IRQ_Handler (void) __attribute__ ((weak, alias("Default_Handler"))); +void FIQ_Handler (void) __attribute__ ((weak, alias("Default_Handler"))); + +/*---------------------------------------------------------------------------- + Exception / Interrupt Vector Table + *----------------------------------------------------------------------------*/ +__ASM void Vectors(void) { + IMPORT Undef_Handler + IMPORT SVC_Handler + IMPORT PAbt_Handler + IMPORT DAbt_Handler + IMPORT IRQ_Handler + IMPORT FIQ_Handler + LDR PC, =Reset_Handler + LDR PC, =Undef_Handler + LDR PC, =SVC_Handler + LDR PC, =PAbt_Handler + LDR PC, =DAbt_Handler + NOP + LDR PC, =IRQ_Handler + LDR PC, =FIQ_Handler +} + +/*---------------------------------------------------------------------------- + Reset Handler called on controller reset + *----------------------------------------------------------------------------*/ +__ASM void Reset_Handler(void) { + + // Mask interrupts + CPSID if + + // Put any cores other than 0 to sleep + MRC p15, 0, R0, c0, c0, 5 // Read MPIDR + ANDS R0, R0, #3 +goToSleep + WFINE + BNE goToSleep + + // Reset SCTLR Settings + MRC p15, 0, R0, c1, c0, 0 // Read CP15 System Control register + BIC R0, R0, #(0x1 << 12) // Clear I bit 12 to disable I Cache + BIC R0, R0, #(0x1 << 2) // Clear C bit 2 to disable D Cache + BIC R0, R0, #0x1 // Clear M bit 0 to disable MMU + BIC R0, R0, #(0x1 << 11) // Clear Z bit 11 to disable branch prediction + BIC R0, R0, #(0x1 << 13) // Clear V bit 13 to disable hivecs + MCR p15, 0, R0, c1, c0, 0 // Write value back to CP15 System Control register + ISB + + // Configure ACTLR + MRC p15, 0, r0, c1, c0, 1 // Read CP15 Auxiliary Control Register + ORR r0, r0, #(1 << 1) // Enable L2 prefetch hint (UNK/WI since r4p1) + MCR p15, 0, r0, c1, c0, 1 // Write CP15 Auxiliary Control Register + + // Set Vector Base Address Register (VBAR) to point to this application's vector table + LDR R0, =Vectors + MCR p15, 0, R0, c12, c0, 0 + + // Setup Stack for each exceptional mode + IMPORT |Image$$ARM_LIB_STACK$$ZI$$Limit| + LDR R0, =|Image$$ARM_LIB_STACK$$ZI$$Limit| + + //Enter Undefined Instruction Mode and set its Stack Pointer + CPS #UND_MODE + MOV SP, R0 + SUB R0, R0, #__UND_STACK_SIZE + + // Enter Abort Mode and set its Stack Pointer + CPS #ABT_MODE + MOV SP, R0 + SUB R0, R0, #__ABT_STACK_SIZE + + // Enter FIQ Mode and set its Stack Pointer + CPS #FIQ_MODE + MOV SP, R0 + SUB R0, R0, #__FIQ_STACK_SIZE + + // Enter IRQ Mode and set its Stack Pointer + CPS #IRQ_MODE + MOV SP, R0 + SUB R0, R0, #__IRQ_STACK_SIZE + + // Enter Supervisor Mode and set its Stack Pointer + CPS #SVC_MODE + MOV SP, R0 + SUB R0, R0, #__SVC_STACK_SIZE + + // Enter System Mode to complete initialization and enter kernel + CPS #SYS_MODE + MOV SP, R0 + + // Call SystemInit + IMPORT SystemInit + BL SystemInit + + // Unmask interrupts + CPSIE if + + // Call __main + IMPORT __main + BL __main +} + +/*---------------------------------------------------------------------------- + Default Handler for Exceptions / Interrupts + *----------------------------------------------------------------------------*/ +void Default_Handler(void) { + while(1); +} diff --git a/targets/TARGET_RENESAS/TARGET_RZ_A1XX/TARGET_GR_LYCHEE/device/TOOLCHAIN_ARM_STD/sys.cpp b/targets/TARGET_RENESAS/TARGET_RZ_A1XX/TARGET_GR_LYCHEE/device/TOOLCHAIN_ARM_STD/sys.cpp new file mode 100644 index 0000000..dfa0bc6 --- /dev/null +++ b/targets/TARGET_RENESAS/TARGET_RZ_A1XX/TARGET_GR_LYCHEE/device/TOOLCHAIN_ARM_STD/sys.cpp @@ -0,0 +1,61 @@ +/* mbed Microcontroller Library - stackheap + * Setup a fixed single stack/heap memory model, + * between the top of the RW/ZI region and the stackpointer + ******************************************************************************* + * Copyright (c) 2017 ARM Limited. + * All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions are met: + * + * 1. Redistributions of source code must retain the above copyright notice, + * this list of conditions and the following disclaimer. + * 2. Redistributions in binary form must reproduce the above copyright notice, + * this list of conditions and the following disclaimer in the documentation + * and/or other materials provided with the distribution. + * 3. Neither the name of ARM Limited nor the names of its contributors + * may be used to endorse or promote products derived from this software + * without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" + * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE + * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE + * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE + * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL + * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR + * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER + * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, + * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE + * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + ******************************************************************************* + */ + +#ifdef __cplusplus +extern "C" { +#endif + +#if defined(__ARMCC_VERSION) && (__ARMCC_VERSION >= 6010050) +#include +#endif + +#include +#include + +extern char Image$$ARM_LIB_HEAP$$Base[]; +extern char Image$$ARM_LIB_STACK$$Base[]; + +extern __value_in_regs struct __initial_stackheap _mbed_user_setup_stackheap(uint32_t R0, uint32_t R1, uint32_t R2, uint32_t R3) { + uint32_t zi_limit = (uint32_t)Image$$ARM_LIB_HEAP$$Base; + uint32_t sp_limit = (uint32_t)Image$$ARM_LIB_STACK$$Base; + + zi_limit = (zi_limit + 7) & ~0x7; // ensure zi_limit is 8-byte aligned + + struct __initial_stackheap r; + r.heap_base = zi_limit; + r.heap_limit = sp_limit; + return r; +} + +#ifdef __cplusplus +} +#endif diff --git a/targets/TARGET_RENESAS/TARGET_RZ_A1XX/TARGET_GR_LYCHEE/device/TOOLCHAIN_GCC_ARM/RZA1LU.ld b/targets/TARGET_RENESAS/TARGET_RZ_A1XX/TARGET_GR_LYCHEE/device/TOOLCHAIN_GCC_ARM/RZA1LU.ld new file mode 100644 index 0000000..6986987 --- /dev/null +++ b/targets/TARGET_RENESAS/TARGET_RZ_A1XX/TARGET_GR_LYCHEE/device/TOOLCHAIN_GCC_ARM/RZA1LU.ld @@ -0,0 +1,224 @@ +/* Linker script for mbed RZ_A1LU */ + +/* Linker script to configure memory regions. */ +MEMORY +{ + ROM (rx) : ORIGIN = 0x00000000, LENGTH = 0x02000000 + BOOT_LOADER (rx) : ORIGIN = 0x18000000, LENGTH = 0x00004000 + SFLASH (rx) : ORIGIN = 0x18004000, LENGTH = 0x07FFC000 + L_TTB (rw) : ORIGIN = 0x20000000, LENGTH = 0x00004000 + RAM (rwx) : ORIGIN = 0x20020000, LENGTH = 0x001E0000 + RAM_NC (rwx) : ORIGIN = 0x20200000, LENGTH = 0x00100000 +} + +/* Linker script to place sections and symbol values. Should be used together + * with other linker script that defines memory regions FLASH and RAM. + * It references following symbols, which must be defined in code: + * Reset_Handler : Entry of reset handler + * + * It defines following symbols, which code can use without definition: + * __exidx_start + * __exidx_end + * __etext + * __data_start__ + * __preinit_array_start + * __preinit_array_end + * __init_array_start + * __init_array_end + * __fini_array_start + * __fini_array_end + * __data_end__ + * __bss_start__ + * __bss_end__ + * __end__ + * end + * __HeapLimit + * __StackLimit + * __StackTop + * __stack + */ +ENTRY(Reset_Handler) + +SECTIONS +{ + .boot : + { + KEEP(*(.boot_loader)) + } > BOOT_LOADER + + .text : + { + + Image$$VECTORS$$Base = .; + * (RESET) + . += 0x00000400; + + KEEP(*(.isr_vector)) + *(SVC_TABLE) + *(.text*) + + KEEP(*(.init)) + KEEP(*(.fini)) + + /* .ctors */ + *crtbegin.o(.ctors) + *crtbegin?.o(.ctors) + *(EXCLUDE_FILE(*crtend?.o *crtend.o) .ctors) + *(SORT(.ctors.*)) + *(.ctors) + + /* .dtors */ + *crtbegin.o(.dtors) + *crtbegin?.o(.dtors) + *(EXCLUDE_FILE(*crtend?.o *crtend.o) .dtors) + *(SORT(.dtors.*)) + *(.dtors) + Image$$VECTORS$$Limit = .; + + Image$$RO_DATA$$Base = .; + *(.rodata*) + Image$$RO_DATA$$Limit = .; + + KEEP(*(.eh_frame*)) + } > SFLASH + + .ARM.extab : + { + *(.ARM.extab* .gnu.linkonce.armextab.*) + } > SFLASH + + __exidx_start = .; + .ARM.exidx : + { + *(.ARM.exidx* .gnu.linkonce.armexidx.*) + } > SFLASH + __exidx_end = .; + + + .copy.table : + { + . = ALIGN(4); + __copy_table_start__ = .; + LONG (__etext) + LONG (__data_start__) + LONG (__data_end__ - __data_start__) + LONG (__etext2) + LONG (__nc_data_start) + LONG (__nc_data_end - __nc_data_start) + __copy_table_end__ = .; + } > SFLASH + + .zero.table : + { + . = ALIGN(4); + __zero_table_start__ = .; + LONG (__bss_start__) + LONG (__bss_end__ - __bss_start__) + LONG (__nc_bss_start) + LONG (__nc_bss_end - __nc_bss_start) + __zero_table_end__ = .; + } > SFLASH + + __etext = .; + + .ttb : + { + Image$$TTB$$ZI$$Base = .; + . += 0x00004000; + Image$$TTB$$ZI$$Limit = .; + } > L_TTB + + .data : AT (__etext) + { + Image$$RW_DATA$$Base = .; + __data_start__ = .; + *(vtable) + *(.data*) + Image$$RW_DATA$$Limit = .; + + . = ALIGN(4); + /* preinit data */ + PROVIDE (__preinit_array_start = .); + KEEP(*(.preinit_array)) + PROVIDE (__preinit_array_end = .); + + . = ALIGN(4); + /* init data */ + PROVIDE (__init_array_start = .); + KEEP(*(SORT(.init_array.*))) + KEEP(*(.init_array)) + PROVIDE (__init_array_end = .); + + + . = ALIGN(4); + /* finit data */ + PROVIDE (__fini_array_start = .); + KEEP(*(SORT(.fini_array.*))) + KEEP(*(.fini_array)) + PROVIDE (__fini_array_end = .); + + . = ALIGN(4); + /* All data end */ + __data_end__ = .; + + } > RAM + + .bss ALIGN(0x10): + { + Image$$RW_IRAM1$$Base = .; + __bss_start__ = .; + *(.bss*) + *(COMMON) + __bss_end__ = .; + Image$$RW_IRAM1$$Limit = .; + } > RAM + + .heap : + { + __end__ = .; + end = __end__; + *(.heap*) + } > RAM + + /* .stack_dummy section doesn't contains any symbols. It is only + * used for linker to calculate size of stack sections, and assign + * values to stack symbols later */ + .stack_dummy (COPY): + { + *(.stack*) + } > RAM + + /* Set stack top to end of RAM, and stack limit move down by + * size of stack_dummy section */ + __StackTop = ORIGIN(RAM) + LENGTH(RAM); + _estack = __StackTop; + __StackLimit = __StackTop - SIZEOF(.stack_dummy); + __HeapLimit = __StackLimit; + PROVIDE(__stack = __StackTop); + + /* Check if data + heap + stack exceeds RAM limit */ + ASSERT(__StackLimit >= __HeapLimit, "region RAM overflowed with stack") + + __etext2 = __etext + SIZEOF(.data); + .nc_data : AT (__etext2) + { + Image$$RW_DATA_NC$$Base = .; + __nc_data_start = .; + *(NC_DATA) + + . = ALIGN(4); + __nc_data_end = .; + Image$$RW_DATA_NC$$Limit = .; + } > RAM_NC + + .nc_bss (NOLOAD) : + { + Image$$ZI_DATA_NC$$Base = .; + __nc_bss_start = .; + *(NC_BSS) + + . = ALIGN(4); + __nc_bss_end = .; + Image$$ZI_DATA_NC$$Limit = .; + } > RAM_NC +} diff --git a/targets/TARGET_RENESAS/TARGET_RZ_A1XX/TARGET_GR_LYCHEE/device/TOOLCHAIN_GCC_ARM/startup_RZ1ALU.S b/targets/TARGET_RENESAS/TARGET_RZ_A1XX/TARGET_GR_LYCHEE/device/TOOLCHAIN_GCC_ARM/startup_RZ1ALU.S new file mode 100644 index 0000000..4c1a629 --- /dev/null +++ b/targets/TARGET_RENESAS/TARGET_RZ_A1XX/TARGET_GR_LYCHEE/device/TOOLCHAIN_GCC_ARM/startup_RZ1ALU.S @@ -0,0 +1,249 @@ +/* File: startup_ARMCM3.s + * Purpose: startup file for Cortex-M3/M4 devices. Should use with + * GNU Tools for ARM Embedded Processors + * Version: V1.1 + * Date: 17 June 2011 + * + * Copyright (C) 2011 ARM Limited. All rights reserved. + * ARM Limited (ARM) is supplying this software for use with Cortex-M3/M4 + * processor based microcontrollers. This file can be freely distributed + * within development tools that are supporting such ARM based processors. + * + * THIS SOFTWARE IS PROVIDED "AS IS". NO WARRANTIES, WHETHER EXPRESS, IMPLIED + * OR STATUTORY, INCLUDING, BUT NOT LIMITED TO, IMPLIED WARRANTIES OF + * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE APPLY TO THIS SOFTWARE. + * ARM SHALL NOT, IN ANY CIRCUMSTANCES, BE LIABLE FOR SPECIAL, INCIDENTAL, OR + * CONSEQUENTIAL DAMAGES, FOR ANY REASON WHATSOEVER. + */ + .syntax unified + .extern _start + +@ Standard definitions of mode bits and interrupt (I & F) flags in PSRs + .equ Mode_USR , 0x10 + .equ Mode_FIQ , 0x11 + .equ Mode_IRQ , 0x12 + .equ Mode_SVC , 0x13 + .equ Mode_ABT , 0x17 + .equ Mode_UND , 0x1B + .equ Mode_SYS , 0x1F + + .equ I_Bit , 0x80 @ when I bit is set, IRQ is disabled + .equ F_Bit , 0x40 @ when F bit is set, FIQ is disabled + .equ T_Bit , 0x20 @ when T bit is set, core is in Thumb state + +@ Stack Configuration + + .EQU UND_Stack_Size , 0x00000100 + .EQU SVC_Stack_Size , 0x00008000 + .EQU ABT_Stack_Size , 0x00000100 + .EQU FIQ_Stack_Size , 0x00000100 + .EQU IRQ_Stack_Size , 0x0000F000 + + .EQU ISR_Stack_Size, (UND_Stack_Size + SVC_Stack_Size + ABT_Stack_Size + FIQ_Stack_Size + IRQ_Stack_Size) + + .section .stack + .align 3 + .globl __StackTop + .globl __StackLimit +__StackLimit: + .space ISR_Stack_Size +__initial_sp: + .size __StackLimit, . - __StackLimit +__StackTop: + .size __StackTop, . - __StackTop + + +@ Heap Configuration + + .EQU Heap_Size , 0x00080000 + + .section .heap + .align 3 + .globl __HeapBase + .globl __HeapLimit +__HeapBase: + .space Heap_Size + .size __HeapBase, . - __HeapBase +__HeapLimit: + .size __HeapLimit, . - __HeapLimit + + + .section .isr_vector + .align 2 + .globl __isr_vector +__isr_vector: + .long 0xe59ff018 /* 0x00 */ + .long 0xe59ff018 /* 0x04 */ + .long 0xe59ff018 /* 0x08 */ + .long 0xe59ff018 /* 0x0c */ + .long 0xe59ff018 /* 0x10 */ + .long 0xe59ff018 /* 0x14 */ + .long 0xe59ff018 /* 0x18 */ + .long 0xe59ff018 /* 0x1c */ + + .long Reset_Handler /* 0x20 */ + .long Undef_Handler /* 0x24 */ + .long SVC_Handler /* 0x28 */ + .long PAbt_Handler /* 0x2c */ + .long DAbt_Handler /* 0x30 */ + .long 0 /* Reserved */ + .long IRQ_Handler /* IRQ */ + .long FIQ_Handler /* FIQ */ + + + .size __isr_vector, . - __isr_vector + + .text + .align 2 + .globl Reset_Handler + .type Reset_Handler, %function +Reset_Handler: + @ Mask interrupts + CPSID if + + @ Put any cores other than 0 to sleep + mrc p15, 0, r0, c0, c0, 5 @ Read MPIDR + ands r0, r0, #3 +goToSleep: + wfine + bne goToSleep + + @ Reset SCTLR Settings + mrc p15, 0, r0, c1, c0, 0 @ Read CP15 System Control register + bic r0, r0, #(0x1 << 12) @ Clear I bit 12 to disable I Cache + bic r0, r0, #(0x1 << 2) @ Clear C bit 2 to disable D Cache + bic r0, r0, #0x1 @ Clear M bit 0 to disable MMU + bic r0, r0, #(0x1 << 11) @ Clear Z bit 11 to disable branch prediction + bic r0, r0, #(0x1 << 13) @ Clear V bit 13 to disable hivecs + mcr p15, 0, r0, c1, c0, 0 @ Write value back to CP15 System Control register + isb + + @ Configure ACTLR + MRC p15, 0, r0, c1, c0, 1 @ Read CP15 Auxiliary Control Register + ORR r0, r0, #(1 << 1) @ Enable L2 prefetch hint (UNK/WI since r4p1) + MCR p15, 0, r0, c1, c0, 1 @ Write CP15 Auxiliary Control Register + + @ Set Vector Base Address Register (VBAR) to point to this application's vector table + ldr r0, =__isr_vector + mcr p15, 0, r0, c12, c0, 0 + +@ Setup Stack for each exceptional mode + ldr r0, =__StackTop + +@ Enter Undefined Instruction Mode and set its Stack Pointer + msr cpsr_c, #(Mode_UND | I_Bit | F_Bit) + mov sp, r0 + sub r0, r0, #UND_Stack_Size + +@ Enter Abort Mode and set its Stack Pointer + msr cpsr_c, #(Mode_ABT | I_Bit | F_Bit) + mov sp, r0 + sub r0, r0, #ABT_Stack_Size + +@ Enter FIQ Mode and set its Stack Pointer + msr cpsr_c, #(Mode_FIQ | I_Bit | F_Bit) + mov sp, r0 + sub r0, r0, #FIQ_Stack_Size + +@ Enter IRQ Mode and set its Stack Pointer + msr cpsr_c, #(Mode_IRQ | I_Bit | F_Bit) + mov sp, r0 + sub r0, r0, #IRQ_Stack_Size + +@ Enter Supervisor Mode and set its Stack Pointer + msr cpsr_c, #(Mode_SVC | I_Bit | F_Bit) + mov sp, r0 + +@ Enter System Mode to complete initialization and enter kernel + msr cpsr_c, #(Mode_SYS | I_Bit | F_Bit) + mov sp, r0 + +@ USR/SYS stack pointer will be set during kernel init + ldr r0, =SystemInit + blx r0 + + @ Unmask interrupts + CPSIE if + +@ data sections copy + ldr r4, =__copy_table_start__ + ldr r5, =__copy_table_end__ + +.L_loop0: + cmp r4, r5 + bge .L_loop0_done + ldr r1, [r4] + ldr r2, [r4, #4] + ldr r3, [r4, #8] + +.L_loop0_0: + subs r3, #4 + ittt ge + ldrge r0, [r1, r3] + strge r0, [r2, r3] + bge .L_loop0_0 + + adds r4, #12 + b .L_loop0 + +.L_loop0_done: + +@ bss sections clear + ldr r3, =__zero_table_start__ + ldr r4, =__zero_table_end__ + +.L_loop2: + cmp r3, r4 + bge .L_loop2_done + ldr r1, [r3] + ldr r2, [r3, #4] + movs r0, 0 + +.L_loop2_0: + subs r2, #4 + itt ge + strge r0, [r1, r2] + bge .L_loop2_0 + + adds r3, #8 + b .L_loop2 +.L_loop2_done: + + + ldr r0, =_start + bx r0 + + ldr r0, sf_boot @ dummy to keep boot loader area +loop_here: + b loop_here + +sf_boot: + .word boot_loader + + .pool + .size Reset_Handler, . - Reset_Handler + + + .text + +/* Macro to define default handlers. Default handler + * will be weak symbol and just dead loops. They can be + * overwritten by other handlers */ + .macro def_default_handler handler_name + .align 1 + .thumb_func + .weak \handler_name + .type \handler_name, %function +\handler_name : + b . + .size \handler_name, . - \handler_name + .endm + + def_default_handler Undef_Handler + def_default_handler SVC_Handler + def_default_handler PAbt_Handler + def_default_handler DAbt_Handler + def_default_handler IRQ_Handler + def_default_handler FIQ_Handler + + .END diff --git a/targets/TARGET_RENESAS/TARGET_RZ_A1XX/TARGET_GR_LYCHEE/device/TOOLCHAIN_IAR/MBRZA1LU.icf b/targets/TARGET_RENESAS/TARGET_RZ_A1XX/TARGET_GR_LYCHEE/device/TOOLCHAIN_IAR/MBRZA1LU.icf new file mode 100644 index 0000000..5d72266 --- /dev/null +++ b/targets/TARGET_RENESAS/TARGET_RZ_A1XX/TARGET_GR_LYCHEE/device/TOOLCHAIN_IAR/MBRZA1LU.icf @@ -0,0 +1,63 @@ +/*###ICF### Section handled by ICF editor, don't touch! ****/ +/*-Editor annotation file-*/ +/* IcfEditorFile="$TOOLKIT_DIR$\config\ide\IcfEditor\a_v1_0.xml" */ +/*-Specials-*/ +define symbol __ICFEDIT_intvec_start__ = 0x18004000; +/*-Memory Regions-*/ +define symbol __ICFEDIT_region_ROM_start__ = 0x18000000; +define symbol __ICFEDIT_region_ROM_end__ = 0x187FFFFF; +define symbol __ICFEDIT_region_TTB_start__ = 0x20000000; +define symbol __ICFEDIT_region_TTB_end__ = 0x2001FFFF; +define symbol __ICFEDIT_region_RAM_start__ = 0x20020000; +define symbol __ICFEDIT_region_RAM_end__ = 0x202FFFFF; + +/*-Sizes-*/ +define symbol __ICFEDIT_size_cstack__ = 0x00004000; +define symbol __ICFEDIT_size_svcstack__ = 0x00008000; +define symbol __ICFEDIT_size_irqstack__ = 0x00008000; +define symbol __ICFEDIT_size_fiqstack__ = 0x00000100; +define symbol __ICFEDIT_size_undstack__ = 0x00000100; +define symbol __ICFEDIT_size_abtstack__ = 0x00000100; +define symbol __ICFEDIT_size_heap__ = 0x00080000; +/**** End of ICF editor section. ###ICF###*/ + +define symbol __ICFEDIT_region_RetRAM_start__ = 0x20000000; +define symbol __ICFEDIT_region_RetRAM_end__ = 0x2001FFFF; + +define symbol __ICFEDIT_region_MirrorRAM_start__ = 0x60200000; +define symbol __ICFEDIT_region_MirrorRAM_end__ = 0x602FFFFF; + +define symbol __ICFEDIT_region_MirrorRetRAM_start__ = 0x60000000; +define symbol __ICFEDIT_region_MirrorRetRAM_end__ = 0x6001FFFF; + +define memory mem with size = 4G; + +define region ROM_region = mem:[from __ICFEDIT_region_ROM_start__ to __ICFEDIT_region_ROM_end__]; +define region RAM_region = mem:[from __ICFEDIT_region_RAM_start__ to __ICFEDIT_region_RAM_end__]; +define region RetRAM_region = mem:[from __ICFEDIT_region_RetRAM_start__ to __ICFEDIT_region_RetRAM_end__]; +define region MirrorRAM_region = mem:[from __ICFEDIT_region_MirrorRAM_start__ to __ICFEDIT_region_MirrorRAM_end__]; +define region MirrorRetRAM_region = mem:[from __ICFEDIT_region_MirrorRetRAM_start__ to __ICFEDIT_region_MirrorRetRAM_end__]; + +define block ROM_FIXED_ORDER with fixed order { ro code, ro data }; +define block CSTACK with alignment = 8, size = __ICFEDIT_size_cstack__ { }; +define block SVC_STACK with alignment = 8, size = __ICFEDIT_size_svcstack__ { }; +define block IRQ_STACK with alignment = 8, size = __ICFEDIT_size_irqstack__ { }; +define block FIQ_STACK with alignment = 8, size = __ICFEDIT_size_fiqstack__ { }; +define block UND_STACK with alignment = 8, size = __ICFEDIT_size_undstack__ { }; +define block ABT_STACK with alignment = 8, size = __ICFEDIT_size_abtstack__ { }; +define block HEAP with alignment = 8, size = __ICFEDIT_size_heap__ { }; + +initialize by copy { readwrite }; +do not initialize { section .noinit }; +do not initialize { section .retram }; + +place at address mem:__ICFEDIT_intvec_start__ { readonly section .intvec }; + +place in ROM_region { readonly, block ROM_FIXED_ORDER }; +place in RAM_region { readwrite, + block CSTACK, block SVC_STACK, block IRQ_STACK, block FIQ_STACK, + block UND_STACK, block ABT_STACK, block HEAP }; + +place in RetRAM_region { section .retram }; +place in MirrorRAM_region { section .mirrorram }; +place in MirrorRetRAM_region { section .mirrorretram }; diff --git a/targets/TARGET_RENESAS/TARGET_RZ_A1XX/TARGET_GR_LYCHEE/device/TOOLCHAIN_IAR/startup_RZA1LU.S b/targets/TARGET_RENESAS/TARGET_RZ_A1XX/TARGET_GR_LYCHEE/device/TOOLCHAIN_IAR/startup_RZA1LU.S new file mode 100644 index 0000000..9f6858d --- /dev/null +++ b/targets/TARGET_RENESAS/TARGET_RZ_A1XX/TARGET_GR_LYCHEE/device/TOOLCHAIN_IAR/startup_RZA1LU.S @@ -0,0 +1,226 @@ +;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;; +;; +;; Part one of the system initialization code, +;; contains low-level +;; initialization. +;; +;; Copyright 2007 IAR Systems. All rights reserved. +;; +;; $Revision: 49919 $ +;; + + MODULE ?cstartup + + ;; Forward declaration of sections. + SECTION SVC_STACK:DATA:NOROOT(3) + SECTION IRQ_STACK:DATA:NOROOT(3) + SECTION ABT_STACK:DATA:NOROOT(3) + SECTION FIQ_STACK:DATA:NOROOT(3) + SECTION UND_STACK:DATA:NOROOT(3) + SECTION CSTACK:DATA:NOROOT(3) + +; +; The module in this file are included in the libraries, and may be +; replaced by any user-defined modules that define the PUBLIC symbol +; __iar_program_start or a user defined start symbol. +; +; To override the cstartup defined in the library, simply add your +; modified version to the workbench project. + + SECTION .intvec:CODE:NOROOT(2) + + PUBLIC __vector_table + PUBLIC __RST_Handler + EXTERN Undef_Handler + EXTERN SVC_Handler + EXTERN PAbt_Handler + EXTERN DAbt_Handler + EXTERN IRQ_Handler + PUBLIC FIQ_Handler + + DATA + +__iar_init$$done: ; The vector table is not needed + ; until after copy initialization is done + +__vector_table: ; Make this a DATA label, so that stack usage + ; analysis doesn't consider it an uncalled fun + + ARM + + ; All default exception handlers (except reset) are + ; defined as weak symbol definitions. + ; If a handler is defined by the application it will take precedence. + LDR PC,Reset_Addr ; Reset + LDR PC,Undefined_Addr ; Undefined instructions + LDR PC,SWI_Addr ; Software interrupt (SWI/SVC) + LDR PC,Prefetch_Addr ; Prefetch abort + LDR PC,Abort_Addr ; Data abort + DCD 0 ; RESERVED + LDR PC,IRQ_Addr ; IRQ + LDR PC,FIQ_Addr ; FIQ + + DATA + +Reset_Addr: DCD __RST_Handler +Undefined_Addr: DCD Undef_Handler +SWI_Addr: DCD SVC_Handler +Prefetch_Addr: DCD PAbt_Handler +Abort_Addr: DCD DAbt_Handler +IRQ_Addr: DCD IRQ_Handler +FIQ_Addr: DCD FIQ_Handler + + +; -------------------------------------------------- +; ?cstartup -- low-level system initialization code. +; +; After a reset execution starts here, the mode is ARM, supervisor +; with interrupts disabled. +; + + + + SECTION .text:CODE:NOROOT(2) + EXTERN SystemInit + EXTERN __iar_program_start + REQUIRE __vector_table + EXTWEAK __iar_init_core + EXTWEAK __iar_init_vfp + + + ARM + +__RST_Handler: +?cstartup: + +;;; @ Mask interrupts + CPSID if + +;;; @ Put any cores other than 0 to sleep + mrc p15, 0, r0, c0, c0, 5 ;;; @ Read MPIDR + ands r0, r0, #3 + +goToSleep: + wfine + bne goToSleep + +;;; @ Reset SCTLR Settings + mrc p15, 0, r0, c1, c0, 0 ;@ Read CP15 System Control register + bic r0, r0, #(0x1 << 12) ;@ Clear I bit 12 to disable I Cache + bic r0, r0, #(0x1 << 2) ;@ Clear C bit 2 to disable D Cache + bic r0, r0, #0x1 ;@ Clear M bit 0 to disable MMU + bic r0, r0, #(0x1 << 11) ;@ Clear Z bit 11 to disable branch prediction + bic r0, r0, #(0x1 << 13) ;@ Clear V bit 13 to disable hivecs + mcr p15, 0, r0, c1, c0, 0 ;@ Write value back to CP15 System Control register + isb + +;;; @ Configure ACTLR + MRC p15, 0, r0, c1, c0, 1 ;@ Read CP15 Auxiliary Control Register + ORR r0, r0, #(1 << 1) ;@ Enable L2 prefetch hint (UNK/WI since r4p1) + MCR p15, 0, r0, c1, c0, 1 ;@ Write CP15 Auxiliary Control Register + +;; Set Vector Base Address Register (VBAR) to point to this application's vector table + ldr r0, =__vector_table + mcr p15, 0, r0, c12, c0, 0 + + +; +; Add initialization needed before setup of stackpointers here. +; + +; +; Initialize the stack pointers. +; The pattern below can be used for any of the exception stacks: +; FIQ, IRQ, SVC, ABT, UND, SYS. +; The USR mode uses the same stack as SYS. +; The stack segments must be defined in the linker command file, +; and be declared above. +; + + +; -------------------- +; Mode, correspords to bits 0-5 in CPSR + +#define MODE_MSK 0x1F ; Bit mask for mode bits in CPSR + +#define USR_MODE 0x10 ; User mode +#define FIQ_MODE 0x11 ; Fast Interrupt Request mode +#define IRQ_MODE 0x12 ; Interrupt Request mode +#define SVC_MODE 0x13 ; Supervisor mode +#define ABT_MODE 0x17 ; Abort mode +#define UND_MODE 0x1B ; Undefined Instruction mode +#define SYS_MODE 0x1F ; System mode + + MRS r0, cpsr ; Original PSR value + + ;; Set up the SVC stack pointer. + BIC r0, r0, #MODE_MSK ; Clear the mode bits + ORR r0, r0, #SVC_MODE ; Set SVC mode bits + MSR cpsr_c, r0 ; Change the mode + LDR sp, =SFE(SVC_STACK) ; End of SVC_STACK + BIC sp,sp,#0x7 ; Make sure SP is 8 aligned + + ;; Set up the interrupt stack pointer. + + BIC r0, r0, #MODE_MSK ; Clear the mode bits + ORR r0, r0, #IRQ_MODE ; Set IRQ mode bits + MSR cpsr_c, r0 ; Change the mode + LDR sp, =SFE(IRQ_STACK) ; End of IRQ_STACK + BIC sp,sp,#0x7 ; Make sure SP is 8 aligned + + ;; Set up the fast interrupt stack pointer. + + BIC r0, r0, #MODE_MSK ; Clear the mode bits + ORR r0, r0, #FIQ_MODE ; Set FIR mode bits + MSR cpsr_c, r0 ; Change the mode + LDR sp, =SFE(FIQ_STACK) ; End of FIQ_STACK + BIC sp,sp,#0x7 ; Make sure SP is 8 aligned + + + ;; Set up the ABT stack pointer. + + BIC r0 ,r0, #MODE_MSK ; Clear the mode bits + ORR r0 ,r0, #ABT_MODE ; Set System mode bits + MSR cpsr_c, r0 ; Change the mode + LDR sp, =SFE(ABT_STACK) ; End of CSTACK + BIC sp,sp,#0x7 ; Make sure SP is 8 aligned + + + ;; Set up the UDF stack pointer. + + BIC r0 ,r0, #MODE_MSK ; Clear the mode bits + ORR r0 ,r0, #UND_MODE ; Set System mode bits + MSR cpsr_c, r0 ; Change the mode + LDR sp, =SFE(UND_STACK) ; End of CSTACK + BIC sp,sp,#0x7 ; Make sure SP is 8 aligned + + ;; Set up the normal stack pointer. + + BIC r0 ,r0, #MODE_MSK ; Clear the mode bits + ORR r0 ,r0, #SYS_MODE ; Set System mode bits + MSR cpsr_c, r0 ; Change the mode + LDR sp, =SFE(CSTACK) ; End of CSTACK + BIC sp,sp,#0x7 ; Make sure SP is 8 aligned + +;;; +; USR/SYS stack pointer will be set during kernel init + ldr r0, =SystemInit + blx r0 + +;;; Continue to __cmain for C-level initialization. + + FUNCALL __RST_Handler, __iar_program_start + B __iar_program_start + + + ldr r0, sf_boot ;@ dummy to keep boot loader area +loop_here: + b loop_here + +sf_boot: + DC32 0x00000001 + +FIQ_Handler: + B . + + END diff --git a/targets/TARGET_RENESAS/TARGET_RZ_A1XX/TARGET_GR_LYCHEE/device/cmsis.h b/targets/TARGET_RENESAS/TARGET_RZ_A1XX/TARGET_GR_LYCHEE/device/cmsis.h new file mode 100644 index 0000000..8ac17cf --- /dev/null +++ b/targets/TARGET_RENESAS/TARGET_RZ_A1XX/TARGET_GR_LYCHEE/device/cmsis.h @@ -0,0 +1,12 @@ +/* mbed Microcontroller Library - CMSIS + * Copyright (C) 2009-2011 ARM Limited. All rights reserved. + * + * A generic CMSIS include header, pulling in LPC1768 specifics + */ + +#ifndef MBED_CMSIS_H +#define MBED_CMSIS_H + +#include "MBRZA1LU.h" + +#endif diff --git a/targets/TARGET_RENESAS/TARGET_RZ_A1XX/TARGET_GR_LYCHEE/device/cmsis_nvic.c b/targets/TARGET_RENESAS/TARGET_RZ_A1XX/TARGET_GR_LYCHEE/device/cmsis_nvic.c new file mode 100644 index 0000000..5e9683d --- /dev/null +++ b/targets/TARGET_RENESAS/TARGET_RZ_A1XX/TARGET_GR_LYCHEE/device/cmsis_nvic.c @@ -0,0 +1,41 @@ +/* mbed Microcontroller Library + * CMSIS-style functionality to support dynamic vectors + ******************************************************************************* + * Copyright (c) 2015 ARM Limited. All rights reserved. + * All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions are met: + * + * 1. Redistributions of source code must retain the above copyright notice, + * this list of conditions and the following disclaimer. + * 2. Redistributions in binary form must reproduce the above copyright notice, + * this list of conditions and the following disclaimer in the documentation + * and/or other materials provided with the distribution. + * 3. Neither the name of ARM Limited nor the names of its contributors + * may be used to endorse or promote products derived from this software + * without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" + * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE + * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE + * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE + * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL + * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR + * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER + * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, + * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE + * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + ******************************************************************************* + */ +#include "MBRZA1LU.h" +#include "irq_ctrl.h" + +void NVIC_SetVector(IRQn_Type IRQn, uint32_t vector) { + InterruptHandlerRegister(IRQn, (IRQHandler)vector); +} + +uint32_t NVIC_GetVector(IRQn_Type IRQn) { + uint32_t vectors = (uint32_t)IRQ_GetHandler(IRQn); + return vectors; +} diff --git a/targets/TARGET_RENESAS/TARGET_RZ_A1XX/TARGET_GR_LYCHEE/device/inc/RZ_A1LU.h b/targets/TARGET_RENESAS/TARGET_RZ_A1XX/TARGET_GR_LYCHEE/device/inc/RZ_A1LU.h new file mode 100644 index 0000000..4f50834 --- /dev/null +++ b/targets/TARGET_RENESAS/TARGET_RZ_A1XX/TARGET_GR_LYCHEE/device/inc/RZ_A1LU.h @@ -0,0 +1,921 @@ +/****************************************************************************** + * @file RZ_A1LU.h + * @brief CMSIS Cortex-A9 Core Peripheral Access Layer Header File + * @version V1.00 + * @data 10 Mar 2017 + * + * @note + * + ******************************************************************************/ +/* + * Copyright (c) 2013-2014 Renesas Electronics Corporation. All rights reserved. + * Copyright (c) 2009-2017 ARM Limited. All rights reserved. + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the License); you may + * not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an AS IS BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ + +#ifndef __RZ_A1LU_H__ +#define __RZ_A1LU_H__ + +#ifdef __cplusplus +extern "C" { +#endif + +/* ------------------------- Interrupt Number Definition ------------------------ */ + +typedef enum IRQn +{ +/****** SGI Interrupts Numbers ****************************************/ + SGI0_IRQn = 0, + SGI1_IRQn = 1, + SGI2_IRQn = 2, + SGI3_IRQn = 3, + SGI4_IRQn = 4, + SGI5_IRQn = 5, + SGI6_IRQn = 6, + SGI7_IRQn = 7, + SGI8_IRQn = 8, + SGI9_IRQn = 9, + SGI10_IRQn = 10, + SGI11_IRQn = 11, + SGI12_IRQn = 12, + SGI13_IRQn = 13, + SGI14_IRQn = 14, + SGI15_IRQn = 15, + +/****** Cortex-A9 Processor Exceptions Numbers ****************************************/ + /* 16 - 578 */ + PMUIRQ0_IRQn = 16, + COMMRX0_IRQn = 17, + COMMTX0_IRQn = 18, + CTIIRQ0_IRQn = 19, + + IRQ0_IRQn = 32, + IRQ1_IRQn = 33, + IRQ2_IRQn = 34, + IRQ3_IRQn = 35, + IRQ4_IRQn = 36, + IRQ5_IRQn = 37, + IRQ6_IRQn = 38, + IRQ7_IRQn = 39, + + PL310ERR_IRQn = 40, + + DMAINT0_IRQn = 41, /*!< DMAC Interrupt */ + DMAINT1_IRQn = 42, /*!< DMAC Interrupt */ + DMAINT2_IRQn = 43, /*!< DMAC Interrupt */ + DMAINT3_IRQn = 44, /*!< DMAC Interrupt */ + DMAINT4_IRQn = 45, /*!< DMAC Interrupt */ + DMAINT5_IRQn = 46, /*!< DMAC Interrupt */ + DMAINT6_IRQn = 47, /*!< DMAC Interrupt */ + DMAINT7_IRQn = 48, /*!< DMAC Interrupt */ + DMAINT8_IRQn = 49, /*!< DMAC Interrupt */ + DMAINT9_IRQn = 50, /*!< DMAC Interrupt */ + DMAINT10_IRQn = 51, /*!< DMAC Interrupt */ + DMAINT11_IRQn = 52, /*!< DMAC Interrupt */ + DMAINT12_IRQn = 53, /*!< DMAC Interrupt */ + DMAINT13_IRQn = 54, /*!< DMAC Interrupt */ + DMAINT14_IRQn = 55, /*!< DMAC Interrupt */ + DMAINT15_IRQn = 56, /*!< DMAC Interrupt */ + DMAERR_IRQn = 57, /*!< DMAC Interrupt */ + + /* 58-72 Reserved */ + + USBI0_IRQn = 73, + USBI1_IRQn = 74, + + S0_VI_VSYNC0_IRQn = 75, + S0_LO_VSYNC0_IRQn = 76, + S0_VSYNCERR0_IRQn = 77, + GR3_VLINE0_IRQn = 78, + S0_VFIELD0_IRQn = 79, + IV1_VBUFERR0_IRQn = 80, + IV3_VBUFERR0_IRQn = 81, + IV5_VBUFERR0_IRQn = 82, + IV6_VBUFERR0_IRQn = 83, + S0_WLINE0_IRQn = 84, + S1_VI_VSYNC0_IRQn = 85, + S1_LO_VSYNC0_IRQn = 86, + S1_VSYNCERR0_IRQn = 87, + S1_VFIELD0_IRQn = 88, + IV2_VBUFERR0_IRQn = 89, + IV4_VBUFERR0_IRQn = 90, + S1_WLINE0_IRQn = 91, + OIR_VI_VSYNC0_IRQn = 92, + OIR_LO_VSYNC0_IRQn = 93, + OIR_VSYNCERR0_IRQn = 94, + OIR_VFIELD0_IRQn = 95, + IV7_VBUFERR0_IRQn = 96, + IV8_VBUFERR0_IRQn = 97, + /* 98 Reserved */ + S0_VI_VSYNC1_IRQn = 99, + S0_LO_VSYNC1_IRQn = 100, + S0_VSYNCERR1_IRQn = 101, + GR3_VLINE1_IRQn = 102, + S0_VFIELD1_IRQn = 103, + IV1_VBUFERR1_IRQn = 104, + IV3_VBUFERR1_IRQn = 105, + IV5_VBUFERR1_IRQn = 106, + IV6_VBUFERR1_IRQn = 107, + S0_WLINE1_IRQn = 108, + S1_VI_VSYNC1_IRQn = 109, + S1_LO_VSYNC1_IRQn = 110, + S1_VSYNCERR1_IRQn = 111, + S1_VFIELD1_IRQn = 112, + IV2_VBUFERR1_IRQn = 113, + IV4_VBUFERR1_IRQn = 114, + S1_WLINE1_IRQn = 115, + OIR_VI_VSYNC1_IRQn = 116, + OIR_LO_VSYNC1_IRQn = 117, + OIR_VSYNCERR1_IRQn = 118, + OIR_VFIELD1_IRQn = 119, + IV7_VBUFERR1_IRQn = 120, + IV8_VBUFERR1_IRQn = 121, + /* Reserved = 122 */ + + IMRDI_IRQn = 123, + IMR2I0_IRQn = 124, + IMR2I1_IRQn = 125, + + JEDI_IRQn = 126, + JDTI_IRQn = 127, + + CMP0_IRQn = 128, + CMP1_IRQn = 129, + + INT0_IRQn = 130, + INT1_IRQn = 131, + INT2_IRQn = 132, + INT3_IRQn = 133, + + OSTMI0TINT_IRQn = 134, /*!< OSTM Interrupt */ + OSTMI1TINT_IRQn = 135, /*!< OSTM Interrupt */ + + CMI_IRQn = 136, + WTOUT_IRQn = 137, + + ITI_IRQn = 138, + + TGI0A_IRQn = 139, + TGI0B_IRQn = 140, + TGI0C_IRQn = 141, + TGI0D_IRQn = 142, + TGI0V_IRQn = 143, + TGI0E_IRQn = 144, + TGI0F_IRQn = 145, + TGI1A_IRQn = 146, + TGI1B_IRQn = 147, + TGI1V_IRQn = 148, + TGI1U_IRQn = 149, + TGI2A_IRQn = 150, + TGI2B_IRQn = 151, + TGI2V_IRQn = 152, + TGI2U_IRQn = 153, + TGI3A_IRQn = 154, + TGI3B_IRQn = 155, + TGI3C_IRQn = 156, + TGI3D_IRQn = 157, + TGI3V_IRQn = 158, + TGI4A_IRQn = 159, + TGI4B_IRQn = 160, + TGI4C_IRQn = 161, + TGI4D_IRQn = 162, + TGI4V_IRQn = 163, + + CMI1_IRQn = 164, + CMI2_IRQn = 165, + + SGDEI0_IRQn = 166, + SGDEI1_IRQn = 167, + SGDEI2_IRQn = 168, + SGDEI3_IRQn = 169, + + ADI_IRQn = 170, + LMTI_IRQn = 171, + + SSII0_IRQn = 172, /*!< SSIF Interrupt */ + SSIRXI0_IRQn = 173, /*!< SSIF Interrupt */ + SSITXI0_IRQn = 174, /*!< SSIF Interrupt */ + SSII1_IRQn = 175, /*!< SSIF Interrupt */ + SSIRXI1_IRQn = 176, /*!< SSIF Interrupt */ + SSITXI1_IRQn = 177, /*!< SSIF Interrupt */ + SSII2_IRQn = 178, /*!< SSIF Interrupt */ + SSIRTI2_IRQn = 179, /*!< SSIF Interrupt */ + SSII3_IRQn = 180, /*!< SSIF Interrupt */ + SSIRXI3_IRQn = 181, /*!< SSIF Interrupt */ + SSITXI3_IRQn = 182, /*!< SSIF Interrupt */ + SSII4_IRQn = 183, /*!< SSIF Interrupt */ + SSIRTI4_IRQn = 184, /*!< SSIF Interrupt */ + SSII5_IRQn = 185, /*!< SSIF Interrupt */ + SSIRXI5_IRQn = 186, /*!< SSIF Interrupt */ + SSITXI5_IRQn = 187, /*!< SSIF Interrupt */ + + SPDIFI_IRQn = 188, + + INTIICTEI0_IRQn = 189, /*!< RIIC Interrupt */ + INTIICRI0_IRQn = 190, /*!< RIIC Interrupt */ + INTIICTI0_IRQn = 191, /*!< RIIC Interrupt */ + INTIICSPI0_IRQn = 192, /*!< RIIC Interrupt */ + INTIICSTI0_IRQn = 193, /*!< RIIC Interrupt */ + INTIICNAKI0_IRQn = 194, /*!< RIIC Interrupt */ + INTIICALI0_IRQn = 195, /*!< RIIC Interrupt */ + INTIICTMOI0_IRQn = 196, /*!< RIIC Interrupt */ + INTIICTEI1_IRQn = 197, /*!< RIIC Interrupt */ + INTIICRI1_IRQn = 198, /*!< RIIC Interrupt */ + INTIICTI1_IRQn = 199, /*!< RIIC Interrupt */ + INTIICSPI1_IRQn = 200, /*!< RIIC Interrupt */ + INTIICSTI1_IRQn = 201, /*!< RIIC Interrupt */ + INTIICNAKI1_IRQn = 202, /*!< RIIC Interrupt */ + INTIICALI1_IRQn = 203, /*!< RIIC Interrupt */ + INTIICTMOI1_IRQn = 204, /*!< RIIC Interrupt */ + INTIICTEI2_IRQn = 205, /*!< RIIC Interrupt */ + INTIICRI2_IRQn = 206, /*!< RIIC Interrupt */ + INTIICTI2_IRQn = 207, /*!< RIIC Interrupt */ + INTIICSPI2_IRQn = 208, /*!< RIIC Interrupt */ + INTIICSTI2_IRQn = 209, /*!< RIIC Interrupt */ + INTIICNAKI2_IRQn = 210, /*!< RIIC Interrupt */ + INTIICALI2_IRQn = 211, /*!< RIIC Interrupt */ + INTIICTMOI2_IRQn = 212, /*!< RIIC Interrupt */ + INTIICTEI3_IRQn = 213, /*!< RIIC Interrupt */ + INTIICRI3_IRQn = 214, /*!< RIIC Interrupt */ + INTIICTI3_IRQn = 215, /*!< RIIC Interrupt */ + INTIICSPI3_IRQn = 216, /*!< RIIC Interrupt */ + INTIICSTI3_IRQn = 217, /*!< RIIC Interrupt */ + INTIICNAKI3_IRQn = 218, /*!< RIIC Interrupt */ + INTIICALI3_IRQn = 219, /*!< RIIC Interrupt */ + INTIICTMOI3_IRQn = 220, /*!< RIIC Interrupt */ + + SCIFBRI0_IRQn = 221, /*!< SCIF Interrupt */ + SCIFERI0_IRQn = 222, /*!< SCIF Interrupt */ + SCIFRXI0_IRQn = 223, /*!< SCIF Interrupt */ + SCIFTXI0_IRQn = 224, /*!< SCIF Interrupt */ + SCIFBRI1_IRQn = 225, /*!< SCIF Interrupt */ + SCIFERI1_IRQn = 226, /*!< SCIF Interrupt */ + SCIFRXI1_IRQn = 227, /*!< SCIF Interrupt */ + SCIFTXI1_IRQn = 228, /*!< SCIF Interrupt */ + SCIFBRI2_IRQn = 229, /*!< SCIF Interrupt */ + SCIFERI2_IRQn = 230, /*!< SCIF Interrupt */ + SCIFRXI2_IRQn = 231, /*!< SCIF Interrupt */ + SCIFTXI2_IRQn = 232, /*!< SCIF Interrupt */ + SCIFBRI3_IRQn = 233, /*!< SCIF Interrupt */ + SCIFERI3_IRQn = 234, /*!< SCIF Interrupt */ + SCIFRXI3_IRQn = 235, /*!< SCIF Interrupt */ + SCIFTXI3_IRQn = 236, /*!< SCIF Interrupt */ + SCIFBRI4_IRQn = 237, /*!< SCIF Interrupt */ + SCIFERI4_IRQn = 238, /*!< SCIF Interrupt */ + SCIFRXI4_IRQn = 239, /*!< SCIF Interrupt */ + SCIFTXI4_IRQn = 240, /*!< SCIF Interrupt */ + SCIFBRI5_IRQn = 241, /*!< SCIF Interrupt */ + SCIFERI5_IRQn = 242, /*!< SCIF Interrupt */ + SCIFRXI5_IRQn = 243, /*!< SCIF Interrupt */ + SCIFTXI5_IRQn = 244, /*!< SCIF Interrupt */ + SCIFBRI6_IRQn = 245, /*!< SCIF Interrupt */ + SCIFERI6_IRQn = 246, /*!< SCIF Interrupt */ + SCIFRXI6_IRQn = 247, /*!< SCIF Interrupt */ + SCIFTXI6_IRQn = 248, /*!< SCIF Interrupt */ + SCIFBRI7_IRQn = 249, /*!< SCIF Interrupt */ + SCIFERI7_IRQn = 250, /*!< SCIF Interrupt */ + SCIFRXI7_IRQn = 251, /*!< SCIF Interrupt */ + SCIFTXI7_IRQn = 252, /*!< SCIF Interrupt */ + + INTRCANGERR_IRQn = 253, + INTRCANGRECC_IRQn = 254, + INTRCAN0REC_IRQn = 255, + INTRCAN0ERR_IRQn = 256, + INTRCAN0TRX_IRQn = 257, + INTRCAN1REC_IRQn = 258, + INTRCAN1ERR_IRQn = 259, + INTRCAN1TRX_IRQn = 260, + INTRCAN2REC_IRQn = 261, + INTRCAN2ERR_IRQn = 262, + INTRCAN2TRX_IRQn = 263, + INTRCAN3REC_IRQn = 264, + INTRCAN3ERR_IRQn = 265, + INTRCAN3TRX_IRQn = 266, + INTRCAN4REC_IRQn = 267, + INTRCAN4ERR_IRQn = 268, + INTRCAN4TRX_IRQn = 269, + + RSPISPEI0_IRQn = 270, /*!< RSPI Interrupt */ + RSPISPRI0_IRQn = 271, /*!< RSPI Interrupt */ + RSPISPTI0_IRQn = 272, /*!< RSPI Interrupt */ + RSPISPEI1_IRQn = 273, /*!< RSPI Interrupt */ + RSPISPRI1_IRQn = 274, /*!< RSPI Interrupt */ + RSPISPTI1_IRQn = 275, /*!< RSPI Interrupt */ + RSPISPEI2_IRQn = 276, /*!< RSPI Interrupt */ + RSPISPRI2_IRQn = 277, /*!< RSPI Interrupt */ + RSPISPTI2_IRQn = 278, /*!< RSPI Interrupt */ + RSPISPEI3_IRQn = 279, /*!< RSPI Interrupt */ + RSPISPRI3_IRQn = 280, /*!< RSPI Interrupt */ + RSPISPTI3_IRQn = 281, /*!< RSPI Interrupt */ + RSPISPEI4_IRQn = 282, /*!< RSPI Interrupt */ + RSPISPRI4_IRQn = 283, /*!< RSPI Interrupt */ + RSPISPTI4_IRQn = 284, /*!< RSPI Interrupt */ + + IEBBTD_IRQn = 285, + IEBBTERR_IRQn = 286, + IEBBTSTA_IRQn = 287, + IEBBTV_IRQn = 288, + + ISY_IRQn = 289, + IERR_IRQn = 290, + ITARG_IRQn = 291, + ISEC_IRQn = 292, + IBUF_IRQn = 293, + IREADY_IRQn = 294, + + STERB_IRQn = 295, + FLTENDI_IRQn = 296, + FLTREQ0I_IRQn = 297, + FLTREQ1I_IRQn = 298, + + MMC0_IRQn = 299, + MMC1_IRQn = 300, + MMC2_IRQn = 301, + + SCHI0_3_IRQn = 302, + SDHI0_0_IRQn = 303, + SDHI0_1_IRQn = 304, + SCHI1_3_IRQn = 305, + SDHI1_0_IRQn = 306, + SDHI1_1_IRQn = 307, + + ARM_IRQn = 308, + PRD_IRQn = 309, + CUP_IRQn = 310, + + SCUAI0_IRQn = 311, + SCUAI1_IRQn = 312, + SCUFDI0_IRQn = 313, + SCUFDI1_IRQn = 314, + SCUFDI2_IRQn = 315, + SCUFDI3_IRQn = 316, + SCUFUI0_IRQn = 317, + SCUFUI1_IRQn = 318, + SCUFUI2_IRQn = 319, + SCUFUI3_IRQn = 320, + SCUDVI0_IRQn = 321, + SCUDVI1_IRQn = 322, + SCUDVI2_IRQn = 323, + SCUDVI3_IRQn = 324, + + MLB_CINT_IRQn = 325, + MLB_SINT_IRQn = 326, + + DRC10_IRQn = 327, + DRC11_IRQn = 328, + + /* 329-330 Reserved */ + + LINI0_INT_T_IRQn = 331, + LINI0_INT_R_IRQn = 332, + LINI0_INT_S_IRQn = 333, + LINI0_INT_M_IRQn = 334, + LINI1_INT_T_IRQn = 335, + LINI1_INT_R_IRQn = 336, + LINI1_INT_S_IRQn = 337, + LINI1_INT_M_IRQn = 338, + + /* 339-346 Reserved */ + + SCIERI0_IRQn = 347, + SCIRXI0_IRQn = 348, + SCITXI0_IRQn = 349, + SCITEI0_IRQn = 350, + SCIERI1_IRQn = 351, + SCIRXI1_IRQn = 352, + SCITXI1_IRQn = 353, + SCITEI1_IRQn = 354, + + AVBI_DATA = 355, + AVBI_ERROR = 356, + AVBI_MANAGE = 357, + AVBI_MAC = 358, + + ETHERI_IRQn = 359, + + /* 360-363 Reserved */ + + CEUI_IRQn = 364, + + /* 365-380 Reserved */ + + H2XMLB_ERRINT_IRQn = 381, + H2XIC1_ERRINT_IRQn = 382, + X2HPERI1_ERRINT_IRQn = 383, + X2HPERR2_ERRINT_IRQn = 384, + X2HPERR34_ERRINT_IRQn= 385, + X2HPERR5_ERRINT_IRQn = 386, + X2HPERR67_ERRINT_IRQn= 387, + X2HDBGR_ERRINT_IRQn = 388, + X2HBSC_ERRINT_IRQn = 389, + X2HSPI1_ERRINT_IRQn = 390, + X2HSPI2_ERRINT_IRQn = 391, + PRRI_IRQn = 392, + + IFEI0_IRQn = 393, + OFFI0_IRQn = 394, + PFVEI0_IRQn = 395, + IFEI1_IRQn = 396, + OFFI1_IRQn = 397, + PFVEI1_IRQn = 398, + + /* 399-415 Reserved */ + + TINT0_IRQn = 416, + TINT1_IRQn = 417, + TINT2_IRQn = 418, + TINT3_IRQn = 419, + TINT4_IRQn = 420, + TINT5_IRQn = 421, + TINT6_IRQn = 422, + TINT7_IRQn = 423, + TINT8_IRQn = 424, + TINT9_IRQn = 425, + TINT10_IRQn = 426, + TINT11_IRQn = 427, + TINT12_IRQn = 428, + TINT13_IRQn = 429, + TINT14_IRQn = 430, + TINT15_IRQn = 431, + TINT16_IRQn = 432, + TINT17_IRQn = 433, + TINT18_IRQn = 434, + TINT19_IRQn = 435, + TINT20_IRQn = 436, + TINT21_IRQn = 437, + TINT22_IRQn = 438, + TINT23_IRQn = 439, + TINT24_IRQn = 440, + TINT25_IRQn = 441, + TINT26_IRQn = 442, + TINT27_IRQn = 443, + TINT28_IRQn = 444, + TINT29_IRQn = 445, + TINT30_IRQn = 446, + TINT31_IRQn = 447, + TINT32_IRQn = 448, + TINT33_IRQn = 449, + TINT34_IRQn = 450, + TINT35_IRQn = 451, + TINT36_IRQn = 452, + TINT37_IRQn = 453, + TINT38_IRQn = 454, + TINT39_IRQn = 455, + TINT40_IRQn = 456, + TINT41_IRQn = 457, + TINT42_IRQn = 458, + TINT43_IRQn = 459, + TINT44_IRQn = 460, + TINT45_IRQn = 461, + TINT46_IRQn = 462, + TINT47_IRQn = 463, + TINT48_IRQn = 464, + TINT49_IRQn = 465, + TINT50_IRQn = 466, + TINT51_IRQn = 467, + TINT52_IRQn = 468, + TINT53_IRQn = 469, + TINT54_IRQn = 470, + TINT55_IRQn = 471, + TINT56_IRQn = 472, + TINT57_IRQn = 473, + TINT58_IRQn = 474, + TINT59_IRQn = 475, + TINT60_IRQn = 476, + TINT61_IRQn = 477, + TINT62_IRQn = 478, + TINT63_IRQn = 479, + TINT64_IRQn = 480, + TINT65_IRQn = 481, + TINT66_IRQn = 482, + TINT67_IRQn = 483, + TINT68_IRQn = 484, + TINT69_IRQn = 485, + TINT70_IRQn = 486, + TINT71_IRQn = 487, + TINT72_IRQn = 488, + TINT73_IRQn = 489, + TINT74_IRQn = 490, + TINT75_IRQn = 491, + TINT76_IRQn = 492, + TINT77_IRQn = 493, + TINT78_IRQn = 494, + TINT79_IRQn = 495, + TINT80_IRQn = 496, + TINT81_IRQn = 497, + TINT82_IRQn = 498, + TINT83_IRQn = 499, + TINT84_IRQn = 500, + TINT85_IRQn = 501, + TINT86_IRQn = 502, + TINT87_IRQn = 503, + TINT88_IRQn = 504, + TINT89_IRQn = 505, + TINT90_IRQn = 506, + TINT91_IRQn = 507, + TINT92_IRQn = 508, + TINT93_IRQn = 509, + TINT94_IRQn = 510, + TINT95_IRQn = 511, + TINT96_IRQn = 512, + TINT97_IRQn = 513, + TINT98_IRQn = 514, + TINT99_IRQn = 515, + TINT100_IRQn = 516, + TINT101_IRQn = 517, + TINT102_IRQn = 518, + TINT103_IRQn = 519, + TINT104_IRQn = 520, + TINT105_IRQn = 521, + TINT106_IRQn = 522, + TINT107_IRQn = 523, + TINT108_IRQn = 524, + TINT109_IRQn = 525, + TINT110_IRQn = 526, + TINT111_IRQn = 527, + TINT112_IRQn = 528, + TINT113_IRQn = 529, + TINT114_IRQn = 530, + TINT115_IRQn = 531, + TINT116_IRQn = 532, + TINT117_IRQn = 533, + TINT118_IRQn = 534, + TINT119_IRQn = 535, + TINT120_IRQn = 536, + TINT121_IRQn = 537, + TINT122_IRQn = 538, + TINT123_IRQn = 539, + TINT124_IRQn = 540, + TINT125_IRQn = 541, + TINT126_IRQn = 542, + TINT127_IRQn = 543, + TINT128_IRQn = 544, + TINT129_IRQn = 545, + TINT130_IRQn = 546, + TINT131_IRQn = 547, + TINT132_IRQn = 548, + TINT133_IRQn = 549, + TINT134_IRQn = 550, + TINT135_IRQn = 551, + TINT136_IRQn = 552, + TINT137_IRQn = 553, + TINT138_IRQn = 554, + TINT139_IRQn = 555, + TINT140_IRQn = 556, + TINT141_IRQn = 557, + TINT142_IRQn = 558, + TINT143_IRQn = 559, + TINT144_IRQn = 560, + TINT145_IRQn = 561, + TINT146_IRQn = 562, + TINT147_IRQn = 563, + TINT148_IRQn = 564, + TINT149_IRQn = 565, + TINT150_IRQn = 566, + TINT151_IRQn = 567, + TINT152_IRQn = 568, + TINT153_IRQn = 569, + TINT154_IRQn = 570, + TINT155_IRQn = 571, + TINT156_IRQn = 572, + TINT157_IRQn = 573, + TINT158_IRQn = 574, + TINT159_IRQn = 575, + TINT160_IRQn = 576, + TINT161_IRQn = 577, + TINT162_IRQn = 578, + TINT163_IRQn = 579, + TINT164_IRQn = 580, + TINT165_IRQn = 581, + TINT166_IRQn = 582, + TINT167_IRQn = 583, + TINT168_IRQn = 584, + TINT169_IRQn = 585, + TINT170_IRQn = 586 + +} IRQn_Type; + +#define RZ_A1_IRQ_MAX TINT170_IRQn + +/******************************************************************************/ +/* Peripheral memory map */ +/******************************************************************************/ + +#define RZ_A1_NORFLASH_BASE0 (0x00000000UL) /*!< (FLASH0 ) Base Address */ +#define RZ_A1_NORFLASH_BASE1 (0x04000000UL) /*!< (FLASH1 ) Base Address */ +#define RZ_A1_SDRAM_BASE0 (0x08000000UL) /*!< (SDRAM0 ) Base Address */ +#define RZ_A1_SDRAM_BASE1 (0x0C000000UL) /*!< (SDRAM1 ) Base Address */ +#define RZ_A1_USER_AREA0 (0x10000000UL) /*!< (USER0 ) Base Address */ +#define RZ_A1_USER_AREA1 (0x14000000UL) /*!< (USER1 ) Base Address */ +#define RZ_A1_SPI_IO0 (0x18000000UL) /*!< (SPI_IO0 ) Base Address */ +#define RZ_A1_SPI_IO1 (0x1C000000UL) /*!< (SPI_IO1 ) Base Address */ +#define RZ_A1_ONCHIP_SRAM_BASE (0x20000000UL) /*!< (SRAM_OC ) Base Address */ +#define RZ_A1_SPI_MIO_BASE (0x3fe00000UL) /*!< (SPI_MIO ) Base Address */ +#define RZ_A1_BSC_BASE (0x3ff00000UL) /*!< (BSC ) Base Address */ +#define RZ_A1_PERIPH_BASE0 (0xe8000000UL) /*!< (PERIPH0 ) Base Address */ +#define RZ_A1_PERIPH_BASE1 (0xfcf00000UL) /*!< (PERIPH1 ) Base Address */ +#define RZ_A1_GIC_DISTRIBUTOR_BASE (0xe8201000UL) /*!< (GIC DIST ) Base Address */ +#define RZ_A1_GIC_INTERFACE_BASE (0xe8202000UL) /*!< (GIC CPU IF) Base Address */ +#define RZ_A1_PL310_BASE (0x3ffff000UL) /*!< (PL310 ) Base Address */ +#define RZ_A1_ONCHIP_SRAM_NC_BASE (0x60000000UL) /*!< (SRAM_OC ) Base Address */ +#define RZ_A1_PRIVATE_TIMER (0x00000600UL + 0x82000000UL) /*!< (PTIM ) Base Address */ +#define GIC_DISTRIBUTOR_BASE RZ_A1_GIC_DISTRIBUTOR_BASE +#define GIC_INTERFACE_BASE RZ_A1_GIC_INTERFACE_BASE +#define L2C_310_BASE RZ_A1_PL310_BASE +#define TIMER_BASE RZ_A1_PRIVATE_TIMER + +/* -------- Configuration of the Cortex-A9 Processor and Core Peripherals ------- */ +#define __CA_REV 0x0000U /*!< Core revision r0p0 */ +#define __CORTEX_A 9U /*!< Cortex-A9 Core */ +#if (__FPU_PRESENT != 1) +#undef __FPU_PRESENT +#define __FPU_PRESENT 1U /* FPU present */ +#endif +#define __GIC_PRESENT 1U /* GIC present */ +#define __TIM_PRESENT 0U /* TIM present */ +#define __L2C_PRESENT 1U /* L2C present */ + +#include "core_ca.h" +#include +#include "iodefine.h" + +/******************************************************************************/ +/* Clock Settings */ +/******************************************************************************/ +/* + * Clock Mode 0 settings + * SW1-4(MD_CLK):ON + * SW1-5(MD_CLKS):ON + * FRQCR=0x1035 + * CLKEN2 = 0b - unstable + * CLKEN[1:0]=01b - Output, Low, Low + * IFC[1:0] =00b - CPU clock is 1/1 PLL clock + * FRQCR2=0x0001 + * GFC[1:0] =01b - Graphic clock is 2/3 bus clock + */ +#define CM0_RENESAS_RZ_A1_CLKIN ( 13333333u) +#define CM0_RENESAS_RZ_A1_CLKO ( 66666666u) +#define CM0_RENESAS_RZ_A1_I_CLK (400000000u) +#define CM0_RENESAS_RZ_A1_G_CLK (266666666u) +#define CM0_RENESAS_RZ_A1_B_CLK (133333333u) +#define CM0_RENESAS_RZ_A1_P1_CLK ( 66666666u) +#define CM0_RENESAS_RZ_A1_P0_CLK ( 33333333u) + +/* + * Clock Mode 1 settings + * SW1-4(MD_CLK):OFF + * SW1-5(MD_CLKS):ON + * FRQCR=0x1335 + * CLKEN2 = 0b - unstable + * CLKEN[1:0]=01b - Output, Low, Low + * IFC[1:0] =11b - CPU clock is 1/3 PLL clock + * FRQCR2=0x0003 + * GFC[1:0] =11b - graphic clock is 1/3 bus clock + */ +#define CM1_RENESAS_RZ_A1_CLKIN ( 48000000u) +#define CM1_RENESAS_RZ_A1_CLKO ( 64000000u) +#define CM1_RENESAS_RZ_A1_I_CLK (384000000u) +#define CM1_RENESAS_RZ_A1_G_CLK (256000000u) +#define CM1_RENESAS_RZ_A1_B_CLK (128000000u) +#define CM1_RENESAS_RZ_A1_P1_CLK ( 64000000u) +#define CM1_RENESAS_RZ_A1_P0_CLK ( 32000000u) + +/******************************************************************************/ +/* CPG Settings */ +/******************************************************************************/ +#define CPG_FRQCR_SHIFT_CKOEN2 (14) +#define CPG_FRQCR_BIT_CKOEN2 (0x1 << CPG_FRQCR_SHIFT_CKOEN2) +#define CPG_FRQCR_SHIFT_CKOEN0 (12) +#define CPG_FRQCR_BITS_CKOEN0 (0x3 << CPG_FRQCR_SHIFT_CKOEN0) +#define CPG_FRQCR_SHIFT_IFC (8) +#define CPG_FRQCR_BITS_IFC (0x3 << CPG_FRQCR_SHIFT_IFC) + +#define CPG_FRQCR2_SHIFT_GFC (0) +#define CPG_FRQCR2_BITS_GFC (0x3 << CPG_FRQCR2_SHIFT_GFC) + + +#define CPG_STBCR1_BIT_STBY (0x80u) +#define CPG_STBCR1_BIT_DEEP (0x40u) +#define CPG_STBCR2_BIT_HIZ (0x80u) +#define CPG_STBCR2_BIT_MSTP20 (0x01u) /* CoreSight */ +#define CPG_STBCR3_BIT_MSTP37 (0x80u) /* IEBus */ +#define CPG_STBCR3_BIT_MSTP36 (0x40u) /* IrDA */ +#define CPG_STBCR3_BIT_MSTP35 (0x20u) /* LIN0 */ +#define CPG_STBCR3_BIT_MSTP34 (0x10u) /* LIN1 */ +#define CPG_STBCR3_BIT_MSTP33 (0x08u) /* Multi-Function Timer */ +#define CPG_STBCR3_BIT_MSTP32 (0x04u) /* CAN */ +#define CPG_STBCR3_BIT_MSTP31 (0x02u) /* A/D converter (analog voltage) */ +#define CPG_STBCR3_BIT_MSTP30 (0x01u) /* Motor Control PWM Timer */ +#define CPG_STBCR4_BIT_MSTP47 (0x80u) /* SCIF0 */ +#define CPG_STBCR4_BIT_MSTP46 (0x40u) /* SCIF1 */ +#define CPG_STBCR4_BIT_MSTP45 (0x20u) /* SCIF2 */ +#define CPG_STBCR4_BIT_MSTP44 (0x10u) /* SCIF3 */ +#define CPG_STBCR4_BIT_MSTP43 (0x08u) /* SCIF4 */ +#define CPG_STBCR4_BIT_MSTP42 (0x04u) /* SCIF5 */ +#define CPG_STBCR4_BIT_MSTP41 (0x02u) /* SCIF6 */ +#define CPG_STBCR4_BIT_MSTP40 (0x01u) /* SCIF7 */ +#define CPG_STBCR5_BIT_MSTP57 (0x80u) /* SCI0 */ +#define CPG_STBCR5_BIT_MSTP56 (0x40u) /* SCI1 */ +#define CPG_STBCR5_BIT_MSTP55 (0x20u) /* Sound Generator0 */ +#define CPG_STBCR5_BIT_MSTP54 (0x10u) /* Sound Generator1 */ +#define CPG_STBCR5_BIT_MSTP53 (0x08u) /* Sound Generator2 */ +#define CPG_STBCR5_BIT_MSTP52 (0x04u) /* Sound Generator3 */ +#define CPG_STBCR5_BIT_MSTP51 (0x02u) /* OSTM0 */ +#define CPG_STBCR5_BIT_MSTP50 (0x01u) /* OSTM1 */ +#define CPG_STBCR6_BIT_MSTP67 (0x80u) /* A/D converter (clock) */ +#define CPG_STBCR6_BIT_MSTP66 (0x40u) /* Capture Engine */ +#define CPG_STBCR6_BIT_MSTP65 (0x20u) /* Display out comparison0 */ +#define CPG_STBCR6_BIT_MSTP64 (0x10u) /* Display out comparison1 */ +#define CPG_STBCR6_BIT_MSTP63 (0x08u) /* Dynamic Range compression0 */ +#define CPG_STBCR6_BIT_MSTP62 (0x04u) /* Dynamic Range compression1 */ +#define CPG_STBCR6_BIT_MSTP61 (0x02u) /* JPEG Decoder */ +#define CPG_STBCR6_BIT_MSTP60 (0x01u) /* Realtime Clock */ +#define CPG_STBCR7_BIT_MSTP77 (0x80u) /* Video Decoder0 */ +#define CPG_STBCR7_BIT_MSTP76 (0x40u) /* Video Decoder1 */ +#define CPG_STBCR7_BIT_MSTP74 (0x10u) /* Ethernet */ +#define CPG_STBCR7_BIT_MSTP73 (0x04u) /* NAND Flash Memory Controller */ +#define CPG_STBCR7_BIT_MSTP71 (0x02u) /* USB0 */ +#define CPG_STBCR7_BIT_MSTP70 (0x01u) /* USB1 */ +#define CPG_STBCR8_BIT_MSTP87 (0x80u) /* IMR-LS2_0 */ +#define CPG_STBCR8_BIT_MSTP86 (0x40u) /* IMR-LS2_1 */ +#define CPG_STBCR8_BIT_MSTP85 (0x20u) /* IMR-LSD */ +#define CPG_STBCR8_BIT_MSTP84 (0x10u) /* MMC Host Interface */ +#define CPG_STBCR8_BIT_MSTP83 (0x08u) /* MediaLB */ +#define CPG_STBCR8_BIT_MSTP82 (0x04u) /* EthernetAVB */ +#define CPG_STBCR8_BIT_MSTP81 (0x02u) /* SCUX */ +#define CPG_STBCR9_BIT_MSTP97 (0x80u) /* RIIC0 */ +#define CPG_STBCR9_BIT_MSTP96 (0x40u) /* RIIC1 */ +#define CPG_STBCR9_BIT_MSTP95 (0x20u) /* RIIC2 */ +#define CPG_STBCR9_BIT_MSTP94 (0x10u) /* RIIC3 */ +#define CPG_STBCR9_BIT_MSTP93 (0x08u) /* SPI Multi I/O Bus Controller0 */ +#define CPG_STBCR9_BIT_MSTP92 (0x04u) /* SPI Multi I/O Bus Controller1 */ +#define CPG_STBCR9_BIT_MSTP91 (0x02u) /* VDC5_0 */ +#define CPG_STBCR9_BIT_MSTP90 (0x01u) /* VDC5_1 */ +#define CPG_STBCR10_BIT_MSTP107 (0x80u) /* RSPI0 */ +#define CPG_STBCR10_BIT_MSTP106 (0x40u) /* RSPI1 */ +#define CPG_STBCR10_BIT_MSTP105 (0x20u) /* RSPI2 */ +#define CPG_STBCR10_BIT_MSTP104 (0x10u) /* RSPI3 */ +#define CPG_STBCR10_BIT_MSTP103 (0x08u) /* RSPI4 */ +#define CPG_STBCR10_BIT_MSTP102 (0x04u) /* ROMDEC */ +#define CPG_STBCR10_BIT_MSTP101 (0x02u) /* SPIDF */ +#define CPG_STBCR10_BIT_MSTP100 (0x01u) /* OpenVG */ +#define CPG_STBCR11_BIT_MSTP115 (0x20u) /* SSIF0 */ +#define CPG_STBCR11_BIT_MSTP114 (0x10u) /* SSIF1 */ +#define CPG_STBCR11_BIT_MSTP113 (0x08u) /* SSIF2 */ +#define CPG_STBCR11_BIT_MSTP112 (0x04u) /* SSIF3 */ +#define CPG_STBCR11_BIT_MSTP111 (0x02u) /* SSIF4 */ +#define CPG_STBCR11_BIT_MSTP110 (0x01u) /* SSIF5 */ +#define CPG_STBCR12_BIT_MSTP123 (0x08u) /* SD Host Interface00 */ +#define CPG_STBCR12_BIT_MSTP122 (0x04u) /* SD Host Interface01 */ +#define CPG_STBCR12_BIT_MSTP121 (0x02u) /* SD Host Interface10 */ +#define CPG_STBCR12_BIT_MSTP120 (0x01u) /* SD Host Interface11 */ +#define CPG_STBCR13_BIT_MSTP132 (0x04u) /* PFV1 */ +#define CPG_STBCR13_BIT_MSTP131 (0x02u) /* PFV0 */ +#define CPG_SWRSTCR1_BIT_AXTALE (0x80u) /* AUDIO_X1 */ +#define CPG_SWRSTCR1_BIT_SRST16 (0x40u) /* SSIF0 */ +#define CPG_SWRSTCR1_BIT_SRST15 (0x20u) /* SSIF1 */ +#define CPG_SWRSTCR1_BIT_SRST14 (0x10u) /* SSIF2 */ +#define CPG_SWRSTCR1_BIT_SRST13 (0x08u) /* SSIF3 */ +#define CPG_SWRSTCR1_BIT_SRST12 (0x04u) /* SSIF4 */ +#define CPG_SWRSTCR1_BIT_SRST11 (0x02u) /* SSIF5 */ +#define CPG_SWRSTCR2_BIT_SRST21 (0x02u) /* JPEG Decoder */ +#define CPG_SWRSTCR3_BIT_SRST32 (0x04u) /* OpenVG */ +#define CPG_SYSCR1_BIT_VRAME4 (0x10u) /* VRAM E Page4 */ +#define CPG_SYSCR1_BIT_VRAME3 (0x08u) /* VRAM E Page3 */ +#define CPG_SYSCR1_BIT_VRAME2 (0x04u) /* VRAM E Page2 */ +#define CPG_SYSCR1_BIT_VRAME1 (0x02u) /* VRAM E Page1 */ +#define CPG_SYSCR1_BIT_VRAME0 (0x01u) /* VRAM E Page0 */ +#define CPG_SYSCR2_BIT_VRAMWE4 (0x10u) /* VRAM WE Page4 */ +#define CPG_SYSCR2_BIT_VRAMWE3 (0x08u) /* VRAM WE Page3 */ +#define CPG_SYSCR2_BIT_VRAMWE2 (0x04u) /* VRAM WE Page2 */ +#define CPG_SYSCR2_BIT_VRAMWE1 (0x02u) /* VRAM WE Page1 */ +#define CPG_SYSCR2_BIT_VRAMWE0 (0x01u) /* VRAM WE Page0 */ +#define CPG_SYSCR3_BIT_RRAMWE3 (0x08u) /* RRAM WE Page3 */ +#define CPG_SYSCR3_BIT_RRAMWE2 (0x04u) /* RRAM WE Page2 */ +#define CPG_SYSCR3_BIT_RRAMWE1 (0x02u) /* RRAM WE Page1 */ +#define CPG_SYSCR3_BIT_RRAMWE0 (0x01u) /* RRAM WE Page0 */ +#define CPG_CPUSTS_BIT_ISBUSY (0x10u) /* State during Changing of the Frequency of CPU and Return from Software Standby */ +#define CPG_STBREQ1_BIT_STBRQ15 (0x20u) /* CoreSight */ +#define CPG_STBREQ1_BIT_STBRQ13 (0x08u) /* JPEG Control */ +#define CPG_STBREQ1_BIT_STBRQ12 (0x04u) /* EthernetAVB */ +#define CPG_STBREQ1_BIT_STBRQ10 (0x01u) /* Capture Engine */ +#define CPG_STBREQ2_BIT_STBRQ27 (0x80u) /* MediaLB */ +#define CPG_STBREQ2_BIT_STBRQ26 (0x40u) /* Ethernet */ +#define CPG_STBREQ2_BIT_STBRQ25 (0x20u) /* VDC5_0 */ +#define CPG_STBREQ2_BIT_STBRQ24 (0x10u) /* VCD5_1 */ +#define CPG_STBREQ2_BIT_STBRQ23 (0x08u) /* IMR_LS2_0 */ +#define CPG_STBREQ2_BIT_STBRQ22 (0x04u) /* IMR_LS2_1 */ +#define CPG_STBREQ2_BIT_STBRQ21 (0x02u) /* IMR_LSD */ +#define CPG_STBREQ2_BIT_STBRQ20 (0x01u) /* OpenVG */ +#define CPG_STBACK1_BIT_STBAK15 (0x20u) /* CoreSight */ +#define CPG_STBACK1_BIT_STBAK13 (0x08u) /* JPEG Control */ +#define CPG_STBACK1_BIT_STBAK12 (0x04u) /* EthernetAVB */ +#define CPG_STBACK1_BIT_STBAK10 (0x01u) /* Capture Engine */ +#define CPG_STBACK2_BIT_STBAK27 (0x80u) /* MediaLB */ +#define CPG_STBACK2_BIT_STBAK26 (0x40u) /* Ethernet */ +#define CPG_STBACK2_BIT_STBAK25 (0x20u) /* VDC5_0 */ +#define CPG_STBACK2_BIT_STBAK24 (0x10u) /* VCD5_1 */ +#define CPG_STBACK2_BIT_STBAK23 (0x08u) /* IMR_LS2_0 */ +#define CPG_STBACK2_BIT_STBAK22 (0x04u) /* IMR_LS2_1 */ +#define CPG_STBACK2_BIT_STBAK21 (0x02u) /* IMR_LSD */ +#define CPG_STBACK2_BIT_STBAK20 (0x01u) /* OpenVG */ +#define CPG_RRAMKP_BIT_RRAMKP3 (0x08u) /* RRAM KP Page3 */ +#define CPG_RRAMKP_BIT_RRAMKP2 (0x04u) /* RRAM KP Page2 */ +#define CPG_RRAMKP_BIT_RRAMKP1 (0x02u) /* RRAM KP Page1 */ +#define CPG_RRAMKP_BIT_RRAMKP0 (0x01u) /* RRAM KP Page0 */ +#define CPG_DSCTR_BIT_EBUSKEEPE (0x80u) /* Retention of External Memory Control Pin State */ +#define CPG_DSCTR_BIT_RAMBOOT (0x40u) /* Selection of Method after Returning from Deep Standby Mode */ +#define CPG_DSSSR_BIT_P6_2 (0x4000u) /* P6_2 */ +#define CPG_DSSSR_BIT_P3_9 (0x2000u) /* P3_9 */ +#define CPG_DSSSR_BIT_P3_1 (0x1000u) /* P3_1 */ +#define CPG_DSSSR_BIT_P2_12 (0x0800u) /* P2_12 */ +#define CPG_DSSSR_BIT_P8_7 (0x0400u) /* P8_7 */ +#define CPG_DSSSR_BIT_P3_3 (0x0200u) /* P3_3 */ +#define CPG_DSSSR_BIT_NMI (0x0100u) /* NMI */ +#define CPG_DSSSR_BIT_RTCAR (0x0040u) /* RTCAR */ +#define CPG_DSSSR_BIT_P6_4 (0x0020u) /* P6_4 */ +#define CPG_DSSSR_BIT_P5_9 (0x0010u) /* P5_9 */ +#define CPG_DSSSR_BIT_P7_8 (0x0008u) /* P7_8 */ +#define CPG_DSSSR_BIT_P2_15 (0x0004u) /* P2_15 */ +#define CPG_DSSSR_BIT_P9_1 (0x0002u) /* P9_1 */ +#define CPG_DSSSR_BIT_P8_2 (0x0001u) /* P8_2 */ +#define CPG_DSESR_BIT_P6_2E (0x4000u) /* P6_2 */ +#define CPG_DSESR_BIT_P3_9E (0x2000u) /* P3_9 */ +#define CPG_DSESR_BIT_P3_1E (0x1000u) /* P3_1 */ +#define CPG_DSESR_BIT_P2_12E (0x0800u) /* P2_12 */ +#define CPG_DSESR_BIT_P8_7E (0x0400u) /* P8_7 */ +#define CPG_DSESR_BIT_P3_3E (0x0200u) /* P3_3 */ +#define CPG_DSESR_BIT_NMIE (0x0100u) /* NMI */ +#define CPG_DSESR_BIT_P6_4E (0x0020u) /* P6_4 */ +#define CPG_DSESR_BIT_P5_9E (0x0010u) /* P5_9 */ +#define CPG_DSESR_BIT_P7_8E (0x0008u) /* P7_8 */ +#define CPG_DSESR_BIT_P2_15E (0x0004u) /* P2_15 */ +#define CPG_DSESR_BIT_P9_1E (0x0002u) /* P9_1 */ +#define CPG_DSESR_BIT_P8_2E (0x0001u) /* P8_2 */ +#define CPG_DSFR_BIT_IOKEEP (0x8000u) /* Release of Pin State Retention */ +#define CPG_DSFR_BIT_P6_2F (0x4000u) /* P6_2 */ +#define CPG_DSFR_BIT_P3_9F (0x2000u) /* P3_9 */ +#define CPG_DSFR_BIT_P3_1F (0x1000u) /* P3_1 */ +#define CPG_DSFR_BIT_P2_12F (0x0800u) /* P2_12 */ +#define CPG_DSFR_BIT_P8_7F (0x0400u) /* P8_7 */ +#define CPG_DSFR_BIT_P3_3F (0x0200u) /* P3_3 */ +#define CPG_DSFR_BIT_NMIF (0x0100u) /* NMI */ +#define CPG_DSFR_BIT_RTCARF (0x0040u) /* RTCAR */ +#define CPG_DSFR_BIT_P6_4F (0x0020u) /* P6_4 */ +#define CPG_DSFR_BIT_P5_9F (0x0010u) /* P5_9 */ +#define CPG_DSFR_BIT_P7_8F (0x0008u) /* P7_8 */ +#define CPG_DSFR_BIT_P2_15F (0x0004u) /* P2_15 */ +#define CPG_DSFR_BIT_P9_1F (0x0002u) /* P9_1 */ +#define CPG_DSFR_BIT_P8_2F (0x0001u) /* P8_2 */ +#define CPG_XTALCTR_BIT_GAIN1 (0x02u) /* RTC_X3, RTC_X4 */ +#define CPG_XTALCTR_BIT_GAIN0 (0x01u) /* EXTAL, XTAL */ + +/******************************************************************************/ +/* GPIO Settings */ +/******************************************************************************/ +#define GPIO_BIT_N0 (1u << 0) +#define GPIO_BIT_N1 (1u << 1) +#define GPIO_BIT_N2 (1u << 2) +#define GPIO_BIT_N3 (1u << 3) +#define GPIO_BIT_N4 (1u << 4) +#define GPIO_BIT_N5 (1u << 5) +#define GPIO_BIT_N6 (1u << 6) +#define GPIO_BIT_N7 (1u << 7) +#define GPIO_BIT_N8 (1u << 8) +#define GPIO_BIT_N9 (1u << 9) +#define GPIO_BIT_N10 (1u << 10) +#define GPIO_BIT_N11 (1u << 11) +#define GPIO_BIT_N12 (1u << 12) +#define GPIO_BIT_N13 (1u << 13) +#define GPIO_BIT_N14 (1u << 14) +#define GPIO_BIT_N15 (1u << 15) + +#define MD_BOOT10_MASK (0x3) + +#define MD_BOOT10_BM0 (0x0) +#define MD_BOOT10_BM1 (0x2) +#define MD_BOOT10_BM3 (0x1) +#define MD_BOOT10_BM4_5 (0x3) + +#define MD_CLK (1u << 2) +#define MD_CLKS (1u << 3) + + +#ifdef __cplusplus +} +#endif + +#endif // __RZ_A1LU_H__ diff --git a/targets/TARGET_RENESAS/TARGET_RZ_A1XX/TARGET_GR_LYCHEE/device/inc/iobitmasks/bsc_iobitmask.h b/targets/TARGET_RENESAS/TARGET_RZ_A1XX/TARGET_GR_LYCHEE/device/inc/iobitmasks/bsc_iobitmask.h new file mode 100644 index 0000000..1f01629 --- /dev/null +++ b/targets/TARGET_RENESAS/TARGET_RZ_A1XX/TARGET_GR_LYCHEE/device/inc/iobitmasks/bsc_iobitmask.h @@ -0,0 +1,357 @@ +/******************************************************************************* +* DISCLAIMER +* This software is supplied by Renesas Electronics Corporation and is only +* intended for use with Renesas products. No other uses are authorized. This +* software is owned by Renesas Electronics Corporation and is protected under +* all applicable laws, including copyright laws. +* THIS SOFTWARE IS PROVIDED "AS IS" AND RENESAS MAKES NO WARRANTIES REGARDING +* THIS SOFTWARE, WHETHER EXPRESS, IMPLIED OR STATUTORY, INCLUDING BUT NOT +* LIMITED TO WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE +* AND NON-INFRINGEMENT. ALL SUCH WARRANTIES ARE EXPRESSLY DISCLAIMED. +* TO THE MAXIMUM EXTENT PERMITTED NOT PROHIBITED BY LAW, NEITHER RENESAS +* ELECTRONICS CORPORATION NOR ANY OF ITS AFFILIATED COMPANIES SHALL BE LIABLE +* FOR ANY DIRECT, INDIRECT, SPECIAL, INCIDENTAL OR CONSEQUENTIAL DAMAGES FOR +* ANY REASON RELATED TO THIS SOFTWARE, EVEN IF RENESAS OR ITS AFFILIATES HAVE +* BEEN ADVISED OF THE POSSIBILITY OF SUCH DAMAGES. +* Renesas reserves the right, without notice, to make changes to this software +* and to discontinue the availability of this software. By using this software, +* you agree to the additional terms and conditions found by accessing the +* following link: +* http://www.renesas.com/disclaimer +* Copyright (C) 2012 - 2014 Renesas Electronics Corporation. All rights reserved. +*******************************************************************************/ +/******************************************************************************* +* File Name : bsc_iobitmask.h +* $Rev: 1115 $ +* $Date:: 2014-07-09 15:35:02 +0900#$ +* Description : BSC register define header +*******************************************************************************/ +#ifndef BSC_IOBITMASK_H +#define BSC_IOBITMASK_H + + +/* ==== Mask values for IO registers ==== */ +#define BSC_CMNCR_HIZCNT (0x00000001uL) +#define BSC_CMNCR_HIZMEM (0x00000002uL) +#define BSC_CMNCR_DPRTY (0x00000600uL) +#define BSC_CMNCR_AL0 (0x01000000uL) +#define BSC_CMNCR_TL0 (0x10000000uL) + +#define BSC_CS0BCR_BSZ (0x00000600uL) +#define BSC_CS0BCR_TYPE (0x00007000uL) +#define BSC_CS0BCR_IWRRS (0x00070000uL) +#define BSC_CS0BCR_IWRRD (0x00380000uL) +#define BSC_CS0BCR_IWRWS (0x01C00000uL) +#define BSC_CS0BCR_IWRWD (0x0E000000uL) +#define BSC_CS0BCR_IWW (0x70000000uL) + +#define BSC_CS1BCR_BSZ (0x00000600uL) +#define BSC_CS1BCR_TYPE (0x00007000uL) +#define BSC_CS1BCR_IWRRS (0x00070000uL) +#define BSC_CS1BCR_IWRRD (0x00380000uL) +#define BSC_CS1BCR_IWRWS (0x01C00000uL) +#define BSC_CS1BCR_IWRWD (0x0E000000uL) +#define BSC_CS1BCR_IWW (0x70000000uL) + +#define BSC_CS2BCR_BSZ (0x00000600uL) +#define BSC_CS2BCR_TYPE (0x00007000uL) +#define BSC_CS2BCR_IWRRS (0x00070000uL) +#define BSC_CS2BCR_IWRRD (0x00380000uL) +#define BSC_CS2BCR_IWRWS (0x01C00000uL) +#define BSC_CS2BCR_IWRWD (0x0E000000uL) +#define BSC_CS2BCR_IWW (0x70000000uL) + +#define BSC_CS3BCR_BSZ (0x00000600uL) +#define BSC_CS3BCR_TYPE (0x00007000uL) +#define BSC_CS3BCR_IWRRS (0x00070000uL) +#define BSC_CS3BCR_IWRRD (0x00380000uL) +#define BSC_CS3BCR_IWRWS (0x01C00000uL) +#define BSC_CS3BCR_IWRWD (0x0E000000uL) +#define BSC_CS3BCR_IWW (0x70000000uL) + +#define BSC_CS4BCR_BSZ (0x00000600uL) +#define BSC_CS4BCR_TYPE (0x00007000uL) +#define BSC_CS4BCR_IWRRS (0x00070000uL) +#define BSC_CS4BCR_IWRRD (0x00380000uL) +#define BSC_CS4BCR_IWRWS (0x01C00000uL) +#define BSC_CS4BCR_IWRWD (0x0E000000uL) +#define BSC_CS4BCR_IWW (0x70000000uL) + +#define BSC_CS5BCR_BSZ (0x00000600uL) +#define BSC_CS5BCR_TYPE (0x00007000uL) +#define BSC_CS5BCR_IWRRS (0x00070000uL) +#define BSC_CS5BCR_IWRRD (0x00380000uL) +#define BSC_CS5BCR_IWRWS (0x01C00000uL) +#define BSC_CS5BCR_IWRWD (0x0E000000uL) +#define BSC_CS5BCR_IWW (0x70000000uL) + +#define BSC_CS0WCR_NORMAL_HW (0x00000003uL) +#define BSC_CS0WCR_NORMAL_WM (0x00000040uL) +#define BSC_CS0WCR_NORMAL_WR (0x00000780uL) +#define BSC_CS0WCR_NORMAL_SW (0x00001800uL) +#define BSC_CS0WCR_NORMAL_BAS (0x00100000uL) + +#define BSC_CS1WCR_NORMAL_HW (0x00000003uL) +#define BSC_CS1WCR_NORMAL_WM (0x00000040uL) +#define BSC_CS1WCR_NORMAL_WR (0x00000780uL) +#define BSC_CS1WCR_NORMAL_SW (0x00001800uL) +#define BSC_CS1WCR_NORMAL_WW (0x00070000uL) +#define BSC_CS1WCR_NORMAL_BAS (0x00100000uL) + +#define BSC_CS2WCR_NORMAL_WM (0x00000040uL) +#define BSC_CS2WCR_NORMAL_WR (0x00000780uL) +#define BSC_CS2WCR_NORMAL_BAS (0x00100000uL) + +#define BSC_CS3WCR_NORMAL_WM (0x00000040uL) +#define BSC_CS3WCR_NORMAL_WR (0x00000780uL) +#define BSC_CS3WCR_NORMAL_BAS (0x00100000uL) + +#define BSC_CS4WCR_NORMAL_HW (0x00000003uL) +#define BSC_CS4WCR_NORMAL_WM (0x00000040uL) +#define BSC_CS4WCR_NORMAL_WR (0x00000780uL) +#define BSC_CS4WCR_NORMAL_SW (0x00001800uL) +#define BSC_CS4WCR_NORMAL_WW (0x00070000uL) +#define BSC_CS4WCR_NORMAL_BAS (0x00100000uL) + +#define BSC_CS5WCR_NORMAL_HW (0x00000003uL) +#define BSC_CS5WCR_NORMAL_WM (0x00000040uL) +#define BSC_CS5WCR_NORMAL_WR (0x00000780uL) +#define BSC_CS5WCR_NORMAL_SW (0x00001800uL) +#define BSC_CS5WCR_NORMAL_WW (0x00070000uL) +#define BSC_CS5WCR_NORMAL_MPXWBAS (0x00100000uL) +#define BSC_CS5WCR_NORMAL_SZSEL (0x00200000uL) + +#define BSC_CS0WCR_BROM_ASY_WM (0x00000040uL) +#define BSC_CS0WCR_BROM_ASY_W (0x00000780uL) +#define BSC_CS0WCR_BROM_ASY_BW (0x00030000uL) +#define BSC_CS0WCR_BROM_ASY_BST (0x00300000uL) + +#define BSC_CS4WCR_BROM_ASY_HW (0x00000003uL) +#define BSC_CS4WCR_BROM_ASY_WM (0x00000040uL) +#define BSC_CS4WCR_BROM_ASY_W (0x00000780uL) +#define BSC_CS4WCR_BROM_ASY_SW (0x00001800uL) +#define BSC_CS4WCR_BROM_ASY_BW (0x00030000uL) +#define BSC_CS4WCR_BROM_ASY_BST (0x00300000uL) + +#define BSC_CS2WCR_SDRAM_A2CL (0x00000180uL) + +#define BSC_CS3WCR_SDRAM_WTRC (0x00000003uL) +#define BSC_CS3WCR_SDRAM_TRWL (0x00000018uL) +#define BSC_CS3WCR_SDRAM_A3CL (0x00000180uL) +#define BSC_CS3WCR_SDRAM_WTRCD (0x00000C00uL) +#define BSC_CS3WCR_SDRAM_WTRP (0x00006000uL) + +#define BSC_CS0WCR_BROM_SY_WM (0x00000040uL) +#define BSC_CS0WCR_BROM_SY_W (0x00000780uL) +#define BSC_CS0WCR_BROM_SY_BW (0x00030000uL) + +#define BSC_SDCR_A3COL (0x00000003uL) +#define BSC_SDCR_A3ROW (0x00000018uL) +#define BSC_SDCR_BACTV (0x00000100uL) +#define BSC_SDCR_PDOWN (0x00000200uL) +#define BSC_SDCR_RMODE (0x00000400uL) +#define BSC_SDCR_RFSH (0x00000800uL) +#define BSC_SDCR_DEEP (0x00002000uL) +#define BSC_SDCR_A2COL (0x00030000uL) +#define BSC_SDCR_A2ROW (0x00180000uL) + +#define BSC_RTCSR_RRC (0x00000007uL) +#define BSC_RTCSR_CKS (0x00000038uL) +#define BSC_RTCSR_CMIE (0x00000040uL) +#define BSC_RTCSR_CMF (0x00000080uL) + +#define BSC_RTCNT_D (0xFFFFFFFFuL) + +#define BSC_RTCOR_D (0xFFFFFFFFuL) + +#define BSC_TOSCOR0_D (0x0000FFFFuL) + +#define BSC_TOSCOR1_D (0x0000FFFFuL) + +#define BSC_TOSCOR2_D (0x0000FFFFuL) + +#define BSC_TOSCOR3_D (0x0000FFFFuL) + +#define BSC_TOSCOR4_D (0x0000FFFFuL) + +#define BSC_TOSCOR5_D (0x0000FFFFuL) + +#define BSC_TOSTR_CS0TOSTF (0x00000001uL) +#define BSC_TOSTR_CS1TOSTF (0x00000002uL) +#define BSC_TOSTR_CS2TOSTF (0x00000004uL) +#define BSC_TOSTR_CS3TOSTF (0x00000008uL) +#define BSC_TOSTR_CS4TOSTF (0x00000010uL) +#define BSC_TOSTR_CS5TOSTF (0x00000020uL) + +#define BSC_TOENR_CS0TOEN (0x00000001uL) +#define BSC_TOENR_CS1TOEN (0x00000002uL) +#define BSC_TOENR_CS2TOEN (0x00000004uL) +#define BSC_TOENR_CS3TOEN (0x00000008uL) +#define BSC_TOENR_CS4TOEN (0x00000010uL) +#define BSC_TOENR_CS5TOEN (0x00000020uL) + + +/* ==== Shift values for IO registers ==== */ +#define BSC_CMNCR_HIZCNT_SHIFT (0u) +#define BSC_CMNCR_HIZMEM_SHIFT (1u) +#define BSC_CMNCR_DPRTY_SHIFT (9u) +#define BSC_CMNCR_AL0_SHIFT (24u) +#define BSC_CMNCR_TL0_SHIFT (28u) + +#define BSC_CS0BCR_BSZ_SHIFT (9u) +#define BSC_CS0BCR_TYPE_SHIFT (12u) +#define BSC_CS0BCR_IWRRS_SHIFT (16u) +#define BSC_CS0BCR_IWRRD_SHIFT (19u) +#define BSC_CS0BCR_IWRWS_SHIFT (22u) +#define BSC_CS0BCR_IWRWD_SHIFT (25u) +#define BSC_CS0BCR_IWW_SHIFT (28u) + +#define BSC_CS1BCR_BSZ_SHIFT (9u) +#define BSC_CS1BCR_TYPE_SHIFT (12u) +#define BSC_CS1BCR_IWRRS_SHIFT (16u) +#define BSC_CS1BCR_IWRRD_SHIFT (19u) +#define BSC_CS1BCR_IWRWS_SHIFT (22u) +#define BSC_CS1BCR_IWRWD_SHIFT (25u) +#define BSC_CS1BCR_IWW_SHIFT (28u) + +#define BSC_CS2BCR_BSZ_SHIFT (9u) +#define BSC_CS2BCR_TYPE_SHIFT (12u) +#define BSC_CS2BCR_IWRRS_SHIFT (16u) +#define BSC_CS2BCR_IWRRD_SHIFT (19u) +#define BSC_CS2BCR_IWRWS_SHIFT (22u) +#define BSC_CS2BCR_IWRWD_SHIFT (25u) +#define BSC_CS2BCR_IWW_SHIFT (28u) + +#define BSC_CS3BCR_BSZ_SHIFT (9u) +#define BSC_CS3BCR_TYPE_SHIFT (12u) +#define BSC_CS3BCR_IWRRS_SHIFT (16u) +#define BSC_CS3BCR_IWRRD_SHIFT (19u) +#define BSC_CS3BCR_IWRWS_SHIFT (22u) +#define BSC_CS3BCR_IWRWD_SHIFT (25u) +#define BSC_CS3BCR_IWW_SHIFT (28u) + +#define BSC_CS4BCR_BSZ_SHIFT (9u) +#define BSC_CS4BCR_TYPE_SHIFT (12u) +#define BSC_CS4BCR_IWRRS_SHIFT (16u) +#define BSC_CS4BCR_IWRRD_SHIFT (19u) +#define BSC_CS4BCR_IWRWS_SHIFT (22u) +#define BSC_CS4BCR_IWRWD_SHIFT (25u) +#define BSC_CS4BCR_IWW_SHIFT (28u) + +#define BSC_CS5BCR_BSZ_SHIFT (9u) +#define BSC_CS5BCR_TYPE_SHIFT (12u) +#define BSC_CS5BCR_IWRRS_SHIFT (16u) +#define BSC_CS5BCR_IWRRD_SHIFT (19u) +#define BSC_CS5BCR_IWRWS_SHIFT (22u) +#define BSC_CS5BCR_IWRWD_SHIFT (25u) +#define BSC_CS5BCR_IWW_SHIFT (28u) + +#define BSC_CS0WCR_NORMAL_HW_SHIFT (0u) +#define BSC_CS0WCR_NORMAL_WM_SHIFT (6u) +#define BSC_CS0WCR_NORMAL_WR_SHIFT (7u) +#define BSC_CS0WCR_NORMAL_SW_SHIFT (11u) +#define BSC_CS0WCR_NORMAL_BAS_SHIFT (20u) + +#define BSC_CS1WCR_NORMAL_HW_SHIFT (0u) +#define BSC_CS1WCR_NORMAL_WM_SHIFT (6u) +#define BSC_CS1WCR_NORMAL_WR_SHIFT (7u) +#define BSC_CS1WCR_NORMAL_SW_SHIFT (11u) +#define BSC_CS1WCR_NORMAL_WW_SHIFT (16u) +#define BSC_CS1WCR_NORMAL_BAS_SHIFT (20u) + +#define BSC_CS2WCR_NORMAL_WM_SHIFT (6u) +#define BSC_CS2WCR_NORMAL_WR_SHIFT (7u) +#define BSC_CS2WCR_NORMAL_BAS_SHIFT (20u) + +#define BSC_CS3WCR_NORMAL_WM_SHIFT (6u) +#define BSC_CS3WCR_NORMAL_WR_SHIFT (7u) +#define BSC_CS3WCR_NORMAL_BAS_SHIFT (20u) + +#define BSC_CS4WCR_NORMAL_HW_SHIFT (0u) +#define BSC_CS4WCR_NORMAL_WM_SHIFT (6u) +#define BSC_CS4WCR_NORMAL_WR_SHIFT (7u) +#define BSC_CS4WCR_NORMAL_SW_SHIFT (11u) +#define BSC_CS4WCR_NORMAL_WW_SHIFT (16u) +#define BSC_CS4WCR_NORMAL_BAS_SHIFT (20u) + +#define BSC_CS5WCR_NORMAL_HW_SHIFT (0u) +#define BSC_CS5WCR_NORMAL_WM_SHIFT (6u) +#define BSC_CS5WCR_NORMAL_WR_SHIFT (7u) +#define BSC_CS5WCR_NORMAL_SW_SHIFT (11u) +#define BSC_CS5WCR_NORMAL_WW_SHIFT (16u) +#define BSC_CS5WCR_NORMAL_MPXWBAS_SHIFT (20u) +#define BSC_CS5WCR_NORMAL_SZSEL_SHIFT (21u) + +#define BSC_CS0WCR_BROM_ASY_WM_SHIFT (6u) +#define BSC_CS0WCR_BROM_ASY_W_SHIFT (7u) +#define BSC_CS0WCR_BROM_ASY_BW_SHIFT (16u) +#define BSC_CS0WCR_BROM_ASY_BST_SHIFT (20u) + +#define BSC_CS4WCR_BROM_ASY_HW_SHIFT (0u) +#define BSC_CS4WCR_BROM_ASY_WM_SHIFT (6u) +#define BSC_CS4WCR_BROM_ASY_W_SHIFT (7u) +#define BSC_CS4WCR_BROM_ASY_SW_SHIFT (11u) +#define BSC_CS4WCR_BROM_ASY_BW_SHIFT (16u) +#define BSC_CS4WCR_BROM_ASY_BST_SHIFT (20u) + +#define BSC_CS2WCR_SDRAM_A2CL_SHIFT (7u) + +#define BSC_CS3WCR_SDRAM_WTRC_SHIFT (0u) +#define BSC_CS3WCR_SDRAM_TRWL_SHIFT (3u) +#define BSC_CS3WCR_SDRAM_A3CL_SHIFT (7u) +#define BSC_CS3WCR_SDRAM_WTRCD_SHIFT (10u) +#define BSC_CS3WCR_SDRAM_WTRP_SHIFT (13u) + +#define BSC_CS0WCR_BROM_SY_WM_SHIFT (6u) +#define BSC_CS0WCR_BROM_SY_W_SHIFT (7u) +#define BSC_CS0WCR_BROM_SY_BW_SHIFT (16u) + +#define BSC_SDCR_A3COL_SHIFT (0u) +#define BSC_SDCR_A3ROW_SHIFT (3u) +#define BSC_SDCR_BACTV_SHIFT (8u) +#define BSC_SDCR_PDOWN_SHIFT (9u) +#define BSC_SDCR_RMODE_SHIFT (10u) +#define BSC_SDCR_RFSH_SHIFT (11u) +#define BSC_SDCR_DEEP_SHIFT (13u) +#define BSC_SDCR_A2COL_SHIFT (16u) +#define BSC_SDCR_A2ROW_SHIFT (19u) + +#define BSC_RTCSR_RRC_SHIFT (0u) +#define BSC_RTCSR_CKS_SHIFT (3u) +#define BSC_RTCSR_CMIE_SHIFT (6u) +#define BSC_RTCSR_CMF_SHIFT (7u) + +#define BSC_RTCNT_D_SHIFT (0u) + +#define BSC_RTCOR_D_SHIFT (0u) + +#define BSC_TOSCOR0_D_SHIFT (0u) + +#define BSC_TOSCOR1_D_SHIFT (0u) + +#define BSC_TOSCOR2_D_SHIFT (0u) + +#define BSC_TOSCOR3_D_SHIFT (0u) + +#define BSC_TOSCOR4_D_SHIFT (0u) + +#define BSC_TOSCOR5_D_SHIFT (0u) + +#define BSC_TOSTR_CS0TOSTF_SHIFT (0u) +#define BSC_TOSTR_CS1TOSTF_SHIFT (1u) +#define BSC_TOSTR_CS2TOSTF_SHIFT (2u) +#define BSC_TOSTR_CS3TOSTF_SHIFT (3u) +#define BSC_TOSTR_CS4TOSTF_SHIFT (4u) +#define BSC_TOSTR_CS5TOSTF_SHIFT (5u) + +#define BSC_TOENR_CS0TOEN_SHIFT (0u) +#define BSC_TOENR_CS1TOEN_SHIFT (1u) +#define BSC_TOENR_CS2TOEN_SHIFT (2u) +#define BSC_TOENR_CS3TOEN_SHIFT (3u) +#define BSC_TOENR_CS4TOEN_SHIFT (4u) +#define BSC_TOENR_CS5TOEN_SHIFT (5u) + + +#endif /* BSC_IOBITMASK_H */ + +/* End of File */ diff --git a/targets/TARGET_RENESAS/TARGET_RZ_A1XX/TARGET_GR_LYCHEE/device/inc/iobitmasks/cpg_iobitmask.h b/targets/TARGET_RENESAS/TARGET_RZ_A1XX/TARGET_GR_LYCHEE/device/inc/iobitmasks/cpg_iobitmask.h new file mode 100644 index 0000000..d1a7717 --- /dev/null +++ b/targets/TARGET_RENESAS/TARGET_RZ_A1XX/TARGET_GR_LYCHEE/device/inc/iobitmasks/cpg_iobitmask.h @@ -0,0 +1,461 @@ +/******************************************************************************* +* DISCLAIMER +* This software is supplied by Renesas Electronics Corporation and is only +* intended for use with Renesas products. No other uses are authorized. This +* software is owned by Renesas Electronics Corporation and is protected under +* all applicable laws, including copyright laws. +* THIS SOFTWARE IS PROVIDED "AS IS" AND RENESAS MAKES NO WARRANTIES REGARDING +* THIS SOFTWARE, WHETHER EXPRESS, IMPLIED OR STATUTORY, INCLUDING BUT NOT +* LIMITED TO WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE +* AND NON-INFRINGEMENT. ALL SUCH WARRANTIES ARE EXPRESSLY DISCLAIMED. +* TO THE MAXIMUM EXTENT PERMITTED NOT PROHIBITED BY LAW, NEITHER RENESAS +* ELECTRONICS CORPORATION NOR ANY OF ITS AFFILIATED COMPANIES SHALL BE LIABLE +* FOR ANY DIRECT, INDIRECT, SPECIAL, INCIDENTAL OR CONSEQUENTIAL DAMAGES FOR +* ANY REASON RELATED TO THIS SOFTWARE, EVEN IF RENESAS OR ITS AFFILIATES HAVE +* BEEN ADVISED OF THE POSSIBILITY OF SUCH DAMAGES. +* Renesas reserves the right, without notice, to make changes to this software +* and to discontinue the availability of this software. By using this software, +* you agree to the additional terms and conditions found by accessing the +* following link: +* http://www.renesas.com/disclaimer +* Copyright (C) 2012 - 2014 Renesas Electronics Corporation. All rights reserved. +*******************************************************************************/ +/******************************************************************************* +* File Name : cpg_iobitmask.h +* $Rev: 1115 $ +* $Date:: 2014-07-09 15:35:02 +0900#$ +* Description : CPG register define header +*******************************************************************************/ +#ifndef CPG_IOBITMASK_H +#define CPG_IOBITMASK_H + + +/* ==== Mask values for IO registers ==== */ +#define CPG_FRQCR_IFC (0x0300u) +#define CPG_FRQCR_CKOEN (0x3000u) +#define CPG_FRQCR_CKOEN2 (0x4000u) + +#define CPG_FRQCR2_GFC (0x0003u) + +#define CPG_CPUSTS_ISBUSY (0x10u) + +#define CPG_STBCR1_DEEP (0x40u) +#define CPG_STBCR1_STBY (0x80u) + +#define CPG_STBCR2_MSTP20 (0x01u) +#define CPG_STBCR2_HIZ (0x80u) + +#define CPG_STBREQ1_STBRQ10 (0x01u) +#define CPG_STBREQ1_STBRQ12 (0x04u) +#define CPG_STBREQ1_STBRQ13 (0x08u) +#define CPG_STBREQ1_STBRQ15 (0x20u) + +#define CPG_STBREQ2_STBRQ20 (0x01u) +#define CPG_STBREQ2_STBRQ21 (0x02u) +#define CPG_STBREQ2_STBRQ22 (0x04u) +#define CPG_STBREQ2_STBRQ23 (0x08u) +#define CPG_STBREQ2_STBRQ24 (0x10u) +#define CPG_STBREQ2_STBRQ25 (0x20u) +#define CPG_STBREQ2_STBRQ26 (0x40u) +#define CPG_STBREQ2_STBRQ27 (0x80u) + +#define CPG_STBACK1_STBAK10 (0x01u) +#define CPG_STBACK1_STBAK12 (0x04u) +#define CPG_STBACK1_STBAK13 (0x08u) +#define CPG_STBACK1_STBAK15 (0x20u) + +#define CPG_STBACK2_STBAK20 (0x01u) +#define CPG_STBACK2_STBAK21 (0x02u) +#define CPG_STBACK2_STBAK22 (0x04u) +#define CPG_STBACK2_STBAK23 (0x08u) +#define CPG_STBACK2_STBAK24 (0x10u) +#define CPG_STBACK2_STBAK25 (0x20u) +#define CPG_STBACK2_STBAK26 (0x40u) +#define CPG_STBACK2_STBAK27 (0x80u) + +#define CPG_SYSCR1_VRAME0 (0x01u) +#define CPG_SYSCR1_VRAME1 (0x02u) +#define CPG_SYSCR1_VRAME2 (0x04u) +#define CPG_SYSCR1_VRAME3 (0x08u) +#define CPG_SYSCR1_VRAME4 (0x10u) + +#define CPG_SYSCR2_VRAMWE0 (0x01u) +#define CPG_SYSCR2_VRAMWE1 (0x02u) +#define CPG_SYSCR2_VRAMWE2 (0x04u) +#define CPG_SYSCR2_VRAMWE3 (0x08u) +#define CPG_SYSCR2_VRAMWE4 (0x10u) + +#define CPG_SYSCR3_RRAMWE0 (0x01u) +#define CPG_SYSCR3_RRAMWE1 (0x02u) +#define CPG_SYSCR3_RRAMWE2 (0x04u) +#define CPG_SYSCR3_RRAMWE3 (0x08u) + +#define CPG_STBCR3_MSTP30 (0x01u) +#define CPG_STBCR3_MSTP31 (0x02u) +#define CPG_STBCR3_MSTP32 (0x04u) +#define CPG_STBCR3_MSTP33 (0x08u) +#define CPG_STBCR3_MSTP34 (0x10u) +#define CPG_STBCR3_MSTP35 (0x20u) +#define CPG_STBCR3_MSTP36 (0x40u) +#define CPG_STBCR3_MSTP37 (0x80u) + +#define CPG_STBCR4_MSTP40 (0x01u) +#define CPG_STBCR4_MSTP41 (0x02u) +#define CPG_STBCR4_MSTP42 (0x04u) +#define CPG_STBCR4_MSTP43 (0x08u) +#define CPG_STBCR4_MSTP44 (0x10u) +#define CPG_STBCR4_MSTP45 (0x20u) +#define CPG_STBCR4_MSTP46 (0x40u) +#define CPG_STBCR4_MSTP47 (0x80u) + +#define CPG_STBCR5_MSTP50 (0x01u) +#define CPG_STBCR5_MSTP51 (0x02u) +#define CPG_STBCR5_MSTP52 (0x04u) +#define CPG_STBCR5_MSTP53 (0x08u) +#define CPG_STBCR5_MSTP54 (0x10u) +#define CPG_STBCR5_MSTP55 (0x20u) +#define CPG_STBCR5_MSTP56 (0x40u) +#define CPG_STBCR5_MSTP57 (0x80u) + +#define CPG_STBCR6_MSTP60 (0x01u) +#define CPG_STBCR6_MSTP61 (0x02u) +#define CPG_STBCR6_MSTP62 (0x04u) +#define CPG_STBCR6_MSTP63 (0x08u) +#define CPG_STBCR6_MSTP64 (0x10u) +#define CPG_STBCR6_MSTP65 (0x20u) +#define CPG_STBCR6_MSTP66 (0x40u) +#define CPG_STBCR6_MSTP67 (0x80u) + +#define CPG_STBCR7_MSTP70 (0x01u) +#define CPG_STBCR7_MSTP71 (0x02u) +#define CPG_STBCR7_MSTP73 (0x08u) +#define CPG_STBCR7_MSTP74 (0x10u) +#define CPG_STBCR7_MSTP76 (0x40u) +#define CPG_STBCR7_MSTP77 (0x80u) + +#define CPG_STBCR8_MSTP81 (0x02u) +#define CPG_STBCR8_MSTP82 (0x04u) +#define CPG_STBCR8_MSTP83 (0x08u) +#define CPG_STBCR8_MSTP84 (0x10u) +#define CPG_STBCR8_MSTP85 (0x20u) +#define CPG_STBCR8_MSTP86 (0x40u) +#define CPG_STBCR8_MSTP87 (0x80u) + +#define CPG_STBCR9_MSTP90 (0x01u) +#define CPG_STBCR9_MSTP91 (0x02u) +#define CPG_STBCR9_MSTP92 (0x04u) +#define CPG_STBCR9_MSTP93 (0x08u) +#define CPG_STBCR9_MSTP94 (0x10u) +#define CPG_STBCR9_MSTP95 (0x20u) +#define CPG_STBCR9_MSTP96 (0x40u) +#define CPG_STBCR9_MSTP97 (0x80u) + +#define CPG_STBCR10_MSTP100 (0x01u) +#define CPG_STBCR10_MSTP101 (0x02u) +#define CPG_STBCR10_MSTP102 (0x04u) +#define CPG_STBCR10_MSTP103 (0x08u) +#define CPG_STBCR10_MSTP104 (0x10u) +#define CPG_STBCR10_MSTP105 (0x20u) +#define CPG_STBCR10_MSTP106 (0x40u) +#define CPG_STBCR10_MSTP107 (0x80u) + +#define CPG_STBCR11_MSTP110 (0x01u) +#define CPG_STBCR11_MSTP111 (0x02u) +#define CPG_STBCR11_MSTP112 (0x04u) +#define CPG_STBCR11_MSTP113 (0x08u) +#define CPG_STBCR11_MSTP114 (0x10u) +#define CPG_STBCR11_MSTP115 (0x20u) + +#define CPG_STBCR12_MSTP120 (0x01u) +#define CPG_STBCR12_MSTP121 (0x02u) +#define CPG_STBCR12_MSTP122 (0x04u) +#define CPG_STBCR12_MSTP123 (0x08u) + +#define CPG_STBCR13_MSTP131 (0x02u) +#define CPG_STBCR13_MSTP132 (0x04u) + +#define CPG_SWRSTCR1_SRST11 (0x02u) +#define CPG_SWRSTCR1_SRST12 (0x04u) +#define CPG_SWRSTCR1_SRST13 (0x08u) +#define CPG_SWRSTCR1_SRST14 (0x10u) +#define CPG_SWRSTCR1_SRST15 (0x20u) +#define CPG_SWRSTCR1_SRST16 (0x40u) +#define CPG_SWRSTCR1_AXTALE (0x80u) + +#define CPG_SWRSTCR2_SRST21 (0x02u) + +#define CPG_SWRSTCR3_SRST32 (0x04u) + +#define CPG_RRAMKP_RRAMKP0 (0x01u) +#define CPG_RRAMKP_RRAMKP1 (0x02u) +#define CPG_RRAMKP_RRAMKP2 (0x04u) +#define CPG_RRAMKP_RRAMKP3 (0x08u) + +#define CPG_DSCTR_RAMBOOT (0x40u) +#define CPG_DSCTR_EBUSKEEPE (0x80u) + +#define CPG_DSSSR_P8_2 (0x0001u) +#define CPG_DSSSR_P9_1 (0x0002u) +#define CPG_DSSSR_P2_15 (0x0004u) +#define CPG_DSSSR_P7_8 (0x0008u) +#define CPG_DSSSR_P5_9 (0x0010u) +#define CPG_DSSSR_P6_4 (0x0020u) +#define CPG_DSSSR_RTCAR (0x0040u) +#define CPG_DSSSR_NMI (0x0100u) +#define CPG_DSSSR_P3_3 (0x0200u) +#define CPG_DSSSR_P8_7 (0x0400u) +#define CPG_DSSSR_P2_12 (0x0800u) +#define CPG_DSSSR_P3_1 (0x1000u) +#define CPG_DSSSR_P3_9 (0x2000u) +#define CPG_DSSSR_P6_2 (0x4000u) + +#define CPG_DSESR_P8_2E (0x0001u) +#define CPG_DSESR_P9_1E (0x0002u) +#define CPG_DSESR_P2_15E (0x0004u) +#define CPG_DSESR_P7_8E (0x0008u) +#define CPG_DSESR_P5_9E (0x0010u) +#define CPG_DSESR_P6_4E (0x0020u) +#define CPG_DSESR_NMIE (0x0100u) +#define CPG_DSESR_P3_3E (0x0200u) +#define CPG_DSESR_P8_7E (0x0400u) +#define CPG_DSESR_P2_12E (0x0800u) +#define CPG_DSESR_P3_1E (0x1000u) +#define CPG_DSESR_P3_9E (0x2000u) +#define CPG_DSESR_P6_2E (0x4000u) + +#define CPG_DSFR_P8_2F (0x0001u) +#define CPG_DSFR_P9_1F (0x0002u) +#define CPG_DSFR_P2_15F (0x0004u) +#define CPG_DSFR_P7_8F (0x0008u) +#define CPG_DSFR_P5_9F (0x0010u) +#define CPG_DSFR_P6_4F (0x0020u) +#define CPG_DSFR_RTCARF (0x0040u) +#define CPG_DSFR_NMIF (0x0100u) +#define CPG_DSFR_P3_3F (0x0200u) +#define CPG_DSFR_P8_7F (0x0400u) +#define CPG_DSFR_P2_12F (0x0800u) +#define CPG_DSFR_P3_1F (0x1000u) +#define CPG_DSFR_P3_9F (0x2000u) +#define CPG_DSFR_P6_2F (0x4000u) +#define CPG_DSFR_IOKEEP (0x8000u) + +#define CPG_XTALCTR_GAIN0 (0x01u) +#define CPG_XTALCTR_GAIN1 (0x02u) + + +/* ==== Shift values for IO registers ==== */ +#define CPG_FRQCR_IFC_SHIFT (8u) +#define CPG_FRQCR_CKOEN_SHIFT (12u) +#define CPG_FRQCR_CKOEN2_SHIFT (14u) + +#define CPG_FRQCR2_GFC_SHIFT (0u) + +#define CPG_CPUSTS_ISBUSY_SHIFT (4u) + +#define CPG_STBCR1_DEEP_SHIFT (6u) +#define CPG_STBCR1_STBY_SHIFT (7u) + +#define CPG_STBCR2_MSTP20_SHIFT (0u) +#define CPG_STBCR2_HIZ_SHIFT (7u) + +#define CPG_STBREQ1_STBRQ10_SHIFT (0u) +#define CPG_STBREQ1_STBRQ12_SHIFT (2u) +#define CPG_STBREQ1_STBRQ13_SHIFT (3u) +#define CPG_STBREQ1_STBRQ15_SHIFT (5u) + +#define CPG_STBREQ2_STBRQ20_SHIFT (0u) +#define CPG_STBREQ2_STBRQ21_SHIFT (1u) +#define CPG_STBREQ2_STBRQ22_SHIFT (2u) +#define CPG_STBREQ2_STBRQ23_SHIFT (3u) +#define CPG_STBREQ2_STBRQ24_SHIFT (4u) +#define CPG_STBREQ2_STBRQ25_SHIFT (5u) +#define CPG_STBREQ2_STBRQ26_SHIFT (6u) +#define CPG_STBREQ2_STBRQ27_SHIFT (7u) + +#define CPG_STBACK1_STBAK10_SHIFT (0u) +#define CPG_STBACK1_STBAK12_SHIFT (2u) +#define CPG_STBACK1_STBAK13_SHIFT (3u) +#define CPG_STBACK1_STBAK15_SHIFT (5u) + +#define CPG_STBACK2_STBAK20_SHIFT (0u) +#define CPG_STBACK2_STBAK21_SHIFT (1u) +#define CPG_STBACK2_STBAK22_SHIFT (2u) +#define CPG_STBACK2_STBAK23_SHIFT (3u) +#define CPG_STBACK2_STBAK24_SHIFT (4u) +#define CPG_STBACK2_STBAK25_SHIFT (5u) +#define CPG_STBACK2_STBAK26_SHIFT (6u) +#define CPG_STBACK2_STBAK27_SHIFT (7u) + +#define CPG_SYSCR1_VRAME0_SHIFT (0u) +#define CPG_SYSCR1_VRAME1_SHIFT (1u) +#define CPG_SYSCR1_VRAME2_SHIFT (2u) +#define CPG_SYSCR1_VRAME3_SHIFT (3u) +#define CPG_SYSCR1_VRAME4_SHIFT (4u) + +#define CPG_SYSCR2_VRAMWE0_SHIFT (0u) +#define CPG_SYSCR2_VRAMWE1_SHIFT (1u) +#define CPG_SYSCR2_VRAMWE2_SHIFT (2u) +#define CPG_SYSCR2_VRAMWE3_SHIFT (3u) +#define CPG_SYSCR2_VRAMWE4_SHIFT (4u) + +#define CPG_SYSCR3_RRAMWE0_SHIFT (0u) +#define CPG_SYSCR3_RRAMWE1_SHIFT (1u) +#define CPG_SYSCR3_RRAMWE2_SHIFT (2u) +#define CPG_SYSCR3_RRAMWE3_SHIFT (3u) + +#define CPG_STBCR3_MSTP30_SHIFT (0u) +#define CPG_STBCR3_MSTP31_SHIFT (1u) +#define CPG_STBCR3_MSTP32_SHIFT (2u) +#define CPG_STBCR3_MSTP33_SHIFT (3u) +#define CPG_STBCR3_MSTP34_SHIFT (4u) +#define CPG_STBCR3_MSTP35_SHIFT (5u) +#define CPG_STBCR3_MSTP36_SHIFT (6u) +#define CPG_STBCR3_MSTP37_SHIFT (7u) + +#define CPG_STBCR4_MSTP40_SHIFT (0u) +#define CPG_STBCR4_MSTP41_SHIFT (1u) +#define CPG_STBCR4_MSTP42_SHIFT (2u) +#define CPG_STBCR4_MSTP43_SHIFT (3u) +#define CPG_STBCR4_MSTP44_SHIFT (4u) +#define CPG_STBCR4_MSTP45_SHIFT (5u) +#define CPG_STBCR4_MSTP46_SHIFT (6u) +#define CPG_STBCR4_MSTP47_SHIFT (7u) + +#define CPG_STBCR5_MSTP50_SHIFT (0u) +#define CPG_STBCR5_MSTP51_SHIFT (1u) +#define CPG_STBCR5_MSTP52_SHIFT (2u) +#define CPG_STBCR5_MSTP53_SHIFT (3u) +#define CPG_STBCR5_MSTP54_SHIFT (4u) +#define CPG_STBCR5_MSTP55_SHIFT (5u) +#define CPG_STBCR5_MSTP56_SHIFT (6u) +#define CPG_STBCR5_MSTP57_SHIFT (7u) + +#define CPG_STBCR6_MSTP60_SHIFT (0u) +#define CPG_STBCR6_MSTP61_SHIFT (1u) +#define CPG_STBCR6_MSTP62_SHIFT (2u) +#define CPG_STBCR6_MSTP63_SHIFT (3u) +#define CPG_STBCR6_MSTP64_SHIFT (4u) +#define CPG_STBCR6_MSTP65_SHIFT (5u) +#define CPG_STBCR6_MSTP66_SHIFT (6u) +#define CPG_STBCR6_MSTP67_SHIFT (7u) + +#define CPG_STBCR7_MSTP70_SHIFT (0u) +#define CPG_STBCR7_MSTP71_SHIFT (1u) +#define CPG_STBCR7_MSTP73_SHIFT (3u) +#define CPG_STBCR7_MSTP74_SHIFT (4u) +#define CPG_STBCR7_MSTP76_SHIFT (6u) +#define CPG_STBCR7_MSTP77_SHIFT (7u) + +#define CPG_STBCR8_MSTP81_SHIFT (1u) +#define CPG_STBCR8_MSTP82_SHIFT (2u) +#define CPG_STBCR8_MSTP83_SHIFT (3u) +#define CPG_STBCR8_MSTP84_SHIFT (4u) +#define CPG_STBCR8_MSTP85_SHIFT (5u) +#define CPG_STBCR8_MSTP86_SHIFT (6u) +#define CPG_STBCR8_MSTP87_SHIFT (7u) + +#define CPG_STBCR9_MSTP90_SHIFT (0u) +#define CPG_STBCR9_MSTP91_SHIFT (1u) +#define CPG_STBCR9_MSTP92_SHIFT (2u) +#define CPG_STBCR9_MSTP93_SHIFT (3u) +#define CPG_STBCR9_MSTP94_SHIFT (4u) +#define CPG_STBCR9_MSTP95_SHIFT (5u) +#define CPG_STBCR9_MSTP96_SHIFT (6u) +#define CPG_STBCR9_MSTP97_SHIFT (7u) + +#define CPG_STBCR10_MSTP100_SHIFT (0u) +#define CPG_STBCR10_MSTP101_SHIFT (1u) +#define CPG_STBCR10_MSTP102_SHIFT (2u) +#define CPG_STBCR10_MSTP103_SHIFT (3u) +#define CPG_STBCR10_MSTP104_SHIFT (4u) +#define CPG_STBCR10_MSTP105_SHIFT (5u) +#define CPG_STBCR10_MSTP106_SHIFT (6u) +#define CPG_STBCR10_MSTP107_SHIFT (7u) + +#define CPG_STBCR11_MSTP110_SHIFT (0u) +#define CPG_STBCR11_MSTP111_SHIFT (1u) +#define CPG_STBCR11_MSTP112_SHIFT (2u) +#define CPG_STBCR11_MSTP113_SHIFT (3u) +#define CPG_STBCR11_MSTP114_SHIFT (4u) +#define CPG_STBCR11_MSTP115_SHIFT (5u) + +#define CPG_STBCR12_MSTP120_SHIFT (0u) +#define CPG_STBCR12_MSTP121_SHIFT (1u) +#define CPG_STBCR12_MSTP122_SHIFT (2u) +#define CPG_STBCR12_MSTP123_SHIFT (3u) + +#define CPG_STBCR13_MSTP131_SHIFT (1u) +#define CPG_STBCR13_MSTP132_SHIFT (2u) + +#define CPG_SWRSTCR1_SRST11_SHIFT (1u) +#define CPG_SWRSTCR1_SRST12_SHIFT (2u) +#define CPG_SWRSTCR1_SRST13_SHIFT (3u) +#define CPG_SWRSTCR1_SRST14_SHIFT (4u) +#define CPG_SWRSTCR1_SRST15_SHIFT (5u) +#define CPG_SWRSTCR1_SRST16_SHIFT (6u) +#define CPG_SWRSTCR1_AXTALE_SHIFT (7u) + +#define CPG_SWRSTCR2_SRST21_SHIFT (1u) + +#define CPG_SWRSTCR3_SRST32_SHIFT (2u) + +#define CPG_RRAMKP_RRAMKP0_SHIFT (0u) +#define CPG_RRAMKP_RRAMKP1_SHIFT (1u) +#define CPG_RRAMKP_RRAMKP2_SHIFT (2u) +#define CPG_RRAMKP_RRAMKP3_SHIFT (3u) + +#define CPG_DSCTR_RAMBOOT_SHIFT (6u) +#define CPG_DSCTR_EBUSKEEPE_SHIFT (7u) + +#define CPG_DSSSR_P8_2_SHIFT (0u) +#define CPG_DSSSR_P9_1_SHIFT (1u) +#define CPG_DSSSR_P2_15_SHIFT (2u) +#define CPG_DSSSR_P7_8_SHIFT (3u) +#define CPG_DSSSR_P5_9_SHIFT (4u) +#define CPG_DSSSR_P6_4_SHIFT (5u) +#define CPG_DSSSR_RTCAR_SHIFT (6u) +#define CPG_DSSSR_NMI_SHIFT (8u) +#define CPG_DSSSR_P3_3_SHIFT (9u) +#define CPG_DSSSR_P8_7_SHIFT (10u) +#define CPG_DSSSR_P2_12_SHIFT (11u) +#define CPG_DSSSR_P3_1_SHIFT (12u) +#define CPG_DSSSR_P3_9_SHIFT (13u) +#define CPG_DSSSR_P6_2_SHIFT (14u) + +#define CPG_DSESR_P8_2E_SHIFT (0u) +#define CPG_DSESR_P9_1E_SHIFT (1u) +#define CPG_DSESR_P2_15E_SHIFT (2u) +#define CPG_DSESR_P7_8E_SHIFT (3u) +#define CPG_DSESR_P5_9E_SHIFT (4u) +#define CPG_DSESR_P6_4E_SHIFT (5u) +#define CPG_DSESR_NMIE_SHIFT (8u) +#define CPG_DSESR_P3_3E_SHIFT (9u) +#define CPG_DSESR_P8_7E_SHIFT (10u) +#define CPG_DSESR_P2_12E_SHIFT (11u) +#define CPG_DSESR_P3_1E_SHIFT (12u) +#define CPG_DSESR_P3_9E_SHIFT (13u) +#define CPG_DSESR_P6_2E_SHIFT (14u) + +#define CPG_DSFR_P8_2F_SHIFT (0u) +#define CPG_DSFR_P9_1F_SHIFT (1u) +#define CPG_DSFR_P2_15F_SHIFT (2u) +#define CPG_DSFR_P7_8F_SHIFT (3u) +#define CPG_DSFR_P5_9F_SHIFT (4u) +#define CPG_DSFR_P6_4F_SHIFT (5u) +#define CPG_DSFR_RTCARF_SHIFT (6u) +#define CPG_DSFR_NMIF_SHIFT (8u) +#define CPG_DSFR_P3_3F_SHIFT (9u) +#define CPG_DSFR_P8_7F_SHIFT (10u) +#define CPG_DSFR_P2_12F_SHIFT (11u) +#define CPG_DSFR_P3_1F_SHIFT (12u) +#define CPG_DSFR_P3_9F_SHIFT (13u) +#define CPG_DSFR_P6_2F_SHIFT (14u) +#define CPG_DSFR_IOKEEP_SHIFT (15u) + +#define CPG_XTALCTR_GAIN0_SHIFT (0u) +#define CPG_XTALCTR_GAIN1_SHIFT (1u) + + +#endif /* CPG_IOBITMASK_H */ + +/* End of File */ diff --git a/targets/TARGET_RENESAS/TARGET_RZ_A1XX/TARGET_GR_LYCHEE/device/inc/iobitmasks/dmac_iobitmask.h b/targets/TARGET_RENESAS/TARGET_RZ_A1XX/TARGET_GR_LYCHEE/device/inc/iobitmasks/dmac_iobitmask.h new file mode 100644 index 0000000..559a060 --- /dev/null +++ b/targets/TARGET_RENESAS/TARGET_RZ_A1XX/TARGET_GR_LYCHEE/device/inc/iobitmasks/dmac_iobitmask.h @@ -0,0 +1,2675 @@ +/******************************************************************************* +* DISCLAIMER +* This software is supplied by Renesas Electronics Corporation and is only +* intended for use with Renesas products. No other uses are authorized. This +* software is owned by Renesas Electronics Corporation and is protected under +* all applicable laws, including copyright laws. +* THIS SOFTWARE IS PROVIDED "AS IS" AND RENESAS MAKES NO WARRANTIES REGARDING +* THIS SOFTWARE, WHETHER EXPRESS, IMPLIED OR STATUTORY, INCLUDING BUT NOT +* LIMITED TO WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE +* AND NON-INFRINGEMENT. ALL SUCH WARRANTIES ARE EXPRESSLY DISCLAIMED. +* TO THE MAXIMUM EXTENT PERMITTED NOT PROHIBITED BY LAW, NEITHER RENESAS +* ELECTRONICS CORPORATION NOR ANY OF ITS AFFILIATED COMPANIES SHALL BE LIABLE +* FOR ANY DIRECT, INDIRECT, SPECIAL, INCIDENTAL OR CONSEQUENTIAL DAMAGES FOR +* ANY REASON RELATED TO THIS SOFTWARE, EVEN IF RENESAS OR ITS AFFILIATES HAVE +* BEEN ADVISED OF THE POSSIBILITY OF SUCH DAMAGES. +* Renesas reserves the right, without notice, to make changes to this software +* and to discontinue the availability of this software. By using this software, +* you agree to the additional terms and conditions found by accessing the +* following link: +* http://www.renesas.com/disclaimer +* Copyright (C) 2012 - 2014 Renesas Electronics Corporation. All rights reserved. +*******************************************************************************/ +/******************************************************************************* +* File Name : dmac_iobitmask.h +* $Rev: 1114 $ +* $Date:: 2014-07-09 14:56:39 +0900#$ +* Description : DMAC register define header +*******************************************************************************/ +#ifndef DMAC_IOBITMASK_H +#define DMAC_IOBITMASK_H + + +/* ==== Mask values for IO registers ==== */ +/* ---- DMAC0 ---- */ +#define DMAC0_N0SA_n_SA (0xFFFFFFFFuL) + +#define DMAC0_N0DA_n_DA (0xFFFFFFFFuL) + +#define DMAC0_N0TB_n_TB (0xFFFFFFFFuL) + +#define DMAC0_N1SA_n_SA (0xFFFFFFFFuL) + +#define DMAC0_N1DA_n_DA (0xFFFFFFFFuL) + +#define DMAC0_N1TB_n_TB (0xFFFFFFFFuL) + +#define DMAC0_CRSA_n_CRSA (0xFFFFFFFFuL) + +#define DMAC0_CRDA_n_CRDA (0xFFFFFFFFuL) + +#define DMAC0_CRTB_n_CRTB (0xFFFFFFFFuL) + +#define DMAC0_CHSTAT_n_EN (0x00000001uL) +#define DMAC0_CHSTAT_n_RQST (0x00000002uL) +#define DMAC0_CHSTAT_n_TACT (0x00000004uL) +#define DMAC0_CHSTAT_n_SUS (0x00000008uL) +#define DMAC0_CHSTAT_n_ER (0x00000010uL) +#define DMAC0_CHSTAT_n_END (0x00000020uL) +#define DMAC0_CHSTAT_n_TC (0x00000040uL) +#define DMAC0_CHSTAT_n_SR (0x00000080uL) +#define DMAC0_CHSTAT_n_DL (0x00000100uL) +#define DMAC0_CHSTAT_n_DW (0x00000200uL) +#define DMAC0_CHSTAT_n_DER (0x00000400uL) +#define DMAC0_CHSTAT_n_MODE (0x00000800uL) +#define DMAC0_CHSTAT_n_INTMSK (0x00010000uL) + +#define DMAC0_CHCTRL_n_SETEN (0x00000001uL) +#define DMAC0_CHCTRL_n_CLREN (0x00000002uL) +#define DMAC0_CHCTRL_n_STG (0x00000004uL) +#define DMAC0_CHCTRL_n_SWRST (0x00000008uL) +#define DMAC0_CHCTRL_n_CLRRQ (0x00000010uL) +#define DMAC0_CHCTRL_n_CLREND (0x00000020uL) +#define DMAC0_CHCTRL_n_CLRTC (0x00000040uL) +#define DMAC0_CHCTRL_n_SETSUS (0x00000100uL) +#define DMAC0_CHCTRL_n_CLRSUS (0x00000200uL) +#define DMAC0_CHCTRL_n_SETINTMSK (0x00010000uL) +#define DMAC0_CHCTRL_n_CLRINTMSK (0x00020000uL) + +#define DMAC0_CHCFG_n_SEL (0x00000007uL) +#define DMAC0_CHCFG_n_REQD (0x00000008uL) +#define DMAC0_CHCFG_n_LOEN (0x00000010uL) +#define DMAC0_CHCFG_n_HIEN (0x00000020uL) +#define DMAC0_CHCFG_n_LVL (0x00000040uL) +#define DMAC0_CHCFG_n_AM (0x00000700uL) +#define DMAC0_CHCFG_n_SDS (0x0000F000uL) +#define DMAC0_CHCFG_n_DDS (0x000F0000uL) +#define DMAC0_CHCFG_n_SAD (0x00100000uL) +#define DMAC0_CHCFG_n_DAD (0x00200000uL) +#define DMAC0_CHCFG_n_TM (0x00400000uL) +#define DMAC0_CHCFG_n_DEM (0x01000000uL) +#define DMAC0_CHCFG_n_TCM (0x02000000uL) +#define DMAC0_CHCFG_n_SBE (0x08000000uL) +#define DMAC0_CHCFG_n_RSEL (0x10000000uL) +#define DMAC0_CHCFG_n_RSW (0x20000000uL) +#define DMAC0_CHCFG_n_REN (0x40000000uL) +#define DMAC0_CHCFG_n_DMS (0x80000000uL) + +#define DMAC0_CHITVL_n_ITVL (0x0000FFFFuL) + +#define DMAC0_CHEXT_n_SCA (0x000000F0uL) +#define DMAC0_CHEXT_n_DCA (0x0000F000uL) + +#define DMAC0_NXLA_n_NXLA (0xFFFFFFFFuL) + +#define DMAC0_CRLA_n_CRLA (0xFFFFFFFFuL) + +/* ---- DMAC1 ---- */ +#define DMAC1_N0SA_n_SA (0xFFFFFFFFuL) + +#define DMAC1_N0DA_n_DA (0xFFFFFFFFuL) + +#define DMAC1_N0TB_n_TB (0xFFFFFFFFuL) + +#define DMAC1_N1SA_n_SA (0xFFFFFFFFuL) + +#define DMAC1_N1DA_n_DA (0xFFFFFFFFuL) + +#define DMAC1_N1TB_n_TB (0xFFFFFFFFuL) + +#define DMAC1_CRSA_n_CRSA (0xFFFFFFFFuL) + +#define DMAC1_CRDA_n_CRDA (0xFFFFFFFFuL) + +#define DMAC1_CRTB_n_CRTB (0xFFFFFFFFuL) + +#define DMAC1_CHSTAT_n_EN (0x00000001uL) +#define DMAC1_CHSTAT_n_RQST (0x00000002uL) +#define DMAC1_CHSTAT_n_TACT (0x00000004uL) +#define DMAC1_CHSTAT_n_SUS (0x00000008uL) +#define DMAC1_CHSTAT_n_ER (0x00000010uL) +#define DMAC1_CHSTAT_n_END (0x00000020uL) +#define DMAC1_CHSTAT_n_TC (0x00000040uL) +#define DMAC1_CHSTAT_n_SR (0x00000080uL) +#define DMAC1_CHSTAT_n_DL (0x00000100uL) +#define DMAC1_CHSTAT_n_DW (0x00000200uL) +#define DMAC1_CHSTAT_n_DER (0x00000400uL) +#define DMAC1_CHSTAT_n_MODE (0x00000800uL) +#define DMAC1_CHSTAT_n_INTMSK (0x00010000uL) + +#define DMAC1_CHCTRL_n_SETEN (0x00000001uL) +#define DMAC1_CHCTRL_n_CLREN (0x00000002uL) +#define DMAC1_CHCTRL_n_STG (0x00000004uL) +#define DMAC1_CHCTRL_n_SWRST (0x00000008uL) +#define DMAC1_CHCTRL_n_CLRRQ (0x00000010uL) +#define DMAC1_CHCTRL_n_CLREND (0x00000020uL) +#define DMAC1_CHCTRL_n_CLRTC (0x00000040uL) +#define DMAC1_CHCTRL_n_SETSUS (0x00000100uL) +#define DMAC1_CHCTRL_n_CLRSUS (0x00000200uL) +#define DMAC1_CHCTRL_n_SETINTMSK (0x00010000uL) +#define DMAC1_CHCTRL_n_CLRINTMSK (0x00020000uL) + +#define DMAC1_CHCFG_n_SEL (0x00000007uL) +#define DMAC1_CHCFG_n_REQD (0x00000008uL) +#define DMAC1_CHCFG_n_LOEN (0x00000010uL) +#define DMAC1_CHCFG_n_HIEN (0x00000020uL) +#define DMAC1_CHCFG_n_LVL (0x00000040uL) +#define DMAC1_CHCFG_n_AM (0x00000700uL) +#define DMAC1_CHCFG_n_SDS (0x0000F000uL) +#define DMAC1_CHCFG_n_DDS (0x000F0000uL) +#define DMAC1_CHCFG_n_SAD (0x00100000uL) +#define DMAC1_CHCFG_n_DAD (0x00200000uL) +#define DMAC1_CHCFG_n_TM (0x00400000uL) +#define DMAC1_CHCFG_n_DEM (0x01000000uL) +#define DMAC1_CHCFG_n_TCM (0x02000000uL) +#define DMAC1_CHCFG_n_SBE (0x08000000uL) +#define DMAC1_CHCFG_n_RSEL (0x10000000uL) +#define DMAC1_CHCFG_n_RSW (0x20000000uL) +#define DMAC1_CHCFG_n_REN (0x40000000uL) +#define DMAC1_CHCFG_n_DMS (0x80000000uL) + +#define DMAC1_CHITVL_n_ITVL (0x0000FFFFuL) + +#define DMAC1_CHEXT_n_SCA (0x000000F0uL) +#define DMAC1_CHEXT_n_DCA (0x0000F000uL) + +#define DMAC1_NXLA_n_NXLA (0xFFFFFFFFuL) + +#define DMAC1_CRLA_n_CRLA (0xFFFFFFFFuL) + +/* ---- DMAC2 ---- */ +#define DMAC2_N0SA_n_SA (0xFFFFFFFFuL) + +#define DMAC2_N0DA_n_DA (0xFFFFFFFFuL) + +#define DMAC2_N0TB_n_TB (0xFFFFFFFFuL) + +#define DMAC2_N1SA_n_SA (0xFFFFFFFFuL) + +#define DMAC2_N1DA_n_DA (0xFFFFFFFFuL) + +#define DMAC2_N1TB_n_TB (0xFFFFFFFFuL) + +#define DMAC2_CRSA_n_CRSA (0xFFFFFFFFuL) + +#define DMAC2_CRDA_n_CRDA (0xFFFFFFFFuL) + +#define DMAC2_CRTB_n_CRTB (0xFFFFFFFFuL) + +#define DMAC2_CHSTAT_n_EN (0x00000001uL) +#define DMAC2_CHSTAT_n_RQST (0x00000002uL) +#define DMAC2_CHSTAT_n_TACT (0x00000004uL) +#define DMAC2_CHSTAT_n_SUS (0x00000008uL) +#define DMAC2_CHSTAT_n_ER (0x00000010uL) +#define DMAC2_CHSTAT_n_END (0x00000020uL) +#define DMAC2_CHSTAT_n_TC (0x00000040uL) +#define DMAC2_CHSTAT_n_SR (0x00000080uL) +#define DMAC2_CHSTAT_n_DL (0x00000100uL) +#define DMAC2_CHSTAT_n_DW (0x00000200uL) +#define DMAC2_CHSTAT_n_DER (0x00000400uL) +#define DMAC2_CHSTAT_n_MODE (0x00000800uL) +#define DMAC2_CHSTAT_n_INTMSK (0x00010000uL) + +#define DMAC2_CHCTRL_n_SETEN (0x00000001uL) +#define DMAC2_CHCTRL_n_CLREN (0x00000002uL) +#define DMAC2_CHCTRL_n_STG (0x00000004uL) +#define DMAC2_CHCTRL_n_SWRST (0x00000008uL) +#define DMAC2_CHCTRL_n_CLRRQ (0x00000010uL) +#define DMAC2_CHCTRL_n_CLREND (0x00000020uL) +#define DMAC2_CHCTRL_n_CLRTC (0x00000040uL) +#define DMAC2_CHCTRL_n_SETSUS (0x00000100uL) +#define DMAC2_CHCTRL_n_CLRSUS (0x00000200uL) +#define DMAC2_CHCTRL_n_SETINTMSK (0x00010000uL) +#define DMAC2_CHCTRL_n_CLRINTMSK (0x00020000uL) + +#define DMAC2_CHCFG_n_SEL (0x00000007uL) +#define DMAC2_CHCFG_n_REQD (0x00000008uL) +#define DMAC2_CHCFG_n_LOEN (0x00000010uL) +#define DMAC2_CHCFG_n_HIEN (0x00000020uL) +#define DMAC2_CHCFG_n_LVL (0x00000040uL) +#define DMAC2_CHCFG_n_AM (0x00000700uL) +#define DMAC2_CHCFG_n_SDS (0x0000F000uL) +#define DMAC2_CHCFG_n_DDS (0x000F0000uL) +#define DMAC2_CHCFG_n_SAD (0x00100000uL) +#define DMAC2_CHCFG_n_DAD (0x00200000uL) +#define DMAC2_CHCFG_n_TM (0x00400000uL) +#define DMAC2_CHCFG_n_DEM (0x01000000uL) +#define DMAC2_CHCFG_n_TCM (0x02000000uL) +#define DMAC2_CHCFG_n_SBE (0x08000000uL) +#define DMAC2_CHCFG_n_RSEL (0x10000000uL) +#define DMAC2_CHCFG_n_RSW (0x20000000uL) +#define DMAC2_CHCFG_n_REN (0x40000000uL) +#define DMAC2_CHCFG_n_DMS (0x80000000uL) + +#define DMAC2_CHITVL_n_ITVL (0x0000FFFFuL) + +#define DMAC2_CHEXT_n_SCA (0x000000F0uL) +#define DMAC2_CHEXT_n_DCA (0x0000F000uL) + +#define DMAC2_NXLA_n_NXLA (0xFFFFFFFFuL) + +#define DMAC2_CRLA_n_CRLA (0xFFFFFFFFuL) + +/* ---- DMAC3 ---- */ +#define DMAC3_N0SA_n_SA (0xFFFFFFFFuL) + +#define DMAC3_N0DA_n_DA (0xFFFFFFFFuL) + +#define DMAC3_N0TB_n_TB (0xFFFFFFFFuL) + +#define DMAC3_N1SA_n_SA (0xFFFFFFFFuL) + +#define DMAC3_N1DA_n_DA (0xFFFFFFFFuL) + +#define DMAC3_N1TB_n_TB (0xFFFFFFFFuL) + +#define DMAC3_CRSA_n_CRSA (0xFFFFFFFFuL) + +#define DMAC3_CRDA_n_CRDA (0xFFFFFFFFuL) + +#define DMAC3_CRTB_n_CRTB (0xFFFFFFFFuL) + +#define DMAC3_CHSTAT_n_EN (0x00000001uL) +#define DMAC3_CHSTAT_n_RQST (0x00000002uL) +#define DMAC3_CHSTAT_n_TACT (0x00000004uL) +#define DMAC3_CHSTAT_n_SUS (0x00000008uL) +#define DMAC3_CHSTAT_n_ER (0x00000010uL) +#define DMAC3_CHSTAT_n_END (0x00000020uL) +#define DMAC3_CHSTAT_n_TC (0x00000040uL) +#define DMAC3_CHSTAT_n_SR (0x00000080uL) +#define DMAC3_CHSTAT_n_DL (0x00000100uL) +#define DMAC3_CHSTAT_n_DW (0x00000200uL) +#define DMAC3_CHSTAT_n_DER (0x00000400uL) +#define DMAC3_CHSTAT_n_MODE (0x00000800uL) +#define DMAC3_CHSTAT_n_INTMSK (0x00010000uL) + +#define DMAC3_CHCTRL_n_SETEN (0x00000001uL) +#define DMAC3_CHCTRL_n_CLREN (0x00000002uL) +#define DMAC3_CHCTRL_n_STG (0x00000004uL) +#define DMAC3_CHCTRL_n_SWRST (0x00000008uL) +#define DMAC3_CHCTRL_n_CLRRQ (0x00000010uL) +#define DMAC3_CHCTRL_n_CLREND (0x00000020uL) +#define DMAC3_CHCTRL_n_CLRTC (0x00000040uL) +#define DMAC3_CHCTRL_n_SETSUS (0x00000100uL) +#define DMAC3_CHCTRL_n_CLRSUS (0x00000200uL) +#define DMAC3_CHCTRL_n_SETINTMSK (0x00010000uL) +#define DMAC3_CHCTRL_n_CLRINTMSK (0x00020000uL) + +#define DMAC3_CHCFG_n_SEL (0x00000007uL) +#define DMAC3_CHCFG_n_REQD (0x00000008uL) +#define DMAC3_CHCFG_n_LOEN (0x00000010uL) +#define DMAC3_CHCFG_n_HIEN (0x00000020uL) +#define DMAC3_CHCFG_n_LVL (0x00000040uL) +#define DMAC3_CHCFG_n_AM (0x00000700uL) +#define DMAC3_CHCFG_n_SDS (0x0000F000uL) +#define DMAC3_CHCFG_n_DDS (0x000F0000uL) +#define DMAC3_CHCFG_n_SAD (0x00100000uL) +#define DMAC3_CHCFG_n_DAD (0x00200000uL) +#define DMAC3_CHCFG_n_TM (0x00400000uL) +#define DMAC3_CHCFG_n_DEM (0x01000000uL) +#define DMAC3_CHCFG_n_TCM (0x02000000uL) +#define DMAC3_CHCFG_n_SBE (0x08000000uL) +#define DMAC3_CHCFG_n_RSEL (0x10000000uL) +#define DMAC3_CHCFG_n_RSW (0x20000000uL) +#define DMAC3_CHCFG_n_REN (0x40000000uL) +#define DMAC3_CHCFG_n_DMS (0x80000000uL) + +#define DMAC3_CHITVL_n_ITVL (0x0000FFFFuL) + +#define DMAC3_CHEXT_n_SCA (0x000000F0uL) +#define DMAC3_CHEXT_n_DCA (0x0000F000uL) + +#define DMAC3_NXLA_n_NXLA (0xFFFFFFFFuL) + +#define DMAC3_CRLA_n_CRLA (0xFFFFFFFFuL) + +/* ---- DMAC4 ---- */ +#define DMAC4_N0SA_n_SA (0xFFFFFFFFuL) + +#define DMAC4_N0DA_n_DA (0xFFFFFFFFuL) + +#define DMAC4_N0TB_n_TB (0xFFFFFFFFuL) + +#define DMAC4_N1SA_n_SA (0xFFFFFFFFuL) + +#define DMAC4_N1DA_n_DA (0xFFFFFFFFuL) + +#define DMAC4_N1TB_n_TB (0xFFFFFFFFuL) + +#define DMAC4_CRSA_n_CRSA (0xFFFFFFFFuL) + +#define DMAC4_CRDA_n_CRDA (0xFFFFFFFFuL) + +#define DMAC4_CRTB_n_CRTB (0xFFFFFFFFuL) + +#define DMAC4_CHSTAT_n_EN (0x00000001uL) +#define DMAC4_CHSTAT_n_RQST (0x00000002uL) +#define DMAC4_CHSTAT_n_TACT (0x00000004uL) +#define DMAC4_CHSTAT_n_SUS (0x00000008uL) +#define DMAC4_CHSTAT_n_ER (0x00000010uL) +#define DMAC4_CHSTAT_n_END (0x00000020uL) +#define DMAC4_CHSTAT_n_TC (0x00000040uL) +#define DMAC4_CHSTAT_n_SR (0x00000080uL) +#define DMAC4_CHSTAT_n_DL (0x00000100uL) +#define DMAC4_CHSTAT_n_DW (0x00000200uL) +#define DMAC4_CHSTAT_n_DER (0x00000400uL) +#define DMAC4_CHSTAT_n_MODE (0x00000800uL) +#define DMAC4_CHSTAT_n_INTMSK (0x00010000uL) + +#define DMAC4_CHCTRL_n_SETEN (0x00000001uL) +#define DMAC4_CHCTRL_n_CLREN (0x00000002uL) +#define DMAC4_CHCTRL_n_STG (0x00000004uL) +#define DMAC4_CHCTRL_n_SWRST (0x00000008uL) +#define DMAC4_CHCTRL_n_CLRRQ (0x00000010uL) +#define DMAC4_CHCTRL_n_CLREND (0x00000020uL) +#define DMAC4_CHCTRL_n_CLRTC (0x00000040uL) +#define DMAC4_CHCTRL_n_SETSUS (0x00000100uL) +#define DMAC4_CHCTRL_n_CLRSUS (0x00000200uL) +#define DMAC4_CHCTRL_n_SETINTMSK (0x00010000uL) +#define DMAC4_CHCTRL_n_CLRINTMSK (0x00020000uL) + +#define DMAC4_CHCFG_n_SEL (0x00000007uL) +#define DMAC4_CHCFG_n_REQD (0x00000008uL) +#define DMAC4_CHCFG_n_LOEN (0x00000010uL) +#define DMAC4_CHCFG_n_HIEN (0x00000020uL) +#define DMAC4_CHCFG_n_LVL (0x00000040uL) +#define DMAC4_CHCFG_n_AM (0x00000700uL) +#define DMAC4_CHCFG_n_SDS (0x0000F000uL) +#define DMAC4_CHCFG_n_DDS (0x000F0000uL) +#define DMAC4_CHCFG_n_SAD (0x00100000uL) +#define DMAC4_CHCFG_n_DAD (0x00200000uL) +#define DMAC4_CHCFG_n_TM (0x00400000uL) +#define DMAC4_CHCFG_n_DEM (0x01000000uL) +#define DMAC4_CHCFG_n_TCM (0x02000000uL) +#define DMAC4_CHCFG_n_SBE (0x08000000uL) +#define DMAC4_CHCFG_n_RSEL (0x10000000uL) +#define DMAC4_CHCFG_n_RSW (0x20000000uL) +#define DMAC4_CHCFG_n_REN (0x40000000uL) +#define DMAC4_CHCFG_n_DMS (0x80000000uL) + +#define DMAC4_CHITVL_n_ITVL (0x0000FFFFuL) + +#define DMAC4_CHEXT_n_SCA (0x000000F0uL) +#define DMAC4_CHEXT_n_DCA (0x0000F000uL) + +#define DMAC4_NXLA_n_NXLA (0xFFFFFFFFuL) + +#define DMAC4_CRLA_n_CRLA (0xFFFFFFFFuL) + +/* ---- DMAC5 ---- */ +#define DMAC5_N0SA_n_SA (0xFFFFFFFFuL) + +#define DMAC5_N0DA_n_DA (0xFFFFFFFFuL) + +#define DMAC5_N0TB_n_TB (0xFFFFFFFFuL) + +#define DMAC5_N1SA_n_SA (0xFFFFFFFFuL) + +#define DMAC5_N1DA_n_DA (0xFFFFFFFFuL) + +#define DMAC5_N1TB_n_TB (0xFFFFFFFFuL) + +#define DMAC5_CRSA_n_CRSA (0xFFFFFFFFuL) + +#define DMAC5_CRDA_n_CRDA (0xFFFFFFFFuL) + +#define DMAC5_CRTB_n_CRTB (0xFFFFFFFFuL) + +#define DMAC5_CHSTAT_n_EN (0x00000001uL) +#define DMAC5_CHSTAT_n_RQST (0x00000002uL) +#define DMAC5_CHSTAT_n_TACT (0x00000004uL) +#define DMAC5_CHSTAT_n_SUS (0x00000008uL) +#define DMAC5_CHSTAT_n_ER (0x00000010uL) +#define DMAC5_CHSTAT_n_END (0x00000020uL) +#define DMAC5_CHSTAT_n_TC (0x00000040uL) +#define DMAC5_CHSTAT_n_SR (0x00000080uL) +#define DMAC5_CHSTAT_n_DL (0x00000100uL) +#define DMAC5_CHSTAT_n_DW (0x00000200uL) +#define DMAC5_CHSTAT_n_DER (0x00000400uL) +#define DMAC5_CHSTAT_n_MODE (0x00000800uL) +#define DMAC5_CHSTAT_n_INTMSK (0x00010000uL) + +#define DMAC5_CHCTRL_n_SETEN (0x00000001uL) +#define DMAC5_CHCTRL_n_CLREN (0x00000002uL) +#define DMAC5_CHCTRL_n_STG (0x00000004uL) +#define DMAC5_CHCTRL_n_SWRST (0x00000008uL) +#define DMAC5_CHCTRL_n_CLRRQ (0x00000010uL) +#define DMAC5_CHCTRL_n_CLREND (0x00000020uL) +#define DMAC5_CHCTRL_n_CLRTC (0x00000040uL) +#define DMAC5_CHCTRL_n_SETSUS (0x00000100uL) +#define DMAC5_CHCTRL_n_CLRSUS (0x00000200uL) +#define DMAC5_CHCTRL_n_SETINTMSK (0x00010000uL) +#define DMAC5_CHCTRL_n_CLRINTMSK (0x00020000uL) + +#define DMAC5_CHCFG_n_SEL (0x00000007uL) +#define DMAC5_CHCFG_n_REQD (0x00000008uL) +#define DMAC5_CHCFG_n_LOEN (0x00000010uL) +#define DMAC5_CHCFG_n_HIEN (0x00000020uL) +#define DMAC5_CHCFG_n_LVL (0x00000040uL) +#define DMAC5_CHCFG_n_AM (0x00000700uL) +#define DMAC5_CHCFG_n_SDS (0x0000F000uL) +#define DMAC5_CHCFG_n_DDS (0x000F0000uL) +#define DMAC5_CHCFG_n_SAD (0x00100000uL) +#define DMAC5_CHCFG_n_DAD (0x00200000uL) +#define DMAC5_CHCFG_n_TM (0x00400000uL) +#define DMAC5_CHCFG_n_DEM (0x01000000uL) +#define DMAC5_CHCFG_n_TCM (0x02000000uL) +#define DMAC5_CHCFG_n_SBE (0x08000000uL) +#define DMAC5_CHCFG_n_RSEL (0x10000000uL) +#define DMAC5_CHCFG_n_RSW (0x20000000uL) +#define DMAC5_CHCFG_n_REN (0x40000000uL) +#define DMAC5_CHCFG_n_DMS (0x80000000uL) + +#define DMAC5_CHITVL_n_ITVL (0x0000FFFFuL) + +#define DMAC5_CHEXT_n_SCA (0x000000F0uL) +#define DMAC5_CHEXT_n_DCA (0x0000F000uL) + +#define DMAC5_NXLA_n_NXLA (0xFFFFFFFFuL) + +#define DMAC5_CRLA_n_CRLA (0xFFFFFFFFuL) + +/* ---- DMAC6 ---- */ +#define DMAC6_N0SA_n_SA (0xFFFFFFFFuL) + +#define DMAC6_N0DA_n_DA (0xFFFFFFFFuL) + +#define DMAC6_N0TB_n_TB (0xFFFFFFFFuL) + +#define DMAC6_N1SA_n_SA (0xFFFFFFFFuL) + +#define DMAC6_N1DA_n_DA (0xFFFFFFFFuL) + +#define DMAC6_N1TB_n_TB (0xFFFFFFFFuL) + +#define DMAC6_CRSA_n_CRSA (0xFFFFFFFFuL) + +#define DMAC6_CRDA_n_CRDA (0xFFFFFFFFuL) + +#define DMAC6_CRTB_n_CRTB (0xFFFFFFFFuL) + +#define DMAC6_CHSTAT_n_EN (0x00000001uL) +#define DMAC6_CHSTAT_n_RQST (0x00000002uL) +#define DMAC6_CHSTAT_n_TACT (0x00000004uL) +#define DMAC6_CHSTAT_n_SUS (0x00000008uL) +#define DMAC6_CHSTAT_n_ER (0x00000010uL) +#define DMAC6_CHSTAT_n_END (0x00000020uL) +#define DMAC6_CHSTAT_n_TC (0x00000040uL) +#define DMAC6_CHSTAT_n_SR (0x00000080uL) +#define DMAC6_CHSTAT_n_DL (0x00000100uL) +#define DMAC6_CHSTAT_n_DW (0x00000200uL) +#define DMAC6_CHSTAT_n_DER (0x00000400uL) +#define DMAC6_CHSTAT_n_MODE (0x00000800uL) +#define DMAC6_CHSTAT_n_INTMSK (0x00010000uL) + +#define DMAC6_CHCTRL_n_SETEN (0x00000001uL) +#define DMAC6_CHCTRL_n_CLREN (0x00000002uL) +#define DMAC6_CHCTRL_n_STG (0x00000004uL) +#define DMAC6_CHCTRL_n_SWRST (0x00000008uL) +#define DMAC6_CHCTRL_n_CLRRQ (0x00000010uL) +#define DMAC6_CHCTRL_n_CLREND (0x00000020uL) +#define DMAC6_CHCTRL_n_CLRTC (0x00000040uL) +#define DMAC6_CHCTRL_n_SETSUS (0x00000100uL) +#define DMAC6_CHCTRL_n_CLRSUS (0x00000200uL) +#define DMAC6_CHCTRL_n_SETINTMSK (0x00010000uL) +#define DMAC6_CHCTRL_n_CLRINTMSK (0x00020000uL) + +#define DMAC6_CHCFG_n_SEL (0x00000007uL) +#define DMAC6_CHCFG_n_REQD (0x00000008uL) +#define DMAC6_CHCFG_n_LOEN (0x00000010uL) +#define DMAC6_CHCFG_n_HIEN (0x00000020uL) +#define DMAC6_CHCFG_n_LVL (0x00000040uL) +#define DMAC6_CHCFG_n_AM (0x00000700uL) +#define DMAC6_CHCFG_n_SDS (0x0000F000uL) +#define DMAC6_CHCFG_n_DDS (0x000F0000uL) +#define DMAC6_CHCFG_n_SAD (0x00100000uL) +#define DMAC6_CHCFG_n_DAD (0x00200000uL) +#define DMAC6_CHCFG_n_TM (0x00400000uL) +#define DMAC6_CHCFG_n_DEM (0x01000000uL) +#define DMAC6_CHCFG_n_TCM (0x02000000uL) +#define DMAC6_CHCFG_n_SBE (0x08000000uL) +#define DMAC6_CHCFG_n_RSEL (0x10000000uL) +#define DMAC6_CHCFG_n_RSW (0x20000000uL) +#define DMAC6_CHCFG_n_REN (0x40000000uL) +#define DMAC6_CHCFG_n_DMS (0x80000000uL) + +#define DMAC6_CHITVL_n_ITVL (0x0000FFFFuL) + +#define DMAC6_CHEXT_n_SCA (0x000000F0uL) +#define DMAC6_CHEXT_n_DCA (0x0000F000uL) + +#define DMAC6_NXLA_n_NXLA (0xFFFFFFFFuL) + +#define DMAC6_CRLA_n_CRLA (0xFFFFFFFFuL) + +/* ---- DMAC7 ---- */ +#define DMAC7_N0SA_n_SA (0xFFFFFFFFuL) + +#define DMAC7_N0DA_n_DA (0xFFFFFFFFuL) + +#define DMAC7_N0TB_n_TB (0xFFFFFFFFuL) + +#define DMAC7_N1SA_n_SA (0xFFFFFFFFuL) + +#define DMAC7_N1DA_n_DA (0xFFFFFFFFuL) + +#define DMAC7_N1TB_n_TB (0xFFFFFFFFuL) + +#define DMAC7_CRSA_n_CRSA (0xFFFFFFFFuL) + +#define DMAC7_CRDA_n_CRDA (0xFFFFFFFFuL) + +#define DMAC7_CRTB_n_CRTB (0xFFFFFFFFuL) + +#define DMAC7_CHSTAT_n_EN (0x00000001uL) +#define DMAC7_CHSTAT_n_RQST (0x00000002uL) +#define DMAC7_CHSTAT_n_TACT (0x00000004uL) +#define DMAC7_CHSTAT_n_SUS (0x00000008uL) +#define DMAC7_CHSTAT_n_ER (0x00000010uL) +#define DMAC7_CHSTAT_n_END (0x00000020uL) +#define DMAC7_CHSTAT_n_TC (0x00000040uL) +#define DMAC7_CHSTAT_n_SR (0x00000080uL) +#define DMAC7_CHSTAT_n_DL (0x00000100uL) +#define DMAC7_CHSTAT_n_DW (0x00000200uL) +#define DMAC7_CHSTAT_n_DER (0x00000400uL) +#define DMAC7_CHSTAT_n_MODE (0x00000800uL) +#define DMAC7_CHSTAT_n_INTMSK (0x00010000uL) + +#define DMAC7_CHCTRL_n_SETEN (0x00000001uL) +#define DMAC7_CHCTRL_n_CLREN (0x00000002uL) +#define DMAC7_CHCTRL_n_STG (0x00000004uL) +#define DMAC7_CHCTRL_n_SWRST (0x00000008uL) +#define DMAC7_CHCTRL_n_CLRRQ (0x00000010uL) +#define DMAC7_CHCTRL_n_CLREND (0x00000020uL) +#define DMAC7_CHCTRL_n_CLRTC (0x00000040uL) +#define DMAC7_CHCTRL_n_SETSUS (0x00000100uL) +#define DMAC7_CHCTRL_n_CLRSUS (0x00000200uL) +#define DMAC7_CHCTRL_n_SETINTMSK (0x00010000uL) +#define DMAC7_CHCTRL_n_CLRINTMSK (0x00020000uL) + +#define DMAC7_CHCFG_n_SEL (0x00000007uL) +#define DMAC7_CHCFG_n_REQD (0x00000008uL) +#define DMAC7_CHCFG_n_LOEN (0x00000010uL) +#define DMAC7_CHCFG_n_HIEN (0x00000020uL) +#define DMAC7_CHCFG_n_LVL (0x00000040uL) +#define DMAC7_CHCFG_n_AM (0x00000700uL) +#define DMAC7_CHCFG_n_SDS (0x0000F000uL) +#define DMAC7_CHCFG_n_DDS (0x000F0000uL) +#define DMAC7_CHCFG_n_SAD (0x00100000uL) +#define DMAC7_CHCFG_n_DAD (0x00200000uL) +#define DMAC7_CHCFG_n_TM (0x00400000uL) +#define DMAC7_CHCFG_n_DEM (0x01000000uL) +#define DMAC7_CHCFG_n_TCM (0x02000000uL) +#define DMAC7_CHCFG_n_SBE (0x08000000uL) +#define DMAC7_CHCFG_n_RSEL (0x10000000uL) +#define DMAC7_CHCFG_n_RSW (0x20000000uL) +#define DMAC7_CHCFG_n_REN (0x40000000uL) +#define DMAC7_CHCFG_n_DMS (0x80000000uL) + +#define DMAC7_CHITVL_n_ITVL (0x0000FFFFuL) + +#define DMAC7_CHEXT_n_SCA (0x000000F0uL) +#define DMAC7_CHEXT_n_DCA (0x0000F000uL) + +#define DMAC7_NXLA_n_NXLA (0xFFFFFFFFuL) + +#define DMAC7_CRLA_n_CRLA (0xFFFFFFFFuL) + +/* ---- DMAC0-7 ---- */ +#define DMAC07_DCTRL_0_7_PR (0x00000001uL) +#define DMAC07_DCTRL_0_7_LVINT (0x00000002uL) +#define DMAC07_DCTRL_0_7_LDCA (0x0000003CuL) +#define DMAC07_DCTRL_0_7_LWCA (0x000003C0uL) + +#define DMAC07_DSTAT_EN_0_7_EN0 (0x00000001uL) +#define DMAC07_DSTAT_EN_0_7_EN1 (0x00000002uL) +#define DMAC07_DSTAT_EN_0_7_EN2 (0x00000004uL) +#define DMAC07_DSTAT_EN_0_7_EN3 (0x00000008uL) +#define DMAC07_DSTAT_EN_0_7_EN4 (0x00000010uL) +#define DMAC07_DSTAT_EN_0_7_EN5 (0x00000020uL) +#define DMAC07_DSTAT_EN_0_7_EN6 (0x00000040uL) +#define DMAC07_DSTAT_EN_0_7_EN7 (0x00000080uL) + +#define DMAC07_DSTAT_ER_0_7_ER0 (0x00000001uL) +#define DMAC07_DSTAT_ER_0_7_ER1 (0x00000002uL) +#define DMAC07_DSTAT_ER_0_7_ER2 (0x00000004uL) +#define DMAC07_DSTAT_ER_0_7_ER3 (0x00000008uL) +#define DMAC07_DSTAT_ER_0_7_ER4 (0x00000010uL) +#define DMAC07_DSTAT_ER_0_7_ER5 (0x00000020uL) +#define DMAC07_DSTAT_ER_0_7_ER6 (0x00000040uL) +#define DMAC07_DSTAT_ER_0_7_ER7 (0x00000080uL) + +#define DMAC07_DSTAT_END_0_7_END0 (0x00000001uL) +#define DMAC07_DSTAT_END_0_7_END1 (0x00000002uL) +#define DMAC07_DSTAT_END_0_7_END2 (0x00000004uL) +#define DMAC07_DSTAT_END_0_7_END3 (0x00000008uL) +#define DMAC07_DSTAT_END_0_7_END4 (0x00000010uL) +#define DMAC07_DSTAT_END_0_7_END5 (0x00000020uL) +#define DMAC07_DSTAT_END_0_7_END6 (0x00000040uL) +#define DMAC07_DSTAT_END_0_7_END7 (0x00000080uL) + +#define DMAC07_DSTAT_TC_0_7_TC0 (0x00000001uL) +#define DMAC07_DSTAT_TC_0_7_TC1 (0x00000002uL) +#define DMAC07_DSTAT_TC_0_7_TC2 (0x00000004uL) +#define DMAC07_DSTAT_TC_0_7_TC3 (0x00000008uL) +#define DMAC07_DSTAT_TC_0_7_TC4 (0x00000010uL) +#define DMAC07_DSTAT_TC_0_7_TC5 (0x00000020uL) +#define DMAC07_DSTAT_TC_0_7_TC6 (0x00000040uL) +#define DMAC07_DSTAT_TC_0_7_TC7 (0x00000080uL) + +#define DMAC07_DSTAT_SUS_0_7_SUS0 (0x00000001uL) +#define DMAC07_DSTAT_SUS_0_7_SUS1 (0x00000002uL) +#define DMAC07_DSTAT_SUS_0_7_SUS2 (0x00000004uL) +#define DMAC07_DSTAT_SUS_0_7_SUS3 (0x00000008uL) +#define DMAC07_DSTAT_SUS_0_7_SUS4 (0x00000010uL) +#define DMAC07_DSTAT_SUS_0_7_SUS5 (0x00000020uL) +#define DMAC07_DSTAT_SUS_0_7_SUS6 (0x00000040uL) +#define DMAC07_DSTAT_SUS_0_7_SUS7 (0x00000080uL) + +/* ---- DMAC8 ---- */ +#define DMAC8_N0SA_n_SA (0xFFFFFFFFuL) + +#define DMAC8_N0DA_n_DA (0xFFFFFFFFuL) + +#define DMAC8_N0TB_n_TB (0xFFFFFFFFuL) + +#define DMAC8_N1SA_n_SA (0xFFFFFFFFuL) + +#define DMAC8_N1DA_n_DA (0xFFFFFFFFuL) + +#define DMAC8_N1TB_n_TB (0xFFFFFFFFuL) + +#define DMAC8_CRSA_n_CRSA (0xFFFFFFFFuL) + +#define DMAC8_CRDA_n_CRDA (0xFFFFFFFFuL) + +#define DMAC8_CRTB_n_CRTB (0xFFFFFFFFuL) + +#define DMAC8_CHSTAT_n_EN (0x00000001uL) +#define DMAC8_CHSTAT_n_RQST (0x00000002uL) +#define DMAC8_CHSTAT_n_TACT (0x00000004uL) +#define DMAC8_CHSTAT_n_SUS (0x00000008uL) +#define DMAC8_CHSTAT_n_ER (0x00000010uL) +#define DMAC8_CHSTAT_n_END (0x00000020uL) +#define DMAC8_CHSTAT_n_TC (0x00000040uL) +#define DMAC8_CHSTAT_n_SR (0x00000080uL) +#define DMAC8_CHSTAT_n_DL (0x00000100uL) +#define DMAC8_CHSTAT_n_DW (0x00000200uL) +#define DMAC8_CHSTAT_n_DER (0x00000400uL) +#define DMAC8_CHSTAT_n_MODE (0x00000800uL) +#define DMAC8_CHSTAT_n_INTMSK (0x00010000uL) + +#define DMAC8_CHCTRL_n_SETEN (0x00000001uL) +#define DMAC8_CHCTRL_n_CLREN (0x00000002uL) +#define DMAC8_CHCTRL_n_STG (0x00000004uL) +#define DMAC8_CHCTRL_n_SWRST (0x00000008uL) +#define DMAC8_CHCTRL_n_CLRRQ (0x00000010uL) +#define DMAC8_CHCTRL_n_CLREND (0x00000020uL) +#define DMAC8_CHCTRL_n_CLRTC (0x00000040uL) +#define DMAC8_CHCTRL_n_SETSUS (0x00000100uL) +#define DMAC8_CHCTRL_n_CLRSUS (0x00000200uL) +#define DMAC8_CHCTRL_n_SETINTMSK (0x00010000uL) +#define DMAC8_CHCTRL_n_CLRINTMSK (0x00020000uL) + +#define DMAC8_CHCFG_n_SEL (0x00000007uL) +#define DMAC8_CHCFG_n_REQD (0x00000008uL) +#define DMAC8_CHCFG_n_LOEN (0x00000010uL) +#define DMAC8_CHCFG_n_HIEN (0x00000020uL) +#define DMAC8_CHCFG_n_LVL (0x00000040uL) +#define DMAC8_CHCFG_n_AM (0x00000700uL) +#define DMAC8_CHCFG_n_SDS (0x0000F000uL) +#define DMAC8_CHCFG_n_DDS (0x000F0000uL) +#define DMAC8_CHCFG_n_SAD (0x00100000uL) +#define DMAC8_CHCFG_n_DAD (0x00200000uL) +#define DMAC8_CHCFG_n_TM (0x00400000uL) +#define DMAC8_CHCFG_n_DEM (0x01000000uL) +#define DMAC8_CHCFG_n_TCM (0x02000000uL) +#define DMAC8_CHCFG_n_SBE (0x08000000uL) +#define DMAC8_CHCFG_n_RSEL (0x10000000uL) +#define DMAC8_CHCFG_n_RSW (0x20000000uL) +#define DMAC8_CHCFG_n_REN (0x40000000uL) +#define DMAC8_CHCFG_n_DMS (0x80000000uL) + +#define DMAC8_CHITVL_n_ITVL (0x0000FFFFuL) + +#define DMAC8_CHEXT_n_SCA (0x000000F0uL) +#define DMAC8_CHEXT_n_DCA (0x0000F000uL) + +#define DMAC8_NXLA_n_NXLA (0xFFFFFFFFuL) + +#define DMAC8_CRLA_n_CRLA (0xFFFFFFFFuL) + +/* ---- DMAC9 ---- */ +#define DMAC9_N0SA_n_SA (0xFFFFFFFFuL) + +#define DMAC9_N0DA_n_DA (0xFFFFFFFFuL) + +#define DMAC9_N0TB_n_TB (0xFFFFFFFFuL) + +#define DMAC9_N1SA_n_SA (0xFFFFFFFFuL) + +#define DMAC9_N1DA_n_DA (0xFFFFFFFFuL) + +#define DMAC9_N1TB_n_TB (0xFFFFFFFFuL) + +#define DMAC9_CRSA_n_CRSA (0xFFFFFFFFuL) + +#define DMAC9_CRDA_n_CRDA (0xFFFFFFFFuL) + +#define DMAC9_CRTB_n_CRTB (0xFFFFFFFFuL) + +#define DMAC9_CHSTAT_n_EN (0x00000001uL) +#define DMAC9_CHSTAT_n_RQST (0x00000002uL) +#define DMAC9_CHSTAT_n_TACT (0x00000004uL) +#define DMAC9_CHSTAT_n_SUS (0x00000008uL) +#define DMAC9_CHSTAT_n_ER (0x00000010uL) +#define DMAC9_CHSTAT_n_END (0x00000020uL) +#define DMAC9_CHSTAT_n_TC (0x00000040uL) +#define DMAC9_CHSTAT_n_SR (0x00000080uL) +#define DMAC9_CHSTAT_n_DL (0x00000100uL) +#define DMAC9_CHSTAT_n_DW (0x00000200uL) +#define DMAC9_CHSTAT_n_DER (0x00000400uL) +#define DMAC9_CHSTAT_n_MODE (0x00000800uL) +#define DMAC9_CHSTAT_n_INTMSK (0x00010000uL) + +#define DMAC9_CHCTRL_n_SETEN (0x00000001uL) +#define DMAC9_CHCTRL_n_CLREN (0x00000002uL) +#define DMAC9_CHCTRL_n_STG (0x00000004uL) +#define DMAC9_CHCTRL_n_SWRST (0x00000008uL) +#define DMAC9_CHCTRL_n_CLRRQ (0x00000010uL) +#define DMAC9_CHCTRL_n_CLREND (0x00000020uL) +#define DMAC9_CHCTRL_n_CLRTC (0x00000040uL) +#define DMAC9_CHCTRL_n_SETSUS (0x00000100uL) +#define DMAC9_CHCTRL_n_CLRSUS (0x00000200uL) +#define DMAC9_CHCTRL_n_SETINTMSK (0x00010000uL) +#define DMAC9_CHCTRL_n_CLRINTMSK (0x00020000uL) + +#define DMAC9_CHCFG_n_SEL (0x00000007uL) +#define DMAC9_CHCFG_n_REQD (0x00000008uL) +#define DMAC9_CHCFG_n_LOEN (0x00000010uL) +#define DMAC9_CHCFG_n_HIEN (0x00000020uL) +#define DMAC9_CHCFG_n_LVL (0x00000040uL) +#define DMAC9_CHCFG_n_AM (0x00000700uL) +#define DMAC9_CHCFG_n_SDS (0x0000F000uL) +#define DMAC9_CHCFG_n_DDS (0x000F0000uL) +#define DMAC9_CHCFG_n_SAD (0x00100000uL) +#define DMAC9_CHCFG_n_DAD (0x00200000uL) +#define DMAC9_CHCFG_n_TM (0x00400000uL) +#define DMAC9_CHCFG_n_DEM (0x01000000uL) +#define DMAC9_CHCFG_n_TCM (0x02000000uL) +#define DMAC9_CHCFG_n_SBE (0x08000000uL) +#define DMAC9_CHCFG_n_RSEL (0x10000000uL) +#define DMAC9_CHCFG_n_RSW (0x20000000uL) +#define DMAC9_CHCFG_n_REN (0x40000000uL) +#define DMAC9_CHCFG_n_DMS (0x80000000uL) + +#define DMAC9_CHITVL_n_ITVL (0x0000FFFFuL) + +#define DMAC9_CHEXT_n_SCA (0x000000F0uL) +#define DMAC9_CHEXT_n_DCA (0x0000F000uL) + +#define DMAC9_NXLA_n_NXLA (0xFFFFFFFFuL) + +#define DMAC9_CRLA_n_CRLA (0xFFFFFFFFuL) + +/* ---- DMAC10 ---- */ +#define DMAC10_N0SA_n_SA (0xFFFFFFFFuL) + +#define DMAC10_N0DA_n_DA (0xFFFFFFFFuL) + +#define DMAC10_N0TB_n_TB (0xFFFFFFFFuL) + +#define DMAC10_N1SA_n_SA (0xFFFFFFFFuL) + +#define DMAC10_N1DA_n_DA (0xFFFFFFFFuL) + +#define DMAC10_N1TB_n_TB (0xFFFFFFFFuL) + +#define DMAC10_CRSA_n_CRSA (0xFFFFFFFFuL) + +#define DMAC10_CRDA_n_CRDA (0xFFFFFFFFuL) + +#define DMAC10_CRTB_n_CRTB (0xFFFFFFFFuL) + +#define DMAC10_CHSTAT_n_EN (0x00000001uL) +#define DMAC10_CHSTAT_n_RQST (0x00000002uL) +#define DMAC10_CHSTAT_n_TACT (0x00000004uL) +#define DMAC10_CHSTAT_n_SUS (0x00000008uL) +#define DMAC10_CHSTAT_n_ER (0x00000010uL) +#define DMAC10_CHSTAT_n_END (0x00000020uL) +#define DMAC10_CHSTAT_n_TC (0x00000040uL) +#define DMAC10_CHSTAT_n_SR (0x00000080uL) +#define DMAC10_CHSTAT_n_DL (0x00000100uL) +#define DMAC10_CHSTAT_n_DW (0x00000200uL) +#define DMAC10_CHSTAT_n_DER (0x00000400uL) +#define DMAC10_CHSTAT_n_MODE (0x00000800uL) +#define DMAC10_CHSTAT_n_INTMSK (0x00010000uL) + +#define DMAC10_CHCTRL_n_SETEN (0x00000001uL) +#define DMAC10_CHCTRL_n_CLREN (0x00000002uL) +#define DMAC10_CHCTRL_n_STG (0x00000004uL) +#define DMAC10_CHCTRL_n_SWRST (0x00000008uL) +#define DMAC10_CHCTRL_n_CLRRQ (0x00000010uL) +#define DMAC10_CHCTRL_n_CLREND (0x00000020uL) +#define DMAC10_CHCTRL_n_CLRTC (0x00000040uL) +#define DMAC10_CHCTRL_n_SETSUS (0x00000100uL) +#define DMAC10_CHCTRL_n_CLRSUS (0x00000200uL) +#define DMAC10_CHCTRL_n_SETINTMSK (0x00010000uL) +#define DMAC10_CHCTRL_n_CLRINTMSK (0x00020000uL) + +#define DMAC10_CHCFG_n_SEL (0x00000007uL) +#define DMAC10_CHCFG_n_REQD (0x00000008uL) +#define DMAC10_CHCFG_n_LOEN (0x00000010uL) +#define DMAC10_CHCFG_n_HIEN (0x00000020uL) +#define DMAC10_CHCFG_n_LVL (0x00000040uL) +#define DMAC10_CHCFG_n_AM (0x00000700uL) +#define DMAC10_CHCFG_n_SDS (0x0000F000uL) +#define DMAC10_CHCFG_n_DDS (0x000F0000uL) +#define DMAC10_CHCFG_n_SAD (0x00100000uL) +#define DMAC10_CHCFG_n_DAD (0x00200000uL) +#define DMAC10_CHCFG_n_TM (0x00400000uL) +#define DMAC10_CHCFG_n_DEM (0x01000000uL) +#define DMAC10_CHCFG_n_TCM (0x02000000uL) +#define DMAC10_CHCFG_n_SBE (0x08000000uL) +#define DMAC10_CHCFG_n_RSEL (0x10000000uL) +#define DMAC10_CHCFG_n_RSW (0x20000000uL) +#define DMAC10_CHCFG_n_REN (0x40000000uL) +#define DMAC10_CHCFG_n_DMS (0x80000000uL) + +#define DMAC10_CHITVL_n_ITVL (0x0000FFFFuL) + +#define DMAC10_CHEXT_n_SCA (0x000000F0uL) +#define DMAC10_CHEXT_n_DCA (0x0000F000uL) + +#define DMAC10_NXLA_n_NXLA (0xFFFFFFFFuL) + +#define DMAC10_CRLA_n_CRLA (0xFFFFFFFFuL) + +/* ---- DMAC11 ---- */ +#define DMAC11_N0SA_n_SA (0xFFFFFFFFuL) + +#define DMAC11_N0DA_n_DA (0xFFFFFFFFuL) + +#define DMAC11_N0TB_n_TB (0xFFFFFFFFuL) + +#define DMAC11_N1SA_n_SA (0xFFFFFFFFuL) + +#define DMAC11_N1DA_n_DA (0xFFFFFFFFuL) + +#define DMAC11_N1TB_n_TB (0xFFFFFFFFuL) + +#define DMAC11_CRSA_n_CRSA (0xFFFFFFFFuL) + +#define DMAC11_CRDA_n_CRDA (0xFFFFFFFFuL) + +#define DMAC11_CRTB_n_CRTB (0xFFFFFFFFuL) + +#define DMAC11_CHSTAT_n_EN (0x00000001uL) +#define DMAC11_CHSTAT_n_RQST (0x00000002uL) +#define DMAC11_CHSTAT_n_TACT (0x00000004uL) +#define DMAC11_CHSTAT_n_SUS (0x00000008uL) +#define DMAC11_CHSTAT_n_ER (0x00000010uL) +#define DMAC11_CHSTAT_n_END (0x00000020uL) +#define DMAC11_CHSTAT_n_TC (0x00000040uL) +#define DMAC11_CHSTAT_n_SR (0x00000080uL) +#define DMAC11_CHSTAT_n_DL (0x00000100uL) +#define DMAC11_CHSTAT_n_DW (0x00000200uL) +#define DMAC11_CHSTAT_n_DER (0x00000400uL) +#define DMAC11_CHSTAT_n_MODE (0x00000800uL) +#define DMAC11_CHSTAT_n_INTMSK (0x00010000uL) + +#define DMAC11_CHCTRL_n_SETEN (0x00000001uL) +#define DMAC11_CHCTRL_n_CLREN (0x00000002uL) +#define DMAC11_CHCTRL_n_STG (0x00000004uL) +#define DMAC11_CHCTRL_n_SWRST (0x00000008uL) +#define DMAC11_CHCTRL_n_CLRRQ (0x00000010uL) +#define DMAC11_CHCTRL_n_CLREND (0x00000020uL) +#define DMAC11_CHCTRL_n_CLRTC (0x00000040uL) +#define DMAC11_CHCTRL_n_SETSUS (0x00000100uL) +#define DMAC11_CHCTRL_n_CLRSUS (0x00000200uL) +#define DMAC11_CHCTRL_n_SETINTMSK (0x00010000uL) +#define DMAC11_CHCTRL_n_CLRINTMSK (0x00020000uL) + +#define DMAC11_CHCFG_n_SEL (0x00000007uL) +#define DMAC11_CHCFG_n_REQD (0x00000008uL) +#define DMAC11_CHCFG_n_LOEN (0x00000010uL) +#define DMAC11_CHCFG_n_HIEN (0x00000020uL) +#define DMAC11_CHCFG_n_LVL (0x00000040uL) +#define DMAC11_CHCFG_n_AM (0x00000700uL) +#define DMAC11_CHCFG_n_SDS (0x0000F000uL) +#define DMAC11_CHCFG_n_DDS (0x000F0000uL) +#define DMAC11_CHCFG_n_SAD (0x00100000uL) +#define DMAC11_CHCFG_n_DAD (0x00200000uL) +#define DMAC11_CHCFG_n_TM (0x00400000uL) +#define DMAC11_CHCFG_n_DEM (0x01000000uL) +#define DMAC11_CHCFG_n_TCM (0x02000000uL) +#define DMAC11_CHCFG_n_SBE (0x08000000uL) +#define DMAC11_CHCFG_n_RSEL (0x10000000uL) +#define DMAC11_CHCFG_n_RSW (0x20000000uL) +#define DMAC11_CHCFG_n_REN (0x40000000uL) +#define DMAC11_CHCFG_n_DMS (0x80000000uL) + +#define DMAC11_CHITVL_n_ITVL (0x0000FFFFuL) + +#define DMAC11_CHEXT_n_SCA (0x000000F0uL) +#define DMAC11_CHEXT_n_DCA (0x0000F000uL) + +#define DMAC11_NXLA_n_NXLA (0xFFFFFFFFuL) + +#define DMAC11_CRLA_n_CRLA (0xFFFFFFFFuL) + +/* ---- DMAC12 ---- */ +#define DMAC12_N0SA_n_SA (0xFFFFFFFFuL) + +#define DMAC12_N0DA_n_DA (0xFFFFFFFFuL) + +#define DMAC12_N0TB_n_TB (0xFFFFFFFFuL) + +#define DMAC12_N1SA_n_SA (0xFFFFFFFFuL) + +#define DMAC12_N1DA_n_DA (0xFFFFFFFFuL) + +#define DMAC12_N1TB_n_TB (0xFFFFFFFFuL) + +#define DMAC12_CRSA_n_CRSA (0xFFFFFFFFuL) + +#define DMAC12_CRDA_n_CRDA (0xFFFFFFFFuL) + +#define DMAC12_CRTB_n_CRTB (0xFFFFFFFFuL) + +#define DMAC12_CHSTAT_n_EN (0x00000001uL) +#define DMAC12_CHSTAT_n_RQST (0x00000002uL) +#define DMAC12_CHSTAT_n_TACT (0x00000004uL) +#define DMAC12_CHSTAT_n_SUS (0x00000008uL) +#define DMAC12_CHSTAT_n_ER (0x00000010uL) +#define DMAC12_CHSTAT_n_END (0x00000020uL) +#define DMAC12_CHSTAT_n_TC (0x00000040uL) +#define DMAC12_CHSTAT_n_SR (0x00000080uL) +#define DMAC12_CHSTAT_n_DL (0x00000100uL) +#define DMAC12_CHSTAT_n_DW (0x00000200uL) +#define DMAC12_CHSTAT_n_DER (0x00000400uL) +#define DMAC12_CHSTAT_n_MODE (0x00000800uL) +#define DMAC12_CHSTAT_n_INTMSK (0x00010000uL) + +#define DMAC12_CHCTRL_n_SETEN (0x00000001uL) +#define DMAC12_CHCTRL_n_CLREN (0x00000002uL) +#define DMAC12_CHCTRL_n_STG (0x00000004uL) +#define DMAC12_CHCTRL_n_SWRST (0x00000008uL) +#define DMAC12_CHCTRL_n_CLRRQ (0x00000010uL) +#define DMAC12_CHCTRL_n_CLREND (0x00000020uL) +#define DMAC12_CHCTRL_n_CLRTC (0x00000040uL) +#define DMAC12_CHCTRL_n_SETSUS (0x00000100uL) +#define DMAC12_CHCTRL_n_CLRSUS (0x00000200uL) +#define DMAC12_CHCTRL_n_SETINTMSK (0x00010000uL) +#define DMAC12_CHCTRL_n_CLRINTMSK (0x00020000uL) + +#define DMAC12_CHCFG_n_SEL (0x00000007uL) +#define DMAC12_CHCFG_n_REQD (0x00000008uL) +#define DMAC12_CHCFG_n_LOEN (0x00000010uL) +#define DMAC12_CHCFG_n_HIEN (0x00000020uL) +#define DMAC12_CHCFG_n_LVL (0x00000040uL) +#define DMAC12_CHCFG_n_AM (0x00000700uL) +#define DMAC12_CHCFG_n_SDS (0x0000F000uL) +#define DMAC12_CHCFG_n_DDS (0x000F0000uL) +#define DMAC12_CHCFG_n_SAD (0x00100000uL) +#define DMAC12_CHCFG_n_DAD (0x00200000uL) +#define DMAC12_CHCFG_n_TM (0x00400000uL) +#define DMAC12_CHCFG_n_DEM (0x01000000uL) +#define DMAC12_CHCFG_n_TCM (0x02000000uL) +#define DMAC12_CHCFG_n_SBE (0x08000000uL) +#define DMAC12_CHCFG_n_RSEL (0x10000000uL) +#define DMAC12_CHCFG_n_RSW (0x20000000uL) +#define DMAC12_CHCFG_n_REN (0x40000000uL) +#define DMAC12_CHCFG_n_DMS (0x80000000uL) + +#define DMAC12_CHITVL_n_ITVL (0x0000FFFFuL) + +#define DMAC12_CHEXT_n_SCA (0x000000F0uL) +#define DMAC12_CHEXT_n_DCA (0x0000F000uL) + +#define DMAC12_NXLA_n_NXLA (0xFFFFFFFFuL) + +#define DMAC12_CRLA_n_CRLA (0xFFFFFFFFuL) + +/* ---- DMAC13 ---- */ +#define DMAC13_N0SA_n_SA (0xFFFFFFFFuL) + +#define DMAC13_N0DA_n_DA (0xFFFFFFFFuL) + +#define DMAC13_N0TB_n_TB (0xFFFFFFFFuL) + +#define DMAC13_N1SA_n_SA (0xFFFFFFFFuL) + +#define DMAC13_N1DA_n_DA (0xFFFFFFFFuL) + +#define DMAC13_N1TB_n_TB (0xFFFFFFFFuL) + +#define DMAC13_CRSA_n_CRSA (0xFFFFFFFFuL) + +#define DMAC13_CRDA_n_CRDA (0xFFFFFFFFuL) + +#define DMAC13_CRTB_n_CRTB (0xFFFFFFFFuL) + +#define DMAC13_CHSTAT_n_EN (0x00000001uL) +#define DMAC13_CHSTAT_n_RQST (0x00000002uL) +#define DMAC13_CHSTAT_n_TACT (0x00000004uL) +#define DMAC13_CHSTAT_n_SUS (0x00000008uL) +#define DMAC13_CHSTAT_n_ER (0x00000010uL) +#define DMAC13_CHSTAT_n_END (0x00000020uL) +#define DMAC13_CHSTAT_n_TC (0x00000040uL) +#define DMAC13_CHSTAT_n_SR (0x00000080uL) +#define DMAC13_CHSTAT_n_DL (0x00000100uL) +#define DMAC13_CHSTAT_n_DW (0x00000200uL) +#define DMAC13_CHSTAT_n_DER (0x00000400uL) +#define DMAC13_CHSTAT_n_MODE (0x00000800uL) +#define DMAC13_CHSTAT_n_INTMSK (0x00010000uL) + +#define DMAC13_CHCTRL_n_SETEN (0x00000001uL) +#define DMAC13_CHCTRL_n_CLREN (0x00000002uL) +#define DMAC13_CHCTRL_n_STG (0x00000004uL) +#define DMAC13_CHCTRL_n_SWRST (0x00000008uL) +#define DMAC13_CHCTRL_n_CLRRQ (0x00000010uL) +#define DMAC13_CHCTRL_n_CLREND (0x00000020uL) +#define DMAC13_CHCTRL_n_CLRTC (0x00000040uL) +#define DMAC13_CHCTRL_n_SETSUS (0x00000100uL) +#define DMAC13_CHCTRL_n_CLRSUS (0x00000200uL) +#define DMAC13_CHCTRL_n_SETINTMSK (0x00010000uL) +#define DMAC13_CHCTRL_n_CLRINTMSK (0x00020000uL) + +#define DMAC13_CHCFG_n_SEL (0x00000007uL) +#define DMAC13_CHCFG_n_REQD (0x00000008uL) +#define DMAC13_CHCFG_n_LOEN (0x00000010uL) +#define DMAC13_CHCFG_n_HIEN (0x00000020uL) +#define DMAC13_CHCFG_n_LVL (0x00000040uL) +#define DMAC13_CHCFG_n_AM (0x00000700uL) +#define DMAC13_CHCFG_n_SDS (0x0000F000uL) +#define DMAC13_CHCFG_n_DDS (0x000F0000uL) +#define DMAC13_CHCFG_n_SAD (0x00100000uL) +#define DMAC13_CHCFG_n_DAD (0x00200000uL) +#define DMAC13_CHCFG_n_TM (0x00400000uL) +#define DMAC13_CHCFG_n_DEM (0x01000000uL) +#define DMAC13_CHCFG_n_TCM (0x02000000uL) +#define DMAC13_CHCFG_n_SBE (0x08000000uL) +#define DMAC13_CHCFG_n_RSEL (0x10000000uL) +#define DMAC13_CHCFG_n_RSW (0x20000000uL) +#define DMAC13_CHCFG_n_REN (0x40000000uL) +#define DMAC13_CHCFG_n_DMS (0x80000000uL) + +#define DMAC13_CHITVL_n_ITVL (0x0000FFFFuL) + +#define DMAC13_CHEXT_n_SCA (0x000000F0uL) +#define DMAC13_CHEXT_n_DCA (0x0000F000uL) + +#define DMAC13_NXLA_n_NXLA (0xFFFFFFFFuL) + +#define DMAC13_CRLA_n_CRLA (0xFFFFFFFFuL) + +/* ---- DMAC14 ---- */ +#define DMAC14_N0SA_n_SA (0xFFFFFFFFuL) + +#define DMAC14_N0DA_n_DA (0xFFFFFFFFuL) + +#define DMAC14_N0TB_n_TB (0xFFFFFFFFuL) + +#define DMAC14_N1SA_n_SA (0xFFFFFFFFuL) + +#define DMAC14_N1DA_n_DA (0xFFFFFFFFuL) + +#define DMAC14_N1TB_n_TB (0xFFFFFFFFuL) + +#define DMAC14_CRSA_n_CRSA (0xFFFFFFFFuL) + +#define DMAC14_CRDA_n_CRDA (0xFFFFFFFFuL) + +#define DMAC14_CRTB_n_CRTB (0xFFFFFFFFuL) + +#define DMAC14_CHSTAT_n_EN (0x00000001uL) +#define DMAC14_CHSTAT_n_RQST (0x00000002uL) +#define DMAC14_CHSTAT_n_TACT (0x00000004uL) +#define DMAC14_CHSTAT_n_SUS (0x00000008uL) +#define DMAC14_CHSTAT_n_ER (0x00000010uL) +#define DMAC14_CHSTAT_n_END (0x00000020uL) +#define DMAC14_CHSTAT_n_TC (0x00000040uL) +#define DMAC14_CHSTAT_n_SR (0x00000080uL) +#define DMAC14_CHSTAT_n_DL (0x00000100uL) +#define DMAC14_CHSTAT_n_DW (0x00000200uL) +#define DMAC14_CHSTAT_n_DER (0x00000400uL) +#define DMAC14_CHSTAT_n_MODE (0x00000800uL) +#define DMAC14_CHSTAT_n_INTMSK (0x00010000uL) + +#define DMAC14_CHCTRL_n_SETEN (0x00000001uL) +#define DMAC14_CHCTRL_n_CLREN (0x00000002uL) +#define DMAC14_CHCTRL_n_STG (0x00000004uL) +#define DMAC14_CHCTRL_n_SWRST (0x00000008uL) +#define DMAC14_CHCTRL_n_CLRRQ (0x00000010uL) +#define DMAC14_CHCTRL_n_CLREND (0x00000020uL) +#define DMAC14_CHCTRL_n_CLRTC (0x00000040uL) +#define DMAC14_CHCTRL_n_SETSUS (0x00000100uL) +#define DMAC14_CHCTRL_n_CLRSUS (0x00000200uL) +#define DMAC14_CHCTRL_n_SETINTMSK (0x00010000uL) +#define DMAC14_CHCTRL_n_CLRINTMSK (0x00020000uL) + +#define DMAC14_CHCFG_n_SEL (0x00000007uL) +#define DMAC14_CHCFG_n_REQD (0x00000008uL) +#define DMAC14_CHCFG_n_LOEN (0x00000010uL) +#define DMAC14_CHCFG_n_HIEN (0x00000020uL) +#define DMAC14_CHCFG_n_LVL (0x00000040uL) +#define DMAC14_CHCFG_n_AM (0x00000700uL) +#define DMAC14_CHCFG_n_SDS (0x0000F000uL) +#define DMAC14_CHCFG_n_DDS (0x000F0000uL) +#define DMAC14_CHCFG_n_SAD (0x00100000uL) +#define DMAC14_CHCFG_n_DAD (0x00200000uL) +#define DMAC14_CHCFG_n_TM (0x00400000uL) +#define DMAC14_CHCFG_n_DEM (0x01000000uL) +#define DMAC14_CHCFG_n_TCM (0x02000000uL) +#define DMAC14_CHCFG_n_SBE (0x08000000uL) +#define DMAC14_CHCFG_n_RSEL (0x10000000uL) +#define DMAC14_CHCFG_n_RSW (0x20000000uL) +#define DMAC14_CHCFG_n_REN (0x40000000uL) +#define DMAC14_CHCFG_n_DMS (0x80000000uL) + +#define DMAC14_CHITVL_n_ITVL (0x0000FFFFuL) + +#define DMAC14_CHEXT_n_SCA (0x000000F0uL) +#define DMAC14_CHEXT_n_DCA (0x0000F000uL) + +#define DMAC14_NXLA_n_NXLA (0xFFFFFFFFuL) + +#define DMAC14_CRLA_n_CRLA (0xFFFFFFFFuL) + +/* ---- DMAC15 ---- */ +#define DMAC15_N0SA_n_SA (0xFFFFFFFFuL) + +#define DMAC15_N0DA_n_DA (0xFFFFFFFFuL) + +#define DMAC15_N0TB_n_TB (0xFFFFFFFFuL) + +#define DMAC15_N1SA_n_SA (0xFFFFFFFFuL) + +#define DMAC15_N1DA_n_DA (0xFFFFFFFFuL) + +#define DMAC15_N1TB_n_TB (0xFFFFFFFFuL) + +#define DMAC15_CRSA_n_CRSA (0xFFFFFFFFuL) + +#define DMAC15_CRDA_n_CRDA (0xFFFFFFFFuL) + +#define DMAC15_CRTB_n_CRTB (0xFFFFFFFFuL) + +#define DMAC15_CHSTAT_n_EN (0x00000001uL) +#define DMAC15_CHSTAT_n_RQST (0x00000002uL) +#define DMAC15_CHSTAT_n_TACT (0x00000004uL) +#define DMAC15_CHSTAT_n_SUS (0x00000008uL) +#define DMAC15_CHSTAT_n_ER (0x00000010uL) +#define DMAC15_CHSTAT_n_END (0x00000020uL) +#define DMAC15_CHSTAT_n_TC (0x00000040uL) +#define DMAC15_CHSTAT_n_SR (0x00000080uL) +#define DMAC15_CHSTAT_n_DL (0x00000100uL) +#define DMAC15_CHSTAT_n_DW (0x00000200uL) +#define DMAC15_CHSTAT_n_DER (0x00000400uL) +#define DMAC15_CHSTAT_n_MODE (0x00000800uL) +#define DMAC15_CHSTAT_n_INTMSK (0x00010000uL) + +#define DMAC15_CHCTRL_n_SETEN (0x00000001uL) +#define DMAC15_CHCTRL_n_CLREN (0x00000002uL) +#define DMAC15_CHCTRL_n_STG (0x00000004uL) +#define DMAC15_CHCTRL_n_SWRST (0x00000008uL) +#define DMAC15_CHCTRL_n_CLRRQ (0x00000010uL) +#define DMAC15_CHCTRL_n_CLREND (0x00000020uL) +#define DMAC15_CHCTRL_n_CLRTC (0x00000040uL) +#define DMAC15_CHCTRL_n_SETSUS (0x00000100uL) +#define DMAC15_CHCTRL_n_CLRSUS (0x00000200uL) +#define DMAC15_CHCTRL_n_SETINTMSK (0x00010000uL) +#define DMAC15_CHCTRL_n_CLRINTMSK (0x00020000uL) + +#define DMAC15_CHCFG_n_SEL (0x00000007uL) +#define DMAC15_CHCFG_n_REQD (0x00000008uL) +#define DMAC15_CHCFG_n_LOEN (0x00000010uL) +#define DMAC15_CHCFG_n_HIEN (0x00000020uL) +#define DMAC15_CHCFG_n_LVL (0x00000040uL) +#define DMAC15_CHCFG_n_AM (0x00000700uL) +#define DMAC15_CHCFG_n_SDS (0x0000F000uL) +#define DMAC15_CHCFG_n_DDS (0x000F0000uL) +#define DMAC15_CHCFG_n_SAD (0x00100000uL) +#define DMAC15_CHCFG_n_DAD (0x00200000uL) +#define DMAC15_CHCFG_n_TM (0x00400000uL) +#define DMAC15_CHCFG_n_DEM (0x01000000uL) +#define DMAC15_CHCFG_n_TCM (0x02000000uL) +#define DMAC15_CHCFG_n_SBE (0x08000000uL) +#define DMAC15_CHCFG_n_RSEL (0x10000000uL) +#define DMAC15_CHCFG_n_RSW (0x20000000uL) +#define DMAC15_CHCFG_n_REN (0x40000000uL) +#define DMAC15_CHCFG_n_DMS (0x80000000uL) + +#define DMAC15_CHITVL_n_ITVL (0x0000FFFFuL) + +#define DMAC15_CHEXT_n_SCA (0x000000F0uL) +#define DMAC15_CHEXT_n_DCA (0x0000F000uL) + +#define DMAC15_NXLA_n_NXLA (0xFFFFFFFFuL) + +#define DMAC15_CRLA_n_CRLA (0xFFFFFFFFuL) + +/* ---- DMAC8-15 ---- */ +#define DMAC815_DCTRL_8_15_PR (0x00000001uL) +#define DMAC815_DCTRL_8_15_LVINT (0x00000002uL) +#define DMAC815_DCTRL_8_15_LDCA (0x0000003CuL) +#define DMAC815_DCTRL_8_15_LWCA (0x00003C00uL) + +#define DMAC815_DSTAT_EN_8_15_EN8 (0x00000001uL) +#define DMAC815_DSTAT_EN_8_15_EN9 (0x00000002uL) +#define DMAC815_DSTAT_EN_8_15_EN10 (0x00000004uL) +#define DMAC815_DSTAT_EN_8_15_EN11 (0x00000008uL) +#define DMAC815_DSTAT_EN_8_15_EN12 (0x00000010uL) +#define DMAC815_DSTAT_EN_8_15_EN13 (0x00000020uL) +#define DMAC815_DSTAT_EN_8_15_EN14 (0x00000040uL) +#define DMAC815_DSTAT_EN_8_15_EN15 (0x00000080uL) + +#define DMAC815_DSTAT_ER_8_15_ER8 (0x00000001uL) +#define DMAC815_DSTAT_ER_8_15_ER9 (0x00000002uL) +#define DMAC815_DSTAT_ER_8_15_ER10 (0x00000004uL) +#define DMAC815_DSTAT_ER_8_15_ER11 (0x00000008uL) +#define DMAC815_DSTAT_ER_8_15_ER12 (0x00000010uL) +#define DMAC815_DSTAT_ER_8_15_ER13 (0x00000020uL) +#define DMAC815_DSTAT_ER_8_15_ER14 (0x00000040uL) +#define DMAC815_DSTAT_ER_8_15_ER15 (0x00000080uL) + +#define DMAC815_DSTAT_END_8_15_END8 (0x00000001uL) +#define DMAC815_DSTAT_END_8_15_END9 (0x00000002uL) +#define DMAC815_DSTAT_END_8_15_END10 (0x00000004uL) +#define DMAC815_DSTAT_END_8_15_END11 (0x00000008uL) +#define DMAC815_DSTAT_END_8_15_END12 (0x00000010uL) +#define DMAC815_DSTAT_END_8_15_END13 (0x00000020uL) +#define DMAC815_DSTAT_END_8_15_END14 (0x00000040uL) +#define DMAC815_DSTAT_END_8_15_END15 (0x00000080uL) + +#define DMAC815_DSTAT_TC_8_15_TC8 (0x00000001uL) +#define DMAC815_DSTAT_TC_8_15_TC9 (0x00000002uL) +#define DMAC815_DSTAT_TC_8_15_TC10 (0x00000004uL) +#define DMAC815_DSTAT_TC_8_15_TC11 (0x00000008uL) +#define DMAC815_DSTAT_TC_8_15_TC12 (0x00000010uL) +#define DMAC815_DSTAT_TC_8_15_TC13 (0x00000020uL) +#define DMAC815_DSTAT_TC_8_15_TC14 (0x00000040uL) +#define DMAC815_DSTAT_TC_8_15_TC15 (0x00000080uL) + +#define DMAC815_DSTAT_SUS_8_15_SUS8 (0x00000001uL) +#define DMAC815_DSTAT_SUS_8_15_SUS9 (0x00000002uL) +#define DMAC815_DSTAT_SUS_8_15_SUS10 (0x00000004uL) +#define DMAC815_DSTAT_SUS_8_15_SUS11 (0x00000008uL) +#define DMAC815_DSTAT_SUS_8_15_SUS12 (0x00000010uL) +#define DMAC815_DSTAT_SUS_8_15_SUS13 (0x00000020uL) +#define DMAC815_DSTAT_SUS_8_15_SUS14 (0x00000040uL) +#define DMAC815_DSTAT_SUS_8_15_SUS15 (0x00000080uL) + +/* ---- DMAC0-1 ---- */ +#define DMAC01_DMARS_CH0_RID (0x00000003uL) +#define DMAC01_DMARS_CH0_MID (0x000001FCuL) +#define DMAC01_DMARS_CH1_RID (0x00030000uL) +#define DMAC01_DMARS_CH1_MID (0x01FC0000uL) + +/* ---- DMAC2-3 ---- */ +#define DMAC23_DMARS_CH2_RID (0x00000003uL) +#define DMAC23_DMARS_CH2_MID (0x000001FCuL) +#define DMAC23_DMARS_CH3_RID (0x00030000uL) +#define DMAC23_DMARS_CH3_MID (0x01FC0000uL) + +/* ---- DMAC4-5 ---- */ +#define DMAC45_DMARS_CH4_RID (0x00000003uL) +#define DMAC45_DMARS_CH4_MID (0x000001FCuL) +#define DMAC45_DMARS_CH5_RID (0x00030000uL) +#define DMAC45_DMARS_CH5_MID (0x01FC0000uL) + +/* ---- DMAC6-7 ---- */ +#define DMAC67_DMARS_CH6_RID (0x00000003uL) +#define DMAC67_DMARS_CH6_MID (0x000001FCuL) +#define DMAC67_DMARS_CH7_RID (0x00030000uL) +#define DMAC67_DMARS_CH7_MID (0x01FC0000uL) + +/* ---- DMAC8-9 ---- */ +#define DMAC89_DMARS_CH8_RID (0x00000003uL) +#define DMAC89_DMARS_CH8_MID (0x000001FCuL) +#define DMAC89_DMARS_CH9_RID (0x00030000uL) +#define DMAC89_DMARS_CH9_MID (0x01FC0000uL) + +/* ---- DMAC10-11 ---- */ +#define DMAC1011_DMARS_CH10_RID (0x00000003uL) +#define DMAC1011_DMARS_CH10_MID (0x000001FCuL) +#define DMAC1011_DMARS_CH11_RID (0x00030000uL) +#define DMAC1011_DMARS_CH11_MID (0x01FC0000uL) + +/* ---- DMAC12-13 ---- */ +#define DMAC1213_DMARS_CH12_RID (0x00000003uL) +#define DMAC1213_DMARS_CH12_MID (0x000001FCuL) +#define DMAC1213_DMARS_CH13_RID (0x00030000uL) +#define DMAC1213_DMARS_CH13_MID (0x01FC0000uL) + +/* ---- DMAC14-15 ---- */ +#define DMAC1415_DMARS_CH14_RID (0x00000003uL) +#define DMAC1415_DMARS_CH14_MID (0x000001FCuL) +#define DMAC1415_DMARS_CH15_RID (0x00030000uL) +#define DMAC1415_DMARS_CH15_MID (0x01FC0000uL) + + +/* ==== Shift values for IO registers ==== */ +/* ---- DMAC0 ---- */ +#define DMAC0_N0SA_n_SA_SHIFT (0u) + +#define DMAC0_N0DA_n_DA_SHIFT (0u) + +#define DMAC0_N0TB_n_TB_SHIFT (0u) + +#define DMAC0_N1SA_n_SA_SHIFT (0u) + +#define DMAC0_N1DA_n_DA_SHIFT (0u) + +#define DMAC0_N1TB_n_TB_SHIFT (0u) + +#define DMAC0_CRSA_n_CRSA_SHIFT (0u) + +#define DMAC0_CRDA_n_CRDA_SHIFT (0u) + +#define DMAC0_CRTB_n_CRTB_SHIFT (0u) + +#define DMAC0_CHSTAT_n_EN_SHIFT (0u) +#define DMAC0_CHSTAT_n_RQST_SHIFT (1u) +#define DMAC0_CHSTAT_n_TACT_SHIFT (2u) +#define DMAC0_CHSTAT_n_SUS_SHIFT (3u) +#define DMAC0_CHSTAT_n_ER_SHIFT (4u) +#define DMAC0_CHSTAT_n_END_SHIFT (5u) +#define DMAC0_CHSTAT_n_TC_SHIFT (6u) +#define DMAC0_CHSTAT_n_SR_SHIFT (7u) +#define DMAC0_CHSTAT_n_DL_SHIFT (8u) +#define DMAC0_CHSTAT_n_DW_SHIFT (9u) +#define DMAC0_CHSTAT_n_DER_SHIFT (10u) +#define DMAC0_CHSTAT_n_MODE_SHIFT (11u) +#define DMAC0_CHSTAT_n_INTMSK_SHIFT (16u) + +#define DMAC0_CHCTRL_n_SETEN_SHIFT (0u) +#define DMAC0_CHCTRL_n_CLREN_SHIFT (1u) +#define DMAC0_CHCTRL_n_STG_SHIFT (2u) +#define DMAC0_CHCTRL_n_SWRST_SHIFT (3u) +#define DMAC0_CHCTRL_n_CLRRQ_SHIFT (4u) +#define DMAC0_CHCTRL_n_CLREND_SHIFT (5u) +#define DMAC0_CHCTRL_n_CLRTC_SHIFT (6u) +#define DMAC0_CHCTRL_n_SETSUS_SHIFT (8u) +#define DMAC0_CHCTRL_n_CLRSUS_SHIFT (9u) +#define DMAC0_CHCTRL_n_SETINTMSK_SHIFT (16u) +#define DMAC0_CHCTRL_n_CLRINTMSK_SHIFT (17u) + +#define DMAC0_CHCFG_n_SEL_SHIFT (0u) +#define DMAC0_CHCFG_n_REQD_SHIFT (3u) +#define DMAC0_CHCFG_n_LOEN_SHIFT (4u) +#define DMAC0_CHCFG_n_HIEN_SHIFT (5u) +#define DMAC0_CHCFG_n_LVL_SHIFT (6u) +#define DMAC0_CHCFG_n_AM_SHIFT (8u) +#define DMAC0_CHCFG_n_SDS_SHIFT (12u) +#define DMAC0_CHCFG_n_DDS_SHIFT (16u) +#define DMAC0_CHCFG_n_SAD_SHIFT (20u) +#define DMAC0_CHCFG_n_DAD_SHIFT (21u) +#define DMAC0_CHCFG_n_TM_SHIFT (22u) +#define DMAC0_CHCFG_n_DEM_SHIFT (24u) +#define DMAC0_CHCFG_n_TCM_SHIFT (25u) +#define DMAC0_CHCFG_n_SBE_SHIFT (27u) +#define DMAC0_CHCFG_n_RSEL_SHIFT (28u) +#define DMAC0_CHCFG_n_RSW_SHIFT (29u) +#define DMAC0_CHCFG_n_REN_SHIFT (30u) +#define DMAC0_CHCFG_n_DMS_SHIFT (31u) + +#define DMAC0_CHITVL_n_ITVL_SHIFT (0u) + +#define DMAC0_CHEXT_n_SCA_SHIFT (4u) +#define DMAC0_CHEXT_n_DCA_SHIFT (12u) + +#define DMAC0_NXLA_n_NXLA_SHIFT (0u) + +#define DMAC0_CRLA_n_CRLA_SHIFT (0u) + +/* ---- DMAC1 ---- */ +#define DMAC1_N0SA_n_SA_SHIFT (0u) + +#define DMAC1_N0DA_n_DA_SHIFT (0u) + +#define DMAC1_N0TB_n_TB_SHIFT (0u) + +#define DMAC1_N1SA_n_SA_SHIFT (0u) + +#define DMAC1_N1DA_n_DA_SHIFT (0u) + +#define DMAC1_N1TB_n_TB_SHIFT (0u) + +#define DMAC1_CRSA_n_CRSA_SHIFT (0u) + +#define DMAC1_CRDA_n_CRDA_SHIFT (0u) + +#define DMAC1_CRTB_n_CRTB_SHIFT (0u) + +#define DMAC1_CHSTAT_n_EN_SHIFT (0u) +#define DMAC1_CHSTAT_n_RQST_SHIFT (1u) +#define DMAC1_CHSTAT_n_TACT_SHIFT (2u) +#define DMAC1_CHSTAT_n_SUS_SHIFT (3u) +#define DMAC1_CHSTAT_n_ER_SHIFT (4u) +#define DMAC1_CHSTAT_n_END_SHIFT (5u) +#define DMAC1_CHSTAT_n_TC_SHIFT (6u) +#define DMAC1_CHSTAT_n_SR_SHIFT (7u) +#define DMAC1_CHSTAT_n_DL_SHIFT (8u) +#define DMAC1_CHSTAT_n_DW_SHIFT (9u) +#define DMAC1_CHSTAT_n_DER_SHIFT (10u) +#define DMAC1_CHSTAT_n_MODE_SHIFT (11u) +#define DMAC1_CHSTAT_n_INTMSK_SHIFT (16u) + +#define DMAC1_CHCTRL_n_SETEN_SHIFT (0u) +#define DMAC1_CHCTRL_n_CLREN_SHIFT (1u) +#define DMAC1_CHCTRL_n_STG_SHIFT (2u) +#define DMAC1_CHCTRL_n_SWRST_SHIFT (3u) +#define DMAC1_CHCTRL_n_CLRRQ_SHIFT (4u) +#define DMAC1_CHCTRL_n_CLREND_SHIFT (5u) +#define DMAC1_CHCTRL_n_CLRTC_SHIFT (6u) +#define DMAC1_CHCTRL_n_SETSUS_SHIFT (8u) +#define DMAC1_CHCTRL_n_CLRSUS_SHIFT (9u) +#define DMAC1_CHCTRL_n_SETINTMSK_SHIFT (16u) +#define DMAC1_CHCTRL_n_CLRINTMSK_SHIFT (17u) + +#define DMAC1_CHCFG_n_SEL_SHIFT (0u) +#define DMAC1_CHCFG_n_REQD_SHIFT (3u) +#define DMAC1_CHCFG_n_LOEN_SHIFT (4u) +#define DMAC1_CHCFG_n_HIEN_SHIFT (5u) +#define DMAC1_CHCFG_n_LVL_SHIFT (6u) +#define DMAC1_CHCFG_n_AM_SHIFT (8u) +#define DMAC1_CHCFG_n_SDS_SHIFT (12u) +#define DMAC1_CHCFG_n_DDS_SHIFT (16u) +#define DMAC1_CHCFG_n_SAD_SHIFT (20u) +#define DMAC1_CHCFG_n_DAD_SHIFT (21u) +#define DMAC1_CHCFG_n_TM_SHIFT (22u) +#define DMAC1_CHCFG_n_DEM_SHIFT (24u) +#define DMAC1_CHCFG_n_TCM_SHIFT (25u) +#define DMAC1_CHCFG_n_SBE_SHIFT (27u) +#define DMAC1_CHCFG_n_RSEL_SHIFT (28u) +#define DMAC1_CHCFG_n_RSW_SHIFT (29u) +#define DMAC1_CHCFG_n_REN_SHIFT (30u) +#define DMAC1_CHCFG_n_DMS_SHIFT (31u) + +#define DMAC1_CHITVL_n_ITVL_SHIFT (0u) + +#define DMAC1_CHEXT_n_SCA_SHIFT (4u) +#define DMAC1_CHEXT_n_DCA_SHIFT (12u) + +#define DMAC1_NXLA_n_NXLA_SHIFT (0u) + +#define DMAC1_CRLA_n_CRLA_SHIFT (0u) + +/* ---- DMAC2 ---- */ +#define DMAC2_N0SA_n_SA_SHIFT (0u) + +#define DMAC2_N0DA_n_DA_SHIFT (0u) + +#define DMAC2_N0TB_n_TB_SHIFT (0u) + +#define DMAC2_N1SA_n_SA_SHIFT (0u) + +#define DMAC2_N1DA_n_DA_SHIFT (0u) + +#define DMAC2_N1TB_n_TB_SHIFT (0u) + +#define DMAC2_CRSA_n_CRSA_SHIFT (0u) + +#define DMAC2_CRDA_n_CRDA_SHIFT (0u) + +#define DMAC2_CRTB_n_CRTB_SHIFT (0u) + +#define DMAC2_CHSTAT_n_EN_SHIFT (0u) +#define DMAC2_CHSTAT_n_RQST_SHIFT (1u) +#define DMAC2_CHSTAT_n_TACT_SHIFT (2u) +#define DMAC2_CHSTAT_n_SUS_SHIFT (3u) +#define DMAC2_CHSTAT_n_ER_SHIFT (4u) +#define DMAC2_CHSTAT_n_END_SHIFT (5u) +#define DMAC2_CHSTAT_n_TC_SHIFT (6u) +#define DMAC2_CHSTAT_n_SR_SHIFT (7u) +#define DMAC2_CHSTAT_n_DL_SHIFT (8u) +#define DMAC2_CHSTAT_n_DW_SHIFT (9u) +#define DMAC2_CHSTAT_n_DER_SHIFT (10u) +#define DMAC2_CHSTAT_n_MODE_SHIFT (11u) +#define DMAC2_CHSTAT_n_INTMSK_SHIFT (16u) + +#define DMAC2_CHCTRL_n_SETEN_SHIFT (0u) +#define DMAC2_CHCTRL_n_CLREN_SHIFT (1u) +#define DMAC2_CHCTRL_n_STG_SHIFT (2u) +#define DMAC2_CHCTRL_n_SWRST_SHIFT (3u) +#define DMAC2_CHCTRL_n_CLRRQ_SHIFT (4u) +#define DMAC2_CHCTRL_n_CLREND_SHIFT (5u) +#define DMAC2_CHCTRL_n_CLRTC_SHIFT (6u) +#define DMAC2_CHCTRL_n_SETSUS_SHIFT (8u) +#define DMAC2_CHCTRL_n_CLRSUS_SHIFT (9u) +#define DMAC2_CHCTRL_n_SETINTMSK_SHIFT (16u) +#define DMAC2_CHCTRL_n_CLRINTMSK_SHIFT (17u) + +#define DMAC2_CHCFG_n_SEL_SHIFT (0u) +#define DMAC2_CHCFG_n_REQD_SHIFT (3u) +#define DMAC2_CHCFG_n_LOEN_SHIFT (4u) +#define DMAC2_CHCFG_n_HIEN_SHIFT (5u) +#define DMAC2_CHCFG_n_LVL_SHIFT (6u) +#define DMAC2_CHCFG_n_AM_SHIFT (8u) +#define DMAC2_CHCFG_n_SDS_SHIFT (12u) +#define DMAC2_CHCFG_n_DDS_SHIFT (16u) +#define DMAC2_CHCFG_n_SAD_SHIFT (20u) +#define DMAC2_CHCFG_n_DAD_SHIFT (21u) +#define DMAC2_CHCFG_n_TM_SHIFT (22u) +#define DMAC2_CHCFG_n_DEM_SHIFT (24u) +#define DMAC2_CHCFG_n_TCM_SHIFT (25u) +#define DMAC2_CHCFG_n_SBE_SHIFT (27u) +#define DMAC2_CHCFG_n_RSEL_SHIFT (28u) +#define DMAC2_CHCFG_n_RSW_SHIFT (29u) +#define DMAC2_CHCFG_n_REN_SHIFT (30u) +#define DMAC2_CHCFG_n_DMS_SHIFT (31u) + +#define DMAC2_CHITVL_n_ITVL_SHIFT (0u) + +#define DMAC2_CHEXT_n_SCA_SHIFT (4u) +#define DMAC2_CHEXT_n_DCA_SHIFT (12u) + +#define DMAC2_NXLA_n_NXLA_SHIFT (0u) + +#define DMAC2_CRLA_n_CRLA_SHIFT (0u) + +/* ---- DMAC3 ---- */ +#define DMAC3_N0SA_n_SA_SHIFT (0u) + +#define DMAC3_N0DA_n_DA_SHIFT (0u) + +#define DMAC3_N0TB_n_TB_SHIFT (0u) + +#define DMAC3_N1SA_n_SA_SHIFT (0u) + +#define DMAC3_N1DA_n_DA_SHIFT (0u) + +#define DMAC3_N1TB_n_TB_SHIFT (0u) + +#define DMAC3_CRSA_n_CRSA_SHIFT (0u) + +#define DMAC3_CRDA_n_CRDA_SHIFT (0u) + +#define DMAC3_CRTB_n_CRTB_SHIFT (0u) + +#define DMAC3_CHSTAT_n_EN_SHIFT (0u) +#define DMAC3_CHSTAT_n_RQST_SHIFT (1u) +#define DMAC3_CHSTAT_n_TACT_SHIFT (2u) +#define DMAC3_CHSTAT_n_SUS_SHIFT (3u) +#define DMAC3_CHSTAT_n_ER_SHIFT (4u) +#define DMAC3_CHSTAT_n_END_SHIFT (5u) +#define DMAC3_CHSTAT_n_TC_SHIFT (6u) +#define DMAC3_CHSTAT_n_SR_SHIFT (7u) +#define DMAC3_CHSTAT_n_DL_SHIFT (8u) +#define DMAC3_CHSTAT_n_DW_SHIFT (9u) +#define DMAC3_CHSTAT_n_DER_SHIFT (10u) +#define DMAC3_CHSTAT_n_MODE_SHIFT (11u) +#define DMAC3_CHSTAT_n_INTMSK_SHIFT (16u) + +#define DMAC3_CHCTRL_n_SETEN_SHIFT (0u) +#define DMAC3_CHCTRL_n_CLREN_SHIFT (1u) +#define DMAC3_CHCTRL_n_STG_SHIFT (2u) +#define DMAC3_CHCTRL_n_SWRST_SHIFT (3u) +#define DMAC3_CHCTRL_n_CLRRQ_SHIFT (4u) +#define DMAC3_CHCTRL_n_CLREND_SHIFT (5u) +#define DMAC3_CHCTRL_n_CLRTC_SHIFT (6u) +#define DMAC3_CHCTRL_n_SETSUS_SHIFT (8u) +#define DMAC3_CHCTRL_n_CLRSUS_SHIFT (9u) +#define DMAC3_CHCTRL_n_SETINTMSK_SHIFT (16u) +#define DMAC3_CHCTRL_n_CLRINTMSK_SHIFT (17u) + +#define DMAC3_CHCFG_n_SEL_SHIFT (0u) +#define DMAC3_CHCFG_n_REQD_SHIFT (3u) +#define DMAC3_CHCFG_n_LOEN_SHIFT (4u) +#define DMAC3_CHCFG_n_HIEN_SHIFT (5u) +#define DMAC3_CHCFG_n_LVL_SHIFT (6u) +#define DMAC3_CHCFG_n_AM_SHIFT (8u) +#define DMAC3_CHCFG_n_SDS_SHIFT (12u) +#define DMAC3_CHCFG_n_DDS_SHIFT (16u) +#define DMAC3_CHCFG_n_SAD_SHIFT (20u) +#define DMAC3_CHCFG_n_DAD_SHIFT (21u) +#define DMAC3_CHCFG_n_TM_SHIFT (22u) +#define DMAC3_CHCFG_n_DEM_SHIFT (24u) +#define DMAC3_CHCFG_n_TCM_SHIFT (25u) +#define DMAC3_CHCFG_n_SBE_SHIFT (27u) +#define DMAC3_CHCFG_n_RSEL_SHIFT (28u) +#define DMAC3_CHCFG_n_RSW_SHIFT (29u) +#define DMAC3_CHCFG_n_REN_SHIFT (30u) +#define DMAC3_CHCFG_n_DMS_SHIFT (31u) + +#define DMAC3_CHITVL_n_ITVL_SHIFT (0u) + +#define DMAC3_CHEXT_n_SCA_SHIFT (4u) +#define DMAC3_CHEXT_n_DCA_SHIFT (12u) + +#define DMAC3_NXLA_n_NXLA_SHIFT (0u) + +#define DMAC3_CRLA_n_CRLA_SHIFT (0u) + +/* ---- DMAC4 ---- */ +#define DMAC4_N0SA_n_SA_SHIFT (0u) + +#define DMAC4_N0DA_n_DA_SHIFT (0u) + +#define DMAC4_N0TB_n_TB_SHIFT (0u) + +#define DMAC4_N1SA_n_SA_SHIFT (0u) + +#define DMAC4_N1DA_n_DA_SHIFT (0u) + +#define DMAC4_N1TB_n_TB_SHIFT (0u) + +#define DMAC4_CRSA_n_CRSA_SHIFT (0u) + +#define DMAC4_CRDA_n_CRDA_SHIFT (0u) + +#define DMAC4_CRTB_n_CRTB_SHIFT (0u) + +#define DMAC4_CHSTAT_n_EN_SHIFT (0u) +#define DMAC4_CHSTAT_n_RQST_SHIFT (1u) +#define DMAC4_CHSTAT_n_TACT_SHIFT (2u) +#define DMAC4_CHSTAT_n_SUS_SHIFT (3u) +#define DMAC4_CHSTAT_n_ER_SHIFT (4u) +#define DMAC4_CHSTAT_n_END_SHIFT (5u) +#define DMAC4_CHSTAT_n_TC_SHIFT (6u) +#define DMAC4_CHSTAT_n_SR_SHIFT (7u) +#define DMAC4_CHSTAT_n_DL_SHIFT (8u) +#define DMAC4_CHSTAT_n_DW_SHIFT (9u) +#define DMAC4_CHSTAT_n_DER_SHIFT (10u) +#define DMAC4_CHSTAT_n_MODE_SHIFT (11u) +#define DMAC4_CHSTAT_n_INTMSK_SHIFT (16u) + +#define DMAC4_CHCTRL_n_SETEN_SHIFT (0u) +#define DMAC4_CHCTRL_n_CLREN_SHIFT (1u) +#define DMAC4_CHCTRL_n_STG_SHIFT (2u) +#define DMAC4_CHCTRL_n_SWRST_SHIFT (3u) +#define DMAC4_CHCTRL_n_CLRRQ_SHIFT (4u) +#define DMAC4_CHCTRL_n_CLREND_SHIFT (5u) +#define DMAC4_CHCTRL_n_CLRTC_SHIFT (6u) +#define DMAC4_CHCTRL_n_SETSUS_SHIFT (8u) +#define DMAC4_CHCTRL_n_CLRSUS_SHIFT (9u) +#define DMAC4_CHCTRL_n_SETINTMSK_SHIFT (16u) +#define DMAC4_CHCTRL_n_CLRINTMSK_SHIFT (17u) + +#define DMAC4_CHCFG_n_SEL_SHIFT (0u) +#define DMAC4_CHCFG_n_REQD_SHIFT (3u) +#define DMAC4_CHCFG_n_LOEN_SHIFT (4u) +#define DMAC4_CHCFG_n_HIEN_SHIFT (5u) +#define DMAC4_CHCFG_n_LVL_SHIFT (6u) +#define DMAC4_CHCFG_n_AM_SHIFT (8u) +#define DMAC4_CHCFG_n_SDS_SHIFT (12u) +#define DMAC4_CHCFG_n_DDS_SHIFT (16u) +#define DMAC4_CHCFG_n_SAD_SHIFT (20u) +#define DMAC4_CHCFG_n_DAD_SHIFT (21u) +#define DMAC4_CHCFG_n_TM_SHIFT (22u) +#define DMAC4_CHCFG_n_DEM_SHIFT (24u) +#define DMAC4_CHCFG_n_TCM_SHIFT (25u) +#define DMAC4_CHCFG_n_SBE_SHIFT (27u) +#define DMAC4_CHCFG_n_RSEL_SHIFT (28u) +#define DMAC4_CHCFG_n_RSW_SHIFT (29u) +#define DMAC4_CHCFG_n_REN_SHIFT (30u) +#define DMAC4_CHCFG_n_DMS_SHIFT (31u) + +#define DMAC4_CHITVL_n_ITVL_SHIFT (0u) + +#define DMAC4_CHEXT_n_SCA_SHIFT (4u) +#define DMAC4_CHEXT_n_DCA_SHIFT (12u) + +#define DMAC4_NXLA_n_NXLA_SHIFT (0u) + +#define DMAC4_CRLA_n_CRLA_SHIFT (0u) + +/* ---- DMAC5 ---- */ +#define DMAC5_N0SA_n_SA_SHIFT (0u) + +#define DMAC5_N0DA_n_DA_SHIFT (0u) + +#define DMAC5_N0TB_n_TB_SHIFT (0u) + +#define DMAC5_N1SA_n_SA_SHIFT (0u) + +#define DMAC5_N1DA_n_DA_SHIFT (0u) + +#define DMAC5_N1TB_n_TB_SHIFT (0u) + +#define DMAC5_CRSA_n_CRSA_SHIFT (0u) + +#define DMAC5_CRDA_n_CRDA_SHIFT (0u) + +#define DMAC5_CRTB_n_CRTB_SHIFT (0u) + +#define DMAC5_CHSTAT_n_EN_SHIFT (0u) +#define DMAC5_CHSTAT_n_RQST_SHIFT (1u) +#define DMAC5_CHSTAT_n_TACT_SHIFT (2u) +#define DMAC5_CHSTAT_n_SUS_SHIFT (3u) +#define DMAC5_CHSTAT_n_ER_SHIFT (4u) +#define DMAC5_CHSTAT_n_END_SHIFT (5u) +#define DMAC5_CHSTAT_n_TC_SHIFT (6u) +#define DMAC5_CHSTAT_n_SR_SHIFT (7u) +#define DMAC5_CHSTAT_n_DL_SHIFT (8u) +#define DMAC5_CHSTAT_n_DW_SHIFT (9u) +#define DMAC5_CHSTAT_n_DER_SHIFT (10u) +#define DMAC5_CHSTAT_n_MODE_SHIFT (11u) +#define DMAC5_CHSTAT_n_INTMSK_SHIFT (16u) + +#define DMAC5_CHCTRL_n_SETEN_SHIFT (0u) +#define DMAC5_CHCTRL_n_CLREN_SHIFT (1u) +#define DMAC5_CHCTRL_n_STG_SHIFT (2u) +#define DMAC5_CHCTRL_n_SWRST_SHIFT (3u) +#define DMAC5_CHCTRL_n_CLRRQ_SHIFT (4u) +#define DMAC5_CHCTRL_n_CLREND_SHIFT (5u) +#define DMAC5_CHCTRL_n_CLRTC_SHIFT (6u) +#define DMAC5_CHCTRL_n_SETSUS_SHIFT (8u) +#define DMAC5_CHCTRL_n_CLRSUS_SHIFT (9u) +#define DMAC5_CHCTRL_n_SETINTMSK_SHIFT (16u) +#define DMAC5_CHCTRL_n_CLRINTMSK_SHIFT (17u) + +#define DMAC5_CHCFG_n_SEL_SHIFT (0u) +#define DMAC5_CHCFG_n_REQD_SHIFT (3u) +#define DMAC5_CHCFG_n_LOEN_SHIFT (4u) +#define DMAC5_CHCFG_n_HIEN_SHIFT (5u) +#define DMAC5_CHCFG_n_LVL_SHIFT (6u) +#define DMAC5_CHCFG_n_AM_SHIFT (8u) +#define DMAC5_CHCFG_n_SDS_SHIFT (12u) +#define DMAC5_CHCFG_n_DDS_SHIFT (16u) +#define DMAC5_CHCFG_n_SAD_SHIFT (20u) +#define DMAC5_CHCFG_n_DAD_SHIFT (21u) +#define DMAC5_CHCFG_n_TM_SHIFT (22u) +#define DMAC5_CHCFG_n_DEM_SHIFT (24u) +#define DMAC5_CHCFG_n_TCM_SHIFT (25u) +#define DMAC5_CHCFG_n_SBE_SHIFT (27u) +#define DMAC5_CHCFG_n_RSEL_SHIFT (28u) +#define DMAC5_CHCFG_n_RSW_SHIFT (29u) +#define DMAC5_CHCFG_n_REN_SHIFT (30u) +#define DMAC5_CHCFG_n_DMS_SHIFT (31u) + +#define DMAC5_CHITVL_n_ITVL_SHIFT (0u) + +#define DMAC5_CHEXT_n_SCA_SHIFT (4u) +#define DMAC5_CHEXT_n_DCA_SHIFT (12u) + +#define DMAC5_NXLA_n_NXLA_SHIFT (0u) + +#define DMAC5_CRLA_n_CRLA_SHIFT (0u) + +/* ---- DMAC6 ---- */ +#define DMAC6_N0SA_n_SA_SHIFT (0u) + +#define DMAC6_N0DA_n_DA_SHIFT (0u) + +#define DMAC6_N0TB_n_TB_SHIFT (0u) + +#define DMAC6_N1SA_n_SA_SHIFT (0u) + +#define DMAC6_N1DA_n_DA_SHIFT (0u) + +#define DMAC6_N1TB_n_TB_SHIFT (0u) + +#define DMAC6_CRSA_n_CRSA_SHIFT (0u) + +#define DMAC6_CRDA_n_CRDA_SHIFT (0u) + +#define DMAC6_CRTB_n_CRTB_SHIFT (0u) + +#define DMAC6_CHSTAT_n_EN_SHIFT (0u) +#define DMAC6_CHSTAT_n_RQST_SHIFT (1u) +#define DMAC6_CHSTAT_n_TACT_SHIFT (2u) +#define DMAC6_CHSTAT_n_SUS_SHIFT (3u) +#define DMAC6_CHSTAT_n_ER_SHIFT (4u) +#define DMAC6_CHSTAT_n_END_SHIFT (5u) +#define DMAC6_CHSTAT_n_TC_SHIFT (6u) +#define DMAC6_CHSTAT_n_SR_SHIFT (7u) +#define DMAC6_CHSTAT_n_DL_SHIFT (8u) +#define DMAC6_CHSTAT_n_DW_SHIFT (9u) +#define DMAC6_CHSTAT_n_DER_SHIFT (10u) +#define DMAC6_CHSTAT_n_MODE_SHIFT (11u) +#define DMAC6_CHSTAT_n_INTMSK_SHIFT (16u) + +#define DMAC6_CHCTRL_n_SETEN_SHIFT (0u) +#define DMAC6_CHCTRL_n_CLREN_SHIFT (1u) +#define DMAC6_CHCTRL_n_STG_SHIFT (2u) +#define DMAC6_CHCTRL_n_SWRST_SHIFT (3u) +#define DMAC6_CHCTRL_n_CLRRQ_SHIFT (4u) +#define DMAC6_CHCTRL_n_CLREND_SHIFT (5u) +#define DMAC6_CHCTRL_n_CLRTC_SHIFT (6u) +#define DMAC6_CHCTRL_n_SETSUS_SHIFT (8u) +#define DMAC6_CHCTRL_n_CLRSUS_SHIFT (9u) +#define DMAC6_CHCTRL_n_SETINTMSK_SHIFT (16u) +#define DMAC6_CHCTRL_n_CLRINTMSK_SHIFT (17u) + +#define DMAC6_CHCFG_n_SEL_SHIFT (0u) +#define DMAC6_CHCFG_n_REQD_SHIFT (3u) +#define DMAC6_CHCFG_n_LOEN_SHIFT (4u) +#define DMAC6_CHCFG_n_HIEN_SHIFT (5u) +#define DMAC6_CHCFG_n_LVL_SHIFT (6u) +#define DMAC6_CHCFG_n_AM_SHIFT (8u) +#define DMAC6_CHCFG_n_SDS_SHIFT (12u) +#define DMAC6_CHCFG_n_DDS_SHIFT (16u) +#define DMAC6_CHCFG_n_SAD_SHIFT (20u) +#define DMAC6_CHCFG_n_DAD_SHIFT (21u) +#define DMAC6_CHCFG_n_TM_SHIFT (22u) +#define DMAC6_CHCFG_n_DEM_SHIFT (24u) +#define DMAC6_CHCFG_n_TCM_SHIFT (25u) +#define DMAC6_CHCFG_n_SBE_SHIFT (27u) +#define DMAC6_CHCFG_n_RSEL_SHIFT (28u) +#define DMAC6_CHCFG_n_RSW_SHIFT (29u) +#define DMAC6_CHCFG_n_REN_SHIFT (30u) +#define DMAC6_CHCFG_n_DMS_SHIFT (31u) + +#define DMAC6_CHITVL_n_ITVL_SHIFT (0u) + +#define DMAC6_CHEXT_n_SCA_SHIFT (4u) +#define DMAC6_CHEXT_n_DCA_SHIFT (12u) + +#define DMAC6_NXLA_n_NXLA_SHIFT (0u) + +#define DMAC6_CRLA_n_CRLA_SHIFT (0u) + +/* ---- DMAC7 ---- */ +#define DMAC7_N0SA_n_SA_SHIFT (0u) + +#define DMAC7_N0DA_n_DA_SHIFT (0u) + +#define DMAC7_N0TB_n_TB_SHIFT (0u) + +#define DMAC7_N1SA_n_SA_SHIFT (0u) + +#define DMAC7_N1DA_n_DA_SHIFT (0u) + +#define DMAC7_N1TB_n_TB_SHIFT (0u) + +#define DMAC7_CRSA_n_CRSA_SHIFT (0u) + +#define DMAC7_CRDA_n_CRDA_SHIFT (0u) + +#define DMAC7_CRTB_n_CRTB_SHIFT (0u) + +#define DMAC7_CHSTAT_n_EN_SHIFT (0u) +#define DMAC7_CHSTAT_n_RQST_SHIFT (1u) +#define DMAC7_CHSTAT_n_TACT_SHIFT (2u) +#define DMAC7_CHSTAT_n_SUS_SHIFT (3u) +#define DMAC7_CHSTAT_n_ER_SHIFT (4u) +#define DMAC7_CHSTAT_n_END_SHIFT (5u) +#define DMAC7_CHSTAT_n_TC_SHIFT (6u) +#define DMAC7_CHSTAT_n_SR_SHIFT (7u) +#define DMAC7_CHSTAT_n_DL_SHIFT (8u) +#define DMAC7_CHSTAT_n_DW_SHIFT (9u) +#define DMAC7_CHSTAT_n_DER_SHIFT (10u) +#define DMAC7_CHSTAT_n_MODE_SHIFT (11u) +#define DMAC7_CHSTAT_n_INTMSK_SHIFT (16u) + +#define DMAC7_CHCTRL_n_SETEN_SHIFT (0u) +#define DMAC7_CHCTRL_n_CLREN_SHIFT (1u) +#define DMAC7_CHCTRL_n_STG_SHIFT (2u) +#define DMAC7_CHCTRL_n_SWRST_SHIFT (3u) +#define DMAC7_CHCTRL_n_CLRRQ_SHIFT (4u) +#define DMAC7_CHCTRL_n_CLREND_SHIFT (5u) +#define DMAC7_CHCTRL_n_CLRTC_SHIFT (6u) +#define DMAC7_CHCTRL_n_SETSUS_SHIFT (8u) +#define DMAC7_CHCTRL_n_CLRSUS_SHIFT (9u) +#define DMAC7_CHCTRL_n_SETINTMSK_SHIFT (16u) +#define DMAC7_CHCTRL_n_CLRINTMSK_SHIFT (17u) + +#define DMAC7_CHCFG_n_SEL_SHIFT (0u) +#define DMAC7_CHCFG_n_REQD_SHIFT (3u) +#define DMAC7_CHCFG_n_LOEN_SHIFT (4u) +#define DMAC7_CHCFG_n_HIEN_SHIFT (5u) +#define DMAC7_CHCFG_n_LVL_SHIFT (6u) +#define DMAC7_CHCFG_n_AM_SHIFT (8u) +#define DMAC7_CHCFG_n_SDS_SHIFT (12u) +#define DMAC7_CHCFG_n_DDS_SHIFT (16u) +#define DMAC7_CHCFG_n_SAD_SHIFT (20u) +#define DMAC7_CHCFG_n_DAD_SHIFT (21u) +#define DMAC7_CHCFG_n_TM_SHIFT (22u) +#define DMAC7_CHCFG_n_DEM_SHIFT (24u) +#define DMAC7_CHCFG_n_TCM_SHIFT (25u) +#define DMAC7_CHCFG_n_SBE_SHIFT (27u) +#define DMAC7_CHCFG_n_RSEL_SHIFT (28u) +#define DMAC7_CHCFG_n_RSW_SHIFT (29u) +#define DMAC7_CHCFG_n_REN_SHIFT (30u) +#define DMAC7_CHCFG_n_DMS_SHIFT (31u) + +#define DMAC7_CHITVL_n_ITVL_SHIFT (0u) + +#define DMAC7_CHEXT_n_SCA_SHIFT (4u) +#define DMAC7_CHEXT_n_DCA_SHIFT (12u) + +#define DMAC7_NXLA_n_NXLA_SHIFT (0u) + +#define DMAC7_CRLA_n_CRLA_SHIFT (0u) + +/* ---- DMAC0-7 ---- */ +#define DMAC07_DCTRL_0_7_PR_SHIFT (0u) +#define DMAC07_DCTRL_0_7_LVINT_SHIFT (1u) +#define DMAC07_DCTRL_0_7_LDCA_SHIFT (2u) +#define DMAC07_DCTRL_0_7_LWCA_SHIFT (6u) + +#define DMAC07_DSTAT_EN_0_7_EN0_SHIFT (0u) +#define DMAC07_DSTAT_EN_0_7_EN1_SHIFT (1u) +#define DMAC07_DSTAT_EN_0_7_EN2_SHIFT (2u) +#define DMAC07_DSTAT_EN_0_7_EN3_SHIFT (3u) +#define DMAC07_DSTAT_EN_0_7_EN4_SHIFT (4u) +#define DMAC07_DSTAT_EN_0_7_EN5_SHIFT (5u) +#define DMAC07_DSTAT_EN_0_7_EN6_SHIFT (6u) +#define DMAC07_DSTAT_EN_0_7_EN7_SHIFT (7u) + +#define DMAC07_DSTAT_ER_0_7_ER0_SHIFT (0u) +#define DMAC07_DSTAT_ER_0_7_ER1_SHIFT (1u) +#define DMAC07_DSTAT_ER_0_7_ER2_SHIFT (2u) +#define DMAC07_DSTAT_ER_0_7_ER3_SHIFT (3u) +#define DMAC07_DSTAT_ER_0_7_ER4_SHIFT (4u) +#define DMAC07_DSTAT_ER_0_7_ER5_SHIFT (5u) +#define DMAC07_DSTAT_ER_0_7_ER6_SHIFT (6u) +#define DMAC07_DSTAT_ER_0_7_ER7_SHIFT (7u) + +#define DMAC07_DSTAT_END_0_7_END0_SHIFT (0u) +#define DMAC07_DSTAT_END_0_7_END1_SHIFT (1u) +#define DMAC07_DSTAT_END_0_7_END2_SHIFT (2u) +#define DMAC07_DSTAT_END_0_7_END3_SHIFT (3u) +#define DMAC07_DSTAT_END_0_7_END4_SHIFT (4u) +#define DMAC07_DSTAT_END_0_7_END5_SHIFT (5u) +#define DMAC07_DSTAT_END_0_7_END6_SHIFT (6u) +#define DMAC07_DSTAT_END_0_7_END7_SHIFT (7u) + +#define DMAC07_DSTAT_TC_0_7_TC0_SHIFT (0u) +#define DMAC07_DSTAT_TC_0_7_TC1_SHIFT (1u) +#define DMAC07_DSTAT_TC_0_7_TC2_SHIFT (2u) +#define DMAC07_DSTAT_TC_0_7_TC3_SHIFT (3u) +#define DMAC07_DSTAT_TC_0_7_TC4_SHIFT (4u) +#define DMAC07_DSTAT_TC_0_7_TC5_SHIFT (5u) +#define DMAC07_DSTAT_TC_0_7_TC6_SHIFT (6u) +#define DMAC07_DSTAT_TC_0_7_TC7_SHIFT (7u) + +#define DMAC07_DSTAT_SUS_0_7_SUS0_SHIFT (0u) +#define DMAC07_DSTAT_SUS_0_7_SUS1_SHIFT (1u) +#define DMAC07_DSTAT_SUS_0_7_SUS2_SHIFT (2u) +#define DMAC07_DSTAT_SUS_0_7_SUS3_SHIFT (3u) +#define DMAC07_DSTAT_SUS_0_7_SUS4_SHIFT (4u) +#define DMAC07_DSTAT_SUS_0_7_SUS5_SHIFT (5u) +#define DMAC07_DSTAT_SUS_0_7_SUS6_SHIFT (6u) +#define DMAC07_DSTAT_SUS_0_7_SUS7_SHIFT (7u) + +/* ---- DMAC8 ---- */ +#define DMAC8_N0SA_n_SA_SHIFT (0u) + +#define DMAC8_N0DA_n_DA_SHIFT (0u) + +#define DMAC8_N0TB_n_TB_SHIFT (0u) + +#define DMAC8_N1SA_n_SA_SHIFT (0u) + +#define DMAC8_N1DA_n_DA_SHIFT (0u) + +#define DMAC8_N1TB_n_TB_SHIFT (0u) + +#define DMAC8_CRSA_n_CRSA_SHIFT (0u) + +#define DMAC8_CRDA_n_CRDA_SHIFT (0u) + +#define DMAC8_CRTB_n_CRTB_SHIFT (0u) + +#define DMAC8_CHSTAT_n_EN_SHIFT (0u) +#define DMAC8_CHSTAT_n_RQST_SHIFT (1u) +#define DMAC8_CHSTAT_n_TACT_SHIFT (2u) +#define DMAC8_CHSTAT_n_SUS_SHIFT (3u) +#define DMAC8_CHSTAT_n_ER_SHIFT (4u) +#define DMAC8_CHSTAT_n_END_SHIFT (5u) +#define DMAC8_CHSTAT_n_TC_SHIFT (6u) +#define DMAC8_CHSTAT_n_SR_SHIFT (7u) +#define DMAC8_CHSTAT_n_DL_SHIFT (8u) +#define DMAC8_CHSTAT_n_DW_SHIFT (9u) +#define DMAC8_CHSTAT_n_DER_SHIFT (10u) +#define DMAC8_CHSTAT_n_MODE_SHIFT (11u) +#define DMAC8_CHSTAT_n_INTMSK_SHIFT (16u) + +#define DMAC8_CHCTRL_n_SETEN_SHIFT (0u) +#define DMAC8_CHCTRL_n_CLREN_SHIFT (1u) +#define DMAC8_CHCTRL_n_STG_SHIFT (2u) +#define DMAC8_CHCTRL_n_SWRST_SHIFT (3u) +#define DMAC8_CHCTRL_n_CLRRQ_SHIFT (4u) +#define DMAC8_CHCTRL_n_CLREND_SHIFT (5u) +#define DMAC8_CHCTRL_n_CLRTC_SHIFT (6u) +#define DMAC8_CHCTRL_n_SETSUS_SHIFT (8u) +#define DMAC8_CHCTRL_n_CLRSUS_SHIFT (9u) +#define DMAC8_CHCTRL_n_SETINTMSK_SHIFT (16u) +#define DMAC8_CHCTRL_n_CLRINTMSK_SHIFT (17u) + +#define DMAC8_CHCFG_n_SEL_SHIFT (0u) +#define DMAC8_CHCFG_n_REQD_SHIFT (3u) +#define DMAC8_CHCFG_n_LOEN_SHIFT (4u) +#define DMAC8_CHCFG_n_HIEN_SHIFT (5u) +#define DMAC8_CHCFG_n_LVL_SHIFT (6u) +#define DMAC8_CHCFG_n_AM_SHIFT (8u) +#define DMAC8_CHCFG_n_SDS_SHIFT (12u) +#define DMAC8_CHCFG_n_DDS_SHIFT (16u) +#define DMAC8_CHCFG_n_SAD_SHIFT (20u) +#define DMAC8_CHCFG_n_DAD_SHIFT (21u) +#define DMAC8_CHCFG_n_TM_SHIFT (22u) +#define DMAC8_CHCFG_n_DEM_SHIFT (24u) +#define DMAC8_CHCFG_n_TCM_SHIFT (25u) +#define DMAC8_CHCFG_n_SBE_SHIFT (27u) +#define DMAC8_CHCFG_n_RSEL_SHIFT (28u) +#define DMAC8_CHCFG_n_RSW_SHIFT (29u) +#define DMAC8_CHCFG_n_REN_SHIFT (30u) +#define DMAC8_CHCFG_n_DMS_SHIFT (31u) + +#define DMAC8_CHITVL_n_ITVL_SHIFT (0u) + +#define DMAC8_CHEXT_n_SCA_SHIFT (4u) +#define DMAC8_CHEXT_n_DCA_SHIFT (12u) + +#define DMAC8_NXLA_n_NXLA_SHIFT (0u) + +#define DMAC8_CRLA_n_CRLA_SHIFT (0u) + +/* ---- DMAC9 ---- */ +#define DMAC9_N0SA_n_SA_SHIFT (0u) + +#define DMAC9_N0DA_n_DA_SHIFT (0u) + +#define DMAC9_N0TB_n_TB_SHIFT (0u) + +#define DMAC9_N1SA_n_SA_SHIFT (0u) + +#define DMAC9_N1DA_n_DA_SHIFT (0u) + +#define DMAC9_N1TB_n_TB_SHIFT (0u) + +#define DMAC9_CRSA_n_CRSA_SHIFT (0u) + +#define DMAC9_CRDA_n_CRDA_SHIFT (0u) + +#define DMAC9_CRTB_n_CRTB_SHIFT (0u) + +#define DMAC9_CHSTAT_n_EN_SHIFT (0u) +#define DMAC9_CHSTAT_n_RQST_SHIFT (1u) +#define DMAC9_CHSTAT_n_TACT_SHIFT (2u) +#define DMAC9_CHSTAT_n_SUS_SHIFT (3u) +#define DMAC9_CHSTAT_n_ER_SHIFT (4u) +#define DMAC9_CHSTAT_n_END_SHIFT (5u) +#define DMAC9_CHSTAT_n_TC_SHIFT (6u) +#define DMAC9_CHSTAT_n_SR_SHIFT (7u) +#define DMAC9_CHSTAT_n_DL_SHIFT (8u) +#define DMAC9_CHSTAT_n_DW_SHIFT (9u) +#define DMAC9_CHSTAT_n_DER_SHIFT (10u) +#define DMAC9_CHSTAT_n_MODE_SHIFT (11u) +#define DMAC9_CHSTAT_n_INTMSK_SHIFT (16u) + +#define DMAC9_CHCTRL_n_SETEN_SHIFT (0u) +#define DMAC9_CHCTRL_n_CLREN_SHIFT (1u) +#define DMAC9_CHCTRL_n_STG_SHIFT (2u) +#define DMAC9_CHCTRL_n_SWRST_SHIFT (3u) +#define DMAC9_CHCTRL_n_CLRRQ_SHIFT (4u) +#define DMAC9_CHCTRL_n_CLREND_SHIFT (5u) +#define DMAC9_CHCTRL_n_CLRTC_SHIFT (6u) +#define DMAC9_CHCTRL_n_SETSUS_SHIFT (8u) +#define DMAC9_CHCTRL_n_CLRSUS_SHIFT (9u) +#define DMAC9_CHCTRL_n_SETINTMSK_SHIFT (16u) +#define DMAC9_CHCTRL_n_CLRINTMSK_SHIFT (17u) + +#define DMAC9_CHCFG_n_SEL_SHIFT (0u) +#define DMAC9_CHCFG_n_REQD_SHIFT (3u) +#define DMAC9_CHCFG_n_LOEN_SHIFT (4u) +#define DMAC9_CHCFG_n_HIEN_SHIFT (5u) +#define DMAC9_CHCFG_n_LVL_SHIFT (6u) +#define DMAC9_CHCFG_n_AM_SHIFT (8u) +#define DMAC9_CHCFG_n_SDS_SHIFT (12u) +#define DMAC9_CHCFG_n_DDS_SHIFT (16u) +#define DMAC9_CHCFG_n_SAD_SHIFT (20u) +#define DMAC9_CHCFG_n_DAD_SHIFT (21u) +#define DMAC9_CHCFG_n_TM_SHIFT (22u) +#define DMAC9_CHCFG_n_DEM_SHIFT (24u) +#define DMAC9_CHCFG_n_TCM_SHIFT (25u) +#define DMAC9_CHCFG_n_SBE_SHIFT (27u) +#define DMAC9_CHCFG_n_RSEL_SHIFT (28u) +#define DMAC9_CHCFG_n_RSW_SHIFT (29u) +#define DMAC9_CHCFG_n_REN_SHIFT (30u) +#define DMAC9_CHCFG_n_DMS_SHIFT (31u) + +#define DMAC9_CHITVL_n_ITVL_SHIFT (0u) + +#define DMAC9_CHEXT_n_SCA_SHIFT (4u) +#define DMAC9_CHEXT_n_DCA_SHIFT (12u) + +#define DMAC9_NXLA_n_NXLA_SHIFT (0u) + +#define DMAC9_CRLA_n_CRLA_SHIFT (0u) + +/* ---- DMAC10 ---- */ +#define DMAC10_N0SA_n_SA_SHIFT (0u) + +#define DMAC10_N0DA_n_DA_SHIFT (0u) + +#define DMAC10_N0TB_n_TB_SHIFT (0u) + +#define DMAC10_N1SA_n_SA_SHIFT (0u) + +#define DMAC10_N1DA_n_DA_SHIFT (0u) + +#define DMAC10_N1TB_n_TB_SHIFT (0u) + +#define DMAC10_CRSA_n_CRSA_SHIFT (0u) + +#define DMAC10_CRDA_n_CRDA_SHIFT (0u) + +#define DMAC10_CRTB_n_CRTB_SHIFT (0u) + +#define DMAC10_CHSTAT_n_EN_SHIFT (0u) +#define DMAC10_CHSTAT_n_RQST_SHIFT (1u) +#define DMAC10_CHSTAT_n_TACT_SHIFT (2u) +#define DMAC10_CHSTAT_n_SUS_SHIFT (3u) +#define DMAC10_CHSTAT_n_ER_SHIFT (4u) +#define DMAC10_CHSTAT_n_END_SHIFT (5u) +#define DMAC10_CHSTAT_n_TC_SHIFT (6u) +#define DMAC10_CHSTAT_n_SR_SHIFT (7u) +#define DMAC10_CHSTAT_n_DL_SHIFT (8u) +#define DMAC10_CHSTAT_n_DW_SHIFT (9u) +#define DMAC10_CHSTAT_n_DER_SHIFT (10u) +#define DMAC10_CHSTAT_n_MODE_SHIFT (11u) +#define DMAC10_CHSTAT_n_INTMSK_SHIFT (16u) + +#define DMAC10_CHCTRL_n_SETEN_SHIFT (0u) +#define DMAC10_CHCTRL_n_CLREN_SHIFT (1u) +#define DMAC10_CHCTRL_n_STG_SHIFT (2u) +#define DMAC10_CHCTRL_n_SWRST_SHIFT (3u) +#define DMAC10_CHCTRL_n_CLRRQ_SHIFT (4u) +#define DMAC10_CHCTRL_n_CLREND_SHIFT (5u) +#define DMAC10_CHCTRL_n_CLRTC_SHIFT (6u) +#define DMAC10_CHCTRL_n_SETSUS_SHIFT (8u) +#define DMAC10_CHCTRL_n_CLRSUS_SHIFT (9u) +#define DMAC10_CHCTRL_n_SETINTMSK_SHIFT (16u) +#define DMAC10_CHCTRL_n_CLRINTMSK_SHIFT (17u) + +#define DMAC10_CHCFG_n_SEL_SHIFT (0u) +#define DMAC10_CHCFG_n_REQD_SHIFT (3u) +#define DMAC10_CHCFG_n_LOEN_SHIFT (4u) +#define DMAC10_CHCFG_n_HIEN_SHIFT (5u) +#define DMAC10_CHCFG_n_LVL_SHIFT (6u) +#define DMAC10_CHCFG_n_AM_SHIFT (8u) +#define DMAC10_CHCFG_n_SDS_SHIFT (12u) +#define DMAC10_CHCFG_n_DDS_SHIFT (16u) +#define DMAC10_CHCFG_n_SAD_SHIFT (20u) +#define DMAC10_CHCFG_n_DAD_SHIFT (21u) +#define DMAC10_CHCFG_n_TM_SHIFT (22u) +#define DMAC10_CHCFG_n_DEM_SHIFT (24u) +#define DMAC10_CHCFG_n_TCM_SHIFT (25u) +#define DMAC10_CHCFG_n_SBE_SHIFT (27u) +#define DMAC10_CHCFG_n_RSEL_SHIFT (28u) +#define DMAC10_CHCFG_n_RSW_SHIFT (29u) +#define DMAC10_CHCFG_n_REN_SHIFT (30u) +#define DMAC10_CHCFG_n_DMS_SHIFT (31u) + +#define DMAC10_CHITVL_n_ITVL_SHIFT (0u) + +#define DMAC10_CHEXT_n_SCA_SHIFT (4u) +#define DMAC10_CHEXT_n_DCA_SHIFT (12u) + +#define DMAC10_NXLA_n_NXLA_SHIFT (0u) + +#define DMAC10_CRLA_n_CRLA_SHIFT (0u) + +/* ---- DMAC11 ---- */ +#define DMAC11_N0SA_n_SA_SHIFT (0u) + +#define DMAC11_N0DA_n_DA_SHIFT (0u) + +#define DMAC11_N0TB_n_TB_SHIFT (0u) + +#define DMAC11_N1SA_n_SA_SHIFT (0u) + +#define DMAC11_N1DA_n_DA_SHIFT (0u) + +#define DMAC11_N1TB_n_TB_SHIFT (0u) + +#define DMAC11_CRSA_n_CRSA_SHIFT (0u) + +#define DMAC11_CRDA_n_CRDA_SHIFT (0u) + +#define DMAC11_CRTB_n_CRTB_SHIFT (0u) + +#define DMAC11_CHSTAT_n_EN_SHIFT (0u) +#define DMAC11_CHSTAT_n_RQST_SHIFT (1u) +#define DMAC11_CHSTAT_n_TACT_SHIFT (2u) +#define DMAC11_CHSTAT_n_SUS_SHIFT (3u) +#define DMAC11_CHSTAT_n_ER_SHIFT (4u) +#define DMAC11_CHSTAT_n_END_SHIFT (5u) +#define DMAC11_CHSTAT_n_TC_SHIFT (6u) +#define DMAC11_CHSTAT_n_SR_SHIFT (7u) +#define DMAC11_CHSTAT_n_DL_SHIFT (8u) +#define DMAC11_CHSTAT_n_DW_SHIFT (9u) +#define DMAC11_CHSTAT_n_DER_SHIFT (10u) +#define DMAC11_CHSTAT_n_MODE_SHIFT (11u) +#define DMAC11_CHSTAT_n_INTMSK_SHIFT (16u) + +#define DMAC11_CHCTRL_n_SETEN_SHIFT (0u) +#define DMAC11_CHCTRL_n_CLREN_SHIFT (1u) +#define DMAC11_CHCTRL_n_STG_SHIFT (2u) +#define DMAC11_CHCTRL_n_SWRST_SHIFT (3u) +#define DMAC11_CHCTRL_n_CLRRQ_SHIFT (4u) +#define DMAC11_CHCTRL_n_CLREND_SHIFT (5u) +#define DMAC11_CHCTRL_n_CLRTC_SHIFT (6u) +#define DMAC11_CHCTRL_n_SETSUS_SHIFT (8u) +#define DMAC11_CHCTRL_n_CLRSUS_SHIFT (9u) +#define DMAC11_CHCTRL_n_SETINTMSK_SHIFT (16u) +#define DMAC11_CHCTRL_n_CLRINTMSK_SHIFT (17u) + +#define DMAC11_CHCFG_n_SEL_SHIFT (0u) +#define DMAC11_CHCFG_n_REQD_SHIFT (3u) +#define DMAC11_CHCFG_n_LOEN_SHIFT (4u) +#define DMAC11_CHCFG_n_HIEN_SHIFT (5u) +#define DMAC11_CHCFG_n_LVL_SHIFT (6u) +#define DMAC11_CHCFG_n_AM_SHIFT (8u) +#define DMAC11_CHCFG_n_SDS_SHIFT (12u) +#define DMAC11_CHCFG_n_DDS_SHIFT (16u) +#define DMAC11_CHCFG_n_SAD_SHIFT (20u) +#define DMAC11_CHCFG_n_DAD_SHIFT (21u) +#define DMAC11_CHCFG_n_TM_SHIFT (22u) +#define DMAC11_CHCFG_n_DEM_SHIFT (24u) +#define DMAC11_CHCFG_n_TCM_SHIFT (25u) +#define DMAC11_CHCFG_n_SBE_SHIFT (27u) +#define DMAC11_CHCFG_n_RSEL_SHIFT (28u) +#define DMAC11_CHCFG_n_RSW_SHIFT (29u) +#define DMAC11_CHCFG_n_REN_SHIFT (30u) +#define DMAC11_CHCFG_n_DMS_SHIFT (31u) + +#define DMAC11_CHITVL_n_ITVL_SHIFT (0u) + +#define DMAC11_CHEXT_n_SCA_SHIFT (4u) +#define DMAC11_CHEXT_n_DCA_SHIFT (12u) + +#define DMAC11_NXLA_n_NXLA_SHIFT (0u) + +#define DMAC11_CRLA_n_CRLA_SHIFT (0u) + +/* ---- DMAC12 ---- */ +#define DMAC12_N0SA_n_SA_SHIFT (0u) + +#define DMAC12_N0DA_n_DA_SHIFT (0u) + +#define DMAC12_N0TB_n_TB_SHIFT (0u) + +#define DMAC12_N1SA_n_SA_SHIFT (0u) + +#define DMAC12_N1DA_n_DA_SHIFT (0u) + +#define DMAC12_N1TB_n_TB_SHIFT (0u) + +#define DMAC12_CRSA_n_CRSA_SHIFT (0u) + +#define DMAC12_CRDA_n_CRDA_SHIFT (0u) + +#define DMAC12_CRTB_n_CRTB_SHIFT (0u) + +#define DMAC12_CHSTAT_n_EN_SHIFT (0u) +#define DMAC12_CHSTAT_n_RQST_SHIFT (1u) +#define DMAC12_CHSTAT_n_TACT_SHIFT (2u) +#define DMAC12_CHSTAT_n_SUS_SHIFT (3u) +#define DMAC12_CHSTAT_n_ER_SHIFT (4u) +#define DMAC12_CHSTAT_n_END_SHIFT (5u) +#define DMAC12_CHSTAT_n_TC_SHIFT (6u) +#define DMAC12_CHSTAT_n_SR_SHIFT (7u) +#define DMAC12_CHSTAT_n_DL_SHIFT (8u) +#define DMAC12_CHSTAT_n_DW_SHIFT (9u) +#define DMAC12_CHSTAT_n_DER_SHIFT (10u) +#define DMAC12_CHSTAT_n_MODE_SHIFT (11u) +#define DMAC12_CHSTAT_n_INTMSK_SHIFT (16u) + +#define DMAC12_CHCTRL_n_SETEN_SHIFT (0u) +#define DMAC12_CHCTRL_n_CLREN_SHIFT (1u) +#define DMAC12_CHCTRL_n_STG_SHIFT (2u) +#define DMAC12_CHCTRL_n_SWRST_SHIFT (3u) +#define DMAC12_CHCTRL_n_CLRRQ_SHIFT (4u) +#define DMAC12_CHCTRL_n_CLREND_SHIFT (5u) +#define DMAC12_CHCTRL_n_CLRTC_SHIFT (6u) +#define DMAC12_CHCTRL_n_SETSUS_SHIFT (8u) +#define DMAC12_CHCTRL_n_CLRSUS_SHIFT (9u) +#define DMAC12_CHCTRL_n_SETINTMSK_SHIFT (16u) +#define DMAC12_CHCTRL_n_CLRINTMSK_SHIFT (17u) + +#define DMAC12_CHCFG_n_SEL_SHIFT (0u) +#define DMAC12_CHCFG_n_REQD_SHIFT (3u) +#define DMAC12_CHCFG_n_LOEN_SHIFT (4u) +#define DMAC12_CHCFG_n_HIEN_SHIFT (5u) +#define DMAC12_CHCFG_n_LVL_SHIFT (6u) +#define DMAC12_CHCFG_n_AM_SHIFT (8u) +#define DMAC12_CHCFG_n_SDS_SHIFT (12u) +#define DMAC12_CHCFG_n_DDS_SHIFT (16u) +#define DMAC12_CHCFG_n_SAD_SHIFT (20u) +#define DMAC12_CHCFG_n_DAD_SHIFT (21u) +#define DMAC12_CHCFG_n_TM_SHIFT (22u) +#define DMAC12_CHCFG_n_DEM_SHIFT (24u) +#define DMAC12_CHCFG_n_TCM_SHIFT (25u) +#define DMAC12_CHCFG_n_SBE_SHIFT (27u) +#define DMAC12_CHCFG_n_RSEL_SHIFT (28u) +#define DMAC12_CHCFG_n_RSW_SHIFT (29u) +#define DMAC12_CHCFG_n_REN_SHIFT (30u) +#define DMAC12_CHCFG_n_DMS_SHIFT (31u) + +#define DMAC12_CHITVL_n_ITVL_SHIFT (0u) + +#define DMAC12_CHEXT_n_SCA_SHIFT (4u) +#define DMAC12_CHEXT_n_DCA_SHIFT (12u) + +#define DMAC12_NXLA_n_NXLA_SHIFT (0u) + +#define DMAC12_CRLA_n_CRLA_SHIFT (0u) + +/* ---- DMAC13 ---- */ +#define DMAC13_N0SA_n_SA_SHIFT (0u) + +#define DMAC13_N0DA_n_DA_SHIFT (0u) + +#define DMAC13_N0TB_n_TB_SHIFT (0u) + +#define DMAC13_N1SA_n_SA_SHIFT (0u) + +#define DMAC13_N1DA_n_DA_SHIFT (0u) + +#define DMAC13_N1TB_n_TB_SHIFT (0u) + +#define DMAC13_CRSA_n_CRSA_SHIFT (0u) + +#define DMAC13_CRDA_n_CRDA_SHIFT (0u) + +#define DMAC13_CRTB_n_CRTB_SHIFT (0u) + +#define DMAC13_CHSTAT_n_EN_SHIFT (0u) +#define DMAC13_CHSTAT_n_RQST_SHIFT (1u) +#define DMAC13_CHSTAT_n_TACT_SHIFT (2u) +#define DMAC13_CHSTAT_n_SUS_SHIFT (3u) +#define DMAC13_CHSTAT_n_ER_SHIFT (4u) +#define DMAC13_CHSTAT_n_END_SHIFT (5u) +#define DMAC13_CHSTAT_n_TC_SHIFT (6u) +#define DMAC13_CHSTAT_n_SR_SHIFT (7u) +#define DMAC13_CHSTAT_n_DL_SHIFT (8u) +#define DMAC13_CHSTAT_n_DW_SHIFT (9u) +#define DMAC13_CHSTAT_n_DER_SHIFT (10u) +#define DMAC13_CHSTAT_n_MODE_SHIFT (11u) +#define DMAC13_CHSTAT_n_INTMSK_SHIFT (16u) + +#define DMAC13_CHCTRL_n_SETEN_SHIFT (0u) +#define DMAC13_CHCTRL_n_CLREN_SHIFT (1u) +#define DMAC13_CHCTRL_n_STG_SHIFT (2u) +#define DMAC13_CHCTRL_n_SWRST_SHIFT (3u) +#define DMAC13_CHCTRL_n_CLRRQ_SHIFT (4u) +#define DMAC13_CHCTRL_n_CLREND_SHIFT (5u) +#define DMAC13_CHCTRL_n_CLRTC_SHIFT (6u) +#define DMAC13_CHCTRL_n_SETSUS_SHIFT (8u) +#define DMAC13_CHCTRL_n_CLRSUS_SHIFT (9u) +#define DMAC13_CHCTRL_n_SETINTMSK_SHIFT (16u) +#define DMAC13_CHCTRL_n_CLRINTMSK_SHIFT (17u) + +#define DMAC13_CHCFG_n_SEL_SHIFT (0u) +#define DMAC13_CHCFG_n_REQD_SHIFT (3u) +#define DMAC13_CHCFG_n_LOEN_SHIFT (4u) +#define DMAC13_CHCFG_n_HIEN_SHIFT (5u) +#define DMAC13_CHCFG_n_LVL_SHIFT (6u) +#define DMAC13_CHCFG_n_AM_SHIFT (8u) +#define DMAC13_CHCFG_n_SDS_SHIFT (12u) +#define DMAC13_CHCFG_n_DDS_SHIFT (16u) +#define DMAC13_CHCFG_n_SAD_SHIFT (20u) +#define DMAC13_CHCFG_n_DAD_SHIFT (21u) +#define DMAC13_CHCFG_n_TM_SHIFT (22u) +#define DMAC13_CHCFG_n_DEM_SHIFT (24u) +#define DMAC13_CHCFG_n_TCM_SHIFT (25u) +#define DMAC13_CHCFG_n_SBE_SHIFT (27u) +#define DMAC13_CHCFG_n_RSEL_SHIFT (28u) +#define DMAC13_CHCFG_n_RSW_SHIFT (29u) +#define DMAC13_CHCFG_n_REN_SHIFT (30u) +#define DMAC13_CHCFG_n_DMS_SHIFT (31u) + +#define DMAC13_CHITVL_n_ITVL_SHIFT (0u) + +#define DMAC13_CHEXT_n_SCA_SHIFT (4u) +#define DMAC13_CHEXT_n_DCA_SHIFT (12u) + +#define DMAC13_NXLA_n_NXLA_SHIFT (0u) + +#define DMAC13_CRLA_n_CRLA_SHIFT (0u) + +/* ---- DMAC14 ---- */ +#define DMAC14_N0SA_n_SA_SHIFT (0u) + +#define DMAC14_N0DA_n_DA_SHIFT (0u) + +#define DMAC14_N0TB_n_TB_SHIFT (0u) + +#define DMAC14_N1SA_n_SA_SHIFT (0u) + +#define DMAC14_N1DA_n_DA_SHIFT (0u) + +#define DMAC14_N1TB_n_TB_SHIFT (0u) + +#define DMAC14_CRSA_n_CRSA_SHIFT (0u) + +#define DMAC14_CRDA_n_CRDA_SHIFT (0u) + +#define DMAC14_CRTB_n_CRTB_SHIFT (0u) + +#define DMAC14_CHSTAT_n_EN_SHIFT (0u) +#define DMAC14_CHSTAT_n_RQST_SHIFT (1u) +#define DMAC14_CHSTAT_n_TACT_SHIFT (2u) +#define DMAC14_CHSTAT_n_SUS_SHIFT (3u) +#define DMAC14_CHSTAT_n_ER_SHIFT (4u) +#define DMAC14_CHSTAT_n_END_SHIFT (5u) +#define DMAC14_CHSTAT_n_TC_SHIFT (6u) +#define DMAC14_CHSTAT_n_SR_SHIFT (7u) +#define DMAC14_CHSTAT_n_DL_SHIFT (8u) +#define DMAC14_CHSTAT_n_DW_SHIFT (9u) +#define DMAC14_CHSTAT_n_DER_SHIFT (10u) +#define DMAC14_CHSTAT_n_MODE_SHIFT (11u) +#define DMAC14_CHSTAT_n_INTMSK_SHIFT (16u) + +#define DMAC14_CHCTRL_n_SETEN_SHIFT (0u) +#define DMAC14_CHCTRL_n_CLREN_SHIFT (1u) +#define DMAC14_CHCTRL_n_STG_SHIFT (2u) +#define DMAC14_CHCTRL_n_SWRST_SHIFT (3u) +#define DMAC14_CHCTRL_n_CLRRQ_SHIFT (4u) +#define DMAC14_CHCTRL_n_CLREND_SHIFT (5u) +#define DMAC14_CHCTRL_n_CLRTC_SHIFT (6u) +#define DMAC14_CHCTRL_n_SETSUS_SHIFT (8u) +#define DMAC14_CHCTRL_n_CLRSUS_SHIFT (9u) +#define DMAC14_CHCTRL_n_SETINTMSK_SHIFT (16u) +#define DMAC14_CHCTRL_n_CLRINTMSK_SHIFT (17u) + +#define DMAC14_CHCFG_n_SEL_SHIFT (0u) +#define DMAC14_CHCFG_n_REQD_SHIFT (3u) +#define DMAC14_CHCFG_n_LOEN_SHIFT (4u) +#define DMAC14_CHCFG_n_HIEN_SHIFT (5u) +#define DMAC14_CHCFG_n_LVL_SHIFT (6u) +#define DMAC14_CHCFG_n_AM_SHIFT (8u) +#define DMAC14_CHCFG_n_SDS_SHIFT (12u) +#define DMAC14_CHCFG_n_DDS_SHIFT (16u) +#define DMAC14_CHCFG_n_SAD_SHIFT (20u) +#define DMAC14_CHCFG_n_DAD_SHIFT (21u) +#define DMAC14_CHCFG_n_TM_SHIFT (22u) +#define DMAC14_CHCFG_n_DEM_SHIFT (24u) +#define DMAC14_CHCFG_n_TCM_SHIFT (25u) +#define DMAC14_CHCFG_n_SBE_SHIFT (27u) +#define DMAC14_CHCFG_n_RSEL_SHIFT (28u) +#define DMAC14_CHCFG_n_RSW_SHIFT (29u) +#define DMAC14_CHCFG_n_REN_SHIFT (30u) +#define DMAC14_CHCFG_n_DMS_SHIFT (31u) + +#define DMAC14_CHITVL_n_ITVL_SHIFT (0u) + +#define DMAC14_CHEXT_n_SCA_SHIFT (4u) +#define DMAC14_CHEXT_n_DCA_SHIFT (12u) + +#define DMAC14_NXLA_n_NXLA_SHIFT (0u) + +#define DMAC14_CRLA_n_CRLA_SHIFT (0u) + +/* ---- DMAC15 ---- */ +#define DMAC15_N0SA_n_SA_SHIFT (0u) + +#define DMAC15_N0DA_n_DA_SHIFT (0u) + +#define DMAC15_N0TB_n_TB_SHIFT (0u) + +#define DMAC15_N1SA_n_SA_SHIFT (0u) + +#define DMAC15_N1DA_n_DA_SHIFT (0u) + +#define DMAC15_N1TB_n_TB_SHIFT (0u) + +#define DMAC15_CRSA_n_CRSA_SHIFT (0u) + +#define DMAC15_CRDA_n_CRDA_SHIFT (0u) + +#define DMAC15_CRTB_n_CRTB_SHIFT (0u) + +#define DMAC15_CHSTAT_n_EN_SHIFT (0u) +#define DMAC15_CHSTAT_n_RQST_SHIFT (1u) +#define DMAC15_CHSTAT_n_TACT_SHIFT (2u) +#define DMAC15_CHSTAT_n_SUS_SHIFT (3u) +#define DMAC15_CHSTAT_n_ER_SHIFT (4u) +#define DMAC15_CHSTAT_n_END_SHIFT (5u) +#define DMAC15_CHSTAT_n_TC_SHIFT (6u) +#define DMAC15_CHSTAT_n_SR_SHIFT (7u) +#define DMAC15_CHSTAT_n_DL_SHIFT (8u) +#define DMAC15_CHSTAT_n_DW_SHIFT (9u) +#define DMAC15_CHSTAT_n_DER_SHIFT (10u) +#define DMAC15_CHSTAT_n_MODE_SHIFT (11u) +#define DMAC15_CHSTAT_n_INTMSK_SHIFT (16u) + +#define DMAC15_CHCTRL_n_SETEN_SHIFT (0u) +#define DMAC15_CHCTRL_n_CLREN_SHIFT (1u) +#define DMAC15_CHCTRL_n_STG_SHIFT (2u) +#define DMAC15_CHCTRL_n_SWRST_SHIFT (3u) +#define DMAC15_CHCTRL_n_CLRRQ_SHIFT (4u) +#define DMAC15_CHCTRL_n_CLREND_SHIFT (5u) +#define DMAC15_CHCTRL_n_CLRTC_SHIFT (6u) +#define DMAC15_CHCTRL_n_SETSUS_SHIFT (8u) +#define DMAC15_CHCTRL_n_CLRSUS_SHIFT (9u) +#define DMAC15_CHCTRL_n_SETINTMSK_SHIFT (16u) +#define DMAC15_CHCTRL_n_CLRINTMSK_SHIFT (17u) + +#define DMAC15_CHCFG_n_SEL_SHIFT (0u) +#define DMAC15_CHCFG_n_REQD_SHIFT (3u) +#define DMAC15_CHCFG_n_LOEN_SHIFT (4u) +#define DMAC15_CHCFG_n_HIEN_SHIFT (5u) +#define DMAC15_CHCFG_n_LVL_SHIFT (6u) +#define DMAC15_CHCFG_n_AM_SHIFT (8u) +#define DMAC15_CHCFG_n_SDS_SHIFT (12u) +#define DMAC15_CHCFG_n_DDS_SHIFT (16u) +#define DMAC15_CHCFG_n_SAD_SHIFT (20u) +#define DMAC15_CHCFG_n_DAD_SHIFT (21u) +#define DMAC15_CHCFG_n_TM_SHIFT (22u) +#define DMAC15_CHCFG_n_DEM_SHIFT (24u) +#define DMAC15_CHCFG_n_TCM_SHIFT (25u) +#define DMAC15_CHCFG_n_SBE_SHIFT (27u) +#define DMAC15_CHCFG_n_RSEL_SHIFT (28u) +#define DMAC15_CHCFG_n_RSW_SHIFT (29u) +#define DMAC15_CHCFG_n_REN_SHIFT (30u) +#define DMAC15_CHCFG_n_DMS_SHIFT (31u) + +#define DMAC15_CHITVL_n_ITVL_SHIFT (0u) + +#define DMAC15_CHEXT_n_SCA_SHIFT (4u) +#define DMAC15_CHEXT_n_DCA_SHIFT (12u) + +#define DMAC15_NXLA_n_NXLA_SHIFT (0u) + +#define DMAC15_CRLA_n_CRLA_SHIFT (0u) + +/* ---- DMAC8-15 ---- */ +#define DMAC815_DCTRL_8_15_PR_SHIFT (0u) +#define DMAC815_DCTRL_8_15_LVINT_SHIFT (1u) +#define DMAC815_DCTRL_8_15_LDCA_SHIFT (2u) +#define DMAC815_DCTRL_8_15_LWCA_SHIFT (10u) + +#define DMAC815_DSTAT_EN_8_15_EN8_SHIFT (0u) +#define DMAC815_DSTAT_EN_8_15_EN9_SHIFT (1u) +#define DMAC815_DSTAT_EN_8_15_EN10_SHIFT (2u) +#define DMAC815_DSTAT_EN_8_15_EN11_SHIFT (3u) +#define DMAC815_DSTAT_EN_8_15_EN12_SHIFT (4u) +#define DMAC815_DSTAT_EN_8_15_EN13_SHIFT (5u) +#define DMAC815_DSTAT_EN_8_15_EN14_SHIFT (6u) +#define DMAC815_DSTAT_EN_8_15_EN15_SHIFT (7u) + +#define DMAC815_DSTAT_ER_8_15_ER8_SHIFT (0u) +#define DMAC815_DSTAT_ER_8_15_ER9_SHIFT (1u) +#define DMAC815_DSTAT_ER_8_15_ER10_SHIFT (2u) +#define DMAC815_DSTAT_ER_8_15_ER11_SHIFT (3u) +#define DMAC815_DSTAT_ER_8_15_ER12_SHIFT (4u) +#define DMAC815_DSTAT_ER_8_15_ER13_SHIFT (5u) +#define DMAC815_DSTAT_ER_8_15_ER14_SHIFT (6u) +#define DMAC815_DSTAT_ER_8_15_ER15_SHIFT (7u) + +#define DMAC815_DSTAT_END_8_15_END8_SHIFT (0u) +#define DMAC815_DSTAT_END_8_15_END9_SHIFT (1u) +#define DMAC815_DSTAT_END_8_15_END10_SHIFT (2u) +#define DMAC815_DSTAT_END_8_15_END11_SHIFT (3u) +#define DMAC815_DSTAT_END_8_15_END12_SHIFT (4u) +#define DMAC815_DSTAT_END_8_15_END13_SHIFT (5u) +#define DMAC815_DSTAT_END_8_15_END14_SHIFT (6u) +#define DMAC815_DSTAT_END_8_15_END15_SHIFT (7u) + +#define DMAC815_DSTAT_TC_8_15_TC8_SHIFT (0u) +#define DMAC815_DSTAT_TC_8_15_TC9_SHIFT (1u) +#define DMAC815_DSTAT_TC_8_15_TC10_SHIFT (2u) +#define DMAC815_DSTAT_TC_8_15_TC11_SHIFT (3u) +#define DMAC815_DSTAT_TC_8_15_TC12_SHIFT (4u) +#define DMAC815_DSTAT_TC_8_15_TC13_SHIFT (5u) +#define DMAC815_DSTAT_TC_8_15_TC14_SHIFT (6u) +#define DMAC815_DSTAT_TC_8_15_TC15_SHIFT (7u) + +#define DMAC815_DSTAT_SUS_8_15_SUS8_SHIFT (0u) +#define DMAC815_DSTAT_SUS_8_15_SUS9_SHIFT (1u) +#define DMAC815_DSTAT_SUS_8_15_SUS10_SHIFT (2u) +#define DMAC815_DSTAT_SUS_8_15_SUS11_SHIFT (3u) +#define DMAC815_DSTAT_SUS_8_15_SUS12_SHIFT (4u) +#define DMAC815_DSTAT_SUS_8_15_SUS13_SHIFT (5u) +#define DMAC815_DSTAT_SUS_8_15_SUS14_SHIFT (6u) +#define DMAC815_DSTAT_SUS_8_15_SUS15_SHIFT (7u) + +/* ---- DMAC0-1 ---- */ +#define DMAC01_DMARS_CH0_RID_SHIFT (0u) +#define DMAC01_DMARS_CH0_MID_SHIFT (2u) +#define DMAC01_DMARS_CH1_RID_SHIFT (16u) +#define DMAC01_DMARS_CH1_MID_SHIFT (18u) + +/* ---- DMAC2-3 ---- */ +#define DMAC23_DMARS_CH2_RID_SHIFT (0u) +#define DMAC23_DMARS_CH2_MID_SHIFT (2u) +#define DMAC23_DMARS_CH3_RID_SHIFT (16u) +#define DMAC23_DMARS_CH3_MID_SHIFT (18u) + +/* ---- DMAC4-5 ---- */ +#define DMAC45_DMARS_CH4_RID_SHIFT (0u) +#define DMAC45_DMARS_CH4_MID_SHIFT (2u) +#define DMAC45_DMARS_CH5_RID_SHIFT (16u) +#define DMAC45_DMARS_CH5_MID_SHIFT (18u) + +/* ---- DMAC6-7 ---- */ +#define DMAC67_DMARS_CH6_RID_SHIFT (0u) +#define DMAC67_DMARS_CH6_MID_SHIFT (2u) +#define DMAC67_DMARS_CH7_RID_SHIFT (16u) +#define DMAC67_DMARS_CH7_MID_SHIFT (18u) + +/* ---- DMAC8-9 ---- */ +#define DMAC89_DMARS_CH8_RID_SHIFT (0u) +#define DMAC89_DMARS_CH8_MID_SHIFT (2u) +#define DMAC89_DMARS_CH9_RID_SHIFT (16u) +#define DMAC89_DMARS_CH9_MID_SHIFT (18u) + +/* ---- DMAC10-11 ---- */ +#define DMAC1011_DMARS_CH10_RID_SHIFT (0u) +#define DMAC1011_DMARS_CH10_MID_SHIFT (2u) +#define DMAC1011_DMARS_CH11_RID_SHIFT (16u) +#define DMAC1011_DMARS_CH11_MID_SHIFT (18u) + +/* ---- DMAC12-13 ---- */ +#define DMAC1213_DMARS_CH12_RID_SHIFT (0u) +#define DMAC1213_DMARS_CH12_MID_SHIFT (2u) +#define DMAC1213_DMARS_CH13_RID_SHIFT (16u) +#define DMAC1213_DMARS_CH13_MID_SHIFT (18u) + +/* ---- DMAC14-15 ---- */ +#define DMAC1415_DMARS_CH14_RID_SHIFT (0u) +#define DMAC1415_DMARS_CH14_MID_SHIFT (2u) +#define DMAC1415_DMARS_CH15_RID_SHIFT (16u) +#define DMAC1415_DMARS_CH15_MID_SHIFT (18u) + + +#endif /* DMAC_IOBITMASK_H */ + +/* End of File */ diff --git a/targets/TARGET_RENESAS/TARGET_RZ_A1XX/TARGET_GR_LYCHEE/device/inc/iobitmasks/gpio_iobitmask.h b/targets/TARGET_RENESAS/TARGET_RZ_A1XX/TARGET_GR_LYCHEE/device/inc/iobitmasks/gpio_iobitmask.h new file mode 100644 index 0000000..94ba619 --- /dev/null +++ b/targets/TARGET_RENESAS/TARGET_RZ_A1XX/TARGET_GR_LYCHEE/device/inc/iobitmasks/gpio_iobitmask.h @@ -0,0 +1,5793 @@ +/******************************************************************************* +* DISCLAIMER +* This software is supplied by Renesas Electronics Corporation and is only +* intended for use with Renesas products. No other uses are authorized. This +* software is owned by Renesas Electronics Corporation and is protected under +* all applicable laws, including copyright laws. +* THIS SOFTWARE IS PROVIDED "AS IS" AND RENESAS MAKES NO WARRANTIES REGARDING +* THIS SOFTWARE, WHETHER EXPRESS, IMPLIED OR STATUTORY, INCLUDING BUT NOT +* LIMITED TO WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE +* AND NON-INFRINGEMENT. ALL SUCH WARRANTIES ARE EXPRESSLY DISCLAIMED. +* TO THE MAXIMUM EXTENT PERMITTED NOT PROHIBITED BY LAW, NEITHER RENESAS +* ELECTRONICS CORPORATION NOR ANY OF ITS AFFILIATED COMPANIES SHALL BE LIABLE +* FOR ANY DIRECT, INDIRECT, SPECIAL, INCIDENTAL OR CONSEQUENTIAL DAMAGES FOR +* ANY REASON RELATED TO THIS SOFTWARE, EVEN IF RENESAS OR ITS AFFILIATES HAVE +* BEEN ADVISED OF THE POSSIBILITY OF SUCH DAMAGES. +* Renesas reserves the right, without notice, to make changes to this software +* and to discontinue the availability of this software. By using this software, +* you agree to the additional terms and conditions found by accessing the +* following link: +* http://www.renesas.com/disclaimer +* Copyright (C) 2012 - 2014 Renesas Electronics Corporation. All rights reserved. +*******************************************************************************/ +/******************************************************************************* +* File Name : gpio_iobitmask.h +* $Rev: 1115 $ +* $Date:: 2014-07-09 15:35:02 +0900#$ +* Description : General purpose I/O ports register define header +*******************************************************************************/ +#ifndef GPIO_IOBITMASK_H +#define GPIO_IOBITMASK_H + + +/* ==== Mask values for IO registers ==== */ +/* ---- P0 ---- */ +#define GPIO_PPR0_PPR00 (0x0001u) +#define GPIO_PPR0_PPR01 (0x0002u) +#define GPIO_PPR0_PPR02 (0x0004u) +#define GPIO_PPR0_PPR03 (0x0008u) +#define GPIO_PPR0_PPR04 (0x0010u) +#define GPIO_PPR0_PPR05 (0x0020u) + +#define GPIO_PMC0_PMC04 (0x0010u) +#define GPIO_PMC0_PMC05 (0x0020u) + +#define GPIO_PMCSR0_PMCSR04 (0x00000010uL) +#define GPIO_PMCSR0_PMCSR05 (0x00000020uL) + +#define GPIO_PIBC0_PIBC00 (0x0001u) +#define GPIO_PIBC0_PIBC01 (0x0002u) +#define GPIO_PIBC0_PIBC02 (0x0004u) +#define GPIO_PIBC0_PIBC03 (0x0008u) +#define GPIO_PIBC0_PIBC04 (0x0010u) +#define GPIO_PIBC0_PIBC05 (0x0020u) + +/* ---- P1 ---- */ +#define GPIO_P1_P10 (0x0001u) +#define GPIO_P1_P11 (0x0002u) +#define GPIO_P1_P12 (0x0004u) +#define GPIO_P1_P13 (0x0008u) +#define GPIO_P1_P14 (0x0010u) +#define GPIO_P1_P15 (0x0020u) +#define GPIO_P1_P16 (0x0040u) +#define GPIO_P1_P17 (0x0080u) + +#define GPIO_PSR1_PSR10 (0x00000001uL) +#define GPIO_PSR1_PSR11 (0x00000002uL) +#define GPIO_PSR1_PSR12 (0x00000004uL) +#define GPIO_PSR1_PSR13 (0x00000008uL) +#define GPIO_PSR1_PSR14 (0x00000010uL) +#define GPIO_PSR1_PSR15 (0x00000020uL) +#define GPIO_PSR1_PSR16 (0x00000040uL) +#define GPIO_PSR1_PSR17 (0x00000080uL) +#define GPIO_PSR1_PSR116 (0x00010000uL) +#define GPIO_PSR1_PSR117 (0x00020000uL) +#define GPIO_PSR1_PSR118 (0x00040000uL) +#define GPIO_PSR1_PSR119 (0x00080000uL) +#define GPIO_PSR1_PSR120 (0x00100000uL) +#define GPIO_PSR1_PSR121 (0x00200000uL) +#define GPIO_PSR1_PSR122 (0x00400000uL) +#define GPIO_PSR1_PSR123 (0x00800000uL) + +#define GPIO_PPR1_PPR10 (0x0001u) +#define GPIO_PPR1_PPR11 (0x0002u) +#define GPIO_PPR1_PPR12 (0x0004u) +#define GPIO_PPR1_PPR13 (0x0008u) +#define GPIO_PPR1_PPR14 (0x0010u) +#define GPIO_PPR1_PPR15 (0x0020u) +#define GPIO_PPR1_PPR16 (0x0040u) +#define GPIO_PPR1_PPR17 (0x0080u) +#define GPIO_PPR1_PPR18 (0x0100u) +#define GPIO_PPR1_PPR19 (0x0200u) +#define GPIO_PPR1_PPR110 (0x0400u) +#define GPIO_PPR1_PPR111 (0x0800u) +#define GPIO_PPR1_PPR112 (0x1000u) +#define GPIO_PPR1_PPR113 (0x2000u) +#define GPIO_PPR1_PPR114 (0x4000u) +#define GPIO_PPR1_PPR115 (0x8000u) + +#define GPIO_PM1_PM10 (0x0001u) +#define GPIO_PM1_PM11 (0x0002u) +#define GPIO_PM1_PM12 (0x0004u) +#define GPIO_PM1_PM13 (0x0008u) +#define GPIO_PM1_PM14 (0x0010u) +#define GPIO_PM1_PM15 (0x0020u) +#define GPIO_PM1_PM16 (0x0040u) +#define GPIO_PM1_PM17 (0x0080u) + +#define GPIO_PMC1_PMC10 (0x0001u) +#define GPIO_PMC1_PMC11 (0x0002u) +#define GPIO_PMC1_PMC12 (0x0004u) +#define GPIO_PMC1_PMC13 (0x0008u) +#define GPIO_PMC1_PMC14 (0x0010u) +#define GPIO_PMC1_PMC15 (0x0020u) +#define GPIO_PMC1_PMC16 (0x0040u) +#define GPIO_PMC1_PMC17 (0x0080u) +#define GPIO_PMC1_PMC18 (0x0100u) +#define GPIO_PMC1_PMC19 (0x0200u) +#define GPIO_PMC1_PMC110 (0x0400u) +#define GPIO_PMC1_PMC111 (0x0800u) +#define GPIO_PMC1_PMC112 (0x1000u) +#define GPIO_PMC1_PMC113 (0x2000u) +#define GPIO_PMC1_PMC114 (0x4000u) +#define GPIO_PMC1_PMC115 (0x8000u) + +#define GPIO_PFC1_PFC10 (0x0001u) +#define GPIO_PFC1_PFC11 (0x0002u) +#define GPIO_PFC1_PFC12 (0x0004u) +#define GPIO_PFC1_PFC13 (0x0008u) +#define GPIO_PFC1_PFC14 (0x0010u) +#define GPIO_PFC1_PFC15 (0x0020u) +#define GPIO_PFC1_PFC16 (0x0040u) +#define GPIO_PFC1_PFC17 (0x0080u) +#define GPIO_PFC1_PFC18 (0x0100u) +#define GPIO_PFC1_PFC19 (0x0200u) +#define GPIO_PFC1_PFC110 (0x0400u) +#define GPIO_PFC1_PFC111 (0x0800u) +#define GPIO_PFC1_PFC112 (0x1000u) +#define GPIO_PFC1_PFC113 (0x2000u) +#define GPIO_PFC1_PFC114 (0x4000u) +#define GPIO_PFC1_PFC115 (0x8000u) + +#define GPIO_PFCE1_PFCE10 (0x0001u) +#define GPIO_PFCE1_PFCE11 (0x0002u) +#define GPIO_PFCE1_PFCE12 (0x0004u) +#define GPIO_PFCE1_PFCE13 (0x0008u) +#define GPIO_PFCE1_PFCE14 (0x0010u) +#define GPIO_PFCE1_PFCE15 (0x0020u) +#define GPIO_PFCE1_PFCE16 (0x0040u) +#define GPIO_PFCE1_PFCE17 (0x0080u) +#define GPIO_PFCE1_PFCE18 (0x0100u) +#define GPIO_PFCE1_PFCE19 (0x0200u) +#define GPIO_PFCE1_PFCE110 (0x0400u) +#define GPIO_PFCE1_PFCE111 (0x0800u) +#define GPIO_PFCE1_PFCE112 (0x1000u) +#define GPIO_PFCE1_PFCE113 (0x2000u) +#define GPIO_PFCE1_PFCE114 (0x4000u) +#define GPIO_PFCE1_PFCE115 (0x8000u) + +#define GPIO_PNOT1_PNOT10 (0x0001u) +#define GPIO_PNOT1_PNOT11 (0x0002u) +#define GPIO_PNOT1_PNOT12 (0x0004u) +#define GPIO_PNOT1_PNOT13 (0x0008u) +#define GPIO_PNOT1_PNOT14 (0x0010u) +#define GPIO_PNOT1_PNOT15 (0x0020u) +#define GPIO_PNOT1_PNOT16 (0x0040u) +#define GPIO_PNOT1_PNOT17 (0x0080u) + +#define GPIO_PMSR1_PMSR10 (0x00000001uL) +#define GPIO_PMSR1_PMSR11 (0x00000002uL) +#define GPIO_PMSR1_PMSR12 (0x00000004uL) +#define GPIO_PMSR1_PMSR13 (0x00000008uL) +#define GPIO_PMSR1_PMSR14 (0x00000010uL) +#define GPIO_PMSR1_PMSR15 (0x00000020uL) +#define GPIO_PMSR1_PMSR16 (0x00000040uL) +#define GPIO_PMSR1_PMSR17 (0x00000080uL) +#define GPIO_PMSR1_PMSR116 (0x00010000uL) +#define GPIO_PMSR1_PMSR117 (0x00020000uL) +#define GPIO_PMSR1_PMSR118 (0x00040000uL) +#define GPIO_PMSR1_PMSR119 (0x00080000uL) +#define GPIO_PMSR1_PMSR120 (0x00100000uL) +#define GPIO_PMSR1_PMSR121 (0x00200000uL) +#define GPIO_PMSR1_PMSR122 (0x00400000uL) +#define GPIO_PMSR1_PMSR123 (0x00800000uL) + +#define GPIO_PMCSR1_PMCSR10 (0x00000001uL) +#define GPIO_PMCSR1_PMCSR11 (0x00000002uL) +#define GPIO_PMCSR1_PMCSR12 (0x00000004uL) +#define GPIO_PMCSR1_PMCSR13 (0x00000008uL) +#define GPIO_PMCSR1_PMCSR14 (0x00000010uL) +#define GPIO_PMCSR1_PMCSR15 (0x00000020uL) +#define GPIO_PMCSR1_PMCSR16 (0x00000040uL) +#define GPIO_PMCSR1_PMCSR17 (0x00000080uL) +#define GPIO_PMCSR1_PMCSR116 (0x00010000uL) +#define GPIO_PMCSR1_PMCSR117 (0x00020000uL) +#define GPIO_PMCSR1_PMCSR118 (0x00040000uL) +#define GPIO_PMCSR1_PMCSR119 (0x00080000uL) +#define GPIO_PMCSR1_PMCSR120 (0x00100000uL) +#define GPIO_PMCSR1_PMCSR121 (0x00200000uL) +#define GPIO_PMCSR1_PMCSR122 (0x00400000uL) +#define GPIO_PMCSR1_PMCSR123 (0x00800000uL) + +#define GPIO_PFCAE1_PFCAE10 (0x0001u) +#define GPIO_PFCAE1_PFCAE11 (0x0002u) +#define GPIO_PFCAE1_PFCAE12 (0x0004u) +#define GPIO_PFCAE1_PFCAE13 (0x0008u) +#define GPIO_PFCAE1_PFCAE14 (0x0010u) +#define GPIO_PFCAE1_PFCAE15 (0x0020u) +#define GPIO_PFCAE1_PFCAE16 (0x0040u) +#define GPIO_PFCAE1_PFCAE17 (0x0080u) +#define GPIO_PFCAE1_PFCAE18 (0x0100u) +#define GPIO_PFCAE1_PFCAE19 (0x0200u) +#define GPIO_PFCAE1_PFCAE110 (0x0400u) +#define GPIO_PFCAE1_PFCAE111 (0x0800u) +#define GPIO_PFCAE1_PFCAE112 (0x1000u) +#define GPIO_PFCAE1_PFCAE113 (0x2000u) +#define GPIO_PFCAE1_PFCAE114 (0x4000u) +#define GPIO_PFCAE1_PFCAE115 (0x8000u) + +#define GPIO_PIBC1_PIBC10 (0x0001u) +#define GPIO_PIBC1_PIBC11 (0x0002u) +#define GPIO_PIBC1_PIBC12 (0x0004u) +#define GPIO_PIBC1_PIBC13 (0x0008u) +#define GPIO_PIBC1_PIBC14 (0x0010u) +#define GPIO_PIBC1_PIBC15 (0x0020u) +#define GPIO_PIBC1_PIBC16 (0x0040u) +#define GPIO_PIBC1_PIBC17 (0x0080u) +#define GPIO_PIBC1_PIBC18 (0x0100u) +#define GPIO_PIBC1_PIBC19 (0x0200u) +#define GPIO_PIBC1_PIBC110 (0x0400u) +#define GPIO_PIBC1_PIBC111 (0x0800u) +#define GPIO_PIBC1_PIBC112 (0x1000u) +#define GPIO_PIBC1_PIBC113 (0x2000u) +#define GPIO_PIBC1_PIBC114 (0x4000u) +#define GPIO_PIBC1_PIBC115 (0x8000u) + +#define GPIO_PBDC1_PBDC10 (0x0001u) +#define GPIO_PBDC1_PBDC11 (0x0002u) +#define GPIO_PBDC1_PBDC12 (0x0004u) +#define GPIO_PBDC1_PBDC13 (0x0008u) +#define GPIO_PBDC1_PBDC14 (0x0010u) +#define GPIO_PBDC1_PBDC15 (0x0020u) +#define GPIO_PBDC1_PBDC16 (0x0040u) +#define GPIO_PBDC1_PBDC17 (0x0080u) +#define GPIO_PBDC1_PBDC18 (0x0100u) +#define GPIO_PBDC1_PBDC19 (0x0200u) +#define GPIO_PBDC1_PBDC110 (0x0400u) +#define GPIO_PBDC1_PBDC111 (0x0800u) +#define GPIO_PBDC1_PBDC112 (0x1000u) +#define GPIO_PBDC1_PBDC113 (0x2000u) +#define GPIO_PBDC1_PBDC114 (0x4000u) +#define GPIO_PBDC1_PBDC115 (0x8000u) + +#define GPIO_PIPC1_PIPC10 (0x0001u) +#define GPIO_PIPC1_PIPC11 (0x0002u) +#define GPIO_PIPC1_PIPC12 (0x0004u) +#define GPIO_PIPC1_PIPC13 (0x0008u) +#define GPIO_PIPC1_PIPC14 (0x0010u) +#define GPIO_PIPC1_PIPC15 (0x0020u) +#define GPIO_PIPC1_PIPC16 (0x0040u) +#define GPIO_PIPC1_PIPC17 (0x0080u) + +/* ---- P2 ---- */ +#define GPIO_P2_P20 (0x0001u) +#define GPIO_P2_P21 (0x0002u) +#define GPIO_P2_P22 (0x0004u) +#define GPIO_P2_P23 (0x0008u) +#define GPIO_P2_P24 (0x0010u) +#define GPIO_P2_P25 (0x0020u) +#define GPIO_P2_P26 (0x0040u) +#define GPIO_P2_P27 (0x0080u) +#define GPIO_P2_P28 (0x0100u) +#define GPIO_P2_P29 (0x0200u) +#define GPIO_P2_P210 (0x0400u) +#define GPIO_P2_P211 (0x0800u) +#define GPIO_P2_P212 (0x1000u) +#define GPIO_P2_P213 (0x2000u) +#define GPIO_P2_P214 (0x4000u) +#define GPIO_P2_P215 (0x8000u) + +#define GPIO_PSR2_PSR20 (0x00000001uL) +#define GPIO_PSR2_PSR21 (0x00000002uL) +#define GPIO_PSR2_PSR22 (0x00000004uL) +#define GPIO_PSR2_PSR23 (0x00000008uL) +#define GPIO_PSR2_PSR24 (0x00000010uL) +#define GPIO_PSR2_PSR25 (0x00000020uL) +#define GPIO_PSR2_PSR26 (0x00000040uL) +#define GPIO_PSR2_PSR27 (0x00000080uL) +#define GPIO_PSR2_PSR28 (0x00000100uL) +#define GPIO_PSR2_PSR29 (0x00000200uL) +#define GPIO_PSR2_PSR210 (0x00000400uL) +#define GPIO_PSR2_PSR211 (0x00000800uL) +#define GPIO_PSR2_PSR212 (0x00001000uL) +#define GPIO_PSR2_PSR213 (0x00002000uL) +#define GPIO_PSR2_PSR214 (0x00004000uL) +#define GPIO_PSR2_PSR215 (0x00008000uL) +#define GPIO_PSR2_PSR216 (0x00010000uL) +#define GPIO_PSR2_PSR217 (0x00020000uL) +#define GPIO_PSR2_PSR218 (0x00040000uL) +#define GPIO_PSR2_PSR219 (0x00080000uL) +#define GPIO_PSR2_PSR220 (0x00100000uL) +#define GPIO_PSR2_PSR221 (0x00200000uL) +#define GPIO_PSR2_PSR222 (0x00400000uL) +#define GPIO_PSR2_PSR223 (0x00800000uL) +#define GPIO_PSR2_PSR224 (0x01000000uL) +#define GPIO_PSR2_PSR225 (0x02000000uL) +#define GPIO_PSR2_PSR226 (0x04000000uL) +#define GPIO_PSR2_PSR227 (0x08000000uL) +#define GPIO_PSR2_PSR228 (0x10000000uL) +#define GPIO_PSR2_PSR229 (0x20000000uL) +#define GPIO_PSR2_PSR230 (0x40000000uL) +#define GPIO_PSR2_PSR231 (0x80000000uL) + +#define GPIO_PPR2_PPR20 (0x0001u) +#define GPIO_PPR2_PPR21 (0x0002u) +#define GPIO_PPR2_PPR22 (0x0004u) +#define GPIO_PPR2_PPR23 (0x0008u) +#define GPIO_PPR2_PPR24 (0x0010u) +#define GPIO_PPR2_PPR25 (0x0020u) +#define GPIO_PPR2_PPR26 (0x0040u) +#define GPIO_PPR2_PPR27 (0x0080u) +#define GPIO_PPR2_PPR28 (0x0100u) +#define GPIO_PPR2_PPR29 (0x0200u) +#define GPIO_PPR2_PPR210 (0x0400u) +#define GPIO_PPR2_PPR211 (0x0800u) +#define GPIO_PPR2_PPR212 (0x1000u) +#define GPIO_PPR2_PPR213 (0x2000u) +#define GPIO_PPR2_PPR214 (0x4000u) +#define GPIO_PPR2_PPR215 (0x8000u) + +#define GPIO_PM2_PM20 (0x0001u) +#define GPIO_PM2_PM21 (0x0002u) +#define GPIO_PM2_PM22 (0x0004u) +#define GPIO_PM2_PM23 (0x0008u) +#define GPIO_PM2_PM24 (0x0010u) +#define GPIO_PM2_PM25 (0x0020u) +#define GPIO_PM2_PM26 (0x0040u) +#define GPIO_PM2_PM27 (0x0080u) +#define GPIO_PM2_PM28 (0x0100u) +#define GPIO_PM2_PM29 (0x0200u) +#define GPIO_PM2_PM210 (0x0400u) +#define GPIO_PM2_PM211 (0x0800u) +#define GPIO_PM2_PM212 (0x1000u) +#define GPIO_PM2_PM213 (0x2000u) +#define GPIO_PM2_PM214 (0x4000u) +#define GPIO_PM2_PM215 (0x8000u) + +#define GPIO_PMC2_PMC20 (0x0001u) +#define GPIO_PMC2_PMC21 (0x0002u) +#define GPIO_PMC2_PMC22 (0x0004u) +#define GPIO_PMC2_PMC23 (0x0008u) +#define GPIO_PMC2_PMC24 (0x0010u) +#define GPIO_PMC2_PMC25 (0x0020u) +#define GPIO_PMC2_PMC26 (0x0040u) +#define GPIO_PMC2_PMC27 (0x0080u) +#define GPIO_PMC2_PMC28 (0x0100u) +#define GPIO_PMC2_PMC29 (0x0200u) +#define GPIO_PMC2_PMC210 (0x0400u) +#define GPIO_PMC2_PMC211 (0x0800u) +#define GPIO_PMC2_PMC212 (0x1000u) +#define GPIO_PMC2_PMC213 (0x2000u) +#define GPIO_PMC2_PMC214 (0x4000u) +#define GPIO_PMC2_PMC215 (0x8000u) + +#define GPIO_PFC2_PFC20 (0x0001u) +#define GPIO_PFC2_PFC21 (0x0002u) +#define GPIO_PFC2_PFC22 (0x0004u) +#define GPIO_PFC2_PFC23 (0x0008u) +#define GPIO_PFC2_PFC24 (0x0010u) +#define GPIO_PFC2_PFC25 (0x0020u) +#define GPIO_PFC2_PFC26 (0x0040u) +#define GPIO_PFC2_PFC27 (0x0080u) +#define GPIO_PFC2_PFC28 (0x0100u) +#define GPIO_PFC2_PFC29 (0x0200u) +#define GPIO_PFC2_PFC210 (0x0400u) +#define GPIO_PFC2_PFC211 (0x0800u) +#define GPIO_PFC2_PFC212 (0x1000u) +#define GPIO_PFC2_PFC213 (0x2000u) +#define GPIO_PFC2_PFC214 (0x4000u) +#define GPIO_PFC2_PFC215 (0x8000u) + +#define GPIO_PFCE2_PFCE20 (0x0001u) +#define GPIO_PFCE2_PFCE21 (0x0002u) +#define GPIO_PFCE2_PFCE22 (0x0004u) +#define GPIO_PFCE2_PFCE23 (0x0008u) +#define GPIO_PFCE2_PFCE24 (0x0010u) +#define GPIO_PFCE2_PFCE25 (0x0020u) +#define GPIO_PFCE2_PFCE26 (0x0040u) +#define GPIO_PFCE2_PFCE27 (0x0080u) +#define GPIO_PFCE2_PFCE28 (0x0100u) +#define GPIO_PFCE2_PFCE29 (0x0200u) +#define GPIO_PFCE2_PFCE210 (0x0400u) +#define GPIO_PFCE2_PFCE211 (0x0800u) +#define GPIO_PFCE2_PFCE212 (0x1000u) +#define GPIO_PFCE2_PFCE213 (0x2000u) +#define GPIO_PFCE2_PFCE214 (0x4000u) +#define GPIO_PFCE2_PFCE215 (0x8000u) + +#define GPIO_PNOT2_PNOT20 (0x0001u) +#define GPIO_PNOT2_PNOT21 (0x0002u) +#define GPIO_PNOT2_PNOT22 (0x0004u) +#define GPIO_PNOT2_PNOT23 (0x0008u) +#define GPIO_PNOT2_PNOT24 (0x0010u) +#define GPIO_PNOT2_PNOT25 (0x0020u) +#define GPIO_PNOT2_PNOT26 (0x0040u) +#define GPIO_PNOT2_PNOT27 (0x0080u) +#define GPIO_PNOT2_PNOT28 (0x0100u) +#define GPIO_PNOT2_PNOT29 (0x0200u) +#define GPIO_PNOT2_PNOT210 (0x0400u) +#define GPIO_PNOT2_PNOT211 (0x0800u) +#define GPIO_PNOT2_PNOT212 (0x1000u) +#define GPIO_PNOT2_PNOT213 (0x2000u) +#define GPIO_PNOT2_PNOT214 (0x4000u) +#define GPIO_PNOT2_PNOT215 (0x8000u) + +#define GPIO_PMSR2_PMSR20 (0x00000001uL) +#define GPIO_PMSR2_PMSR21 (0x00000002uL) +#define GPIO_PMSR2_PMSR22 (0x00000004uL) +#define GPIO_PMSR2_PMSR23 (0x00000008uL) +#define GPIO_PMSR2_PMSR24 (0x00000010uL) +#define GPIO_PMSR2_PMSR25 (0x00000020uL) +#define GPIO_PMSR2_PMSR26 (0x00000040uL) +#define GPIO_PMSR2_PMSR27 (0x00000080uL) +#define GPIO_PMSR2_PMSR28 (0x00000100uL) +#define GPIO_PMSR2_PMSR29 (0x00000200uL) +#define GPIO_PMSR2_PMSR210 (0x00000400uL) +#define GPIO_PMSR2_PMSR211 (0x00000800uL) +#define GPIO_PMSR2_PMSR212 (0x00001000uL) +#define GPIO_PMSR2_PMSR213 (0x00002000uL) +#define GPIO_PMSR2_PMSR214 (0x00004000uL) +#define GPIO_PMSR2_PMSR215 (0x00008000uL) +#define GPIO_PMSR2_PMSR216 (0x00010000uL) +#define GPIO_PMSR2_PMSR217 (0x00020000uL) +#define GPIO_PMSR2_PMSR218 (0x00040000uL) +#define GPIO_PMSR2_PMSR219 (0x00080000uL) +#define GPIO_PMSR2_PMSR220 (0x00100000uL) +#define GPIO_PMSR2_PMSR221 (0x00200000uL) +#define GPIO_PMSR2_PMSR222 (0x00400000uL) +#define GPIO_PMSR2_PMSR223 (0x00800000uL) +#define GPIO_PMSR2_PMSR224 (0x01000000uL) +#define GPIO_PMSR2_PMSR225 (0x02000000uL) +#define GPIO_PMSR2_PMSR226 (0x04000000uL) +#define GPIO_PMSR2_PMSR227 (0x08000000uL) +#define GPIO_PMSR2_PMSR228 (0x10000000uL) +#define GPIO_PMSR2_PMSR229 (0x20000000uL) +#define GPIO_PMSR2_PMSR230 (0x40000000uL) +#define GPIO_PMSR2_PMSR231 (0x80000000uL) + +#define GPIO_PMCSR2_PMCSR20 (0x00000001uL) +#define GPIO_PMCSR2_PMCSR21 (0x00000002uL) +#define GPIO_PMCSR2_PMCSR22 (0x00000004uL) +#define GPIO_PMCSR2_PMCSR23 (0x00000008uL) +#define GPIO_PMCSR2_PMCSR24 (0x00000010uL) +#define GPIO_PMCSR2_PMCSR25 (0x00000020uL) +#define GPIO_PMCSR2_PMCSR26 (0x00000040uL) +#define GPIO_PMCSR2_PMCSR27 (0x00000080uL) +#define GPIO_PMCSR2_PMCSR28 (0x00000100uL) +#define GPIO_PMCSR2_PMCSR29 (0x00000200uL) +#define GPIO_PMCSR2_PMCSR210 (0x00000400uL) +#define GPIO_PMCSR2_PMCSR211 (0x00000800uL) +#define GPIO_PMCSR2_PMCSR212 (0x00001000uL) +#define GPIO_PMCSR2_PMCSR213 (0x00002000uL) +#define GPIO_PMCSR2_PMCSR214 (0x00004000uL) +#define GPIO_PMCSR2_PMCSR215 (0x00008000uL) +#define GPIO_PMCSR2_PMCSR216 (0x00010000uL) +#define GPIO_PMCSR2_PMCSR217 (0x00020000uL) +#define GPIO_PMCSR2_PMCSR218 (0x00040000uL) +#define GPIO_PMCSR2_PMCSR219 (0x00080000uL) +#define GPIO_PMCSR2_PMCSR220 (0x00100000uL) +#define GPIO_PMCSR2_PMCSR221 (0x00200000uL) +#define GPIO_PMCSR2_PMCSR222 (0x00400000uL) +#define GPIO_PMCSR2_PMCSR223 (0x00800000uL) +#define GPIO_PMCSR2_PMCSR224 (0x01000000uL) +#define GPIO_PMCSR2_PMCSR225 (0x02000000uL) +#define GPIO_PMCSR2_PMCSR226 (0x04000000uL) +#define GPIO_PMCSR2_PMCSR227 (0x08000000uL) +#define GPIO_PMCSR2_PMCSR228 (0x10000000uL) +#define GPIO_PMCSR2_PMCSR229 (0x20000000uL) +#define GPIO_PMCSR2_PMCSR230 (0x40000000uL) +#define GPIO_PMCSR2_PMCSR231 (0x80000000uL) + +#define GPIO_PFCAE2_PFCAE20 (0x0001u) +#define GPIO_PFCAE2_PFCAE21 (0x0002u) +#define GPIO_PFCAE2_PFCAE22 (0x0004u) +#define GPIO_PFCAE2_PFCAE23 (0x0008u) +#define GPIO_PFCAE2_PFCAE24 (0x0010u) +#define GPIO_PFCAE2_PFCAE25 (0x0020u) +#define GPIO_PFCAE2_PFCAE26 (0x0040u) +#define GPIO_PFCAE2_PFCAE27 (0x0080u) +#define GPIO_PFCAE2_PFCAE28 (0x0100u) +#define GPIO_PFCAE2_PFCAE29 (0x0200u) +#define GPIO_PFCAE2_PFCAE210 (0x0400u) +#define GPIO_PFCAE2_PFCAE211 (0x0800u) +#define GPIO_PFCAE2_PFCAE212 (0x1000u) +#define GPIO_PFCAE2_PFCAE213 (0x2000u) +#define GPIO_PFCAE2_PFCAE214 (0x4000u) +#define GPIO_PFCAE2_PFCAE215 (0x8000u) + +#define GPIO_PIBC2_PIBC20 (0x0001u) +#define GPIO_PIBC2_PIBC21 (0x0002u) +#define GPIO_PIBC2_PIBC22 (0x0004u) +#define GPIO_PIBC2_PIBC23 (0x0008u) +#define GPIO_PIBC2_PIBC24 (0x0010u) +#define GPIO_PIBC2_PIBC25 (0x0020u) +#define GPIO_PIBC2_PIBC26 (0x0040u) +#define GPIO_PIBC2_PIBC27 (0x0080u) +#define GPIO_PIBC2_PIBC28 (0x0100u) +#define GPIO_PIBC2_PIBC29 (0x0200u) +#define GPIO_PIBC2_PIBC210 (0x0400u) +#define GPIO_PIBC2_PIBC211 (0x0800u) +#define GPIO_PIBC2_PIBC212 (0x1000u) +#define GPIO_PIBC2_PIBC213 (0x2000u) +#define GPIO_PIBC2_PIBC214 (0x4000u) +#define GPIO_PIBC2_PIBC215 (0x8000u) + +#define GPIO_PBDC2_PBDC20 (0x0001u) +#define GPIO_PBDC2_PBDC21 (0x0002u) +#define GPIO_PBDC2_PBDC22 (0x0004u) +#define GPIO_PBDC2_PBDC23 (0x0008u) +#define GPIO_PBDC2_PBDC24 (0x0010u) +#define GPIO_PBDC2_PBDC25 (0x0020u) +#define GPIO_PBDC2_PBDC26 (0x0040u) +#define GPIO_PBDC2_PBDC27 (0x0080u) +#define GPIO_PBDC2_PBDC28 (0x0100u) +#define GPIO_PBDC2_PBDC29 (0x0200u) +#define GPIO_PBDC2_PBDC210 (0x0400u) +#define GPIO_PBDC2_PBDC211 (0x0800u) +#define GPIO_PBDC2_PBDC212 (0x1000u) +#define GPIO_PBDC2_PBDC213 (0x2000u) +#define GPIO_PBDC2_PBDC214 (0x4000u) +#define GPIO_PBDC2_PBDC215 (0x8000u) + +#define GPIO_PIPC2_PIPC20 (0x0001u) +#define GPIO_PIPC2_PIPC21 (0x0002u) +#define GPIO_PIPC2_PIPC22 (0x0004u) +#define GPIO_PIPC2_PIPC23 (0x0008u) +#define GPIO_PIPC2_PIPC24 (0x0010u) +#define GPIO_PIPC2_PIPC25 (0x0020u) +#define GPIO_PIPC2_PIPC26 (0x0040u) +#define GPIO_PIPC2_PIPC27 (0x0080u) +#define GPIO_PIPC2_PIPC28 (0x0100u) +#define GPIO_PIPC2_PIPC29 (0x0200u) +#define GPIO_PIPC2_PIPC210 (0x0400u) +#define GPIO_PIPC2_PIPC211 (0x0800u) +#define GPIO_PIPC2_PIPC212 (0x1000u) +#define GPIO_PIPC2_PIPC213 (0x2000u) +#define GPIO_PIPC2_PIPC214 (0x4000u) +#define GPIO_PIPC2_PIPC215 (0x8000u) + +/* ---- P3 ---- */ +#define GPIO_P3_P30 (0x0001u) +#define GPIO_P3_P31 (0x0002u) +#define GPIO_P3_P32 (0x0004u) +#define GPIO_P3_P33 (0x0008u) +#define GPIO_P3_P34 (0x0010u) +#define GPIO_P3_P35 (0x0020u) +#define GPIO_P3_P36 (0x0040u) +#define GPIO_P3_P37 (0x0080u) +#define GPIO_P3_P38 (0x0100u) +#define GPIO_P3_P39 (0x0200u) +#define GPIO_P3_P310 (0x0400u) +#define GPIO_P3_P311 (0x0800u) +#define GPIO_P3_P312 (0x1000u) +#define GPIO_P3_P313 (0x2000u) +#define GPIO_P3_P314 (0x4000u) +#define GPIO_P3_P315 (0x8000u) + +#define GPIO_PSR3_PSR30 (0x00000001uL) +#define GPIO_PSR3_PSR31 (0x00000002uL) +#define GPIO_PSR3_PSR32 (0x00000004uL) +#define GPIO_PSR3_PSR33 (0x00000008uL) +#define GPIO_PSR3_PSR34 (0x00000010uL) +#define GPIO_PSR3_PSR35 (0x00000020uL) +#define GPIO_PSR3_PSR36 (0x00000040uL) +#define GPIO_PSR3_PSR37 (0x00000080uL) +#define GPIO_PSR3_PSR38 (0x00000100uL) +#define GPIO_PSR3_PSR39 (0x00000200uL) +#define GPIO_PSR3_PSR310 (0x00000400uL) +#define GPIO_PSR3_PSR311 (0x00000800uL) +#define GPIO_PSR3_PSR312 (0x00001000uL) +#define GPIO_PSR3_PSR313 (0x00002000uL) +#define GPIO_PSR3_PSR314 (0x00004000uL) +#define GPIO_PSR3_PSR315 (0x00008000uL) +#define GPIO_PSR3_PSR316 (0x00010000uL) +#define GPIO_PSR3_PSR317 (0x00020000uL) +#define GPIO_PSR3_PSR318 (0x00040000uL) +#define GPIO_PSR3_PSR319 (0x00080000uL) +#define GPIO_PSR3_PSR320 (0x00100000uL) +#define GPIO_PSR3_PSR321 (0x00200000uL) +#define GPIO_PSR3_PSR322 (0x00400000uL) +#define GPIO_PSR3_PSR323 (0x00800000uL) +#define GPIO_PSR3_PSR324 (0x01000000uL) +#define GPIO_PSR3_PSR325 (0x02000000uL) +#define GPIO_PSR3_PSR326 (0x04000000uL) +#define GPIO_PSR3_PSR327 (0x08000000uL) +#define GPIO_PSR3_PSR328 (0x10000000uL) +#define GPIO_PSR3_PSR329 (0x20000000uL) +#define GPIO_PSR3_PSR330 (0x40000000uL) +#define GPIO_PSR3_PSR331 (0x80000000uL) + +#define GPIO_PPR3_PPR30 (0x0001u) +#define GPIO_PPR3_PPR31 (0x0002u) +#define GPIO_PPR3_PPR32 (0x0004u) +#define GPIO_PPR3_PPR33 (0x0008u) +#define GPIO_PPR3_PPR34 (0x0010u) +#define GPIO_PPR3_PPR35 (0x0020u) +#define GPIO_PPR3_PPR36 (0x0040u) +#define GPIO_PPR3_PPR37 (0x0080u) +#define GPIO_PPR3_PPR38 (0x0100u) +#define GPIO_PPR3_PPR39 (0x0200u) +#define GPIO_PPR3_PPR310 (0x0400u) +#define GPIO_PPR3_PPR311 (0x0800u) +#define GPIO_PPR3_PPR312 (0x1000u) +#define GPIO_PPR3_PPR313 (0x2000u) +#define GPIO_PPR3_PPR314 (0x4000u) +#define GPIO_PPR3_PPR315 (0x8000u) + +#define GPIO_PM3_PM30 (0x0001u) +#define GPIO_PM3_PM31 (0x0002u) +#define GPIO_PM3_PM32 (0x0004u) +#define GPIO_PM3_PM33 (0x0008u) +#define GPIO_PM3_PM34 (0x0010u) +#define GPIO_PM3_PM35 (0x0020u) +#define GPIO_PM3_PM36 (0x0040u) +#define GPIO_PM3_PM37 (0x0080u) +#define GPIO_PM3_PM38 (0x0100u) +#define GPIO_PM3_PM39 (0x0200u) +#define GPIO_PM3_PM310 (0x0400u) +#define GPIO_PM3_PM311 (0x0800u) +#define GPIO_PM3_PM312 (0x1000u) +#define GPIO_PM3_PM313 (0x2000u) +#define GPIO_PM3_PM314 (0x4000u) +#define GPIO_PM3_PM315 (0x8000u) + +#define GPIO_PMC3_PMC30 (0x0001u) +#define GPIO_PMC3_PMC31 (0x0002u) +#define GPIO_PMC3_PMC32 (0x0004u) +#define GPIO_PMC3_PMC33 (0x0008u) +#define GPIO_PMC3_PMC34 (0x0010u) +#define GPIO_PMC3_PMC35 (0x0020u) +#define GPIO_PMC3_PMC36 (0x0040u) +#define GPIO_PMC3_PMC37 (0x0080u) +#define GPIO_PMC3_PMC38 (0x0100u) +#define GPIO_PMC3_PMC39 (0x0200u) +#define GPIO_PMC3_PMC310 (0x0400u) +#define GPIO_PMC3_PMC311 (0x0800u) +#define GPIO_PMC3_PMC312 (0x1000u) +#define GPIO_PMC3_PMC313 (0x2000u) +#define GPIO_PMC3_PMC314 (0x4000u) +#define GPIO_PMC3_PMC315 (0x8000u) + +#define GPIO_PFC3_PFC30 (0x0001u) +#define GPIO_PFC3_PFC31 (0x0002u) +#define GPIO_PFC3_PFC32 (0x0004u) +#define GPIO_PFC3_PFC33 (0x0008u) +#define GPIO_PFC3_PFC34 (0x0010u) +#define GPIO_PFC3_PFC35 (0x0020u) +#define GPIO_PFC3_PFC36 (0x0040u) +#define GPIO_PFC3_PFC37 (0x0080u) +#define GPIO_PFC3_PFC38 (0x0100u) +#define GPIO_PFC3_PFC39 (0x0200u) +#define GPIO_PFC3_PFC310 (0x0400u) +#define GPIO_PFC3_PFC311 (0x0800u) +#define GPIO_PFC3_PFC312 (0x1000u) +#define GPIO_PFC3_PFC313 (0x2000u) +#define GPIO_PFC3_PFC314 (0x4000u) +#define GPIO_PFC3_PFC315 (0x8000u) + +#define GPIO_PFCE3_PFCE30 (0x0001u) +#define GPIO_PFCE3_PFCE31 (0x0002u) +#define GPIO_PFCE3_PFCE32 (0x0004u) +#define GPIO_PFCE3_PFCE33 (0x0008u) +#define GPIO_PFCE3_PFCE34 (0x0010u) +#define GPIO_PFCE3_PFCE35 (0x0020u) +#define GPIO_PFCE3_PFCE36 (0x0040u) +#define GPIO_PFCE3_PFCE37 (0x0080u) +#define GPIO_PFCE3_PFCE38 (0x0100u) +#define GPIO_PFCE3_PFCE39 (0x0200u) +#define GPIO_PFCE3_PFCE310 (0x0400u) +#define GPIO_PFCE3_PFCE311 (0x0800u) +#define GPIO_PFCE3_PFCE312 (0x1000u) +#define GPIO_PFCE3_PFCE313 (0x2000u) +#define GPIO_PFCE3_PFCE314 (0x4000u) +#define GPIO_PFCE3_PFCE315 (0x8000u) + +#define GPIO_PNOT3_PNOT30 (0x0001u) +#define GPIO_PNOT3_PNOT31 (0x0002u) +#define GPIO_PNOT3_PNOT32 (0x0004u) +#define GPIO_PNOT3_PNOT33 (0x0008u) +#define GPIO_PNOT3_PNOT34 (0x0010u) +#define GPIO_PNOT3_PNOT35 (0x0020u) +#define GPIO_PNOT3_PNOT36 (0x0040u) +#define GPIO_PNOT3_PNOT37 (0x0080u) +#define GPIO_PNOT3_PNOT38 (0x0100u) +#define GPIO_PNOT3_PNOT39 (0x0200u) +#define GPIO_PNOT3_PNOT310 (0x0400u) +#define GPIO_PNOT3_PNOT311 (0x0800u) +#define GPIO_PNOT3_PNOT312 (0x1000u) +#define GPIO_PNOT3_PNOT313 (0x2000u) +#define GPIO_PNOT3_PNOT314 (0x4000u) +#define GPIO_PNOT3_PNOT315 (0x8000u) + +#define GPIO_PMSR3_PMSR30 (0x00000001uL) +#define GPIO_PMSR3_PMSR31 (0x00000002uL) +#define GPIO_PMSR3_PMSR32 (0x00000004uL) +#define GPIO_PMSR3_PMSR33 (0x00000008uL) +#define GPIO_PMSR3_PMSR34 (0x00000010uL) +#define GPIO_PMSR3_PMSR35 (0x00000020uL) +#define GPIO_PMSR3_PMSR36 (0x00000040uL) +#define GPIO_PMSR3_PMSR37 (0x00000080uL) +#define GPIO_PMSR3_PMSR38 (0x00000100uL) +#define GPIO_PMSR3_PMSR39 (0x00000200uL) +#define GPIO_PMSR3_PMSR310 (0x00000400uL) +#define GPIO_PMSR3_PMSR311 (0x00000800uL) +#define GPIO_PMSR3_PMSR312 (0x00001000uL) +#define GPIO_PMSR3_PMSR313 (0x00002000uL) +#define GPIO_PMSR3_PMSR314 (0x00004000uL) +#define GPIO_PMSR3_PMSR315 (0x00008000uL) +#define GPIO_PMSR3_PMSR316 (0x00010000uL) +#define GPIO_PMSR3_PMSR317 (0x00020000uL) +#define GPIO_PMSR3_PMSR318 (0x00040000uL) +#define GPIO_PMSR3_PMSR319 (0x00080000uL) +#define GPIO_PMSR3_PMSR320 (0x00100000uL) +#define GPIO_PMSR3_PMSR321 (0x00200000uL) +#define GPIO_PMSR3_PMSR322 (0x00400000uL) +#define GPIO_PMSR3_PMSR323 (0x00800000uL) +#define GPIO_PMSR3_PMSR324 (0x01000000uL) +#define GPIO_PMSR3_PMSR325 (0x02000000uL) +#define GPIO_PMSR3_PMSR326 (0x04000000uL) +#define GPIO_PMSR3_PMSR327 (0x08000000uL) +#define GPIO_PMSR3_PMSR328 (0x10000000uL) +#define GPIO_PMSR3_PMSR329 (0x20000000uL) +#define GPIO_PMSR3_PMSR330 (0x40000000uL) +#define GPIO_PMSR3_PMSR331 (0x80000000uL) + +#define GPIO_PMCSR3_PMCSR30 (0x00000001uL) +#define GPIO_PMCSR3_PMCSR31 (0x00000002uL) +#define GPIO_PMCSR3_PMCSR32 (0x00000004uL) +#define GPIO_PMCSR3_PMCSR33 (0x00000008uL) +#define GPIO_PMCSR3_PMCSR34 (0x00000010uL) +#define GPIO_PMCSR3_PMCSR35 (0x00000020uL) +#define GPIO_PMCSR3_PMCSR36 (0x00000040uL) +#define GPIO_PMCSR3_PMCSR37 (0x00000080uL) +#define GPIO_PMCSR3_PMCSR38 (0x00000100uL) +#define GPIO_PMCSR3_PMCSR39 (0x00000200uL) +#define GPIO_PMCSR3_PMCSR310 (0x00000400uL) +#define GPIO_PMCSR3_PMCSR311 (0x00000800uL) +#define GPIO_PMCSR3_PMCSR312 (0x00001000uL) +#define GPIO_PMCSR3_PMCSR313 (0x00002000uL) +#define GPIO_PMCSR3_PMCSR314 (0x00004000uL) +#define GPIO_PMCSR3_PMCSR315 (0x00008000uL) +#define GPIO_PMCSR3_PMCSR316 (0x00010000uL) +#define GPIO_PMCSR3_PMCSR317 (0x00020000uL) +#define GPIO_PMCSR3_PMCSR318 (0x00040000uL) +#define GPIO_PMCSR3_PMCSR319 (0x00080000uL) +#define GPIO_PMCSR3_PMCSR320 (0x00100000uL) +#define GPIO_PMCSR3_PMCSR321 (0x00200000uL) +#define GPIO_PMCSR3_PMCSR322 (0x00400000uL) +#define GPIO_PMCSR3_PMCSR323 (0x00800000uL) +#define GPIO_PMCSR3_PMCSR324 (0x01000000uL) +#define GPIO_PMCSR3_PMCSR325 (0x02000000uL) +#define GPIO_PMCSR3_PMCSR326 (0x04000000uL) +#define GPIO_PMCSR3_PMCSR327 (0x08000000uL) +#define GPIO_PMCSR3_PMCSR328 (0x10000000uL) +#define GPIO_PMCSR3_PMCSR329 (0x20000000uL) +#define GPIO_PMCSR3_PMCSR330 (0x40000000uL) +#define GPIO_PMCSR3_PMCSR331 (0x80000000uL) + +#define GPIO_PFCAE3_PFCAE30 (0x0001u) +#define GPIO_PFCAE3_PFCAE31 (0x0002u) +#define GPIO_PFCAE3_PFCAE32 (0x0004u) +#define GPIO_PFCAE3_PFCAE33 (0x0008u) +#define GPIO_PFCAE3_PFCAE34 (0x0010u) +#define GPIO_PFCAE3_PFCAE35 (0x0020u) +#define GPIO_PFCAE3_PFCAE36 (0x0040u) +#define GPIO_PFCAE3_PFCAE37 (0x0080u) +#define GPIO_PFCAE3_PFCAE38 (0x0100u) +#define GPIO_PFCAE3_PFCAE39 (0x0200u) +#define GPIO_PFCAE3_PFCAE310 (0x0400u) +#define GPIO_PFCAE3_PFCAE311 (0x0800u) +#define GPIO_PFCAE3_PFCAE312 (0x1000u) +#define GPIO_PFCAE3_PFCAE313 (0x2000u) +#define GPIO_PFCAE3_PFCAE314 (0x4000u) +#define GPIO_PFCAE3_PFCAE315 (0x8000u) + +#define GPIO_PIBC3_PIBC30 (0x0001u) +#define GPIO_PIBC3_PIBC31 (0x0002u) +#define GPIO_PIBC3_PIBC32 (0x0004u) +#define GPIO_PIBC3_PIBC33 (0x0008u) +#define GPIO_PIBC3_PIBC34 (0x0010u) +#define GPIO_PIBC3_PIBC35 (0x0020u) +#define GPIO_PIBC3_PIBC36 (0x0040u) +#define GPIO_PIBC3_PIBC37 (0x0080u) +#define GPIO_PIBC3_PIBC38 (0x0100u) +#define GPIO_PIBC3_PIBC39 (0x0200u) +#define GPIO_PIBC3_PIBC310 (0x0400u) +#define GPIO_PIBC3_PIBC311 (0x0800u) +#define GPIO_PIBC3_PIBC312 (0x1000u) +#define GPIO_PIBC3_PIBC313 (0x2000u) +#define GPIO_PIBC3_PIBC314 (0x4000u) +#define GPIO_PIBC3_PIBC315 (0x8000u) + +#define GPIO_PBDC3_PBDC30 (0x0001u) +#define GPIO_PBDC3_PBDC31 (0x0002u) +#define GPIO_PBDC3_PBDC32 (0x0004u) +#define GPIO_PBDC3_PBDC33 (0x0008u) +#define GPIO_PBDC3_PBDC34 (0x0010u) +#define GPIO_PBDC3_PBDC35 (0x0020u) +#define GPIO_PBDC3_PBDC36 (0x0040u) +#define GPIO_PBDC3_PBDC37 (0x0080u) +#define GPIO_PBDC3_PBDC38 (0x0100u) +#define GPIO_PBDC3_PBDC39 (0x0200u) +#define GPIO_PBDC3_PBDC310 (0x0400u) +#define GPIO_PBDC3_PBDC311 (0x0800u) +#define GPIO_PBDC3_PBDC312 (0x1000u) +#define GPIO_PBDC3_PBDC313 (0x2000u) +#define GPIO_PBDC3_PBDC314 (0x4000u) +#define GPIO_PBDC3_PBDC315 (0x8000u) + +#define GPIO_PIPC3_PIPC30 (0x0001u) +#define GPIO_PIPC3_PIPC31 (0x0002u) +#define GPIO_PIPC3_PIPC32 (0x0004u) +#define GPIO_PIPC3_PIPC33 (0x0008u) +#define GPIO_PIPC3_PIPC34 (0x0010u) +#define GPIO_PIPC3_PIPC35 (0x0020u) +#define GPIO_PIPC3_PIPC36 (0x0040u) +#define GPIO_PIPC3_PIPC37 (0x0080u) +#define GPIO_PIPC3_PIPC38 (0x0100u) +#define GPIO_PIPC3_PIPC39 (0x0200u) +#define GPIO_PIPC3_PIPC310 (0x0400u) +#define GPIO_PIPC3_PIPC311 (0x0800u) +#define GPIO_PIPC3_PIPC312 (0x1000u) +#define GPIO_PIPC3_PIPC313 (0x2000u) +#define GPIO_PIPC3_PIPC314 (0x4000u) +#define GPIO_PIPC3_PIPC315 (0x8000u) + +/* ---- P4 ---- */ +#define GPIO_P4_P40 (0x0001u) +#define GPIO_P4_P41 (0x0002u) +#define GPIO_P4_P42 (0x0004u) +#define GPIO_P4_P43 (0x0008u) +#define GPIO_P4_P44 (0x0010u) +#define GPIO_P4_P45 (0x0020u) +#define GPIO_P4_P46 (0x0040u) +#define GPIO_P4_P47 (0x0080u) +#define GPIO_P4_P48 (0x0100u) +#define GPIO_P4_P49 (0x0200u) +#define GPIO_P4_P410 (0x0400u) +#define GPIO_P4_P411 (0x0800u) +#define GPIO_P4_P412 (0x1000u) +#define GPIO_P4_P413 (0x2000u) +#define GPIO_P4_P414 (0x4000u) +#define GPIO_P4_P415 (0x8000u) + +#define GPIO_PSR4_PSR40 (0x00000001uL) +#define GPIO_PSR4_PSR41 (0x00000002uL) +#define GPIO_PSR4_PSR42 (0x00000004uL) +#define GPIO_PSR4_PSR43 (0x00000008uL) +#define GPIO_PSR4_PSR44 (0x00000010uL) +#define GPIO_PSR4_PSR45 (0x00000020uL) +#define GPIO_PSR4_PSR46 (0x00000040uL) +#define GPIO_PSR4_PSR47 (0x00000080uL) +#define GPIO_PSR4_PSR48 (0x00000100uL) +#define GPIO_PSR4_PSR49 (0x00000200uL) +#define GPIO_PSR4_PSR410 (0x00000400uL) +#define GPIO_PSR4_PSR411 (0x00000800uL) +#define GPIO_PSR4_PSR412 (0x00001000uL) +#define GPIO_PSR4_PSR413 (0x00002000uL) +#define GPIO_PSR4_PSR414 (0x00004000uL) +#define GPIO_PSR4_PSR415 (0x00008000uL) +#define GPIO_PSR4_PSR416 (0x00010000uL) +#define GPIO_PSR4_PSR417 (0x00020000uL) +#define GPIO_PSR4_PSR418 (0x00040000uL) +#define GPIO_PSR4_PSR419 (0x00080000uL) +#define GPIO_PSR4_PSR420 (0x00100000uL) +#define GPIO_PSR4_PSR421 (0x00200000uL) +#define GPIO_PSR4_PSR422 (0x00400000uL) +#define GPIO_PSR4_PSR423 (0x00800000uL) +#define GPIO_PSR4_PSR424 (0x01000000uL) +#define GPIO_PSR4_PSR425 (0x02000000uL) +#define GPIO_PSR4_PSR426 (0x04000000uL) +#define GPIO_PSR4_PSR427 (0x08000000uL) +#define GPIO_PSR4_PSR428 (0x10000000uL) +#define GPIO_PSR4_PSR429 (0x20000000uL) +#define GPIO_PSR4_PSR430 (0x40000000uL) +#define GPIO_PSR4_PSR431 (0x80000000uL) + +#define GPIO_PPR4_PPR40 (0x0001u) +#define GPIO_PPR4_PPR41 (0x0002u) +#define GPIO_PPR4_PPR42 (0x0004u) +#define GPIO_PPR4_PPR43 (0x0008u) +#define GPIO_PPR4_PPR44 (0x0010u) +#define GPIO_PPR4_PPR45 (0x0020u) +#define GPIO_PPR4_PPR46 (0x0040u) +#define GPIO_PPR4_PPR47 (0x0080u) +#define GPIO_PPR4_PPR48 (0x0100u) +#define GPIO_PPR4_PPR49 (0x0200u) +#define GPIO_PPR4_PPR410 (0x0400u) +#define GPIO_PPR4_PPR411 (0x0800u) +#define GPIO_PPR4_PPR412 (0x1000u) +#define GPIO_PPR4_PPR413 (0x2000u) +#define GPIO_PPR4_PPR414 (0x4000u) +#define GPIO_PPR4_PPR415 (0x8000u) + +#define GPIO_PM4_PM40 (0x0001u) +#define GPIO_PM4_PM41 (0x0002u) +#define GPIO_PM4_PM42 (0x0004u) +#define GPIO_PM4_PM43 (0x0008u) +#define GPIO_PM4_PM44 (0x0010u) +#define GPIO_PM4_PM45 (0x0020u) +#define GPIO_PM4_PM46 (0x0040u) +#define GPIO_PM4_PM47 (0x0080u) +#define GPIO_PM4_PM48 (0x0100u) +#define GPIO_PM4_PM49 (0x0200u) +#define GPIO_PM4_PM410 (0x0400u) +#define GPIO_PM4_PM411 (0x0800u) +#define GPIO_PM4_PM412 (0x1000u) +#define GPIO_PM4_PM413 (0x2000u) +#define GPIO_PM4_PM414 (0x4000u) +#define GPIO_PM4_PM415 (0x8000u) + +#define GPIO_PMC4_PMC40 (0x0001u) +#define GPIO_PMC4_PMC41 (0x0002u) +#define GPIO_PMC4_PMC42 (0x0004u) +#define GPIO_PMC4_PMC43 (0x0008u) +#define GPIO_PMC4_PMC44 (0x0010u) +#define GPIO_PMC4_PMC45 (0x0020u) +#define GPIO_PMC4_PMC46 (0x0040u) +#define GPIO_PMC4_PMC47 (0x0080u) +#define GPIO_PMC4_PMC48 (0x0100u) +#define GPIO_PMC4_PMC49 (0x0200u) +#define GPIO_PMC4_PMC410 (0x0400u) +#define GPIO_PMC4_PMC411 (0x0800u) +#define GPIO_PMC4_PMC412 (0x1000u) +#define GPIO_PMC4_PMC413 (0x2000u) +#define GPIO_PMC4_PMC414 (0x4000u) +#define GPIO_PMC4_PMC415 (0x8000u) + +#define GPIO_PFC4_PFC40 (0x0001u) +#define GPIO_PFC4_PFC41 (0x0002u) +#define GPIO_PFC4_PFC42 (0x0004u) +#define GPIO_PFC4_PFC43 (0x0008u) +#define GPIO_PFC4_PFC44 (0x0010u) +#define GPIO_PFC4_PFC45 (0x0020u) +#define GPIO_PFC4_PFC46 (0x0040u) +#define GPIO_PFC4_PFC47 (0x0080u) +#define GPIO_PFC4_PFC48 (0x0100u) +#define GPIO_PFC4_PFC49 (0x0200u) +#define GPIO_PFC4_PFC410 (0x0400u) +#define GPIO_PFC4_PFC411 (0x0800u) +#define GPIO_PFC4_PFC412 (0x1000u) +#define GPIO_PFC4_PFC413 (0x2000u) +#define GPIO_PFC4_PFC414 (0x4000u) +#define GPIO_PFC4_PFC415 (0x8000u) + +#define GPIO_PFCE4_PFCE40 (0x0001u) +#define GPIO_PFCE4_PFCE41 (0x0002u) +#define GPIO_PFCE4_PFCE42 (0x0004u) +#define GPIO_PFCE4_PFCE43 (0x0008u) +#define GPIO_PFCE4_PFCE44 (0x0010u) +#define GPIO_PFCE4_PFCE45 (0x0020u) +#define GPIO_PFCE4_PFCE46 (0x0040u) +#define GPIO_PFCE4_PFCE47 (0x0080u) +#define GPIO_PFCE4_PFCE48 (0x0100u) +#define GPIO_PFCE4_PFCE49 (0x0200u) +#define GPIO_PFCE4_PFCE410 (0x0400u) +#define GPIO_PFCE4_PFCE411 (0x0800u) +#define GPIO_PFCE4_PFCE412 (0x1000u) +#define GPIO_PFCE4_PFCE413 (0x2000u) +#define GPIO_PFCE4_PFCE414 (0x4000u) +#define GPIO_PFCE4_PFCE415 (0x8000u) + +#define GPIO_PNOT4_PNOT40 (0x0001u) +#define GPIO_PNOT4_PNOT41 (0x0002u) +#define GPIO_PNOT4_PNOT42 (0x0004u) +#define GPIO_PNOT4_PNOT43 (0x0008u) +#define GPIO_PNOT4_PNOT44 (0x0010u) +#define GPIO_PNOT4_PNOT45 (0x0020u) +#define GPIO_PNOT4_PNOT46 (0x0040u) +#define GPIO_PNOT4_PNOT47 (0x0080u) +#define GPIO_PNOT4_PNOT48 (0x0100u) +#define GPIO_PNOT4_PNOT49 (0x0200u) +#define GPIO_PNOT4_PNOT410 (0x0400u) +#define GPIO_PNOT4_PNOT411 (0x0800u) +#define GPIO_PNOT4_PNOT412 (0x1000u) +#define GPIO_PNOT4_PNOT413 (0x2000u) +#define GPIO_PNOT4_PNOT414 (0x4000u) +#define GPIO_PNOT4_PNOT415 (0x8000u) + +#define GPIO_PMSR4_PMSR40 (0x00000001uL) +#define GPIO_PMSR4_PMSR41 (0x00000002uL) +#define GPIO_PMSR4_PMSR42 (0x00000004uL) +#define GPIO_PMSR4_PMSR43 (0x00000008uL) +#define GPIO_PMSR4_PMSR44 (0x00000010uL) +#define GPIO_PMSR4_PMSR45 (0x00000020uL) +#define GPIO_PMSR4_PMSR46 (0x00000040uL) +#define GPIO_PMSR4_PMSR47 (0x00000080uL) +#define GPIO_PMSR4_PMSR48 (0x00000100uL) +#define GPIO_PMSR4_PMSR49 (0x00000200uL) +#define GPIO_PMSR4_PMSR410 (0x00000400uL) +#define GPIO_PMSR4_PMSR411 (0x00000800uL) +#define GPIO_PMSR4_PMSR412 (0x00001000uL) +#define GPIO_PMSR4_PMSR413 (0x00002000uL) +#define GPIO_PMSR4_PMSR414 (0x00004000uL) +#define GPIO_PMSR4_PMSR415 (0x00008000uL) +#define GPIO_PMSR4_PMSR416 (0x00010000uL) +#define GPIO_PMSR4_PMSR417 (0x00020000uL) +#define GPIO_PMSR4_PMSR418 (0x00040000uL) +#define GPIO_PMSR4_PMSR419 (0x00080000uL) +#define GPIO_PMSR4_PMSR420 (0x00100000uL) +#define GPIO_PMSR4_PMSR421 (0x00200000uL) +#define GPIO_PMSR4_PMSR422 (0x00400000uL) +#define GPIO_PMSR4_PMSR423 (0x00800000uL) +#define GPIO_PMSR4_PMSR424 (0x01000000uL) +#define GPIO_PMSR4_PMSR425 (0x02000000uL) +#define GPIO_PMSR4_PMSR426 (0x04000000uL) +#define GPIO_PMSR4_PMSR427 (0x08000000uL) +#define GPIO_PMSR4_PMSR428 (0x10000000uL) +#define GPIO_PMSR4_PMSR429 (0x20000000uL) +#define GPIO_PMSR4_PMSR430 (0x40000000uL) +#define GPIO_PMSR4_PMSR431 (0x80000000uL) + +#define GPIO_PMCSR4_PMCSR40 (0x00000001uL) +#define GPIO_PMCSR4_PMCSR41 (0x00000002uL) +#define GPIO_PMCSR4_PMCSR42 (0x00000004uL) +#define GPIO_PMCSR4_PMCSR43 (0x00000008uL) +#define GPIO_PMCSR4_PMCSR44 (0x00000010uL) +#define GPIO_PMCSR4_PMCSR45 (0x00000020uL) +#define GPIO_PMCSR4_PMCSR46 (0x00000040uL) +#define GPIO_PMCSR4_PMCSR47 (0x00000080uL) +#define GPIO_PMCSR4_PMCSR48 (0x00000100uL) +#define GPIO_PMCSR4_PMCSR49 (0x00000200uL) +#define GPIO_PMCSR4_PMCSR410 (0x00000400uL) +#define GPIO_PMCSR4_PMCSR411 (0x00000800uL) +#define GPIO_PMCSR4_PMCSR412 (0x00001000uL) +#define GPIO_PMCSR4_PMCSR413 (0x00002000uL) +#define GPIO_PMCSR4_PMCSR414 (0x00004000uL) +#define GPIO_PMCSR4_PMCSR415 (0x00008000uL) +#define GPIO_PMCSR4_PMCSR416 (0x00010000uL) +#define GPIO_PMCSR4_PMCSR417 (0x00020000uL) +#define GPIO_PMCSR4_PMCSR418 (0x00040000uL) +#define GPIO_PMCSR4_PMCSR419 (0x00080000uL) +#define GPIO_PMCSR4_PMCSR420 (0x00100000uL) +#define GPIO_PMCSR4_PMCSR421 (0x00200000uL) +#define GPIO_PMCSR4_PMCSR422 (0x00400000uL) +#define GPIO_PMCSR4_PMCSR423 (0x00800000uL) +#define GPIO_PMCSR4_PMCSR424 (0x01000000uL) +#define GPIO_PMCSR4_PMCSR425 (0x02000000uL) +#define GPIO_PMCSR4_PMCSR426 (0x04000000uL) +#define GPIO_PMCSR4_PMCSR427 (0x08000000uL) +#define GPIO_PMCSR4_PMCSR428 (0x10000000uL) +#define GPIO_PMCSR4_PMCSR429 (0x20000000uL) +#define GPIO_PMCSR4_PMCSR430 (0x40000000uL) +#define GPIO_PMCSR4_PMCSR431 (0x80000000uL) + +#define GPIO_PFCAE4_PFCAE40 (0x0001u) +#define GPIO_PFCAE4_PFCAE41 (0x0002u) +#define GPIO_PFCAE4_PFCAE42 (0x0004u) +#define GPIO_PFCAE4_PFCAE43 (0x0008u) +#define GPIO_PFCAE4_PFCAE44 (0x0010u) +#define GPIO_PFCAE4_PFCAE45 (0x0020u) +#define GPIO_PFCAE4_PFCAE46 (0x0040u) +#define GPIO_PFCAE4_PFCAE47 (0x0080u) +#define GPIO_PFCAE4_PFCAE48 (0x0100u) +#define GPIO_PFCAE4_PFCAE49 (0x0200u) +#define GPIO_PFCAE4_PFCAE410 (0x0400u) +#define GPIO_PFCAE4_PFCAE411 (0x0800u) +#define GPIO_PFCAE4_PFCAE412 (0x1000u) +#define GPIO_PFCAE4_PFCAE413 (0x2000u) +#define GPIO_PFCAE4_PFCAE414 (0x4000u) +#define GPIO_PFCAE4_PFCAE415 (0x8000u) + +#define GPIO_PIBC4_PIBC40 (0x0001u) +#define GPIO_PIBC4_PIBC41 (0x0002u) +#define GPIO_PIBC4_PIBC42 (0x0004u) +#define GPIO_PIBC4_PIBC43 (0x0008u) +#define GPIO_PIBC4_PIBC44 (0x0010u) +#define GPIO_PIBC4_PIBC45 (0x0020u) +#define GPIO_PIBC4_PIBC46 (0x0040u) +#define GPIO_PIBC4_PIBC47 (0x0080u) +#define GPIO_PIBC4_PIBC48 (0x0100u) +#define GPIO_PIBC4_PIBC49 (0x0200u) +#define GPIO_PIBC4_PIBC410 (0x0400u) +#define GPIO_PIBC4_PIBC411 (0x0800u) +#define GPIO_PIBC4_PIBC412 (0x1000u) +#define GPIO_PIBC4_PIBC413 (0x2000u) +#define GPIO_PIBC4_PIBC414 (0x4000u) +#define GPIO_PIBC4_PIBC415 (0x8000u) + +#define GPIO_PBDC4_PBDC40 (0x0001u) +#define GPIO_PBDC4_PBDC41 (0x0002u) +#define GPIO_PBDC4_PBDC42 (0x0004u) +#define GPIO_PBDC4_PBDC43 (0x0008u) +#define GPIO_PBDC4_PBDC44 (0x0010u) +#define GPIO_PBDC4_PBDC45 (0x0020u) +#define GPIO_PBDC4_PBDC46 (0x0040u) +#define GPIO_PBDC4_PBDC47 (0x0080u) +#define GPIO_PBDC4_PBDC48 (0x0100u) +#define GPIO_PBDC4_PBDC49 (0x0200u) +#define GPIO_PBDC4_PBDC410 (0x0400u) +#define GPIO_PBDC4_PBDC411 (0x0800u) +#define GPIO_PBDC4_PBDC412 (0x1000u) +#define GPIO_PBDC4_PBDC413 (0x2000u) +#define GPIO_PBDC4_PBDC414 (0x4000u) +#define GPIO_PBDC4_PBDC415 (0x8000u) + +#define GPIO_PIPC4_PIPC40 (0x0001u) +#define GPIO_PIPC4_PIPC41 (0x0002u) +#define GPIO_PIPC4_PIPC42 (0x0004u) +#define GPIO_PIPC4_PIPC43 (0x0008u) +#define GPIO_PIPC4_PIPC44 (0x0010u) +#define GPIO_PIPC4_PIPC45 (0x0020u) +#define GPIO_PIPC4_PIPC46 (0x0040u) +#define GPIO_PIPC4_PIPC47 (0x0080u) +#define GPIO_PIPC4_PIPC48 (0x0100u) +#define GPIO_PIPC4_PIPC49 (0x0200u) +#define GPIO_PIPC4_PIPC410 (0x0400u) +#define GPIO_PIPC4_PIPC411 (0x0800u) +#define GPIO_PIPC4_PIPC412 (0x1000u) +#define GPIO_PIPC4_PIPC413 (0x2000u) +#define GPIO_PIPC4_PIPC414 (0x4000u) +#define GPIO_PIPC4_PIPC415 (0x8000u) + +/* ---- P5 ---- */ +#define GPIO_P5_P50 (0x0001u) +#define GPIO_P5_P51 (0x0002u) +#define GPIO_P5_P52 (0x0004u) +#define GPIO_P5_P53 (0x0008u) +#define GPIO_P5_P54 (0x0010u) +#define GPIO_P5_P55 (0x0020u) +#define GPIO_P5_P56 (0x0040u) +#define GPIO_P5_P57 (0x0080u) +#define GPIO_P5_P58 (0x0100u) +#define GPIO_P5_P59 (0x0200u) +#define GPIO_P5_P510 (0x0400u) + +#define GPIO_PSR5_PSR50 (0x00000001uL) +#define GPIO_PSR5_PSR51 (0x00000002uL) +#define GPIO_PSR5_PSR52 (0x00000004uL) +#define GPIO_PSR5_PSR53 (0x00000008uL) +#define GPIO_PSR5_PSR54 (0x00000010uL) +#define GPIO_PSR5_PSR55 (0x00000020uL) +#define GPIO_PSR5_PSR56 (0x00000040uL) +#define GPIO_PSR5_PSR57 (0x00000080uL) +#define GPIO_PSR5_PSR58 (0x00000100uL) +#define GPIO_PSR5_PSR59 (0x00000200uL) +#define GPIO_PSR5_PSR510 (0x00000400uL) +#define GPIO_PSR5_PSR516 (0x00010000uL) +#define GPIO_PSR5_PSR517 (0x00020000uL) +#define GPIO_PSR5_PSR518 (0x00040000uL) +#define GPIO_PSR5_PSR519 (0x00080000uL) +#define GPIO_PSR5_PSR520 (0x00100000uL) +#define GPIO_PSR5_PSR521 (0x00200000uL) +#define GPIO_PSR5_PSR522 (0x00400000uL) +#define GPIO_PSR5_PSR523 (0x00800000uL) +#define GPIO_PSR5_PSR524 (0x01000000uL) +#define GPIO_PSR5_PSR525 (0x02000000uL) +#define GPIO_PSR5_PSR526 (0x04000000uL) + +#define GPIO_PPR5_PPR50 (0x0001u) +#define GPIO_PPR5_PPR51 (0x0002u) +#define GPIO_PPR5_PPR52 (0x0004u) +#define GPIO_PPR5_PPR53 (0x0008u) +#define GPIO_PPR5_PPR54 (0x0010u) +#define GPIO_PPR5_PPR55 (0x0020u) +#define GPIO_PPR5_PPR56 (0x0040u) +#define GPIO_PPR5_PPR57 (0x0080u) +#define GPIO_PPR5_PPR58 (0x0100u) +#define GPIO_PPR5_PPR59 (0x0200u) +#define GPIO_PPR5_PPR510 (0x0400u) + +#define GPIO_PM5_PM50 (0x0001u) +#define GPIO_PM5_PM51 (0x0002u) +#define GPIO_PM5_PM52 (0x0004u) +#define GPIO_PM5_PM53 (0x0008u) +#define GPIO_PM5_PM54 (0x0010u) +#define GPIO_PM5_PM55 (0x0020u) +#define GPIO_PM5_PM56 (0x0040u) +#define GPIO_PM5_PM57 (0x0080u) +#define GPIO_PM5_PM58 (0x0100u) +#define GPIO_PM5_PM59 (0x0200u) +#define GPIO_PM5_PM510 (0x0400u) + +#define GPIO_PMC5_PMC50 (0x0001u) +#define GPIO_PMC5_PMC51 (0x0002u) +#define GPIO_PMC5_PMC52 (0x0004u) +#define GPIO_PMC5_PMC53 (0x0008u) +#define GPIO_PMC5_PMC54 (0x0010u) +#define GPIO_PMC5_PMC55 (0x0020u) +#define GPIO_PMC5_PMC56 (0x0040u) +#define GPIO_PMC5_PMC57 (0x0080u) +#define GPIO_PMC5_PMC58 (0x0100u) +#define GPIO_PMC5_PMC59 (0x0200u) +#define GPIO_PMC5_PMC510 (0x0400u) + +#define GPIO_PFC5_PFC50 (0x0001u) +#define GPIO_PFC5_PFC51 (0x0002u) +#define GPIO_PFC5_PFC52 (0x0004u) +#define GPIO_PFC5_PFC53 (0x0008u) +#define GPIO_PFC5_PFC54 (0x0010u) +#define GPIO_PFC5_PFC55 (0x0020u) +#define GPIO_PFC5_PFC56 (0x0040u) +#define GPIO_PFC5_PFC57 (0x0080u) +#define GPIO_PFC5_PFC58 (0x0100u) +#define GPIO_PFC5_PFC59 (0x0200u) +#define GPIO_PFC5_PFC510 (0x0400u) + +#define GPIO_PFCE5_PFCE50 (0x0001u) +#define GPIO_PFCE5_PFCE51 (0x0002u) +#define GPIO_PFCE5_PFCE52 (0x0004u) +#define GPIO_PFCE5_PFCE53 (0x0008u) +#define GPIO_PFCE5_PFCE54 (0x0010u) +#define GPIO_PFCE5_PFCE55 (0x0020u) +#define GPIO_PFCE5_PFCE56 (0x0040u) +#define GPIO_PFCE5_PFCE57 (0x0080u) +#define GPIO_PFCE5_PFCE58 (0x0100u) +#define GPIO_PFCE5_PFCE59 (0x0200u) +#define GPIO_PFCE5_PFCE510 (0x0400u) + +#define GPIO_PNOT5_PNOT50 (0x0001u) +#define GPIO_PNOT5_PNOT51 (0x0002u) +#define GPIO_PNOT5_PNOT52 (0x0004u) +#define GPIO_PNOT5_PNOT53 (0x0008u) +#define GPIO_PNOT5_PNOT54 (0x0010u) +#define GPIO_PNOT5_PNOT55 (0x0020u) +#define GPIO_PNOT5_PNOT56 (0x0040u) +#define GPIO_PNOT5_PNOT57 (0x0080u) +#define GPIO_PNOT5_PNOT58 (0x0100u) +#define GPIO_PNOT5_PNOT59 (0x0200u) +#define GPIO_PNOT5_PNOT510 (0x0400u) + +#define GPIO_PMSR5_PMSR50 (0x00000001uL) +#define GPIO_PMSR5_PMSR51 (0x00000002uL) +#define GPIO_PMSR5_PMSR52 (0x00000004uL) +#define GPIO_PMSR5_PMSR53 (0x00000008uL) +#define GPIO_PMSR5_PMSR54 (0x00000010uL) +#define GPIO_PMSR5_PMSR55 (0x00000020uL) +#define GPIO_PMSR5_PMSR56 (0x00000040uL) +#define GPIO_PMSR5_PMSR57 (0x00000080uL) +#define GPIO_PMSR5_PMSR58 (0x00000100uL) +#define GPIO_PMSR5_PMSR59 (0x00000200uL) +#define GPIO_PMSR5_PMSR510 (0x00000400uL) +#define GPIO_PMSR5_PMSR516 (0x00010000uL) +#define GPIO_PMSR5_PMSR517 (0x00020000uL) +#define GPIO_PMSR5_PMSR518 (0x00040000uL) +#define GPIO_PMSR5_PMSR519 (0x00080000uL) +#define GPIO_PMSR5_PMSR520 (0x00100000uL) +#define GPIO_PMSR5_PMSR521 (0x00200000uL) +#define GPIO_PMSR5_PMSR522 (0x00400000uL) +#define GPIO_PMSR5_PMSR523 (0x00800000uL) +#define GPIO_PMSR5_PMSR524 (0x01000000uL) +#define GPIO_PMSR5_PMSR525 (0x02000000uL) +#define GPIO_PMSR5_PMSR526 (0x04000000uL) + +#define GPIO_PMCSR5_PMCSR50 (0x00000001uL) +#define GPIO_PMCSR5_PMCSR51 (0x00000002uL) +#define GPIO_PMCSR5_PMCSR52 (0x00000004uL) +#define GPIO_PMCSR5_PMCSR53 (0x00000008uL) +#define GPIO_PMCSR5_PMCSR54 (0x00000010uL) +#define GPIO_PMCSR5_PMCSR55 (0x00000020uL) +#define GPIO_PMCSR5_PMCSR56 (0x00000040uL) +#define GPIO_PMCSR5_PMCSR57 (0x00000080uL) +#define GPIO_PMCSR5_PMCSR58 (0x00000100uL) +#define GPIO_PMCSR5_PMCSR59 (0x00000200uL) +#define GPIO_PMCSR5_PMCSR510 (0x00000400uL) +#define GPIO_PMCSR5_PMCSR516 (0x00010000uL) +#define GPIO_PMCSR5_PMCSR517 (0x00020000uL) +#define GPIO_PMCSR5_PMCSR518 (0x00040000uL) +#define GPIO_PMCSR5_PMCSR519 (0x00080000uL) +#define GPIO_PMCSR5_PMCSR520 (0x00100000uL) +#define GPIO_PMCSR5_PMCSR521 (0x00200000uL) +#define GPIO_PMCSR5_PMCSR522 (0x00400000uL) +#define GPIO_PMCSR5_PMCSR523 (0x00800000uL) +#define GPIO_PMCSR5_PMCSR524 (0x01000000uL) +#define GPIO_PMCSR5_PMCSR525 (0x02000000uL) +#define GPIO_PMCSR5_PMCSR526 (0x04000000uL) + +#define GPIO_PFCAE5_PFCAE50 (0x0001u) +#define GPIO_PFCAE5_PFCAE51 (0x0002u) +#define GPIO_PFCAE5_PFCAE52 (0x0004u) +#define GPIO_PFCAE5_PFCAE53 (0x0008u) +#define GPIO_PFCAE5_PFCAE54 (0x0010u) +#define GPIO_PFCAE5_PFCAE55 (0x0020u) +#define GPIO_PFCAE5_PFCAE56 (0x0040u) +#define GPIO_PFCAE5_PFCAE57 (0x0080u) +#define GPIO_PFCAE5_PFCAE58 (0x0100u) +#define GPIO_PFCAE5_PFCAE59 (0x0200u) +#define GPIO_PFCAE5_PFCAE510 (0x0400u) + +#define GPIO_PIBC5_PIBC50 (0x0001u) +#define GPIO_PIBC5_PIBC51 (0x0002u) +#define GPIO_PIBC5_PIBC52 (0x0004u) +#define GPIO_PIBC5_PIBC53 (0x0008u) +#define GPIO_PIBC5_PIBC54 (0x0010u) +#define GPIO_PIBC5_PIBC55 (0x0020u) +#define GPIO_PIBC5_PIBC56 (0x0040u) +#define GPIO_PIBC5_PIBC57 (0x0080u) +#define GPIO_PIBC5_PIBC58 (0x0100u) +#define GPIO_PIBC5_PIBC59 (0x0200u) +#define GPIO_PIBC5_PIBC510 (0x0400u) + +#define GPIO_PBDC5_PBDC50 (0x0001u) +#define GPIO_PBDC5_PBDC51 (0x0002u) +#define GPIO_PBDC5_PBDC52 (0x0004u) +#define GPIO_PBDC5_PBDC53 (0x0008u) +#define GPIO_PBDC5_PBDC54 (0x0010u) +#define GPIO_PBDC5_PBDC55 (0x0020u) +#define GPIO_PBDC5_PBDC56 (0x0040u) +#define GPIO_PBDC5_PBDC57 (0x0080u) +#define GPIO_PBDC5_PBDC58 (0x0100u) +#define GPIO_PBDC5_PBDC59 (0x0200u) +#define GPIO_PBDC5_PBDC510 (0x0400u) + +#define GPIO_PIPC5_PIPC50 (0x0001u) +#define GPIO_PIPC5_PIPC51 (0x0002u) +#define GPIO_PIPC5_PIPC52 (0x0004u) +#define GPIO_PIPC5_PIPC53 (0x0008u) +#define GPIO_PIPC5_PIPC54 (0x0010u) +#define GPIO_PIPC5_PIPC55 (0x0020u) +#define GPIO_PIPC5_PIPC56 (0x0040u) +#define GPIO_PIPC5_PIPC57 (0x0080u) +#define GPIO_PIPC5_PIPC58 (0x0100u) +#define GPIO_PIPC5_PIPC59 (0x0200u) +#define GPIO_PIPC5_PIPC510 (0x0400u) + +/* ---- P6 ---- */ +#define GPIO_P6_P60 (0x0001u) +#define GPIO_P6_P61 (0x0002u) +#define GPIO_P6_P62 (0x0004u) +#define GPIO_P6_P63 (0x0008u) +#define GPIO_P6_P64 (0x0010u) +#define GPIO_P6_P65 (0x0020u) +#define GPIO_P6_P66 (0x0040u) +#define GPIO_P6_P67 (0x0080u) +#define GPIO_P6_P68 (0x0100u) +#define GPIO_P6_P69 (0x0200u) +#define GPIO_P6_P610 (0x0400u) +#define GPIO_P6_P611 (0x0800u) +#define GPIO_P6_P612 (0x1000u) +#define GPIO_P6_P613 (0x2000u) +#define GPIO_P6_P614 (0x4000u) +#define GPIO_P6_P615 (0x8000u) + +#define GPIO_PSR6_PSR60 (0x00000001uL) +#define GPIO_PSR6_PSR61 (0x00000002uL) +#define GPIO_PSR6_PSR62 (0x00000004uL) +#define GPIO_PSR6_PSR63 (0x00000008uL) +#define GPIO_PSR6_PSR64 (0x00000010uL) +#define GPIO_PSR6_PSR65 (0x00000020uL) +#define GPIO_PSR6_PSR66 (0x00000040uL) +#define GPIO_PSR6_PSR67 (0x00000080uL) +#define GPIO_PSR6_PSR68 (0x00000100uL) +#define GPIO_PSR6_PSR69 (0x00000200uL) +#define GPIO_PSR6_PSR610 (0x00000400uL) +#define GPIO_PSR6_PSR611 (0x00000800uL) +#define GPIO_PSR6_PSR612 (0x00001000uL) +#define GPIO_PSR6_PSR613 (0x00002000uL) +#define GPIO_PSR6_PSR614 (0x00004000uL) +#define GPIO_PSR6_PSR615 (0x00008000uL) +#define GPIO_PSR6_PSR616 (0x00010000uL) +#define GPIO_PSR6_PSR617 (0x00020000uL) +#define GPIO_PSR6_PSR618 (0x00040000uL) +#define GPIO_PSR6_PSR619 (0x00080000uL) +#define GPIO_PSR6_PSR620 (0x00100000uL) +#define GPIO_PSR6_PSR621 (0x00200000uL) +#define GPIO_PSR6_PSR622 (0x00400000uL) +#define GPIO_PSR6_PSR623 (0x00800000uL) +#define GPIO_PSR6_PSR624 (0x01000000uL) +#define GPIO_PSR6_PSR625 (0x02000000uL) +#define GPIO_PSR6_PSR626 (0x04000000uL) +#define GPIO_PSR6_PSR627 (0x08000000uL) +#define GPIO_PSR6_PSR628 (0x10000000uL) +#define GPIO_PSR6_PSR629 (0x20000000uL) +#define GPIO_PSR6_PSR630 (0x40000000uL) +#define GPIO_PSR6_PSR631 (0x80000000uL) + +#define GPIO_PPR6_PPR60 (0x0001u) +#define GPIO_PPR6_PPR61 (0x0002u) +#define GPIO_PPR6_PPR62 (0x0004u) +#define GPIO_PPR6_PPR63 (0x0008u) +#define GPIO_PPR6_PPR64 (0x0010u) +#define GPIO_PPR6_PPR65 (0x0020u) +#define GPIO_PPR6_PPR66 (0x0040u) +#define GPIO_PPR6_PPR67 (0x0080u) +#define GPIO_PPR6_PPR68 (0x0100u) +#define GPIO_PPR6_PPR69 (0x0200u) +#define GPIO_PPR6_PPR610 (0x0400u) +#define GPIO_PPR6_PPR611 (0x0800u) +#define GPIO_PPR6_PPR612 (0x1000u) +#define GPIO_PPR6_PPR613 (0x2000u) +#define GPIO_PPR6_PPR614 (0x4000u) +#define GPIO_PPR6_PPR615 (0x8000u) + +#define GPIO_PM6_PM60 (0x0001u) +#define GPIO_PM6_PM61 (0x0002u) +#define GPIO_PM6_PM62 (0x0004u) +#define GPIO_PM6_PM63 (0x0008u) +#define GPIO_PM6_PM64 (0x0010u) +#define GPIO_PM6_PM65 (0x0020u) +#define GPIO_PM6_PM66 (0x0040u) +#define GPIO_PM6_PM67 (0x0080u) +#define GPIO_PM6_PM68 (0x0100u) +#define GPIO_PM6_PM69 (0x0200u) +#define GPIO_PM6_PM610 (0x0400u) +#define GPIO_PM6_PM611 (0x0800u) +#define GPIO_PM6_PM612 (0x1000u) +#define GPIO_PM6_PM613 (0x2000u) +#define GPIO_PM6_PM614 (0x4000u) +#define GPIO_PM6_PM615 (0x8000u) + +#define GPIO_PMC6_PMC60 (0x0001u) +#define GPIO_PMC6_PMC61 (0x0002u) +#define GPIO_PMC6_PMC62 (0x0004u) +#define GPIO_PMC6_PMC63 (0x0008u) +#define GPIO_PMC6_PMC64 (0x0010u) +#define GPIO_PMC6_PMC65 (0x0020u) +#define GPIO_PMC6_PMC66 (0x0040u) +#define GPIO_PMC6_PMC67 (0x0080u) +#define GPIO_PMC6_PMC68 (0x0100u) +#define GPIO_PMC6_PMC69 (0x0200u) +#define GPIO_PMC6_PMC610 (0x0400u) +#define GPIO_PMC6_PMC611 (0x0800u) +#define GPIO_PMC6_PMC612 (0x1000u) +#define GPIO_PMC6_PMC613 (0x2000u) +#define GPIO_PMC6_PMC614 (0x4000u) +#define GPIO_PMC6_PMC615 (0x8000u) + +#define GPIO_PFC6_PFC60 (0x0001u) +#define GPIO_PFC6_PFC61 (0x0002u) +#define GPIO_PFC6_PFC62 (0x0004u) +#define GPIO_PFC6_PFC63 (0x0008u) +#define GPIO_PFC6_PFC64 (0x0010u) +#define GPIO_PFC6_PFC65 (0x0020u) +#define GPIO_PFC6_PFC66 (0x0040u) +#define GPIO_PFC6_PFC67 (0x0080u) +#define GPIO_PFC6_PFC68 (0x0100u) +#define GPIO_PFC6_PFC69 (0x0200u) +#define GPIO_PFC6_PFC610 (0x0400u) +#define GPIO_PFC6_PFC611 (0x0800u) +#define GPIO_PFC6_PFC612 (0x1000u) +#define GPIO_PFC6_PFC613 (0x2000u) +#define GPIO_PFC6_PFC614 (0x4000u) +#define GPIO_PFC6_PFC615 (0x8000u) + +#define GPIO_PFCE6_PFCE60 (0x0001u) +#define GPIO_PFCE6_PFCE61 (0x0002u) +#define GPIO_PFCE6_PFCE62 (0x0004u) +#define GPIO_PFCE6_PFCE63 (0x0008u) +#define GPIO_PFCE6_PFCE64 (0x0010u) +#define GPIO_PFCE6_PFCE65 (0x0020u) +#define GPIO_PFCE6_PFCE66 (0x0040u) +#define GPIO_PFCE6_PFCE67 (0x0080u) +#define GPIO_PFCE6_PFCE68 (0x0100u) +#define GPIO_PFCE6_PFCE69 (0x0200u) +#define GPIO_PFCE6_PFCE610 (0x0400u) +#define GPIO_PFCE6_PFCE611 (0x0800u) +#define GPIO_PFCE6_PFCE612 (0x1000u) +#define GPIO_PFCE6_PFCE613 (0x2000u) +#define GPIO_PFCE6_PFCE614 (0x4000u) +#define GPIO_PFCE6_PFCE615 (0x8000u) + +#define GPIO_PNOT6_PNOT60 (0x0001u) +#define GPIO_PNOT6_PNOT61 (0x0002u) +#define GPIO_PNOT6_PNOT62 (0x0004u) +#define GPIO_PNOT6_PNOT63 (0x0008u) +#define GPIO_PNOT6_PNOT64 (0x0010u) +#define GPIO_PNOT6_PNOT65 (0x0020u) +#define GPIO_PNOT6_PNOT66 (0x0040u) +#define GPIO_PNOT6_PNOT67 (0x0080u) +#define GPIO_PNOT6_PNOT68 (0x0100u) +#define GPIO_PNOT6_PNOT69 (0x0200u) +#define GPIO_PNOT6_PNOT610 (0x0400u) +#define GPIO_PNOT6_PNOT611 (0x0800u) +#define GPIO_PNOT6_PNOT612 (0x1000u) +#define GPIO_PNOT6_PNOT613 (0x2000u) +#define GPIO_PNOT6_PNOT614 (0x4000u) +#define GPIO_PNOT6_PNOT615 (0x8000u) + +#define GPIO_PMSR6_PMSR60 (0x00000001uL) +#define GPIO_PMSR6_PMSR61 (0x00000002uL) +#define GPIO_PMSR6_PMSR62 (0x00000004uL) +#define GPIO_PMSR6_PMSR63 (0x00000008uL) +#define GPIO_PMSR6_PMSR64 (0x00000010uL) +#define GPIO_PMSR6_PMSR65 (0x00000020uL) +#define GPIO_PMSR6_PMSR66 (0x00000040uL) +#define GPIO_PMSR6_PMSR67 (0x00000080uL) +#define GPIO_PMSR6_PMSR68 (0x00000100uL) +#define GPIO_PMSR6_PMSR69 (0x00000200uL) +#define GPIO_PMSR6_PMSR610 (0x00000400uL) +#define GPIO_PMSR6_PMSR611 (0x00000800uL) +#define GPIO_PMSR6_PMSR612 (0x00001000uL) +#define GPIO_PMSR6_PMSR613 (0x00002000uL) +#define GPIO_PMSR6_PMSR614 (0x00004000uL) +#define GPIO_PMSR6_PMSR615 (0x00008000uL) +#define GPIO_PMSR6_PMSR616 (0x00010000uL) +#define GPIO_PMSR6_PMSR617 (0x00020000uL) +#define GPIO_PMSR6_PMSR618 (0x00040000uL) +#define GPIO_PMSR6_PMSR619 (0x00080000uL) +#define GPIO_PMSR6_PMSR620 (0x00100000uL) +#define GPIO_PMSR6_PMSR621 (0x00200000uL) +#define GPIO_PMSR6_PMSR622 (0x00400000uL) +#define GPIO_PMSR6_PMSR623 (0x00800000uL) +#define GPIO_PMSR6_PMSR624 (0x01000000uL) +#define GPIO_PMSR6_PMSR625 (0x02000000uL) +#define GPIO_PMSR6_PMSR626 (0x04000000uL) +#define GPIO_PMSR6_PMSR627 (0x08000000uL) +#define GPIO_PMSR6_PMSR628 (0x10000000uL) +#define GPIO_PMSR6_PMSR629 (0x20000000uL) +#define GPIO_PMSR6_PMSR630 (0x40000000uL) +#define GPIO_PMSR6_PMSR631 (0x80000000uL) + +#define GPIO_PMCSR6_PMCSR60 (0x00000001uL) +#define GPIO_PMCSR6_PMCSR61 (0x00000002uL) +#define GPIO_PMCSR6_PMCSR62 (0x00000004uL) +#define GPIO_PMCSR6_PMCSR63 (0x00000008uL) +#define GPIO_PMCSR6_PMCSR64 (0x00000010uL) +#define GPIO_PMCSR6_PMCSR65 (0x00000020uL) +#define GPIO_PMCSR6_PMCSR66 (0x00000040uL) +#define GPIO_PMCSR6_PMCSR67 (0x00000080uL) +#define GPIO_PMCSR6_PMCSR68 (0x00000100uL) +#define GPIO_PMCSR6_PMCSR69 (0x00000200uL) +#define GPIO_PMCSR6_PMCSR610 (0x00000400uL) +#define GPIO_PMCSR6_PMCSR611 (0x00000800uL) +#define GPIO_PMCSR6_PMCSR612 (0x00001000uL) +#define GPIO_PMCSR6_PMCSR613 (0x00002000uL) +#define GPIO_PMCSR6_PMCSR614 (0x00004000uL) +#define GPIO_PMCSR6_PMCSR615 (0x00008000uL) +#define GPIO_PMCSR6_PMCSR616 (0x00010000uL) +#define GPIO_PMCSR6_PMCSR617 (0x00020000uL) +#define GPIO_PMCSR6_PMCSR618 (0x00040000uL) +#define GPIO_PMCSR6_PMCSR619 (0x00080000uL) +#define GPIO_PMCSR6_PMCSR620 (0x00100000uL) +#define GPIO_PMCSR6_PMCSR621 (0x00200000uL) +#define GPIO_PMCSR6_PMCSR622 (0x00400000uL) +#define GPIO_PMCSR6_PMCSR623 (0x00800000uL) +#define GPIO_PMCSR6_PMCSR624 (0x01000000uL) +#define GPIO_PMCSR6_PMCSR625 (0x02000000uL) +#define GPIO_PMCSR6_PMCSR626 (0x04000000uL) +#define GPIO_PMCSR6_PMCSR627 (0x08000000uL) +#define GPIO_PMCSR6_PMCSR628 (0x10000000uL) +#define GPIO_PMCSR6_PMCSR629 (0x20000000uL) +#define GPIO_PMCSR6_PMCSR630 (0x40000000uL) +#define GPIO_PMCSR6_PMCSR631 (0x80000000uL) + +#define GPIO_PFCAE6_PFCAE60 (0x0001u) +#define GPIO_PFCAE6_PFCAE61 (0x0002u) +#define GPIO_PFCAE6_PFCAE62 (0x0004u) +#define GPIO_PFCAE6_PFCAE63 (0x0008u) +#define GPIO_PFCAE6_PFCAE64 (0x0010u) +#define GPIO_PFCAE6_PFCAE65 (0x0020u) +#define GPIO_PFCAE6_PFCAE66 (0x0040u) +#define GPIO_PFCAE6_PFCAE67 (0x0080u) +#define GPIO_PFCAE6_PFCAE68 (0x0100u) +#define GPIO_PFCAE6_PFCAE69 (0x0200u) +#define GPIO_PFCAE6_PFCAE610 (0x0400u) +#define GPIO_PFCAE6_PFCAE611 (0x0800u) +#define GPIO_PFCAE6_PFCAE612 (0x1000u) +#define GPIO_PFCAE6_PFCAE613 (0x2000u) +#define GPIO_PFCAE6_PFCAE614 (0x4000u) +#define GPIO_PFCAE6_PFCAE615 (0x8000u) + +#define GPIO_PIBC6_PIBC60 (0x0001u) +#define GPIO_PIBC6_PIBC61 (0x0002u) +#define GPIO_PIBC6_PIBC62 (0x0004u) +#define GPIO_PIBC6_PIBC63 (0x0008u) +#define GPIO_PIBC6_PIBC64 (0x0010u) +#define GPIO_PIBC6_PIBC65 (0x0020u) +#define GPIO_PIBC6_PIBC66 (0x0040u) +#define GPIO_PIBC6_PIBC67 (0x0080u) +#define GPIO_PIBC6_PIBC68 (0x0100u) +#define GPIO_PIBC6_PIBC69 (0x0200u) +#define GPIO_PIBC6_PIBC610 (0x0400u) +#define GPIO_PIBC6_PIBC611 (0x0800u) +#define GPIO_PIBC6_PIBC612 (0x1000u) +#define GPIO_PIBC6_PIBC613 (0x2000u) +#define GPIO_PIBC6_PIBC614 (0x4000u) +#define GPIO_PIBC6_PIBC615 (0x8000u) + +#define GPIO_PBDC6_PBDC60 (0x0001u) +#define GPIO_PBDC6_PBDC61 (0x0002u) +#define GPIO_PBDC6_PBDC62 (0x0004u) +#define GPIO_PBDC6_PBDC63 (0x0008u) +#define GPIO_PBDC6_PBDC64 (0x0010u) +#define GPIO_PBDC6_PBDC65 (0x0020u) +#define GPIO_PBDC6_PBDC66 (0x0040u) +#define GPIO_PBDC6_PBDC67 (0x0080u) +#define GPIO_PBDC6_PBDC68 (0x0100u) +#define GPIO_PBDC6_PBDC69 (0x0200u) +#define GPIO_PBDC6_PBDC610 (0x0400u) +#define GPIO_PBDC6_PBDC611 (0x0800u) +#define GPIO_PBDC6_PBDC612 (0x1000u) +#define GPIO_PBDC6_PBDC613 (0x2000u) +#define GPIO_PBDC6_PBDC614 (0x4000u) +#define GPIO_PBDC6_PBDC615 (0x8000u) + +#define GPIO_PIPC6_PIPC60 (0x0001u) +#define GPIO_PIPC6_PIPC61 (0x0002u) +#define GPIO_PIPC6_PIPC62 (0x0004u) +#define GPIO_PIPC6_PIPC63 (0x0008u) +#define GPIO_PIPC6_PIPC64 (0x0010u) +#define GPIO_PIPC6_PIPC65 (0x0020u) +#define GPIO_PIPC6_PIPC66 (0x0040u) +#define GPIO_PIPC6_PIPC67 (0x0080u) +#define GPIO_PIPC6_PIPC68 (0x0100u) +#define GPIO_PIPC6_PIPC69 (0x0200u) +#define GPIO_PIPC6_PIPC610 (0x0400u) +#define GPIO_PIPC6_PIPC611 (0x0800u) +#define GPIO_PIPC6_PIPC612 (0x1000u) +#define GPIO_PIPC6_PIPC613 (0x2000u) +#define GPIO_PIPC6_PIPC614 (0x4000u) +#define GPIO_PIPC6_PIPC615 (0x8000u) + +/* ---- P7 ---- */ +#define GPIO_P7_P70 (0x0001u) +#define GPIO_P7_P71 (0x0002u) +#define GPIO_P7_P72 (0x0004u) +#define GPIO_P7_P73 (0x0008u) +#define GPIO_P7_P74 (0x0010u) +#define GPIO_P7_P75 (0x0020u) +#define GPIO_P7_P76 (0x0040u) +#define GPIO_P7_P77 (0x0080u) +#define GPIO_P7_P78 (0x0100u) +#define GPIO_P7_P79 (0x0200u) +#define GPIO_P7_P710 (0x0400u) +#define GPIO_P7_P711 (0x0800u) +#define GPIO_P7_P712 (0x1000u) +#define GPIO_P7_P713 (0x2000u) +#define GPIO_P7_P714 (0x4000u) +#define GPIO_P7_P715 (0x8000u) + +#define GPIO_PSR7_PSR70 (0x00000001uL) +#define GPIO_PSR7_PSR71 (0x00000002uL) +#define GPIO_PSR7_PSR72 (0x00000004uL) +#define GPIO_PSR7_PSR73 (0x00000008uL) +#define GPIO_PSR7_PSR74 (0x00000010uL) +#define GPIO_PSR7_PSR75 (0x00000020uL) +#define GPIO_PSR7_PSR76 (0x00000040uL) +#define GPIO_PSR7_PSR77 (0x00000080uL) +#define GPIO_PSR7_PSR78 (0x00000100uL) +#define GPIO_PSR7_PSR79 (0x00000200uL) +#define GPIO_PSR7_PSR710 (0x00000400uL) +#define GPIO_PSR7_PSR711 (0x00000800uL) +#define GPIO_PSR7_PSR712 (0x00001000uL) +#define GPIO_PSR7_PSR713 (0x00002000uL) +#define GPIO_PSR7_PSR714 (0x00004000uL) +#define GPIO_PSR7_PSR715 (0x00008000uL) +#define GPIO_PSR7_PSR716 (0x00010000uL) +#define GPIO_PSR7_PSR717 (0x00020000uL) +#define GPIO_PSR7_PSR718 (0x00040000uL) +#define GPIO_PSR7_PSR719 (0x00080000uL) +#define GPIO_PSR7_PSR720 (0x00100000uL) +#define GPIO_PSR7_PSR721 (0x00200000uL) +#define GPIO_PSR7_PSR722 (0x00400000uL) +#define GPIO_PSR7_PSR723 (0x00800000uL) +#define GPIO_PSR7_PSR724 (0x01000000uL) +#define GPIO_PSR7_PSR725 (0x02000000uL) +#define GPIO_PSR7_PSR726 (0x04000000uL) +#define GPIO_PSR7_PSR727 (0x08000000uL) +#define GPIO_PSR7_PSR728 (0x10000000uL) +#define GPIO_PSR7_PSR729 (0x20000000uL) +#define GPIO_PSR7_PSR730 (0x40000000uL) +#define GPIO_PSR7_PSR731 (0x80000000uL) + +#define GPIO_PPR7_PPR70 (0x0001u) +#define GPIO_PPR7_PPR71 (0x0002u) +#define GPIO_PPR7_PPR72 (0x0004u) +#define GPIO_PPR7_PPR73 (0x0008u) +#define GPIO_PPR7_PPR74 (0x0010u) +#define GPIO_PPR7_PPR75 (0x0020u) +#define GPIO_PPR7_PPR76 (0x0040u) +#define GPIO_PPR7_PPR77 (0x0080u) +#define GPIO_PPR7_PPR78 (0x0100u) +#define GPIO_PPR7_PPR79 (0x0200u) +#define GPIO_PPR7_PPR710 (0x0400u) +#define GPIO_PPR7_PPR711 (0x0800u) +#define GPIO_PPR7_PPR712 (0x1000u) +#define GPIO_PPR7_PPR713 (0x2000u) +#define GPIO_PPR7_PPR714 (0x4000u) +#define GPIO_PPR7_PPR715 (0x8000u) + +#define GPIO_PM7_PM70 (0x0001u) +#define GPIO_PM7_PM71 (0x0002u) +#define GPIO_PM7_PM72 (0x0004u) +#define GPIO_PM7_PM73 (0x0008u) +#define GPIO_PM7_PM74 (0x0010u) +#define GPIO_PM7_PM75 (0x0020u) +#define GPIO_PM7_PM76 (0x0040u) +#define GPIO_PM7_PM77 (0x0080u) +#define GPIO_PM7_PM78 (0x0100u) +#define GPIO_PM7_PM79 (0x0200u) +#define GPIO_PM7_PM710 (0x0400u) +#define GPIO_PM7_PM711 (0x0800u) +#define GPIO_PM7_PM712 (0x1000u) +#define GPIO_PM7_PM713 (0x2000u) +#define GPIO_PM7_PM714 (0x4000u) +#define GPIO_PM7_PM715 (0x8000u) + +#define GPIO_PMC7_PMC70 (0x0001u) +#define GPIO_PMC7_PMC71 (0x0002u) +#define GPIO_PMC7_PMC72 (0x0004u) +#define GPIO_PMC7_PMC73 (0x0008u) +#define GPIO_PMC7_PMC74 (0x0010u) +#define GPIO_PMC7_PMC75 (0x0020u) +#define GPIO_PMC7_PMC76 (0x0040u) +#define GPIO_PMC7_PMC77 (0x0080u) +#define GPIO_PMC7_PMC78 (0x0100u) +#define GPIO_PMC7_PMC79 (0x0200u) +#define GPIO_PMC7_PMC710 (0x0400u) +#define GPIO_PMC7_PMC711 (0x0800u) +#define GPIO_PMC7_PMC712 (0x1000u) +#define GPIO_PMC7_PMC713 (0x2000u) +#define GPIO_PMC7_PMC714 (0x4000u) +#define GPIO_PMC7_PMC715 (0x8000u) + +#define GPIO_PFC7_PFC70 (0x0001u) +#define GPIO_PFC7_PFC71 (0x0002u) +#define GPIO_PFC7_PFC72 (0x0004u) +#define GPIO_PFC7_PFC73 (0x0008u) +#define GPIO_PFC7_PFC74 (0x0010u) +#define GPIO_PFC7_PFC75 (0x0020u) +#define GPIO_PFC7_PFC76 (0x0040u) +#define GPIO_PFC7_PFC77 (0x0080u) +#define GPIO_PFC7_PFC78 (0x0100u) +#define GPIO_PFC7_PFC79 (0x0200u) +#define GPIO_PFC7_PFC710 (0x0400u) +#define GPIO_PFC7_PFC711 (0x0800u) +#define GPIO_PFC7_PFC712 (0x1000u) +#define GPIO_PFC7_PFC713 (0x2000u) +#define GPIO_PFC7_PFC714 (0x4000u) +#define GPIO_PFC7_PFC715 (0x8000u) + +#define GPIO_PFCE7_PFCE70 (0x0001u) +#define GPIO_PFCE7_PFCE71 (0x0002u) +#define GPIO_PFCE7_PFCE72 (0x0004u) +#define GPIO_PFCE7_PFCE73 (0x0008u) +#define GPIO_PFCE7_PFCE74 (0x0010u) +#define GPIO_PFCE7_PFCE75 (0x0020u) +#define GPIO_PFCE7_PFCE76 (0x0040u) +#define GPIO_PFCE7_PFCE77 (0x0080u) +#define GPIO_PFCE7_PFCE78 (0x0100u) +#define GPIO_PFCE7_PFCE79 (0x0200u) +#define GPIO_PFCE7_PFCE710 (0x0400u) +#define GPIO_PFCE7_PFCE711 (0x0800u) +#define GPIO_PFCE7_PFCE712 (0x1000u) +#define GPIO_PFCE7_PFCE713 (0x2000u) +#define GPIO_PFCE7_PFCE714 (0x4000u) +#define GPIO_PFCE7_PFCE715 (0x8000u) + +#define GPIO_PNOT7_PNOT70 (0x0001u) +#define GPIO_PNOT7_PNOT71 (0x0002u) +#define GPIO_PNOT7_PNOT72 (0x0004u) +#define GPIO_PNOT7_PNOT73 (0x0008u) +#define GPIO_PNOT7_PNOT74 (0x0010u) +#define GPIO_PNOT7_PNOT75 (0x0020u) +#define GPIO_PNOT7_PNOT76 (0x0040u) +#define GPIO_PNOT7_PNOT77 (0x0080u) +#define GPIO_PNOT7_PNOT78 (0x0100u) +#define GPIO_PNOT7_PNOT79 (0x0200u) +#define GPIO_PNOT7_PNOT710 (0x0400u) +#define GPIO_PNOT7_PNOT711 (0x0800u) +#define GPIO_PNOT7_PNOT712 (0x1000u) +#define GPIO_PNOT7_PNOT713 (0x2000u) +#define GPIO_PNOT7_PNOT714 (0x4000u) +#define GPIO_PNOT7_PNOT715 (0x8000u) + +#define GPIO_PMSR7_PMSR70 (0x00000001uL) +#define GPIO_PMSR7_PMSR71 (0x00000002uL) +#define GPIO_PMSR7_PMSR72 (0x00000004uL) +#define GPIO_PMSR7_PMSR73 (0x00000008uL) +#define GPIO_PMSR7_PMSR74 (0x00000010uL) +#define GPIO_PMSR7_PMSR75 (0x00000020uL) +#define GPIO_PMSR7_PMSR76 (0x00000040uL) +#define GPIO_PMSR7_PMSR77 (0x00000080uL) +#define GPIO_PMSR7_PMSR78 (0x00000100uL) +#define GPIO_PMSR7_PMSR79 (0x00000200uL) +#define GPIO_PMSR7_PMSR710 (0x00000400uL) +#define GPIO_PMSR7_PMSR711 (0x00000800uL) +#define GPIO_PMSR7_PMSR712 (0x00001000uL) +#define GPIO_PMSR7_PMSR713 (0x00002000uL) +#define GPIO_PMSR7_PMSR714 (0x00004000uL) +#define GPIO_PMSR7_PMSR715 (0x00008000uL) +#define GPIO_PMSR7_PMSR716 (0x00010000uL) +#define GPIO_PMSR7_PMSR717 (0x00020000uL) +#define GPIO_PMSR7_PMSR718 (0x00040000uL) +#define GPIO_PMSR7_PMSR719 (0x00080000uL) +#define GPIO_PMSR7_PMSR720 (0x00100000uL) +#define GPIO_PMSR7_PMSR721 (0x00200000uL) +#define GPIO_PMSR7_PMSR722 (0x00400000uL) +#define GPIO_PMSR7_PMSR723 (0x00800000uL) +#define GPIO_PMSR7_PMSR724 (0x01000000uL) +#define GPIO_PMSR7_PMSR725 (0x02000000uL) +#define GPIO_PMSR7_PMSR726 (0x04000000uL) +#define GPIO_PMSR7_PMSR727 (0x08000000uL) +#define GPIO_PMSR7_PMSR728 (0x10000000uL) +#define GPIO_PMSR7_PMSR729 (0x20000000uL) +#define GPIO_PMSR7_PMSR730 (0x40000000uL) +#define GPIO_PMSR7_PMSR731 (0x80000000uL) + +#define GPIO_PMCSR7_PMCSR70 (0x00000001uL) +#define GPIO_PMCSR7_PMCSR71 (0x00000002uL) +#define GPIO_PMCSR7_PMCSR72 (0x00000004uL) +#define GPIO_PMCSR7_PMCSR73 (0x00000008uL) +#define GPIO_PMCSR7_PMCSR74 (0x00000010uL) +#define GPIO_PMCSR7_PMCSR75 (0x00000020uL) +#define GPIO_PMCSR7_PMCSR76 (0x00000040uL) +#define GPIO_PMCSR7_PMCSR77 (0x00000080uL) +#define GPIO_PMCSR7_PMCSR78 (0x00000100uL) +#define GPIO_PMCSR7_PMCSR79 (0x00000200uL) +#define GPIO_PMCSR7_PMCSR710 (0x00000400uL) +#define GPIO_PMCSR7_PMCSR711 (0x00000800uL) +#define GPIO_PMCSR7_PMCSR712 (0x00001000uL) +#define GPIO_PMCSR7_PMCSR713 (0x00002000uL) +#define GPIO_PMCSR7_PMCSR714 (0x00004000uL) +#define GPIO_PMCSR7_PMCSR715 (0x00008000uL) +#define GPIO_PMCSR7_PMCSR716 (0x00010000uL) +#define GPIO_PMCSR7_PMCSR717 (0x00020000uL) +#define GPIO_PMCSR7_PMCSR718 (0x00040000uL) +#define GPIO_PMCSR7_PMCSR719 (0x00080000uL) +#define GPIO_PMCSR7_PMCSR720 (0x00100000uL) +#define GPIO_PMCSR7_PMCSR721 (0x00200000uL) +#define GPIO_PMCSR7_PMCSR722 (0x00400000uL) +#define GPIO_PMCSR7_PMCSR723 (0x00800000uL) +#define GPIO_PMCSR7_PMCSR724 (0x01000000uL) +#define GPIO_PMCSR7_PMCSR725 (0x02000000uL) +#define GPIO_PMCSR7_PMCSR726 (0x04000000uL) +#define GPIO_PMCSR7_PMCSR727 (0x08000000uL) +#define GPIO_PMCSR7_PMCSR728 (0x10000000uL) +#define GPIO_PMCSR7_PMCSR729 (0x20000000uL) +#define GPIO_PMCSR7_PMCSR730 (0x40000000uL) +#define GPIO_PMCSR7_PMCSR731 (0x80000000uL) + +#define GPIO_PFCAE7_PFCAE70 (0x0001u) +#define GPIO_PFCAE7_PFCAE71 (0x0002u) +#define GPIO_PFCAE7_PFCAE72 (0x0004u) +#define GPIO_PFCAE7_PFCAE73 (0x0008u) +#define GPIO_PFCAE7_PFCAE74 (0x0010u) +#define GPIO_PFCAE7_PFCAE75 (0x0020u) +#define GPIO_PFCAE7_PFCAE76 (0x0040u) +#define GPIO_PFCAE7_PFCAE77 (0x0080u) +#define GPIO_PFCAE7_PFCAE78 (0x0100u) +#define GPIO_PFCAE7_PFCAE79 (0x0200u) +#define GPIO_PFCAE7_PFCAE710 (0x0400u) +#define GPIO_PFCAE7_PFCAE711 (0x0800u) +#define GPIO_PFCAE7_PFCAE712 (0x1000u) +#define GPIO_PFCAE7_PFCAE713 (0x2000u) +#define GPIO_PFCAE7_PFCAE714 (0x4000u) +#define GPIO_PFCAE7_PFCAE715 (0x8000u) + +#define GPIO_PIBC7_PIBC70 (0x0001u) +#define GPIO_PIBC7_PIBC71 (0x0002u) +#define GPIO_PIBC7_PIBC72 (0x0004u) +#define GPIO_PIBC7_PIBC73 (0x0008u) +#define GPIO_PIBC7_PIBC74 (0x0010u) +#define GPIO_PIBC7_PIBC75 (0x0020u) +#define GPIO_PIBC7_PIBC76 (0x0040u) +#define GPIO_PIBC7_PIBC77 (0x0080u) +#define GPIO_PIBC7_PIBC78 (0x0100u) +#define GPIO_PIBC7_PIBC79 (0x0200u) +#define GPIO_PIBC7_PIBC710 (0x0400u) +#define GPIO_PIBC7_PIBC711 (0x0800u) +#define GPIO_PIBC7_PIBC712 (0x1000u) +#define GPIO_PIBC7_PIBC713 (0x2000u) +#define GPIO_PIBC7_PIBC714 (0x4000u) +#define GPIO_PIBC7_PIBC715 (0x8000u) + +#define GPIO_PBDC7_PBDC70 (0x0001u) +#define GPIO_PBDC7_PBDC71 (0x0002u) +#define GPIO_PBDC7_PBDC72 (0x0004u) +#define GPIO_PBDC7_PBDC73 (0x0008u) +#define GPIO_PBDC7_PBDC74 (0x0010u) +#define GPIO_PBDC7_PBDC75 (0x0020u) +#define GPIO_PBDC7_PBDC76 (0x0040u) +#define GPIO_PBDC7_PBDC77 (0x0080u) +#define GPIO_PBDC7_PBDC78 (0x0100u) +#define GPIO_PBDC7_PBDC79 (0x0200u) +#define GPIO_PBDC7_PBDC710 (0x0400u) +#define GPIO_PBDC7_PBDC711 (0x0800u) +#define GPIO_PBDC7_PBDC712 (0x1000u) +#define GPIO_PBDC7_PBDC713 (0x2000u) +#define GPIO_PBDC7_PBDC714 (0x4000u) +#define GPIO_PBDC7_PBDC715 (0x8000u) + +#define GPIO_PIPC7_PIPC70 (0x0001u) +#define GPIO_PIPC7_PIPC71 (0x0002u) +#define GPIO_PIPC7_PIPC72 (0x0004u) +#define GPIO_PIPC7_PIPC73 (0x0008u) +#define GPIO_PIPC7_PIPC74 (0x0010u) +#define GPIO_PIPC7_PIPC75 (0x0020u) +#define GPIO_PIPC7_PIPC76 (0x0040u) +#define GPIO_PIPC7_PIPC77 (0x0080u) +#define GPIO_PIPC7_PIPC78 (0x0100u) +#define GPIO_PIPC7_PIPC79 (0x0200u) +#define GPIO_PIPC7_PIPC710 (0x0400u) +#define GPIO_PIPC7_PIPC711 (0x0800u) +#define GPIO_PIPC7_PIPC712 (0x1000u) +#define GPIO_PIPC7_PIPC713 (0x2000u) +#define GPIO_PIPC7_PIPC714 (0x4000u) +#define GPIO_PIPC7_PIPC715 (0x8000u) + +/* ---- P8 ---- */ +#define GPIO_P8_P80 (0x0001u) +#define GPIO_P8_P81 (0x0002u) +#define GPIO_P8_P82 (0x0004u) +#define GPIO_P8_P83 (0x0008u) +#define GPIO_P8_P84 (0x0010u) +#define GPIO_P8_P85 (0x0020u) +#define GPIO_P8_P86 (0x0040u) +#define GPIO_P8_P87 (0x0080u) +#define GPIO_P8_P88 (0x0100u) +#define GPIO_P8_P89 (0x0200u) +#define GPIO_P8_P810 (0x0400u) +#define GPIO_P8_P811 (0x0800u) +#define GPIO_P8_P812 (0x1000u) +#define GPIO_P8_P813 (0x2000u) +#define GPIO_P8_P814 (0x4000u) +#define GPIO_P8_P815 (0x8000u) + +#define GPIO_PSR8_PSR80 (0x00000001uL) +#define GPIO_PSR8_PSR81 (0x00000002uL) +#define GPIO_PSR8_PSR82 (0x00000004uL) +#define GPIO_PSR8_PSR83 (0x00000008uL) +#define GPIO_PSR8_PSR84 (0x00000010uL) +#define GPIO_PSR8_PSR85 (0x00000020uL) +#define GPIO_PSR8_PSR86 (0x00000040uL) +#define GPIO_PSR8_PSR87 (0x00000080uL) +#define GPIO_PSR8_PSR88 (0x00000100uL) +#define GPIO_PSR8_PSR89 (0x00000200uL) +#define GPIO_PSR8_PSR810 (0x00000400uL) +#define GPIO_PSR8_PSR811 (0x00000800uL) +#define GPIO_PSR8_PSR812 (0x00001000uL) +#define GPIO_PSR8_PSR813 (0x00002000uL) +#define GPIO_PSR8_PSR814 (0x00004000uL) +#define GPIO_PSR8_PSR815 (0x00008000uL) +#define GPIO_PSR8_PSR816 (0x00010000uL) +#define GPIO_PSR8_PSR817 (0x00020000uL) +#define GPIO_PSR8_PSR818 (0x00040000uL) +#define GPIO_PSR8_PSR819 (0x00080000uL) +#define GPIO_PSR8_PSR820 (0x00100000uL) +#define GPIO_PSR8_PSR821 (0x00200000uL) +#define GPIO_PSR8_PSR822 (0x00400000uL) +#define GPIO_PSR8_PSR823 (0x00800000uL) +#define GPIO_PSR8_PSR824 (0x01000000uL) +#define GPIO_PSR8_PSR825 (0x02000000uL) +#define GPIO_PSR8_PSR826 (0x04000000uL) +#define GPIO_PSR8_PSR827 (0x08000000uL) +#define GPIO_PSR8_PSR828 (0x10000000uL) +#define GPIO_PSR8_PSR829 (0x20000000uL) +#define GPIO_PSR8_PSR830 (0x40000000uL) +#define GPIO_PSR8_PSR831 (0x80000000uL) + +#define GPIO_PPR8_PPR80 (0x0001u) +#define GPIO_PPR8_PPR81 (0x0002u) +#define GPIO_PPR8_PPR82 (0x0004u) +#define GPIO_PPR8_PPR83 (0x0008u) +#define GPIO_PPR8_PPR84 (0x0010u) +#define GPIO_PPR8_PPR85 (0x0020u) +#define GPIO_PPR8_PPR86 (0x0040u) +#define GPIO_PPR8_PPR87 (0x0080u) +#define GPIO_PPR8_PPR88 (0x0100u) +#define GPIO_PPR8_PPR89 (0x0200u) +#define GPIO_PPR8_PPR810 (0x0400u) +#define GPIO_PPR8_PPR811 (0x0800u) +#define GPIO_PPR8_PPR812 (0x1000u) +#define GPIO_PPR8_PPR813 (0x2000u) +#define GPIO_PPR8_PPR814 (0x4000u) +#define GPIO_PPR8_PPR815 (0x8000u) + +#define GPIO_PM8_PM80 (0x0001u) +#define GPIO_PM8_PM81 (0x0002u) +#define GPIO_PM8_PM82 (0x0004u) +#define GPIO_PM8_PM83 (0x0008u) +#define GPIO_PM8_PM84 (0x0010u) +#define GPIO_PM8_PM85 (0x0020u) +#define GPIO_PM8_PM86 (0x0040u) +#define GPIO_PM8_PM87 (0x0080u) +#define GPIO_PM8_PM88 (0x0100u) +#define GPIO_PM8_PM89 (0x0200u) +#define GPIO_PM8_PM810 (0x0400u) +#define GPIO_PM8_PM811 (0x0800u) +#define GPIO_PM8_PM812 (0x1000u) +#define GPIO_PM8_PM813 (0x2000u) +#define GPIO_PM8_PM814 (0x4000u) +#define GPIO_PM8_PM815 (0x8000u) + +#define GPIO_PMC8_PMC80 (0x0001u) +#define GPIO_PMC8_PMC81 (0x0002u) +#define GPIO_PMC8_PMC82 (0x0004u) +#define GPIO_PMC8_PMC83 (0x0008u) +#define GPIO_PMC8_PMC84 (0x0010u) +#define GPIO_PMC8_PMC85 (0x0020u) +#define GPIO_PMC8_PMC86 (0x0040u) +#define GPIO_PMC8_PMC87 (0x0080u) +#define GPIO_PMC8_PMC88 (0x0100u) +#define GPIO_PMC8_PMC89 (0x0200u) +#define GPIO_PMC8_PMC810 (0x0400u) +#define GPIO_PMC8_PMC811 (0x0800u) +#define GPIO_PMC8_PMC812 (0x1000u) +#define GPIO_PMC8_PMC813 (0x2000u) +#define GPIO_PMC8_PMC814 (0x4000u) +#define GPIO_PMC8_PMC815 (0x8000u) + +#define GPIO_PFC8_PFC80 (0x0001u) +#define GPIO_PFC8_PFC81 (0x0002u) +#define GPIO_PFC8_PFC82 (0x0004u) +#define GPIO_PFC8_PFC83 (0x0008u) +#define GPIO_PFC8_PFC84 (0x0010u) +#define GPIO_PFC8_PFC85 (0x0020u) +#define GPIO_PFC8_PFC86 (0x0040u) +#define GPIO_PFC8_PFC87 (0x0080u) +#define GPIO_PFC8_PFC88 (0x0100u) +#define GPIO_PFC8_PFC89 (0x0200u) +#define GPIO_PFC8_PFC810 (0x0400u) +#define GPIO_PFC8_PFC811 (0x0800u) +#define GPIO_PFC8_PFC812 (0x1000u) +#define GPIO_PFC8_PFC813 (0x2000u) +#define GPIO_PFC8_PFC814 (0x4000u) +#define GPIO_PFC8_PFC815 (0x8000u) + +#define GPIO_PFCE8_PFCE80 (0x0001u) +#define GPIO_PFCE8_PFCE81 (0x0002u) +#define GPIO_PFCE8_PFCE82 (0x0004u) +#define GPIO_PFCE8_PFCE83 (0x0008u) +#define GPIO_PFCE8_PFCE84 (0x0010u) +#define GPIO_PFCE8_PFCE85 (0x0020u) +#define GPIO_PFCE8_PFCE86 (0x0040u) +#define GPIO_PFCE8_PFCE87 (0x0080u) +#define GPIO_PFCE8_PFCE88 (0x0100u) +#define GPIO_PFCE8_PFCE89 (0x0200u) +#define GPIO_PFCE8_PFCE810 (0x0400u) +#define GPIO_PFCE8_PFCE811 (0x0800u) +#define GPIO_PFCE8_PFCE812 (0x1000u) +#define GPIO_PFCE8_PFCE813 (0x2000u) +#define GPIO_PFCE8_PFCE814 (0x4000u) +#define GPIO_PFCE8_PFCE815 (0x8000u) + +#define GPIO_PNOT8_PNOT80 (0x0001u) +#define GPIO_PNOT8_PNOT81 (0x0002u) +#define GPIO_PNOT8_PNOT82 (0x0004u) +#define GPIO_PNOT8_PNOT83 (0x0008u) +#define GPIO_PNOT8_PNOT84 (0x0010u) +#define GPIO_PNOT8_PNOT85 (0x0020u) +#define GPIO_PNOT8_PNOT86 (0x0040u) +#define GPIO_PNOT8_PNOT87 (0x0080u) +#define GPIO_PNOT8_PNOT88 (0x0100u) +#define GPIO_PNOT8_PNOT89 (0x0200u) +#define GPIO_PNOT8_PNOT810 (0x0400u) +#define GPIO_PNOT8_PNOT811 (0x0800u) +#define GPIO_PNOT8_PNOT812 (0x1000u) +#define GPIO_PNOT8_PNOT813 (0x2000u) +#define GPIO_PNOT8_PNOT814 (0x4000u) +#define GPIO_PNOT8_PNOT815 (0x8000u) + +#define GPIO_PMSR8_PMSR80 (0x00000001uL) +#define GPIO_PMSR8_PMSR81 (0x00000002uL) +#define GPIO_PMSR8_PMSR82 (0x00000004uL) +#define GPIO_PMSR8_PMSR83 (0x00000008uL) +#define GPIO_PMSR8_PMSR84 (0x00000010uL) +#define GPIO_PMSR8_PMSR85 (0x00000020uL) +#define GPIO_PMSR8_PMSR86 (0x00000040uL) +#define GPIO_PMSR8_PMSR87 (0x00000080uL) +#define GPIO_PMSR8_PMSR88 (0x00000100uL) +#define GPIO_PMSR8_PMSR89 (0x00000200uL) +#define GPIO_PMSR8_PMSR810 (0x00000400uL) +#define GPIO_PMSR8_PMSR811 (0x00000800uL) +#define GPIO_PMSR8_PMSR812 (0x00001000uL) +#define GPIO_PMSR8_PMSR813 (0x00002000uL) +#define GPIO_PMSR8_PMSR814 (0x00004000uL) +#define GPIO_PMSR8_PMSR815 (0x00008000uL) +#define GPIO_PMSR8_PMSR816 (0x00010000uL) +#define GPIO_PMSR8_PMSR817 (0x00020000uL) +#define GPIO_PMSR8_PMSR818 (0x00040000uL) +#define GPIO_PMSR8_PMSR819 (0x00080000uL) +#define GPIO_PMSR8_PMSR820 (0x00100000uL) +#define GPIO_PMSR8_PMSR821 (0x00200000uL) +#define GPIO_PMSR8_PMSR822 (0x00400000uL) +#define GPIO_PMSR8_PMSR823 (0x00800000uL) +#define GPIO_PMSR8_PMSR824 (0x01000000uL) +#define GPIO_PMSR8_PMSR825 (0x02000000uL) +#define GPIO_PMSR8_PMSR826 (0x04000000uL) +#define GPIO_PMSR8_PMSR827 (0x08000000uL) +#define GPIO_PMSR8_PMSR828 (0x10000000uL) +#define GPIO_PMSR8_PMSR829 (0x20000000uL) +#define GPIO_PMSR8_PMSR830 (0x40000000uL) +#define GPIO_PMSR8_PMSR831 (0x80000000uL) + +#define GPIO_PMCSR8_PMCSR80 (0x00000001uL) +#define GPIO_PMCSR8_PMCSR81 (0x00000002uL) +#define GPIO_PMCSR8_PMCSR82 (0x00000004uL) +#define GPIO_PMCSR8_PMCSR83 (0x00000008uL) +#define GPIO_PMCSR8_PMCSR84 (0x00000010uL) +#define GPIO_PMCSR8_PMCSR85 (0x00000020uL) +#define GPIO_PMCSR8_PMCSR86 (0x00000040uL) +#define GPIO_PMCSR8_PMCSR87 (0x00000080uL) +#define GPIO_PMCSR8_PMCSR88 (0x00000100uL) +#define GPIO_PMCSR8_PMCSR89 (0x00000200uL) +#define GPIO_PMCSR8_PMCSR810 (0x00000400uL) +#define GPIO_PMCSR8_PMCSR811 (0x00000800uL) +#define GPIO_PMCSR8_PMCSR812 (0x00001000uL) +#define GPIO_PMCSR8_PMCSR813 (0x00002000uL) +#define GPIO_PMCSR8_PMCSR814 (0x00004000uL) +#define GPIO_PMCSR8_PMCSR815 (0x00008000uL) +#define GPIO_PMCSR8_PMCSR816 (0x00010000uL) +#define GPIO_PMCSR8_PMCSR817 (0x00020000uL) +#define GPIO_PMCSR8_PMCSR818 (0x00040000uL) +#define GPIO_PMCSR8_PMCSR819 (0x00080000uL) +#define GPIO_PMCSR8_PMCSR820 (0x00100000uL) +#define GPIO_PMCSR8_PMCSR821 (0x00200000uL) +#define GPIO_PMCSR8_PMCSR822 (0x00400000uL) +#define GPIO_PMCSR8_PMCSR823 (0x00800000uL) +#define GPIO_PMCSR8_PMCSR824 (0x01000000uL) +#define GPIO_PMCSR8_PMCSR825 (0x02000000uL) +#define GPIO_PMCSR8_PMCSR826 (0x04000000uL) +#define GPIO_PMCSR8_PMCSR827 (0x08000000uL) +#define GPIO_PMCSR8_PMCSR828 (0x10000000uL) +#define GPIO_PMCSR8_PMCSR829 (0x20000000uL) +#define GPIO_PMCSR8_PMCSR830 (0x40000000uL) +#define GPIO_PMCSR8_PMCSR831 (0x80000000uL) + +#define GPIO_PFCAE8_PFCAE80 (0x0001u) +#define GPIO_PFCAE8_PFCAE81 (0x0002u) +#define GPIO_PFCAE8_PFCAE82 (0x0004u) +#define GPIO_PFCAE8_PFCAE83 (0x0008u) +#define GPIO_PFCAE8_PFCAE84 (0x0010u) +#define GPIO_PFCAE8_PFCAE85 (0x0020u) +#define GPIO_PFCAE8_PFCAE86 (0x0040u) +#define GPIO_PFCAE8_PFCAE87 (0x0080u) +#define GPIO_PFCAE8_PFCAE88 (0x0100u) +#define GPIO_PFCAE8_PFCAE89 (0x0200u) +#define GPIO_PFCAE8_PFCAE810 (0x0400u) +#define GPIO_PFCAE8_PFCAE811 (0x0800u) +#define GPIO_PFCAE8_PFCAE812 (0x1000u) +#define GPIO_PFCAE8_PFCAE813 (0x2000u) +#define GPIO_PFCAE8_PFCAE814 (0x4000u) +#define GPIO_PFCAE8_PFCAE815 (0x8000u) + +#define GPIO_PIBC8_PIBC80 (0x0001u) +#define GPIO_PIBC8_PIBC81 (0x0002u) +#define GPIO_PIBC8_PIBC82 (0x0004u) +#define GPIO_PIBC8_PIBC83 (0x0008u) +#define GPIO_PIBC8_PIBC84 (0x0010u) +#define GPIO_PIBC8_PIBC85 (0x0020u) +#define GPIO_PIBC8_PIBC86 (0x0040u) +#define GPIO_PIBC8_PIBC87 (0x0080u) +#define GPIO_PIBC8_PIBC88 (0x0100u) +#define GPIO_PIBC8_PIBC89 (0x0200u) +#define GPIO_PIBC8_PIBC810 (0x0400u) +#define GPIO_PIBC8_PIBC811 (0x0800u) +#define GPIO_PIBC8_PIBC812 (0x1000u) +#define GPIO_PIBC8_PIBC813 (0x2000u) +#define GPIO_PIBC8_PIBC814 (0x4000u) +#define GPIO_PIBC8_PIBC815 (0x8000u) + +#define GPIO_PBDC8_PBDC80 (0x0001u) +#define GPIO_PBDC8_PBDC81 (0x0002u) +#define GPIO_PBDC8_PBDC82 (0x0004u) +#define GPIO_PBDC8_PBDC83 (0x0008u) +#define GPIO_PBDC8_PBDC84 (0x0010u) +#define GPIO_PBDC8_PBDC85 (0x0020u) +#define GPIO_PBDC8_PBDC86 (0x0040u) +#define GPIO_PBDC8_PBDC87 (0x0080u) +#define GPIO_PBDC8_PBDC88 (0x0100u) +#define GPIO_PBDC8_PBDC89 (0x0200u) +#define GPIO_PBDC8_PBDC810 (0x0400u) +#define GPIO_PBDC8_PBDC811 (0x0800u) +#define GPIO_PBDC8_PBDC812 (0x1000u) +#define GPIO_PBDC8_PBDC813 (0x2000u) +#define GPIO_PBDC8_PBDC814 (0x4000u) +#define GPIO_PBDC8_PBDC815 (0x8000u) + +#define GPIO_PIPC8_PIPC80 (0x0001u) +#define GPIO_PIPC8_PIPC81 (0x0002u) +#define GPIO_PIPC8_PIPC82 (0x0004u) +#define GPIO_PIPC8_PIPC83 (0x0008u) +#define GPIO_PIPC8_PIPC84 (0x0010u) +#define GPIO_PIPC8_PIPC85 (0x0020u) +#define GPIO_PIPC8_PIPC86 (0x0040u) +#define GPIO_PIPC8_PIPC87 (0x0080u) +#define GPIO_PIPC8_PIPC88 (0x0100u) +#define GPIO_PIPC8_PIPC89 (0x0200u) +#define GPIO_PIPC8_PIPC810 (0x0400u) +#define GPIO_PIPC8_PIPC811 (0x0800u) +#define GPIO_PIPC8_PIPC812 (0x1000u) +#define GPIO_PIPC8_PIPC813 (0x2000u) +#define GPIO_PIPC8_PIPC814 (0x4000u) +#define GPIO_PIPC8_PIPC815 (0x8000u) + +/* ---- P9 ---- */ +#define GPIO_P9_P90 (0x0001u) +#define GPIO_P9_P91 (0x0002u) +#define GPIO_P9_P92 (0x0004u) +#define GPIO_P9_P93 (0x0008u) +#define GPIO_P9_P94 (0x0010u) +#define GPIO_P9_P95 (0x0020u) +#define GPIO_P9_P96 (0x0040u) +#define GPIO_P9_P97 (0x0080u) + +#define GPIO_PSR9_PSR90 (0x00000001uL) +#define GPIO_PSR9_PSR91 (0x00000002uL) +#define GPIO_PSR9_PSR92 (0x00000004uL) +#define GPIO_PSR9_PSR93 (0x00000008uL) +#define GPIO_PSR9_PSR94 (0x00000010uL) +#define GPIO_PSR9_PSR95 (0x00000020uL) +#define GPIO_PSR9_PSR96 (0x00000040uL) +#define GPIO_PSR9_PSR97 (0x00000080uL) +#define GPIO_PSR9_PSR916 (0x00010000uL) +#define GPIO_PSR9_PSR917 (0x00020000uL) +#define GPIO_PSR9_PSR918 (0x00040000uL) +#define GPIO_PSR9_PSR919 (0x00080000uL) +#define GPIO_PSR9_PSR920 (0x00100000uL) +#define GPIO_PSR9_PSR921 (0x00200000uL) +#define GPIO_PSR9_PSR922 (0x00400000uL) +#define GPIO_PSR9_PSR923 (0x00800000uL) + +#define GPIO_PPR9_PPR90 (0x0001u) +#define GPIO_PPR9_PPR91 (0x0002u) +#define GPIO_PPR9_PPR92 (0x0004u) +#define GPIO_PPR9_PPR93 (0x0008u) +#define GPIO_PPR9_PPR94 (0x0010u) +#define GPIO_PPR9_PPR95 (0x0020u) +#define GPIO_PPR9_PPR96 (0x0040u) +#define GPIO_PPR9_PPR97 (0x0080u) + +#define GPIO_PM9_PM90 (0x0001u) +#define GPIO_PM9_PM91 (0x0002u) +#define GPIO_PM9_PM92 (0x0004u) +#define GPIO_PM9_PM93 (0x0008u) +#define GPIO_PM9_PM94 (0x0010u) +#define GPIO_PM9_PM95 (0x0020u) +#define GPIO_PM9_PM96 (0x0040u) +#define GPIO_PM9_PM97 (0x0080u) + +#define GPIO_PMC9_PMC90 (0x0001u) +#define GPIO_PMC9_PMC91 (0x0002u) +#define GPIO_PMC9_PMC92 (0x0004u) +#define GPIO_PMC9_PMC93 (0x0008u) +#define GPIO_PMC9_PMC94 (0x0010u) +#define GPIO_PMC9_PMC95 (0x0020u) +#define GPIO_PMC9_PMC96 (0x0040u) +#define GPIO_PMC9_PMC97 (0x0080u) + +#define GPIO_PFC9_PFC90 (0x0001u) +#define GPIO_PFC9_PFC91 (0x0002u) +#define GPIO_PFC9_PFC92 (0x0004u) +#define GPIO_PFC9_PFC93 (0x0008u) +#define GPIO_PFC9_PFC94 (0x0010u) +#define GPIO_PFC9_PFC95 (0x0020u) +#define GPIO_PFC9_PFC96 (0x0040u) +#define GPIO_PFC9_PFC97 (0x0080u) + +#define GPIO_PFCE9_PFCE90 (0x0001u) +#define GPIO_PFCE9_PFCE91 (0x0002u) +#define GPIO_PFCE9_PFCE92 (0x0004u) +#define GPIO_PFCE9_PFCE93 (0x0008u) +#define GPIO_PFCE9_PFCE94 (0x0010u) +#define GPIO_PFCE9_PFCE95 (0x0020u) +#define GPIO_PFCE9_PFCE96 (0x0040u) +#define GPIO_PFCE9_PFCE97 (0x0080u) + +#define GPIO_PNOT9_PNOT90 (0x0001u) +#define GPIO_PNOT9_PNOT91 (0x0002u) +#define GPIO_PNOT9_PNOT92 (0x0004u) +#define GPIO_PNOT9_PNOT93 (0x0008u) +#define GPIO_PNOT9_PNOT94 (0x0010u) +#define GPIO_PNOT9_PNOT95 (0x0020u) +#define GPIO_PNOT9_PNOT96 (0x0040u) +#define GPIO_PNOT9_PNOT97 (0x0080u) + +#define GPIO_PMSR9_PMSR90 (0x00000001uL) +#define GPIO_PMSR9_PMSR91 (0x00000002uL) +#define GPIO_PMSR9_PMSR92 (0x00000004uL) +#define GPIO_PMSR9_PMSR93 (0x00000008uL) +#define GPIO_PMSR9_PMSR94 (0x00000010uL) +#define GPIO_PMSR9_PMSR95 (0x00000020uL) +#define GPIO_PMSR9_PMSR96 (0x00000040uL) +#define GPIO_PMSR9_PMSR97 (0x00000080uL) +#define GPIO_PMSR9_PMSR916 (0x00010000uL) +#define GPIO_PMSR9_PMSR917 (0x00020000uL) +#define GPIO_PMSR9_PMSR918 (0x00040000uL) +#define GPIO_PMSR9_PMSR919 (0x00080000uL) +#define GPIO_PMSR9_PMSR920 (0x00100000uL) +#define GPIO_PMSR9_PMSR921 (0x00200000uL) +#define GPIO_PMSR9_PMSR922 (0x00400000uL) +#define GPIO_PMSR9_PMSR923 (0x00800000uL) + +#define GPIO_PMCSR9_PMCSR90 (0x00000001uL) +#define GPIO_PMCSR9_PMCSR91 (0x00000002uL) +#define GPIO_PMCSR9_PMCSR92 (0x00000004uL) +#define GPIO_PMCSR9_PMCSR93 (0x00000008uL) +#define GPIO_PMCSR9_PMCSR94 (0x00000010uL) +#define GPIO_PMCSR9_PMCSR95 (0x00000020uL) +#define GPIO_PMCSR9_PMCSR96 (0x00000040uL) +#define GPIO_PMCSR9_PMCSR97 (0x00000080uL) +#define GPIO_PMCSR9_PMCSR916 (0x00010000uL) +#define GPIO_PMCSR9_PMCSR917 (0x00020000uL) +#define GPIO_PMCSR9_PMCSR918 (0x00040000uL) +#define GPIO_PMCSR9_PMCSR919 (0x00080000uL) +#define GPIO_PMCSR9_PMCSR920 (0x00100000uL) +#define GPIO_PMCSR9_PMCSR921 (0x00200000uL) +#define GPIO_PMCSR9_PMCSR922 (0x00400000uL) +#define GPIO_PMCSR9_PMCSR923 (0x00800000uL) + +#define GPIO_PFCAE9_PFCAE90 (0x0001u) +#define GPIO_PFCAE9_PFCAE91 (0x0002u) +#define GPIO_PFCAE9_PFCAE92 (0x0004u) +#define GPIO_PFCAE9_PFCAE93 (0x0008u) +#define GPIO_PFCAE9_PFCAE94 (0x0010u) +#define GPIO_PFCAE9_PFCAE95 (0x0020u) +#define GPIO_PFCAE9_PFCAE96 (0x0040u) +#define GPIO_PFCAE9_PFCAE97 (0x0080u) + +#define GPIO_PIBC9_PIBC90 (0x0001u) +#define GPIO_PIBC9_PIBC91 (0x0002u) +#define GPIO_PIBC9_PIBC92 (0x0004u) +#define GPIO_PIBC9_PIBC93 (0x0008u) +#define GPIO_PIBC9_PIBC94 (0x0010u) +#define GPIO_PIBC9_PIBC95 (0x0020u) +#define GPIO_PIBC9_PIBC96 (0x0040u) +#define GPIO_PIBC9_PIBC97 (0x0080u) + +#define GPIO_PBDC9_PBDC90 (0x0001u) +#define GPIO_PBDC9_PBDC91 (0x0002u) +#define GPIO_PBDC9_PBDC92 (0x0004u) +#define GPIO_PBDC9_PBDC93 (0x0008u) +#define GPIO_PBDC9_PBDC94 (0x0010u) +#define GPIO_PBDC9_PBDC95 (0x0020u) +#define GPIO_PBDC9_PBDC96 (0x0040u) +#define GPIO_PBDC9_PBDC97 (0x0080u) + +#define GPIO_PIPC9_PIPC90 (0x0001u) +#define GPIO_PIPC9_PIPC91 (0x0002u) +#define GPIO_PIPC9_PIPC92 (0x0004u) +#define GPIO_PIPC9_PIPC93 (0x0008u) +#define GPIO_PIPC9_PIPC94 (0x0010u) +#define GPIO_PIPC9_PIPC95 (0x0020u) +#define GPIO_PIPC9_PIPC96 (0x0040u) +#define GPIO_PIPC9_PIPC97 (0x0080u) + +/* ---- P10 ---- */ +#define GPIO_P10_P100 (0x0001u) +#define GPIO_P10_P101 (0x0002u) +#define GPIO_P10_P102 (0x0004u) +#define GPIO_P10_P103 (0x0008u) +#define GPIO_P10_P104 (0x0010u) +#define GPIO_P10_P105 (0x0020u) +#define GPIO_P10_P106 (0x0040u) +#define GPIO_P10_P107 (0x0080u) +#define GPIO_P10_P108 (0x0100u) +#define GPIO_P10_P109 (0x0200u) +#define GPIO_P10_P1010 (0x0400u) +#define GPIO_P10_P1011 (0x0800u) +#define GPIO_P10_P1012 (0x1000u) +#define GPIO_P10_P1013 (0x2000u) +#define GPIO_P10_P1014 (0x4000u) +#define GPIO_P10_P1015 (0x8000u) + +#define GPIO_PSR10_PSR100 (0x00000001uL) +#define GPIO_PSR10_PSR101 (0x00000002uL) +#define GPIO_PSR10_PSR102 (0x00000004uL) +#define GPIO_PSR10_PSR103 (0x00000008uL) +#define GPIO_PSR10_PSR104 (0x00000010uL) +#define GPIO_PSR10_PSR105 (0x00000020uL) +#define GPIO_PSR10_PSR106 (0x00000040uL) +#define GPIO_PSR10_PSR107 (0x00000080uL) +#define GPIO_PSR10_PSR108 (0x00000100uL) +#define GPIO_PSR10_PSR109 (0x00000200uL) +#define GPIO_PSR10_PSR1010 (0x00000400uL) +#define GPIO_PSR10_PSR1011 (0x00000800uL) +#define GPIO_PSR10_PSR1012 (0x00001000uL) +#define GPIO_PSR10_PSR1013 (0x00002000uL) +#define GPIO_PSR10_PSR1014 (0x00004000uL) +#define GPIO_PSR10_PSR1015 (0x00008000uL) +#define GPIO_PSR10_PSR1016 (0x00010000uL) +#define GPIO_PSR10_PSR1017 (0x00020000uL) +#define GPIO_PSR10_PSR1018 (0x00040000uL) +#define GPIO_PSR10_PSR1019 (0x00080000uL) +#define GPIO_PSR10_PSR1020 (0x00100000uL) +#define GPIO_PSR10_PSR1021 (0x00200000uL) +#define GPIO_PSR10_PSR1022 (0x00400000uL) +#define GPIO_PSR10_PSR1023 (0x00800000uL) +#define GPIO_PSR10_PSR1024 (0x01000000uL) +#define GPIO_PSR10_PSR1025 (0x02000000uL) +#define GPIO_PSR10_PSR1026 (0x04000000uL) +#define GPIO_PSR10_PSR1027 (0x08000000uL) +#define GPIO_PSR10_PSR1028 (0x10000000uL) +#define GPIO_PSR10_PSR1029 (0x20000000uL) +#define GPIO_PSR10_PSR1030 (0x40000000uL) +#define GPIO_PSR10_PSR1031 (0x80000000uL) + +#define GPIO_PPR10_PPR100 (0x0001u) +#define GPIO_PPR10_PPR101 (0x0002u) +#define GPIO_PPR10_PPR102 (0x0004u) +#define GPIO_PPR10_PPR103 (0x0008u) +#define GPIO_PPR10_PPR104 (0x0010u) +#define GPIO_PPR10_PPR105 (0x0020u) +#define GPIO_PPR10_PPR106 (0x0040u) +#define GPIO_PPR10_PPR107 (0x0080u) +#define GPIO_PPR10_PPR108 (0x0100u) +#define GPIO_PPR10_PPR109 (0x0200u) +#define GPIO_PPR10_PPR1010 (0x0400u) +#define GPIO_PPR10_PPR1011 (0x0800u) +#define GPIO_PPR10_PPR1012 (0x1000u) +#define GPIO_PPR10_PPR1013 (0x2000u) +#define GPIO_PPR10_PPR1014 (0x4000u) +#define GPIO_PPR10_PPR1015 (0x8000u) + +#define GPIO_PM10_PM100 (0x0001u) +#define GPIO_PM10_PM101 (0x0002u) +#define GPIO_PM10_PM102 (0x0004u) +#define GPIO_PM10_PM103 (0x0008u) +#define GPIO_PM10_PM104 (0x0010u) +#define GPIO_PM10_PM105 (0x0020u) +#define GPIO_PM10_PM106 (0x0040u) +#define GPIO_PM10_PM107 (0x0080u) +#define GPIO_PM10_PM108 (0x0100u) +#define GPIO_PM10_PM109 (0x0200u) +#define GPIO_PM10_PM1010 (0x0400u) +#define GPIO_PM10_PM1011 (0x0800u) +#define GPIO_PM10_PM1012 (0x1000u) +#define GPIO_PM10_PM1013 (0x2000u) +#define GPIO_PM10_PM1014 (0x4000u) +#define GPIO_PM10_PM1015 (0x8000u) + +#define GPIO_PMC10_PMC100 (0x0001u) +#define GPIO_PMC10_PMC101 (0x0002u) +#define GPIO_PMC10_PMC102 (0x0004u) +#define GPIO_PMC10_PMC103 (0x0008u) +#define GPIO_PMC10_PMC104 (0x0010u) +#define GPIO_PMC10_PMC105 (0x0020u) +#define GPIO_PMC10_PMC106 (0x0040u) +#define GPIO_PMC10_PMC107 (0x0080u) +#define GPIO_PMC10_PMC108 (0x0100u) +#define GPIO_PMC10_PMC109 (0x0200u) +#define GPIO_PMC10_PMC1010 (0x0400u) +#define GPIO_PMC10_PMC1011 (0x0800u) +#define GPIO_PMC10_PMC1012 (0x1000u) +#define GPIO_PMC10_PMC1013 (0x2000u) +#define GPIO_PMC10_PMC1014 (0x4000u) +#define GPIO_PMC10_PMC1015 (0x8000u) + +#define GPIO_PFC10_PFC100 (0x0001u) +#define GPIO_PFC10_PFC101 (0x0002u) +#define GPIO_PFC10_PFC102 (0x0004u) +#define GPIO_PFC10_PFC103 (0x0008u) +#define GPIO_PFC10_PFC104 (0x0010u) +#define GPIO_PFC10_PFC105 (0x0020u) +#define GPIO_PFC10_PFC106 (0x0040u) +#define GPIO_PFC10_PFC107 (0x0080u) +#define GPIO_PFC10_PFC108 (0x0100u) +#define GPIO_PFC10_PFC109 (0x0200u) +#define GPIO_PFC10_PFC1010 (0x0400u) +#define GPIO_PFC10_PFC1011 (0x0800u) +#define GPIO_PFC10_PFC1012 (0x1000u) +#define GPIO_PFC10_PFC1013 (0x2000u) +#define GPIO_PFC10_PFC1014 (0x4000u) +#define GPIO_PFC10_PFC1015 (0x8000u) + +#define GPIO_PFCE10_PFCE100 (0x0001u) +#define GPIO_PFCE10_PFCE101 (0x0002u) +#define GPIO_PFCE10_PFCE102 (0x0004u) +#define GPIO_PFCE10_PFCE103 (0x0008u) +#define GPIO_PFCE10_PFCE104 (0x0010u) +#define GPIO_PFCE10_PFCE105 (0x0020u) +#define GPIO_PFCE10_PFCE106 (0x0040u) +#define GPIO_PFCE10_PFCE107 (0x0080u) +#define GPIO_PFCE10_PFCE108 (0x0100u) +#define GPIO_PFCE10_PFCE109 (0x0200u) +#define GPIO_PFCE10_PFCE1010 (0x0400u) +#define GPIO_PFCE10_PFCE1011 (0x0800u) +#define GPIO_PFCE10_PFCE1012 (0x1000u) +#define GPIO_PFCE10_PFCE1013 (0x2000u) +#define GPIO_PFCE10_PFCE1014 (0x4000u) +#define GPIO_PFCE10_PFCE1015 (0x8000u) + +#define GPIO_PNOT10_PNOT100 (0x0001u) +#define GPIO_PNOT10_PNOT101 (0x0002u) +#define GPIO_PNOT10_PNOT102 (0x0004u) +#define GPIO_PNOT10_PNOT103 (0x0008u) +#define GPIO_PNOT10_PNOT104 (0x0010u) +#define GPIO_PNOT10_PNOT105 (0x0020u) +#define GPIO_PNOT10_PNOT106 (0x0040u) +#define GPIO_PNOT10_PNOT107 (0x0080u) +#define GPIO_PNOT10_PNOT108 (0x0100u) +#define GPIO_PNOT10_PNOT109 (0x0200u) +#define GPIO_PNOT10_PNOT1010 (0x0400u) +#define GPIO_PNOT10_PNOT1011 (0x0800u) +#define GPIO_PNOT10_PNOT1012 (0x1000u) +#define GPIO_PNOT10_PNOT1013 (0x2000u) +#define GPIO_PNOT10_PNOT1014 (0x4000u) +#define GPIO_PNOT10_PNOT1015 (0x8000u) + +#define GPIO_PMSR10_PMSR100 (0x00000001uL) +#define GPIO_PMSR10_PMSR101 (0x00000002uL) +#define GPIO_PMSR10_PMSR102 (0x00000004uL) +#define GPIO_PMSR10_PMSR103 (0x00000008uL) +#define GPIO_PMSR10_PMSR104 (0x00000010uL) +#define GPIO_PMSR10_PMSR105 (0x00000020uL) +#define GPIO_PMSR10_PMSR106 (0x00000040uL) +#define GPIO_PMSR10_PMSR107 (0x00000080uL) +#define GPIO_PMSR10_PMSR108 (0x00000100uL) +#define GPIO_PMSR10_PMSR109 (0x00000200uL) +#define GPIO_PMSR10_PMSR1010 (0x00000400uL) +#define GPIO_PMSR10_PMSR1011 (0x00000800uL) +#define GPIO_PMSR10_PMSR1012 (0x00001000uL) +#define GPIO_PMSR10_PMSR1013 (0x00002000uL) +#define GPIO_PMSR10_PMSR1014 (0x00004000uL) +#define GPIO_PMSR10_PMSR1015 (0x00008000uL) +#define GPIO_PMSR10_PMSR1016 (0x00010000uL) +#define GPIO_PMSR10_PMSR1017 (0x00020000uL) +#define GPIO_PMSR10_PMSR1018 (0x00040000uL) +#define GPIO_PMSR10_PMSR1019 (0x00080000uL) +#define GPIO_PMSR10_PMSR1020 (0x00100000uL) +#define GPIO_PMSR10_PMSR1021 (0x00200000uL) +#define GPIO_PMSR10_PMSR1022 (0x00400000uL) +#define GPIO_PMSR10_PMSR1023 (0x00800000uL) +#define GPIO_PMSR10_PMSR1024 (0x01000000uL) +#define GPIO_PMSR10_PMSR1025 (0x02000000uL) +#define GPIO_PMSR10_PMSR1026 (0x04000000uL) +#define GPIO_PMSR10_PMSR1027 (0x08000000uL) +#define GPIO_PMSR10_PMSR1028 (0x10000000uL) +#define GPIO_PMSR10_PMSR1029 (0x20000000uL) +#define GPIO_PMSR10_PMSR1030 (0x40000000uL) +#define GPIO_PMSR10_PMSR1031 (0x80000000uL) + +#define GPIO_PMCSR10_PMCSR100 (0x00000001uL) +#define GPIO_PMCSR10_PMCSR101 (0x00000002uL) +#define GPIO_PMCSR10_PMCSR102 (0x00000004uL) +#define GPIO_PMCSR10_PMCSR103 (0x00000008uL) +#define GPIO_PMCSR10_PMCSR104 (0x00000010uL) +#define GPIO_PMCSR10_PMCSR105 (0x00000020uL) +#define GPIO_PMCSR10_PMCSR106 (0x00000040uL) +#define GPIO_PMCSR10_PMCSR107 (0x00000080uL) +#define GPIO_PMCSR10_PMCSR108 (0x00000100uL) +#define GPIO_PMCSR10_PMCSR109 (0x00000200uL) +#define GPIO_PMCSR10_PMCSR1010 (0x00000400uL) +#define GPIO_PMCSR10_PMCSR1011 (0x00000800uL) +#define GPIO_PMCSR10_PMCSR1012 (0x00001000uL) +#define GPIO_PMCSR10_PMCSR1013 (0x00002000uL) +#define GPIO_PMCSR10_PMCSR1014 (0x00004000uL) +#define GPIO_PMCSR10_PMCSR1015 (0x00008000uL) +#define GPIO_PMCSR10_PMCSR1016 (0x00010000uL) +#define GPIO_PMCSR10_PMCSR1017 (0x00020000uL) +#define GPIO_PMCSR10_PMCSR1018 (0x00040000uL) +#define GPIO_PMCSR10_PMCSR1019 (0x00080000uL) +#define GPIO_PMCSR10_PMCSR1020 (0x00100000uL) +#define GPIO_PMCSR10_PMCSR1021 (0x00200000uL) +#define GPIO_PMCSR10_PMCSR1022 (0x00400000uL) +#define GPIO_PMCSR10_PMCSR1023 (0x00800000uL) +#define GPIO_PMCSR10_PMCSR1024 (0x01000000uL) +#define GPIO_PMCSR10_PMCSR1025 (0x02000000uL) +#define GPIO_PMCSR10_PMCSR1026 (0x04000000uL) +#define GPIO_PMCSR10_PMCSR1027 (0x08000000uL) +#define GPIO_PMCSR10_PMCSR1028 (0x10000000uL) +#define GPIO_PMCSR10_PMCSR1029 (0x20000000uL) +#define GPIO_PMCSR10_PMCSR1030 (0x40000000uL) +#define GPIO_PMCSR10_PMCSR1031 (0x80000000uL) + +#define GPIO_PFCAE10_PFCAE100 (0x0001u) +#define GPIO_PFCAE10_PFCAE101 (0x0002u) +#define GPIO_PFCAE10_PFCAE102 (0x0004u) +#define GPIO_PFCAE10_PFCAE103 (0x0008u) +#define GPIO_PFCAE10_PFCAE104 (0x0010u) +#define GPIO_PFCAE10_PFCAE105 (0x0020u) +#define GPIO_PFCAE10_PFCAE106 (0x0040u) +#define GPIO_PFCAE10_PFCAE107 (0x0080u) +#define GPIO_PFCAE10_PFCAE108 (0x0100u) +#define GPIO_PFCAE10_PFCAE109 (0x0200u) +#define GPIO_PFCAE10_PFCAE1010 (0x0400u) +#define GPIO_PFCAE10_PFCAE1011 (0x0800u) +#define GPIO_PFCAE10_PFCAE1012 (0x1000u) +#define GPIO_PFCAE10_PFCAE1013 (0x2000u) +#define GPIO_PFCAE10_PFCAE1014 (0x4000u) +#define GPIO_PFCAE10_PFCAE1015 (0x8000u) + +#define GPIO_PIBC10_PIBC100 (0x0001u) +#define GPIO_PIBC10_PIBC101 (0x0002u) +#define GPIO_PIBC10_PIBC102 (0x0004u) +#define GPIO_PIBC10_PIBC103 (0x0008u) +#define GPIO_PIBC10_PIBC104 (0x0010u) +#define GPIO_PIBC10_PIBC105 (0x0020u) +#define GPIO_PIBC10_PIBC106 (0x0040u) +#define GPIO_PIBC10_PIBC107 (0x0080u) +#define GPIO_PIBC10_PIBC108 (0x0100u) +#define GPIO_PIBC10_PIBC109 (0x0200u) +#define GPIO_PIBC10_PIBC1010 (0x0400u) +#define GPIO_PIBC10_PIBC1011 (0x0800u) +#define GPIO_PIBC10_PIBC1012 (0x1000u) +#define GPIO_PIBC10_PIBC1013 (0x2000u) +#define GPIO_PIBC10_PIBC1014 (0x4000u) +#define GPIO_PIBC10_PIBC1015 (0x8000u) + +#define GPIO_PBDC10_PBDC100 (0x0001u) +#define GPIO_PBDC10_PBDC101 (0x0002u) +#define GPIO_PBDC10_PBDC102 (0x0004u) +#define GPIO_PBDC10_PBDC103 (0x0008u) +#define GPIO_PBDC10_PBDC104 (0x0010u) +#define GPIO_PBDC10_PBDC105 (0x0020u) +#define GPIO_PBDC10_PBDC106 (0x0040u) +#define GPIO_PBDC10_PBDC107 (0x0080u) +#define GPIO_PBDC10_PBDC108 (0x0100u) +#define GPIO_PBDC10_PBDC109 (0x0200u) +#define GPIO_PBDC10_PBDC1010 (0x0400u) +#define GPIO_PBDC10_PBDC1011 (0x0800u) +#define GPIO_PBDC10_PBDC1012 (0x1000u) +#define GPIO_PBDC10_PBDC1013 (0x2000u) +#define GPIO_PBDC10_PBDC1014 (0x4000u) +#define GPIO_PBDC10_PBDC1015 (0x8000u) + +#define GPIO_PIPC10_PIPC100 (0x0001u) +#define GPIO_PIPC10_PIPC101 (0x0002u) +#define GPIO_PIPC10_PIPC102 (0x0004u) +#define GPIO_PIPC10_PIPC103 (0x0008u) +#define GPIO_PIPC10_PIPC104 (0x0010u) +#define GPIO_PIPC10_PIPC105 (0x0020u) +#define GPIO_PIPC10_PIPC106 (0x0040u) +#define GPIO_PIPC10_PIPC107 (0x0080u) +#define GPIO_PIPC10_PIPC108 (0x0100u) +#define GPIO_PIPC10_PIPC109 (0x0200u) +#define GPIO_PIPC10_PIPC1010 (0x0400u) +#define GPIO_PIPC10_PIPC1011 (0x0800u) +#define GPIO_PIPC10_PIPC1012 (0x1000u) +#define GPIO_PIPC10_PIPC1013 (0x2000u) +#define GPIO_PIPC10_PIPC1014 (0x4000u) +#define GPIO_PIPC10_PIPC1015 (0x8000u) + +/* ---- P11 ---- */ +#define GPIO_P11_P110 (0x0001u) +#define GPIO_P11_P111 (0x0002u) +#define GPIO_P11_P112 (0x0004u) +#define GPIO_P11_P113 (0x0008u) +#define GPIO_P11_P114 (0x0010u) +#define GPIO_P11_P115 (0x0020u) +#define GPIO_P11_P116 (0x0040u) +#define GPIO_P11_P117 (0x0080u) +#define GPIO_P11_P118 (0x0100u) +#define GPIO_P11_P119 (0x0200u) +#define GPIO_P11_P1110 (0x0400u) +#define GPIO_P11_P1111 (0x0800u) +#define GPIO_P11_P1112 (0x1000u) +#define GPIO_P11_P1113 (0x2000u) +#define GPIO_P11_P1114 (0x4000u) +#define GPIO_P11_P1115 (0x8000u) + +#define GPIO_PSR11_PSR110 (0x00000001uL) +#define GPIO_PSR11_PSR111 (0x00000002uL) +#define GPIO_PSR11_PSR112 (0x00000004uL) +#define GPIO_PSR11_PSR113 (0x00000008uL) +#define GPIO_PSR11_PSR114 (0x00000010uL) +#define GPIO_PSR11_PSR115 (0x00000020uL) +#define GPIO_PSR11_PSR116 (0x00000040uL) +#define GPIO_PSR11_PSR117 (0x00000080uL) +#define GPIO_PSR11_PSR118 (0x00000100uL) +#define GPIO_PSR11_PSR119 (0x00000200uL) +#define GPIO_PSR11_PSR1110 (0x00000400uL) +#define GPIO_PSR11_PSR1111 (0x00000800uL) +#define GPIO_PSR11_PSR1112 (0x00001000uL) +#define GPIO_PSR11_PSR1113 (0x00002000uL) +#define GPIO_PSR11_PSR1114 (0x00004000uL) +#define GPIO_PSR11_PSR1115 (0x00008000uL) +#define GPIO_PSR11_PSR1116 (0x00010000uL) +#define GPIO_PSR11_PSR1117 (0x00020000uL) +#define GPIO_PSR11_PSR1118 (0x00040000uL) +#define GPIO_PSR11_PSR1119 (0x00080000uL) +#define GPIO_PSR11_PSR1120 (0x00100000uL) +#define GPIO_PSR11_PSR1121 (0x00200000uL) +#define GPIO_PSR11_PSR1122 (0x00400000uL) +#define GPIO_PSR11_PSR1123 (0x00800000uL) +#define GPIO_PSR11_PSR1124 (0x01000000uL) +#define GPIO_PSR11_PSR1125 (0x02000000uL) +#define GPIO_PSR11_PSR1126 (0x04000000uL) +#define GPIO_PSR11_PSR1127 (0x08000000uL) +#define GPIO_PSR11_PSR1128 (0x10000000uL) +#define GPIO_PSR11_PSR1129 (0x20000000uL) +#define GPIO_PSR11_PSR1130 (0x40000000uL) +#define GPIO_PSR11_PSR1131 (0x80000000uL) + +#define GPIO_PPR11_PPR110 (0x0001u) +#define GPIO_PPR11_PPR111 (0x0002u) +#define GPIO_PPR11_PPR112 (0x0004u) +#define GPIO_PPR11_PPR113 (0x0008u) +#define GPIO_PPR11_PPR114 (0x0010u) +#define GPIO_PPR11_PPR115 (0x0020u) +#define GPIO_PPR11_PPR116 (0x0040u) +#define GPIO_PPR11_PPR117 (0x0080u) +#define GPIO_PPR11_PPR118 (0x0100u) +#define GPIO_PPR11_PPR119 (0x0200u) +#define GPIO_PPR11_PPR1110 (0x0400u) +#define GPIO_PPR11_PPR1111 (0x0800u) +#define GPIO_PPR11_PPR1112 (0x1000u) +#define GPIO_PPR11_PPR1113 (0x2000u) +#define GPIO_PPR11_PPR1114 (0x4000u) +#define GPIO_PPR11_PPR1115 (0x8000u) + +#define GPIO_PM11_PM110 (0x0001u) +#define GPIO_PM11_PM111 (0x0002u) +#define GPIO_PM11_PM112 (0x0004u) +#define GPIO_PM11_PM113 (0x0008u) +#define GPIO_PM11_PM114 (0x0010u) +#define GPIO_PM11_PM115 (0x0020u) +#define GPIO_PM11_PM116 (0x0040u) +#define GPIO_PM11_PM117 (0x0080u) +#define GPIO_PM11_PM118 (0x0100u) +#define GPIO_PM11_PM119 (0x0200u) +#define GPIO_PM11_PM1110 (0x0400u) +#define GPIO_PM11_PM1111 (0x0800u) +#define GPIO_PM11_PM1112 (0x1000u) +#define GPIO_PM11_PM1113 (0x2000u) +#define GPIO_PM11_PM1114 (0x4000u) +#define GPIO_PM11_PM1115 (0x8000u) + +#define GPIO_PMC11_PMC110 (0x0001u) +#define GPIO_PMC11_PMC111 (0x0002u) +#define GPIO_PMC11_PMC112 (0x0004u) +#define GPIO_PMC11_PMC113 (0x0008u) +#define GPIO_PMC11_PMC114 (0x0010u) +#define GPIO_PMC11_PMC115 (0x0020u) +#define GPIO_PMC11_PMC116 (0x0040u) +#define GPIO_PMC11_PMC117 (0x0080u) +#define GPIO_PMC11_PMC118 (0x0100u) +#define GPIO_PMC11_PMC119 (0x0200u) +#define GPIO_PMC11_PMC1110 (0x0400u) +#define GPIO_PMC11_PMC1111 (0x0800u) +#define GPIO_PMC11_PMC1112 (0x1000u) +#define GPIO_PMC11_PMC1113 (0x2000u) +#define GPIO_PMC11_PMC1114 (0x4000u) +#define GPIO_PMC11_PMC1115 (0x8000u) + +#define GPIO_PFC11_PFC110 (0x0001u) +#define GPIO_PFC11_PFC111 (0x0002u) +#define GPIO_PFC11_PFC112 (0x0004u) +#define GPIO_PFC11_PFC113 (0x0008u) +#define GPIO_PFC11_PFC114 (0x0010u) +#define GPIO_PFC11_PFC115 (0x0020u) +#define GPIO_PFC11_PFC116 (0x0040u) +#define GPIO_PFC11_PFC117 (0x0080u) +#define GPIO_PFC11_PFC118 (0x0100u) +#define GPIO_PFC11_PFC119 (0x0200u) +#define GPIO_PFC11_PFC1110 (0x0400u) +#define GPIO_PFC11_PFC1111 (0x0800u) +#define GPIO_PFC11_PFC1112 (0x1000u) +#define GPIO_PFC11_PFC1113 (0x2000u) +#define GPIO_PFC11_PFC1114 (0x4000u) +#define GPIO_PFC11_PFC1115 (0x8000u) + +#define GPIO_PFCE11_PFCE110 (0x0001u) +#define GPIO_PFCE11_PFCE111 (0x0002u) +#define GPIO_PFCE11_PFCE112 (0x0004u) +#define GPIO_PFCE11_PFCE113 (0x0008u) +#define GPIO_PFCE11_PFCE114 (0x0010u) +#define GPIO_PFCE11_PFCE115 (0x0020u) +#define GPIO_PFCE11_PFCE116 (0x0040u) +#define GPIO_PFCE11_PFCE117 (0x0080u) +#define GPIO_PFCE11_PFCE118 (0x0100u) +#define GPIO_PFCE11_PFCE119 (0x0200u) +#define GPIO_PFCE11_PFCE1110 (0x0400u) +#define GPIO_PFCE11_PFCE1111 (0x0800u) +#define GPIO_PFCE11_PFCE1112 (0x1000u) +#define GPIO_PFCE11_PFCE1113 (0x2000u) +#define GPIO_PFCE11_PFCE1114 (0x4000u) +#define GPIO_PFCE11_PFCE1115 (0x8000u) + +#define GPIO_PNOT11_PNOT110 (0x0001u) +#define GPIO_PNOT11_PNOT111 (0x0002u) +#define GPIO_PNOT11_PNOT112 (0x0004u) +#define GPIO_PNOT11_PNOT113 (0x0008u) +#define GPIO_PNOT11_PNOT114 (0x0010u) +#define GPIO_PNOT11_PNOT115 (0x0020u) +#define GPIO_PNOT11_PNOT116 (0x0040u) +#define GPIO_PNOT11_PNOT117 (0x0080u) +#define GPIO_PNOT11_PNOT118 (0x0100u) +#define GPIO_PNOT11_PNOT119 (0x0200u) +#define GPIO_PNOT11_PNOT1110 (0x0400u) +#define GPIO_PNOT11_PNOT1111 (0x0800u) +#define GPIO_PNOT11_PNOT1112 (0x1000u) +#define GPIO_PNOT11_PNOT1113 (0x2000u) +#define GPIO_PNOT11_PNOT1114 (0x4000u) +#define GPIO_PNOT11_PNOT1115 (0x8000u) + +#define GPIO_PMSR11_PMSR110 (0x00000001uL) +#define GPIO_PMSR11_PMSR111 (0x00000002uL) +#define GPIO_PMSR11_PMSR112 (0x00000004uL) +#define GPIO_PMSR11_PMSR113 (0x00000008uL) +#define GPIO_PMSR11_PMSR114 (0x00000010uL) +#define GPIO_PMSR11_PMSR115 (0x00000020uL) +#define GPIO_PMSR11_PMSR116 (0x00000040uL) +#define GPIO_PMSR11_PMSR117 (0x00000080uL) +#define GPIO_PMSR11_PMSR118 (0x00000100uL) +#define GPIO_PMSR11_PMSR119 (0x00000200uL) +#define GPIO_PMSR11_PMSR1110 (0x00000400uL) +#define GPIO_PMSR11_PMSR1111 (0x00000800uL) +#define GPIO_PMSR11_PMSR1112 (0x00001000uL) +#define GPIO_PMSR11_PMSR1113 (0x00002000uL) +#define GPIO_PMSR11_PMSR1114 (0x00004000uL) +#define GPIO_PMSR11_PMSR1115 (0x00008000uL) +#define GPIO_PMSR11_PMSR1116 (0x00010000uL) +#define GPIO_PMSR11_PMSR1117 (0x00020000uL) +#define GPIO_PMSR11_PMSR1118 (0x00040000uL) +#define GPIO_PMSR11_PMSR1119 (0x00080000uL) +#define GPIO_PMSR11_PMSR1120 (0x00100000uL) +#define GPIO_PMSR11_PMSR1121 (0x00200000uL) +#define GPIO_PMSR11_PMSR1122 (0x00400000uL) +#define GPIO_PMSR11_PMSR1123 (0x00800000uL) +#define GPIO_PMSR11_PMSR1124 (0x01000000uL) +#define GPIO_PMSR11_PMSR1125 (0x02000000uL) +#define GPIO_PMSR11_PMSR1126 (0x04000000uL) +#define GPIO_PMSR11_PMSR1127 (0x08000000uL) +#define GPIO_PMSR11_PMSR1128 (0x10000000uL) +#define GPIO_PMSR11_PMSR1129 (0x20000000uL) +#define GPIO_PMSR11_PMSR1130 (0x40000000uL) +#define GPIO_PMSR11_PMSR1131 (0x80000000uL) + +#define GPIO_PMCSR11_PMCSR110 (0x00000001uL) +#define GPIO_PMCSR11_PMCSR111 (0x00000002uL) +#define GPIO_PMCSR11_PMCSR112 (0x00000004uL) +#define GPIO_PMCSR11_PMCSR113 (0x00000008uL) +#define GPIO_PMCSR11_PMCSR114 (0x00000010uL) +#define GPIO_PMCSR11_PMCSR115 (0x00000020uL) +#define GPIO_PMCSR11_PMCSR116 (0x00000040uL) +#define GPIO_PMCSR11_PMCSR117 (0x00000080uL) +#define GPIO_PMCSR11_PMCSR118 (0x00000100uL) +#define GPIO_PMCSR11_PMCSR119 (0x00000200uL) +#define GPIO_PMCSR11_PMCSR1110 (0x00000400uL) +#define GPIO_PMCSR11_PMCSR1111 (0x00000800uL) +#define GPIO_PMCSR11_PMCSR1112 (0x00001000uL) +#define GPIO_PMCSR11_PMCSR1113 (0x00002000uL) +#define GPIO_PMCSR11_PMCSR1114 (0x00004000uL) +#define GPIO_PMCSR11_PMCSR1115 (0x00008000uL) +#define GPIO_PMCSR11_PMCSR1116 (0x00010000uL) +#define GPIO_PMCSR11_PMCSR1117 (0x00020000uL) +#define GPIO_PMCSR11_PMCSR1118 (0x00040000uL) +#define GPIO_PMCSR11_PMCSR1119 (0x00080000uL) +#define GPIO_PMCSR11_PMCSR1120 (0x00100000uL) +#define GPIO_PMCSR11_PMCSR1121 (0x00200000uL) +#define GPIO_PMCSR11_PMCSR1122 (0x00400000uL) +#define GPIO_PMCSR11_PMCSR1123 (0x00800000uL) +#define GPIO_PMCSR11_PMCSR1124 (0x01000000uL) +#define GPIO_PMCSR11_PMCSR1125 (0x02000000uL) +#define GPIO_PMCSR11_PMCSR1126 (0x04000000uL) +#define GPIO_PMCSR11_PMCSR1127 (0x08000000uL) +#define GPIO_PMCSR11_PMCSR1128 (0x10000000uL) +#define GPIO_PMCSR11_PMCSR1129 (0x20000000uL) +#define GPIO_PMCSR11_PMCSR1130 (0x40000000uL) +#define GPIO_PMCSR11_PMCSR1131 (0x80000000uL) + +#define GPIO_PFCAE11_PFCAE110 (0x0001u) +#define GPIO_PFCAE11_PFCAE111 (0x0002u) +#define GPIO_PFCAE11_PFCAE112 (0x0004u) +#define GPIO_PFCAE11_PFCAE113 (0x0008u) +#define GPIO_PFCAE11_PFCAE114 (0x0010u) +#define GPIO_PFCAE11_PFCAE115 (0x0020u) +#define GPIO_PFCAE11_PFCAE116 (0x0040u) +#define GPIO_PFCAE11_PFCAE117 (0x0080u) +#define GPIO_PFCAE11_PFCAE118 (0x0100u) +#define GPIO_PFCAE11_PFCAE119 (0x0200u) +#define GPIO_PFCAE11_PFCAE1110 (0x0400u) +#define GPIO_PFCAE11_PFCAE1111 (0x0800u) +#define GPIO_PFCAE11_PFCAE1112 (0x1000u) +#define GPIO_PFCAE11_PFCAE1113 (0x2000u) +#define GPIO_PFCAE11_PFCAE1114 (0x4000u) +#define GPIO_PFCAE11_PFCAE1115 (0x8000u) + +#define GPIO_PIBC11_PIBC110 (0x0001u) +#define GPIO_PIBC11_PIBC111 (0x0002u) +#define GPIO_PIBC11_PIBC112 (0x0004u) +#define GPIO_PIBC11_PIBC113 (0x0008u) +#define GPIO_PIBC11_PIBC114 (0x0010u) +#define GPIO_PIBC11_PIBC115 (0x0020u) +#define GPIO_PIBC11_PIBC116 (0x0040u) +#define GPIO_PIBC11_PIBC117 (0x0080u) +#define GPIO_PIBC11_PIBC118 (0x0100u) +#define GPIO_PIBC11_PIBC119 (0x0200u) +#define GPIO_PIBC11_PIBC1110 (0x0400u) +#define GPIO_PIBC11_PIBC1111 (0x0800u) +#define GPIO_PIBC11_PIBC1112 (0x1000u) +#define GPIO_PIBC11_PIBC1113 (0x2000u) +#define GPIO_PIBC11_PIBC1114 (0x4000u) +#define GPIO_PIBC11_PIBC1115 (0x8000u) + +#define GPIO_PBDC11_PBDC110 (0x0001u) +#define GPIO_PBDC11_PBDC111 (0x0002u) +#define GPIO_PBDC11_PBDC112 (0x0004u) +#define GPIO_PBDC11_PBDC113 (0x0008u) +#define GPIO_PBDC11_PBDC114 (0x0010u) +#define GPIO_PBDC11_PBDC115 (0x0020u) +#define GPIO_PBDC11_PBDC116 (0x0040u) +#define GPIO_PBDC11_PBDC117 (0x0080u) +#define GPIO_PBDC11_PBDC118 (0x0100u) +#define GPIO_PBDC11_PBDC119 (0x0200u) +#define GPIO_PBDC11_PBDC1110 (0x0400u) +#define GPIO_PBDC11_PBDC1111 (0x0800u) +#define GPIO_PBDC11_PBDC1112 (0x1000u) +#define GPIO_PBDC11_PBDC1113 (0x2000u) +#define GPIO_PBDC11_PBDC1114 (0x4000u) +#define GPIO_PBDC11_PBDC1115 (0x8000u) + +#define GPIO_PIPC11_PIPC110 (0x0001u) +#define GPIO_PIPC11_PIPC111 (0x0002u) +#define GPIO_PIPC11_PIPC112 (0x0004u) +#define GPIO_PIPC11_PIPC113 (0x0008u) +#define GPIO_PIPC11_PIPC114 (0x0010u) +#define GPIO_PIPC11_PIPC115 (0x0020u) +#define GPIO_PIPC11_PIPC116 (0x0040u) +#define GPIO_PIPC11_PIPC117 (0x0080u) +#define GPIO_PIPC11_PIPC118 (0x0100u) +#define GPIO_PIPC11_PIPC119 (0x0200u) +#define GPIO_PIPC11_PIPC1110 (0x0400u) +#define GPIO_PIPC11_PIPC1111 (0x0800u) +#define GPIO_PIPC11_PIPC1112 (0x1000u) +#define GPIO_PIPC11_PIPC1113 (0x2000u) +#define GPIO_PIPC11_PIPC1114 (0x4000u) +#define GPIO_PIPC11_PIPC1115 (0x8000u) + + +/* ==== Shift values for IO registers ==== */ +/* ---- P0 ---- */ +#define GPIO_PPR0_PPR00_SHIFT (0u) +#define GPIO_PPR0_PPR01_SHIFT (1u) +#define GPIO_PPR0_PPR02_SHIFT (2u) +#define GPIO_PPR0_PPR03_SHIFT (3u) +#define GPIO_PPR0_PPR04_SHIFT (4u) +#define GPIO_PPR0_PPR05_SHIFT (5u) + +#define GPIO_PMC0_PMC04_SHIFT (4u) +#define GPIO_PMC0_PMC05_SHIFT (5u) + +#define GPIO_PMCSR0_PMCSR04_SHIFT (4u) +#define GPIO_PMCSR0_PMCSR05_SHIFT (5u) + +#define GPIO_PIBC0_PIBC00_SHIFT (0u) +#define GPIO_PIBC0_PIBC01_SHIFT (1u) +#define GPIO_PIBC0_PIBC02_SHIFT (2u) +#define GPIO_PIBC0_PIBC03_SHIFT (3u) +#define GPIO_PIBC0_PIBC04_SHIFT (4u) +#define GPIO_PIBC0_PIBC05_SHIFT (5u) + +/* ---- P1 ---- */ +#define GPIO_P1_P10_SHIFT (0u) +#define GPIO_P1_P11_SHIFT (1u) +#define GPIO_P1_P12_SHIFT (2u) +#define GPIO_P1_P13_SHIFT (3u) +#define GPIO_P1_P14_SHIFT (4u) +#define GPIO_P1_P15_SHIFT (5u) +#define GPIO_P1_P16_SHIFT (6u) +#define GPIO_P1_P17_SHIFT (7u) + +#define GPIO_PSR1_PSR10_SHIFT (0u) +#define GPIO_PSR1_PSR11_SHIFT (1u) +#define GPIO_PSR1_PSR12_SHIFT (2u) +#define GPIO_PSR1_PSR13_SHIFT (3u) +#define GPIO_PSR1_PSR14_SHIFT (4u) +#define GPIO_PSR1_PSR15_SHIFT (5u) +#define GPIO_PSR1_PSR16_SHIFT (6u) +#define GPIO_PSR1_PSR17_SHIFT (7u) +#define GPIO_PSR1_PSR116_SHIFT (16u) +#define GPIO_PSR1_PSR117_SHIFT (17u) +#define GPIO_PSR1_PSR118_SHIFT (18u) +#define GPIO_PSR1_PSR119_SHIFT (19u) +#define GPIO_PSR1_PSR120_SHIFT (20u) +#define GPIO_PSR1_PSR121_SHIFT (21u) +#define GPIO_PSR1_PSR122_SHIFT (22u) +#define GPIO_PSR1_PSR123_SHIFT (23u) + +#define GPIO_PPR1_PPR10_SHIFT (0u) +#define GPIO_PPR1_PPR11_SHIFT (1u) +#define GPIO_PPR1_PPR12_SHIFT (2u) +#define GPIO_PPR1_PPR13_SHIFT (3u) +#define GPIO_PPR1_PPR14_SHIFT (4u) +#define GPIO_PPR1_PPR15_SHIFT (5u) +#define GPIO_PPR1_PPR16_SHIFT (6u) +#define GPIO_PPR1_PPR17_SHIFT (7u) +#define GPIO_PPR1_PPR18_SHIFT (8u) +#define GPIO_PPR1_PPR19_SHIFT (9u) +#define GPIO_PPR1_PPR110_SHIFT (10u) +#define GPIO_PPR1_PPR111_SHIFT (11u) +#define GPIO_PPR1_PPR112_SHIFT (12u) +#define GPIO_PPR1_PPR113_SHIFT (13u) +#define GPIO_PPR1_PPR114_SHIFT (14u) +#define GPIO_PPR1_PPR115_SHIFT (15u) + +#define GPIO_PM1_PM10_SHIFT (0u) +#define GPIO_PM1_PM11_SHIFT (1u) +#define GPIO_PM1_PM12_SHIFT (2u) +#define GPIO_PM1_PM13_SHIFT (3u) +#define GPIO_PM1_PM14_SHIFT (4u) +#define GPIO_PM1_PM15_SHIFT (5u) +#define GPIO_PM1_PM16_SHIFT (6u) +#define GPIO_PM1_PM17_SHIFT (7u) + +#define GPIO_PMC1_PMC10_SHIFT (0u) +#define GPIO_PMC1_PMC11_SHIFT (1u) +#define GPIO_PMC1_PMC12_SHIFT (2u) +#define GPIO_PMC1_PMC13_SHIFT (3u) +#define GPIO_PMC1_PMC14_SHIFT (4u) +#define GPIO_PMC1_PMC15_SHIFT (5u) +#define GPIO_PMC1_PMC16_SHIFT (6u) +#define GPIO_PMC1_PMC17_SHIFT (7u) +#define GPIO_PMC1_PMC18_SHIFT (8u) +#define GPIO_PMC1_PMC19_SHIFT (9u) +#define GPIO_PMC1_PMC110_SHIFT (10u) +#define GPIO_PMC1_PMC111_SHIFT (11u) +#define GPIO_PMC1_PMC112_SHIFT (12u) +#define GPIO_PMC1_PMC113_SHIFT (13u) +#define GPIO_PMC1_PMC114_SHIFT (14u) +#define GPIO_PMC1_PMC115_SHIFT (15u) + +#define GPIO_PFC1_PFC10_SHIFT (0u) +#define GPIO_PFC1_PFC11_SHIFT (1u) +#define GPIO_PFC1_PFC12_SHIFT (2u) +#define GPIO_PFC1_PFC13_SHIFT (3u) +#define GPIO_PFC1_PFC14_SHIFT (4u) +#define GPIO_PFC1_PFC15_SHIFT (5u) +#define GPIO_PFC1_PFC16_SHIFT (6u) +#define GPIO_PFC1_PFC17_SHIFT (7u) +#define GPIO_PFC1_PFC18_SHIFT (8u) +#define GPIO_PFC1_PFC19_SHIFT (9u) +#define GPIO_PFC1_PFC110_SHIFT (10u) +#define GPIO_PFC1_PFC111_SHIFT (11u) +#define GPIO_PFC1_PFC112_SHIFT (12u) +#define GPIO_PFC1_PFC113_SHIFT (13u) +#define GPIO_PFC1_PFC114_SHIFT (14u) +#define GPIO_PFC1_PFC115_SHIFT (15u) + +#define GPIO_PFCE1_PFCE10_SHIFT (0u) +#define GPIO_PFCE1_PFCE11_SHIFT (1u) +#define GPIO_PFCE1_PFCE12_SHIFT (2u) +#define GPIO_PFCE1_PFCE13_SHIFT (3u) +#define GPIO_PFCE1_PFCE14_SHIFT (4u) +#define GPIO_PFCE1_PFCE15_SHIFT (5u) +#define GPIO_PFCE1_PFCE16_SHIFT (6u) +#define GPIO_PFCE1_PFCE17_SHIFT (7u) +#define GPIO_PFCE1_PFCE18_SHIFT (8u) +#define GPIO_PFCE1_PFCE19_SHIFT (9u) +#define GPIO_PFCE1_PFCE110_SHIFT (10u) +#define GPIO_PFCE1_PFCE111_SHIFT (11u) +#define GPIO_PFCE1_PFCE112_SHIFT (12u) +#define GPIO_PFCE1_PFCE113_SHIFT (13u) +#define GPIO_PFCE1_PFCE114_SHIFT (14u) +#define GPIO_PFCE1_PFCE115_SHIFT (15u) + +#define GPIO_PNOT1_PNOT10_SHIFT (0u) +#define GPIO_PNOT1_PNOT11_SHIFT (1u) +#define GPIO_PNOT1_PNOT12_SHIFT (2u) +#define GPIO_PNOT1_PNOT13_SHIFT (3u) +#define GPIO_PNOT1_PNOT14_SHIFT (4u) +#define GPIO_PNOT1_PNOT15_SHIFT (5u) +#define GPIO_PNOT1_PNOT16_SHIFT (6u) +#define GPIO_PNOT1_PNOT17_SHIFT (7u) + +#define GPIO_PMSR1_PMSR10_SHIFT (0u) +#define GPIO_PMSR1_PMSR11_SHIFT (1u) +#define GPIO_PMSR1_PMSR12_SHIFT (2u) +#define GPIO_PMSR1_PMSR13_SHIFT (3u) +#define GPIO_PMSR1_PMSR14_SHIFT (4u) +#define GPIO_PMSR1_PMSR15_SHIFT (5u) +#define GPIO_PMSR1_PMSR16_SHIFT (6u) +#define GPIO_PMSR1_PMSR17_SHIFT (7u) +#define GPIO_PMSR1_PMSR116_SHIFT (16u) +#define GPIO_PMSR1_PMSR117_SHIFT (17u) +#define GPIO_PMSR1_PMSR118_SHIFT (18u) +#define GPIO_PMSR1_PMSR119_SHIFT (19u) +#define GPIO_PMSR1_PMSR120_SHIFT (20u) +#define GPIO_PMSR1_PMSR121_SHIFT (21u) +#define GPIO_PMSR1_PMSR122_SHIFT (22u) +#define GPIO_PMSR1_PMSR123_SHIFT (23u) + +#define GPIO_PMCSR1_PMCSR10_SHIFT (0u) +#define GPIO_PMCSR1_PMCSR11_SHIFT (1u) +#define GPIO_PMCSR1_PMCSR12_SHIFT (2u) +#define GPIO_PMCSR1_PMCSR13_SHIFT (3u) +#define GPIO_PMCSR1_PMCSR14_SHIFT (4u) +#define GPIO_PMCSR1_PMCSR15_SHIFT (5u) +#define GPIO_PMCSR1_PMCSR16_SHIFT (6u) +#define GPIO_PMCSR1_PMCSR17_SHIFT (7u) +#define GPIO_PMCSR1_PMCSR116_SHIFT (16u) +#define GPIO_PMCSR1_PMCSR117_SHIFT (17u) +#define GPIO_PMCSR1_PMCSR118_SHIFT (18u) +#define GPIO_PMCSR1_PMCSR119_SHIFT (19u) +#define GPIO_PMCSR1_PMCSR120_SHIFT (20u) +#define GPIO_PMCSR1_PMCSR121_SHIFT (21u) +#define GPIO_PMCSR1_PMCSR122_SHIFT (22u) +#define GPIO_PMCSR1_PMCSR123_SHIFT (23u) + +#define GPIO_PFCAE1_PFCAE10_SHIFT (0u) +#define GPIO_PFCAE1_PFCAE11_SHIFT (1u) +#define GPIO_PFCAE1_PFCAE12_SHIFT (2u) +#define GPIO_PFCAE1_PFCAE13_SHIFT (3u) +#define GPIO_PFCAE1_PFCAE14_SHIFT (4u) +#define GPIO_PFCAE1_PFCAE15_SHIFT (5u) +#define GPIO_PFCAE1_PFCAE16_SHIFT (6u) +#define GPIO_PFCAE1_PFCAE17_SHIFT (7u) +#define GPIO_PFCAE1_PFCAE18_SHIFT (8u) +#define GPIO_PFCAE1_PFCAE19_SHIFT (9u) +#define GPIO_PFCAE1_PFCAE110_SHIFT (10u) +#define GPIO_PFCAE1_PFCAE111_SHIFT (11u) +#define GPIO_PFCAE1_PFCAE112_SHIFT (12u) +#define GPIO_PFCAE1_PFCAE113_SHIFT (13u) +#define GPIO_PFCAE1_PFCAE114_SHIFT (14u) +#define GPIO_PFCAE1_PFCAE115_SHIFT (15u) + +#define GPIO_PIBC1_PIBC10_SHIFT (0u) +#define GPIO_PIBC1_PIBC11_SHIFT (1u) +#define GPIO_PIBC1_PIBC12_SHIFT (2u) +#define GPIO_PIBC1_PIBC13_SHIFT (3u) +#define GPIO_PIBC1_PIBC14_SHIFT (4u) +#define GPIO_PIBC1_PIBC15_SHIFT (5u) +#define GPIO_PIBC1_PIBC16_SHIFT (6u) +#define GPIO_PIBC1_PIBC17_SHIFT (7u) +#define GPIO_PIBC1_PIBC18_SHIFT (8u) +#define GPIO_PIBC1_PIBC19_SHIFT (9u) +#define GPIO_PIBC1_PIBC110_SHIFT (10u) +#define GPIO_PIBC1_PIBC111_SHIFT (11u) +#define GPIO_PIBC1_PIBC112_SHIFT (12u) +#define GPIO_PIBC1_PIBC113_SHIFT (13u) +#define GPIO_PIBC1_PIBC114_SHIFT (14u) +#define GPIO_PIBC1_PIBC115_SHIFT (15u) + +#define GPIO_PBDC1_PBDC10_SHIFT (0u) +#define GPIO_PBDC1_PBDC11_SHIFT (1u) +#define GPIO_PBDC1_PBDC12_SHIFT (2u) +#define GPIO_PBDC1_PBDC13_SHIFT (3u) +#define GPIO_PBDC1_PBDC14_SHIFT (4u) +#define GPIO_PBDC1_PBDC15_SHIFT (5u) +#define GPIO_PBDC1_PBDC16_SHIFT (6u) +#define GPIO_PBDC1_PBDC17_SHIFT (7u) +#define GPIO_PBDC1_PBDC18_SHIFT (8u) +#define GPIO_PBDC1_PBDC19_SHIFT (9u) +#define GPIO_PBDC1_PBDC110_SHIFT (10u) +#define GPIO_PBDC1_PBDC111_SHIFT (11u) +#define GPIO_PBDC1_PBDC112_SHIFT (12u) +#define GPIO_PBDC1_PBDC113_SHIFT (13u) +#define GPIO_PBDC1_PBDC114_SHIFT (14u) +#define GPIO_PBDC1_PBDC115_SHIFT (15u) + +#define GPIO_PIPC1_PIPC10_SHIFT (0u) +#define GPIO_PIPC1_PIPC11_SHIFT (1u) +#define GPIO_PIPC1_PIPC12_SHIFT (2u) +#define GPIO_PIPC1_PIPC13_SHIFT (3u) +#define GPIO_PIPC1_PIPC14_SHIFT (4u) +#define GPIO_PIPC1_PIPC15_SHIFT (5u) +#define GPIO_PIPC1_PIPC16_SHIFT (6u) +#define GPIO_PIPC1_PIPC17_SHIFT (7u) + +/* ---- P2 ---- */ +#define GPIO_P2_P20_SHIFT (0u) +#define GPIO_P2_P21_SHIFT (1u) +#define GPIO_P2_P22_SHIFT (2u) +#define GPIO_P2_P23_SHIFT (3u) +#define GPIO_P2_P24_SHIFT (4u) +#define GPIO_P2_P25_SHIFT (5u) +#define GPIO_P2_P26_SHIFT (6u) +#define GPIO_P2_P27_SHIFT (7u) +#define GPIO_P2_P28_SHIFT (8u) +#define GPIO_P2_P29_SHIFT (9u) +#define GPIO_P2_P210_SHIFT (10u) +#define GPIO_P2_P211_SHIFT (11u) +#define GPIO_P2_P212_SHIFT (12u) +#define GPIO_P2_P213_SHIFT (13u) +#define GPIO_P2_P214_SHIFT (14u) +#define GPIO_P2_P215_SHIFT (15u) + +#define GPIO_PSR2_PSR20_SHIFT (0u) +#define GPIO_PSR2_PSR21_SHIFT (1u) +#define GPIO_PSR2_PSR22_SHIFT (2u) +#define GPIO_PSR2_PSR23_SHIFT (3u) +#define GPIO_PSR2_PSR24_SHIFT (4u) +#define GPIO_PSR2_PSR25_SHIFT (5u) +#define GPIO_PSR2_PSR26_SHIFT (6u) +#define GPIO_PSR2_PSR27_SHIFT (7u) +#define GPIO_PSR2_PSR28_SHIFT (8u) +#define GPIO_PSR2_PSR29_SHIFT (9u) +#define GPIO_PSR2_PSR210_SHIFT (10u) +#define GPIO_PSR2_PSR211_SHIFT (11u) +#define GPIO_PSR2_PSR212_SHIFT (12u) +#define GPIO_PSR2_PSR213_SHIFT (13u) +#define GPIO_PSR2_PSR214_SHIFT (14u) +#define GPIO_PSR2_PSR215_SHIFT (15u) +#define GPIO_PSR2_PSR216_SHIFT (16u) +#define GPIO_PSR2_PSR217_SHIFT (17u) +#define GPIO_PSR2_PSR218_SHIFT (18u) +#define GPIO_PSR2_PSR219_SHIFT (19u) +#define GPIO_PSR2_PSR220_SHIFT (20u) +#define GPIO_PSR2_PSR221_SHIFT (21u) +#define GPIO_PSR2_PSR222_SHIFT (22u) +#define GPIO_PSR2_PSR223_SHIFT (23u) +#define GPIO_PSR2_PSR224_SHIFT (24u) +#define GPIO_PSR2_PSR225_SHIFT (25u) +#define GPIO_PSR2_PSR226_SHIFT (26u) +#define GPIO_PSR2_PSR227_SHIFT (27u) +#define GPIO_PSR2_PSR228_SHIFT (28u) +#define GPIO_PSR2_PSR229_SHIFT (29u) +#define GPIO_PSR2_PSR230_SHIFT (30u) +#define GPIO_PSR2_PSR231_SHIFT (31u) + +#define GPIO_PPR2_PPR20_SHIFT (0u) +#define GPIO_PPR2_PPR21_SHIFT (1u) +#define GPIO_PPR2_PPR22_SHIFT (2u) +#define GPIO_PPR2_PPR23_SHIFT (3u) +#define GPIO_PPR2_PPR24_SHIFT (4u) +#define GPIO_PPR2_PPR25_SHIFT (5u) +#define GPIO_PPR2_PPR26_SHIFT (6u) +#define GPIO_PPR2_PPR27_SHIFT (7u) +#define GPIO_PPR2_PPR28_SHIFT (8u) +#define GPIO_PPR2_PPR29_SHIFT (9u) +#define GPIO_PPR2_PPR210_SHIFT (10u) +#define GPIO_PPR2_PPR211_SHIFT (11u) +#define GPIO_PPR2_PPR212_SHIFT (12u) +#define GPIO_PPR2_PPR213_SHIFT (13u) +#define GPIO_PPR2_PPR214_SHIFT (14u) +#define GPIO_PPR2_PPR215_SHIFT (15u) + +#define GPIO_PM2_PM20_SHIFT (0u) +#define GPIO_PM2_PM21_SHIFT (1u) +#define GPIO_PM2_PM22_SHIFT (2u) +#define GPIO_PM2_PM23_SHIFT (3u) +#define GPIO_PM2_PM24_SHIFT (4u) +#define GPIO_PM2_PM25_SHIFT (5u) +#define GPIO_PM2_PM26_SHIFT (6u) +#define GPIO_PM2_PM27_SHIFT (7u) +#define GPIO_PM2_PM28_SHIFT (8u) +#define GPIO_PM2_PM29_SHIFT (9u) +#define GPIO_PM2_PM210_SHIFT (10u) +#define GPIO_PM2_PM211_SHIFT (11u) +#define GPIO_PM2_PM212_SHIFT (12u) +#define GPIO_PM2_PM213_SHIFT (13u) +#define GPIO_PM2_PM214_SHIFT (14u) +#define GPIO_PM2_PM215_SHIFT (15u) + +#define GPIO_PMC2_PMC20_SHIFT (0u) +#define GPIO_PMC2_PMC21_SHIFT (1u) +#define GPIO_PMC2_PMC22_SHIFT (2u) +#define GPIO_PMC2_PMC23_SHIFT (3u) +#define GPIO_PMC2_PMC24_SHIFT (4u) +#define GPIO_PMC2_PMC25_SHIFT (5u) +#define GPIO_PMC2_PMC26_SHIFT (6u) +#define GPIO_PMC2_PMC27_SHIFT (7u) +#define GPIO_PMC2_PMC28_SHIFT (8u) +#define GPIO_PMC2_PMC29_SHIFT (9u) +#define GPIO_PMC2_PMC210_SHIFT (10u) +#define GPIO_PMC2_PMC211_SHIFT (11u) +#define GPIO_PMC2_PMC212_SHIFT (12u) +#define GPIO_PMC2_PMC213_SHIFT (13u) +#define GPIO_PMC2_PMC214_SHIFT (14u) +#define GPIO_PMC2_PMC215_SHIFT (15u) + +#define GPIO_PFC2_PFC20_SHIFT (0u) +#define GPIO_PFC2_PFC21_SHIFT (1u) +#define GPIO_PFC2_PFC22_SHIFT (2u) +#define GPIO_PFC2_PFC23_SHIFT (3u) +#define GPIO_PFC2_PFC24_SHIFT (4u) +#define GPIO_PFC2_PFC25_SHIFT (5u) +#define GPIO_PFC2_PFC26_SHIFT (6u) +#define GPIO_PFC2_PFC27_SHIFT (7u) +#define GPIO_PFC2_PFC28_SHIFT (8u) +#define GPIO_PFC2_PFC29_SHIFT (9u) +#define GPIO_PFC2_PFC210_SHIFT (10u) +#define GPIO_PFC2_PFC211_SHIFT (11u) +#define GPIO_PFC2_PFC212_SHIFT (12u) +#define GPIO_PFC2_PFC213_SHIFT (13u) +#define GPIO_PFC2_PFC214_SHIFT (14u) +#define GPIO_PFC2_PFC215_SHIFT (15u) + +#define GPIO_PFCE2_PFCE20_SHIFT (0u) +#define GPIO_PFCE2_PFCE21_SHIFT (1u) +#define GPIO_PFCE2_PFCE22_SHIFT (2u) +#define GPIO_PFCE2_PFCE23_SHIFT (3u) +#define GPIO_PFCE2_PFCE24_SHIFT (4u) +#define GPIO_PFCE2_PFCE25_SHIFT (5u) +#define GPIO_PFCE2_PFCE26_SHIFT (6u) +#define GPIO_PFCE2_PFCE27_SHIFT (7u) +#define GPIO_PFCE2_PFCE28_SHIFT (8u) +#define GPIO_PFCE2_PFCE29_SHIFT (9u) +#define GPIO_PFCE2_PFCE210_SHIFT (10u) +#define GPIO_PFCE2_PFCE211_SHIFT (11u) +#define GPIO_PFCE2_PFCE212_SHIFT (12u) +#define GPIO_PFCE2_PFCE213_SHIFT (13u) +#define GPIO_PFCE2_PFCE214_SHIFT (14u) +#define GPIO_PFCE2_PFCE215_SHIFT (15u) + +#define GPIO_PNOT2_PNOT20_SHIFT (0u) +#define GPIO_PNOT2_PNOT21_SHIFT (1u) +#define GPIO_PNOT2_PNOT22_SHIFT (2u) +#define GPIO_PNOT2_PNOT23_SHIFT (3u) +#define GPIO_PNOT2_PNOT24_SHIFT (4u) +#define GPIO_PNOT2_PNOT25_SHIFT (5u) +#define GPIO_PNOT2_PNOT26_SHIFT (6u) +#define GPIO_PNOT2_PNOT27_SHIFT (7u) +#define GPIO_PNOT2_PNOT28_SHIFT (8u) +#define GPIO_PNOT2_PNOT29_SHIFT (9u) +#define GPIO_PNOT2_PNOT210_SHIFT (10u) +#define GPIO_PNOT2_PNOT211_SHIFT (11u) +#define GPIO_PNOT2_PNOT212_SHIFT (12u) +#define GPIO_PNOT2_PNOT213_SHIFT (13u) +#define GPIO_PNOT2_PNOT214_SHIFT (14u) +#define GPIO_PNOT2_PNOT215_SHIFT (15u) + +#define GPIO_PMSR2_PMSR20_SHIFT (0u) +#define GPIO_PMSR2_PMSR21_SHIFT (1u) +#define GPIO_PMSR2_PMSR22_SHIFT (2u) +#define GPIO_PMSR2_PMSR23_SHIFT (3u) +#define GPIO_PMSR2_PMSR24_SHIFT (4u) +#define GPIO_PMSR2_PMSR25_SHIFT (5u) +#define GPIO_PMSR2_PMSR26_SHIFT (6u) +#define GPIO_PMSR2_PMSR27_SHIFT (7u) +#define GPIO_PMSR2_PMSR28_SHIFT (8u) +#define GPIO_PMSR2_PMSR29_SHIFT (9u) +#define GPIO_PMSR2_PMSR210_SHIFT (10u) +#define GPIO_PMSR2_PMSR211_SHIFT (11u) +#define GPIO_PMSR2_PMSR212_SHIFT (12u) +#define GPIO_PMSR2_PMSR213_SHIFT (13u) +#define GPIO_PMSR2_PMSR214_SHIFT (14u) +#define GPIO_PMSR2_PMSR215_SHIFT (15u) +#define GPIO_PMSR2_PMSR216_SHIFT (16u) +#define GPIO_PMSR2_PMSR217_SHIFT (17u) +#define GPIO_PMSR2_PMSR218_SHIFT (18u) +#define GPIO_PMSR2_PMSR219_SHIFT (19u) +#define GPIO_PMSR2_PMSR220_SHIFT (20u) +#define GPIO_PMSR2_PMSR221_SHIFT (21u) +#define GPIO_PMSR2_PMSR222_SHIFT (22u) +#define GPIO_PMSR2_PMSR223_SHIFT (23u) +#define GPIO_PMSR2_PMSR224_SHIFT (24u) +#define GPIO_PMSR2_PMSR225_SHIFT (25u) +#define GPIO_PMSR2_PMSR226_SHIFT (26u) +#define GPIO_PMSR2_PMSR227_SHIFT (27u) +#define GPIO_PMSR2_PMSR228_SHIFT (28u) +#define GPIO_PMSR2_PMSR229_SHIFT (29u) +#define GPIO_PMSR2_PMSR230_SHIFT (30u) +#define GPIO_PMSR2_PMSR231_SHIFT (31u) + +#define GPIO_PMCSR2_PMCSR20_SHIFT (0u) +#define GPIO_PMCSR2_PMCSR21_SHIFT (1u) +#define GPIO_PMCSR2_PMCSR22_SHIFT (2u) +#define GPIO_PMCSR2_PMCSR23_SHIFT (3u) +#define GPIO_PMCSR2_PMCSR24_SHIFT (4u) +#define GPIO_PMCSR2_PMCSR25_SHIFT (5u) +#define GPIO_PMCSR2_PMCSR26_SHIFT (6u) +#define GPIO_PMCSR2_PMCSR27_SHIFT (7u) +#define GPIO_PMCSR2_PMCSR28_SHIFT (8u) +#define GPIO_PMCSR2_PMCSR29_SHIFT (9u) +#define GPIO_PMCSR2_PMCSR210_SHIFT (10u) +#define GPIO_PMCSR2_PMCSR211_SHIFT (11u) +#define GPIO_PMCSR2_PMCSR212_SHIFT (12u) +#define GPIO_PMCSR2_PMCSR213_SHIFT (13u) +#define GPIO_PMCSR2_PMCSR214_SHIFT (14u) +#define GPIO_PMCSR2_PMCSR215_SHIFT (15u) +#define GPIO_PMCSR2_PMCSR216_SHIFT (16u) +#define GPIO_PMCSR2_PMCSR217_SHIFT (17u) +#define GPIO_PMCSR2_PMCSR218_SHIFT (18u) +#define GPIO_PMCSR2_PMCSR219_SHIFT (19u) +#define GPIO_PMCSR2_PMCSR220_SHIFT (20u) +#define GPIO_PMCSR2_PMCSR221_SHIFT (21u) +#define GPIO_PMCSR2_PMCSR222_SHIFT (22u) +#define GPIO_PMCSR2_PMCSR223_SHIFT (23u) +#define GPIO_PMCSR2_PMCSR224_SHIFT (24u) +#define GPIO_PMCSR2_PMCSR225_SHIFT (25u) +#define GPIO_PMCSR2_PMCSR226_SHIFT (26u) +#define GPIO_PMCSR2_PMCSR227_SHIFT (27u) +#define GPIO_PMCSR2_PMCSR228_SHIFT (28u) +#define GPIO_PMCSR2_PMCSR229_SHIFT (29u) +#define GPIO_PMCSR2_PMCSR230_SHIFT (30u) +#define GPIO_PMCSR2_PMCSR231_SHIFT (31u) + +#define GPIO_PFCAE2_PFCAE20_SHIFT (0u) +#define GPIO_PFCAE2_PFCAE21_SHIFT (1u) +#define GPIO_PFCAE2_PFCAE22_SHIFT (2u) +#define GPIO_PFCAE2_PFCAE23_SHIFT (3u) +#define GPIO_PFCAE2_PFCAE24_SHIFT (4u) +#define GPIO_PFCAE2_PFCAE25_SHIFT (5u) +#define GPIO_PFCAE2_PFCAE26_SHIFT (6u) +#define GPIO_PFCAE2_PFCAE27_SHIFT (7u) +#define GPIO_PFCAE2_PFCAE28_SHIFT (8u) +#define GPIO_PFCAE2_PFCAE29_SHIFT (9u) +#define GPIO_PFCAE2_PFCAE210_SHIFT (10u) +#define GPIO_PFCAE2_PFCAE211_SHIFT (11u) +#define GPIO_PFCAE2_PFCAE212_SHIFT (12u) +#define GPIO_PFCAE2_PFCAE213_SHIFT (13u) +#define GPIO_PFCAE2_PFCAE214_SHIFT (14u) +#define GPIO_PFCAE2_PFCAE215_SHIFT (15u) + +#define GPIO_PIBC2_PIBC20_SHIFT (0u) +#define GPIO_PIBC2_PIBC21_SHIFT (1u) +#define GPIO_PIBC2_PIBC22_SHIFT (2u) +#define GPIO_PIBC2_PIBC23_SHIFT (3u) +#define GPIO_PIBC2_PIBC24_SHIFT (4u) +#define GPIO_PIBC2_PIBC25_SHIFT (5u) +#define GPIO_PIBC2_PIBC26_SHIFT (6u) +#define GPIO_PIBC2_PIBC27_SHIFT (7u) +#define GPIO_PIBC2_PIBC28_SHIFT (8u) +#define GPIO_PIBC2_PIBC29_SHIFT (9u) +#define GPIO_PIBC2_PIBC210_SHIFT (10u) +#define GPIO_PIBC2_PIBC211_SHIFT (11u) +#define GPIO_PIBC2_PIBC212_SHIFT (12u) +#define GPIO_PIBC2_PIBC213_SHIFT (13u) +#define GPIO_PIBC2_PIBC214_SHIFT (14u) +#define GPIO_PIBC2_PIBC215_SHIFT (15u) + +#define GPIO_PBDC2_PBDC20_SHIFT (0u) +#define GPIO_PBDC2_PBDC21_SHIFT (1u) +#define GPIO_PBDC2_PBDC22_SHIFT (2u) +#define GPIO_PBDC2_PBDC23_SHIFT (3u) +#define GPIO_PBDC2_PBDC24_SHIFT (4u) +#define GPIO_PBDC2_PBDC25_SHIFT (5u) +#define GPIO_PBDC2_PBDC26_SHIFT (6u) +#define GPIO_PBDC2_PBDC27_SHIFT (7u) +#define GPIO_PBDC2_PBDC28_SHIFT (8u) +#define GPIO_PBDC2_PBDC29_SHIFT (9u) +#define GPIO_PBDC2_PBDC210_SHIFT (10u) +#define GPIO_PBDC2_PBDC211_SHIFT (11u) +#define GPIO_PBDC2_PBDC212_SHIFT (12u) +#define GPIO_PBDC2_PBDC213_SHIFT (13u) +#define GPIO_PBDC2_PBDC214_SHIFT (14u) +#define GPIO_PBDC2_PBDC215_SHIFT (15u) + +#define GPIO_PIPC2_PIPC20_SHIFT (0u) +#define GPIO_PIPC2_PIPC21_SHIFT (1u) +#define GPIO_PIPC2_PIPC22_SHIFT (2u) +#define GPIO_PIPC2_PIPC23_SHIFT (3u) +#define GPIO_PIPC2_PIPC24_SHIFT (4u) +#define GPIO_PIPC2_PIPC25_SHIFT (5u) +#define GPIO_PIPC2_PIPC26_SHIFT (6u) +#define GPIO_PIPC2_PIPC27_SHIFT (7u) +#define GPIO_PIPC2_PIPC28_SHIFT (8u) +#define GPIO_PIPC2_PIPC29_SHIFT (9u) +#define GPIO_PIPC2_PIPC210_SHIFT (10u) +#define GPIO_PIPC2_PIPC211_SHIFT (11u) +#define GPIO_PIPC2_PIPC212_SHIFT (12u) +#define GPIO_PIPC2_PIPC213_SHIFT (13u) +#define GPIO_PIPC2_PIPC214_SHIFT (14u) +#define GPIO_PIPC2_PIPC215_SHIFT (15u) + +/* ---- P3 ---- */ +#define GPIO_P3_P30_SHIFT (0u) +#define GPIO_P3_P31_SHIFT (1u) +#define GPIO_P3_P32_SHIFT (2u) +#define GPIO_P3_P33_SHIFT (3u) +#define GPIO_P3_P34_SHIFT (4u) +#define GPIO_P3_P35_SHIFT (5u) +#define GPIO_P3_P36_SHIFT (6u) +#define GPIO_P3_P37_SHIFT (7u) +#define GPIO_P3_P38_SHIFT (8u) +#define GPIO_P3_P39_SHIFT (9u) +#define GPIO_P3_P310_SHIFT (10u) +#define GPIO_P3_P311_SHIFT (11u) +#define GPIO_P3_P312_SHIFT (12u) +#define GPIO_P3_P313_SHIFT (13u) +#define GPIO_P3_P314_SHIFT (14u) +#define GPIO_P3_P315_SHIFT (15u) + +#define GPIO_PSR3_PSR30_SHIFT (0u) +#define GPIO_PSR3_PSR31_SHIFT (1u) +#define GPIO_PSR3_PSR32_SHIFT (2u) +#define GPIO_PSR3_PSR33_SHIFT (3u) +#define GPIO_PSR3_PSR34_SHIFT (4u) +#define GPIO_PSR3_PSR35_SHIFT (5u) +#define GPIO_PSR3_PSR36_SHIFT (6u) +#define GPIO_PSR3_PSR37_SHIFT (7u) +#define GPIO_PSR3_PSR38_SHIFT (8u) +#define GPIO_PSR3_PSR39_SHIFT (9u) +#define GPIO_PSR3_PSR310_SHIFT (10u) +#define GPIO_PSR3_PSR311_SHIFT (11u) +#define GPIO_PSR3_PSR312_SHIFT (12u) +#define GPIO_PSR3_PSR313_SHIFT (13u) +#define GPIO_PSR3_PSR314_SHIFT (14u) +#define GPIO_PSR3_PSR315_SHIFT (15u) +#define GPIO_PSR3_PSR316_SHIFT (16u) +#define GPIO_PSR3_PSR317_SHIFT (17u) +#define GPIO_PSR3_PSR318_SHIFT (18u) +#define GPIO_PSR3_PSR319_SHIFT (19u) +#define GPIO_PSR3_PSR320_SHIFT (20u) +#define GPIO_PSR3_PSR321_SHIFT (21u) +#define GPIO_PSR3_PSR322_SHIFT (22u) +#define GPIO_PSR3_PSR323_SHIFT (23u) +#define GPIO_PSR3_PSR324_SHIFT (24u) +#define GPIO_PSR3_PSR325_SHIFT (25u) +#define GPIO_PSR3_PSR326_SHIFT (26u) +#define GPIO_PSR3_PSR327_SHIFT (27u) +#define GPIO_PSR3_PSR328_SHIFT (28u) +#define GPIO_PSR3_PSR329_SHIFT (29u) +#define GPIO_PSR3_PSR330_SHIFT (30u) +#define GPIO_PSR3_PSR331_SHIFT (31u) + +#define GPIO_PPR3_PPR30_SHIFT (0u) +#define GPIO_PPR3_PPR31_SHIFT (1u) +#define GPIO_PPR3_PPR32_SHIFT (2u) +#define GPIO_PPR3_PPR33_SHIFT (3u) +#define GPIO_PPR3_PPR34_SHIFT (4u) +#define GPIO_PPR3_PPR35_SHIFT (5u) +#define GPIO_PPR3_PPR36_SHIFT (6u) +#define GPIO_PPR3_PPR37_SHIFT (7u) +#define GPIO_PPR3_PPR38_SHIFT (8u) +#define GPIO_PPR3_PPR39_SHIFT (9u) +#define GPIO_PPR3_PPR310_SHIFT (10u) +#define GPIO_PPR3_PPR311_SHIFT (11u) +#define GPIO_PPR3_PPR312_SHIFT (12u) +#define GPIO_PPR3_PPR313_SHIFT (13u) +#define GPIO_PPR3_PPR314_SHIFT (14u) +#define GPIO_PPR3_PPR315_SHIFT (15u) + +#define GPIO_PM3_PM30_SHIFT (0u) +#define GPIO_PM3_PM31_SHIFT (1u) +#define GPIO_PM3_PM32_SHIFT (2u) +#define GPIO_PM3_PM33_SHIFT (3u) +#define GPIO_PM3_PM34_SHIFT (4u) +#define GPIO_PM3_PM35_SHIFT (5u) +#define GPIO_PM3_PM36_SHIFT (6u) +#define GPIO_PM3_PM37_SHIFT (7u) +#define GPIO_PM3_PM38_SHIFT (8u) +#define GPIO_PM3_PM39_SHIFT (9u) +#define GPIO_PM3_PM310_SHIFT (10u) +#define GPIO_PM3_PM311_SHIFT (11u) +#define GPIO_PM3_PM312_SHIFT (12u) +#define GPIO_PM3_PM313_SHIFT (13u) +#define GPIO_PM3_PM314_SHIFT (14u) +#define GPIO_PM3_PM315_SHIFT (15u) + +#define GPIO_PMC3_PMC30_SHIFT (0u) +#define GPIO_PMC3_PMC31_SHIFT (1u) +#define GPIO_PMC3_PMC32_SHIFT (2u) +#define GPIO_PMC3_PMC33_SHIFT (3u) +#define GPIO_PMC3_PMC34_SHIFT (4u) +#define GPIO_PMC3_PMC35_SHIFT (5u) +#define GPIO_PMC3_PMC36_SHIFT (6u) +#define GPIO_PMC3_PMC37_SHIFT (7u) +#define GPIO_PMC3_PMC38_SHIFT (8u) +#define GPIO_PMC3_PMC39_SHIFT (9u) +#define GPIO_PMC3_PMC310_SHIFT (10u) +#define GPIO_PMC3_PMC311_SHIFT (11u) +#define GPIO_PMC3_PMC312_SHIFT (12u) +#define GPIO_PMC3_PMC313_SHIFT (13u) +#define GPIO_PMC3_PMC314_SHIFT (14u) +#define GPIO_PMC3_PMC315_SHIFT (15u) + +#define GPIO_PFC3_PFC30_SHIFT (0u) +#define GPIO_PFC3_PFC31_SHIFT (1u) +#define GPIO_PFC3_PFC32_SHIFT (2u) +#define GPIO_PFC3_PFC33_SHIFT (3u) +#define GPIO_PFC3_PFC34_SHIFT (4u) +#define GPIO_PFC3_PFC35_SHIFT (5u) +#define GPIO_PFC3_PFC36_SHIFT (6u) +#define GPIO_PFC3_PFC37_SHIFT (7u) +#define GPIO_PFC3_PFC38_SHIFT (8u) +#define GPIO_PFC3_PFC39_SHIFT (9u) +#define GPIO_PFC3_PFC310_SHIFT (10u) +#define GPIO_PFC3_PFC311_SHIFT (11u) +#define GPIO_PFC3_PFC312_SHIFT (12u) +#define GPIO_PFC3_PFC313_SHIFT (13u) +#define GPIO_PFC3_PFC314_SHIFT (14u) +#define GPIO_PFC3_PFC315_SHIFT (15u) + +#define GPIO_PFCE3_PFCE30_SHIFT (0u) +#define GPIO_PFCE3_PFCE31_SHIFT (1u) +#define GPIO_PFCE3_PFCE32_SHIFT (2u) +#define GPIO_PFCE3_PFCE33_SHIFT (3u) +#define GPIO_PFCE3_PFCE34_SHIFT (4u) +#define GPIO_PFCE3_PFCE35_SHIFT (5u) +#define GPIO_PFCE3_PFCE36_SHIFT (6u) +#define GPIO_PFCE3_PFCE37_SHIFT (7u) +#define GPIO_PFCE3_PFCE38_SHIFT (8u) +#define GPIO_PFCE3_PFCE39_SHIFT (9u) +#define GPIO_PFCE3_PFCE310_SHIFT (10u) +#define GPIO_PFCE3_PFCE311_SHIFT (11u) +#define GPIO_PFCE3_PFCE312_SHIFT (12u) +#define GPIO_PFCE3_PFCE313_SHIFT (13u) +#define GPIO_PFCE3_PFCE314_SHIFT (14u) +#define GPIO_PFCE3_PFCE315_SHIFT (15u) + +#define GPIO_PNOT3_PNOT30_SHIFT (0u) +#define GPIO_PNOT3_PNOT31_SHIFT (1u) +#define GPIO_PNOT3_PNOT32_SHIFT (2u) +#define GPIO_PNOT3_PNOT33_SHIFT (3u) +#define GPIO_PNOT3_PNOT34_SHIFT (4u) +#define GPIO_PNOT3_PNOT35_SHIFT (5u) +#define GPIO_PNOT3_PNOT36_SHIFT (6u) +#define GPIO_PNOT3_PNOT37_SHIFT (7u) +#define GPIO_PNOT3_PNOT38_SHIFT (8u) +#define GPIO_PNOT3_PNOT39_SHIFT (9u) +#define GPIO_PNOT3_PNOT310_SHIFT (10u) +#define GPIO_PNOT3_PNOT311_SHIFT (11u) +#define GPIO_PNOT3_PNOT312_SHIFT (12u) +#define GPIO_PNOT3_PNOT313_SHIFT (13u) +#define GPIO_PNOT3_PNOT314_SHIFT (14u) +#define GPIO_PNOT3_PNOT315_SHIFT (15u) + +#define GPIO_PMSR3_PMSR30_SHIFT (0u) +#define GPIO_PMSR3_PMSR31_SHIFT (1u) +#define GPIO_PMSR3_PMSR32_SHIFT (2u) +#define GPIO_PMSR3_PMSR33_SHIFT (3u) +#define GPIO_PMSR3_PMSR34_SHIFT (4u) +#define GPIO_PMSR3_PMSR35_SHIFT (5u) +#define GPIO_PMSR3_PMSR36_SHIFT (6u) +#define GPIO_PMSR3_PMSR37_SHIFT (7u) +#define GPIO_PMSR3_PMSR38_SHIFT (8u) +#define GPIO_PMSR3_PMSR39_SHIFT (9u) +#define GPIO_PMSR3_PMSR310_SHIFT (10u) +#define GPIO_PMSR3_PMSR311_SHIFT (11u) +#define GPIO_PMSR3_PMSR312_SHIFT (12u) +#define GPIO_PMSR3_PMSR313_SHIFT (13u) +#define GPIO_PMSR3_PMSR314_SHIFT (14u) +#define GPIO_PMSR3_PMSR315_SHIFT (15u) +#define GPIO_PMSR3_PMSR316_SHIFT (16u) +#define GPIO_PMSR3_PMSR317_SHIFT (17u) +#define GPIO_PMSR3_PMSR318_SHIFT (18u) +#define GPIO_PMSR3_PMSR319_SHIFT (19u) +#define GPIO_PMSR3_PMSR320_SHIFT (20u) +#define GPIO_PMSR3_PMSR321_SHIFT (21u) +#define GPIO_PMSR3_PMSR322_SHIFT (22u) +#define GPIO_PMSR3_PMSR323_SHIFT (23u) +#define GPIO_PMSR3_PMSR324_SHIFT (24u) +#define GPIO_PMSR3_PMSR325_SHIFT (25u) +#define GPIO_PMSR3_PMSR326_SHIFT (26u) +#define GPIO_PMSR3_PMSR327_SHIFT (27u) +#define GPIO_PMSR3_PMSR328_SHIFT (28u) +#define GPIO_PMSR3_PMSR329_SHIFT (29u) +#define GPIO_PMSR3_PMSR330_SHIFT (30u) +#define GPIO_PMSR3_PMSR331_SHIFT (31u) + +#define GPIO_PMCSR3_PMCSR30_SHIFT (0u) +#define GPIO_PMCSR3_PMCSR31_SHIFT (1u) +#define GPIO_PMCSR3_PMCSR32_SHIFT (2u) +#define GPIO_PMCSR3_PMCSR33_SHIFT (3u) +#define GPIO_PMCSR3_PMCSR34_SHIFT (4u) +#define GPIO_PMCSR3_PMCSR35_SHIFT (5u) +#define GPIO_PMCSR3_PMCSR36_SHIFT (6u) +#define GPIO_PMCSR3_PMCSR37_SHIFT (7u) +#define GPIO_PMCSR3_PMCSR38_SHIFT (8u) +#define GPIO_PMCSR3_PMCSR39_SHIFT (9u) +#define GPIO_PMCSR3_PMCSR310_SHIFT (10u) +#define GPIO_PMCSR3_PMCSR311_SHIFT (11u) +#define GPIO_PMCSR3_PMCSR312_SHIFT (12u) +#define GPIO_PMCSR3_PMCSR313_SHIFT (13u) +#define GPIO_PMCSR3_PMCSR314_SHIFT (14u) +#define GPIO_PMCSR3_PMCSR315_SHIFT (15u) +#define GPIO_PMCSR3_PMCSR316_SHIFT (16u) +#define GPIO_PMCSR3_PMCSR317_SHIFT (17u) +#define GPIO_PMCSR3_PMCSR318_SHIFT (18u) +#define GPIO_PMCSR3_PMCSR319_SHIFT (19u) +#define GPIO_PMCSR3_PMCSR320_SHIFT (20u) +#define GPIO_PMCSR3_PMCSR321_SHIFT (21u) +#define GPIO_PMCSR3_PMCSR322_SHIFT (22u) +#define GPIO_PMCSR3_PMCSR323_SHIFT (23u) +#define GPIO_PMCSR3_PMCSR324_SHIFT (24u) +#define GPIO_PMCSR3_PMCSR325_SHIFT (25u) +#define GPIO_PMCSR3_PMCSR326_SHIFT (26u) +#define GPIO_PMCSR3_PMCSR327_SHIFT (27u) +#define GPIO_PMCSR3_PMCSR328_SHIFT (28u) +#define GPIO_PMCSR3_PMCSR329_SHIFT (29u) +#define GPIO_PMCSR3_PMCSR330_SHIFT (30u) +#define GPIO_PMCSR3_PMCSR331_SHIFT (31u) + +#define GPIO_PFCAE3_PFCAE30_SHIFT (0u) +#define GPIO_PFCAE3_PFCAE31_SHIFT (1u) +#define GPIO_PFCAE3_PFCAE32_SHIFT (2u) +#define GPIO_PFCAE3_PFCAE33_SHIFT (3u) +#define GPIO_PFCAE3_PFCAE34_SHIFT (4u) +#define GPIO_PFCAE3_PFCAE35_SHIFT (5u) +#define GPIO_PFCAE3_PFCAE36_SHIFT (6u) +#define GPIO_PFCAE3_PFCAE37_SHIFT (7u) +#define GPIO_PFCAE3_PFCAE38_SHIFT (8u) +#define GPIO_PFCAE3_PFCAE39_SHIFT (9u) +#define GPIO_PFCAE3_PFCAE310_SHIFT (10u) +#define GPIO_PFCAE3_PFCAE311_SHIFT (11u) +#define GPIO_PFCAE3_PFCAE312_SHIFT (12u) +#define GPIO_PFCAE3_PFCAE313_SHIFT (13u) +#define GPIO_PFCAE3_PFCAE314_SHIFT (14u) +#define GPIO_PFCAE3_PFCAE315_SHIFT (15u) + +#define GPIO_PIBC3_PIBC30_SHIFT (0u) +#define GPIO_PIBC3_PIBC31_SHIFT (1u) +#define GPIO_PIBC3_PIBC32_SHIFT (2u) +#define GPIO_PIBC3_PIBC33_SHIFT (3u) +#define GPIO_PIBC3_PIBC34_SHIFT (4u) +#define GPIO_PIBC3_PIBC35_SHIFT (5u) +#define GPIO_PIBC3_PIBC36_SHIFT (6u) +#define GPIO_PIBC3_PIBC37_SHIFT (7u) +#define GPIO_PIBC3_PIBC38_SHIFT (8u) +#define GPIO_PIBC3_PIBC39_SHIFT (9u) +#define GPIO_PIBC3_PIBC310_SHIFT (10u) +#define GPIO_PIBC3_PIBC311_SHIFT (11u) +#define GPIO_PIBC3_PIBC312_SHIFT (12u) +#define GPIO_PIBC3_PIBC313_SHIFT (13u) +#define GPIO_PIBC3_PIBC314_SHIFT (14u) +#define GPIO_PIBC3_PIBC315_SHIFT (15u) + +#define GPIO_PBDC3_PBDC30_SHIFT (0u) +#define GPIO_PBDC3_PBDC31_SHIFT (1u) +#define GPIO_PBDC3_PBDC32_SHIFT (2u) +#define GPIO_PBDC3_PBDC33_SHIFT (3u) +#define GPIO_PBDC3_PBDC34_SHIFT (4u) +#define GPIO_PBDC3_PBDC35_SHIFT (5u) +#define GPIO_PBDC3_PBDC36_SHIFT (6u) +#define GPIO_PBDC3_PBDC37_SHIFT (7u) +#define GPIO_PBDC3_PBDC38_SHIFT (8u) +#define GPIO_PBDC3_PBDC39_SHIFT (9u) +#define GPIO_PBDC3_PBDC310_SHIFT (10u) +#define GPIO_PBDC3_PBDC311_SHIFT (11u) +#define GPIO_PBDC3_PBDC312_SHIFT (12u) +#define GPIO_PBDC3_PBDC313_SHIFT (13u) +#define GPIO_PBDC3_PBDC314_SHIFT (14u) +#define GPIO_PBDC3_PBDC315_SHIFT (15u) + +#define GPIO_PIPC3_PIPC30_SHIFT (0u) +#define GPIO_PIPC3_PIPC31_SHIFT (1u) +#define GPIO_PIPC3_PIPC32_SHIFT (2u) +#define GPIO_PIPC3_PIPC33_SHIFT (3u) +#define GPIO_PIPC3_PIPC34_SHIFT (4u) +#define GPIO_PIPC3_PIPC35_SHIFT (5u) +#define GPIO_PIPC3_PIPC36_SHIFT (6u) +#define GPIO_PIPC3_PIPC37_SHIFT (7u) +#define GPIO_PIPC3_PIPC38_SHIFT (8u) +#define GPIO_PIPC3_PIPC39_SHIFT (9u) +#define GPIO_PIPC3_PIPC310_SHIFT (10u) +#define GPIO_PIPC3_PIPC311_SHIFT (11u) +#define GPIO_PIPC3_PIPC312_SHIFT (12u) +#define GPIO_PIPC3_PIPC313_SHIFT (13u) +#define GPIO_PIPC3_PIPC314_SHIFT (14u) +#define GPIO_PIPC3_PIPC315_SHIFT (15u) + +/* ---- P4 ---- */ +#define GPIO_P4_P40_SHIFT (0u) +#define GPIO_P4_P41_SHIFT (1u) +#define GPIO_P4_P42_SHIFT (2u) +#define GPIO_P4_P43_SHIFT (3u) +#define GPIO_P4_P44_SHIFT (4u) +#define GPIO_P4_P45_SHIFT (5u) +#define GPIO_P4_P46_SHIFT (6u) +#define GPIO_P4_P47_SHIFT (7u) +#define GPIO_P4_P48_SHIFT (8u) +#define GPIO_P4_P49_SHIFT (9u) +#define GPIO_P4_P410_SHIFT (10u) +#define GPIO_P4_P411_SHIFT (11u) +#define GPIO_P4_P412_SHIFT (12u) +#define GPIO_P4_P413_SHIFT (13u) +#define GPIO_P4_P414_SHIFT (14u) +#define GPIO_P4_P415_SHIFT (15u) + +#define GPIO_PSR4_PSR40_SHIFT (0u) +#define GPIO_PSR4_PSR41_SHIFT (1u) +#define GPIO_PSR4_PSR42_SHIFT (2u) +#define GPIO_PSR4_PSR43_SHIFT (3u) +#define GPIO_PSR4_PSR44_SHIFT (4u) +#define GPIO_PSR4_PSR45_SHIFT (5u) +#define GPIO_PSR4_PSR46_SHIFT (6u) +#define GPIO_PSR4_PSR47_SHIFT (7u) +#define GPIO_PSR4_PSR48_SHIFT (8u) +#define GPIO_PSR4_PSR49_SHIFT (9u) +#define GPIO_PSR4_PSR410_SHIFT (10u) +#define GPIO_PSR4_PSR411_SHIFT (11u) +#define GPIO_PSR4_PSR412_SHIFT (12u) +#define GPIO_PSR4_PSR413_SHIFT (13u) +#define GPIO_PSR4_PSR414_SHIFT (14u) +#define GPIO_PSR4_PSR415_SHIFT (15u) +#define GPIO_PSR4_PSR416_SHIFT (16u) +#define GPIO_PSR4_PSR417_SHIFT (17u) +#define GPIO_PSR4_PSR418_SHIFT (18u) +#define GPIO_PSR4_PSR419_SHIFT (19u) +#define GPIO_PSR4_PSR420_SHIFT (20u) +#define GPIO_PSR4_PSR421_SHIFT (21u) +#define GPIO_PSR4_PSR422_SHIFT (22u) +#define GPIO_PSR4_PSR423_SHIFT (23u) +#define GPIO_PSR4_PSR424_SHIFT (24u) +#define GPIO_PSR4_PSR425_SHIFT (25u) +#define GPIO_PSR4_PSR426_SHIFT (26u) +#define GPIO_PSR4_PSR427_SHIFT (27u) +#define GPIO_PSR4_PSR428_SHIFT (28u) +#define GPIO_PSR4_PSR429_SHIFT (29u) +#define GPIO_PSR4_PSR430_SHIFT (30u) +#define GPIO_PSR4_PSR431_SHIFT (31u) + +#define GPIO_PPR4_PPR40_SHIFT (0u) +#define GPIO_PPR4_PPR41_SHIFT (1u) +#define GPIO_PPR4_PPR42_SHIFT (2u) +#define GPIO_PPR4_PPR43_SHIFT (3u) +#define GPIO_PPR4_PPR44_SHIFT (4u) +#define GPIO_PPR4_PPR45_SHIFT (5u) +#define GPIO_PPR4_PPR46_SHIFT (6u) +#define GPIO_PPR4_PPR47_SHIFT (7u) +#define GPIO_PPR4_PPR48_SHIFT (8u) +#define GPIO_PPR4_PPR49_SHIFT (9u) +#define GPIO_PPR4_PPR410_SHIFT (10u) +#define GPIO_PPR4_PPR411_SHIFT (11u) +#define GPIO_PPR4_PPR412_SHIFT (12u) +#define GPIO_PPR4_PPR413_SHIFT (13u) +#define GPIO_PPR4_PPR414_SHIFT (14u) +#define GPIO_PPR4_PPR415_SHIFT (15u) + +#define GPIO_PM4_PM40_SHIFT (0u) +#define GPIO_PM4_PM41_SHIFT (1u) +#define GPIO_PM4_PM42_SHIFT (2u) +#define GPIO_PM4_PM43_SHIFT (3u) +#define GPIO_PM4_PM44_SHIFT (4u) +#define GPIO_PM4_PM45_SHIFT (5u) +#define GPIO_PM4_PM46_SHIFT (6u) +#define GPIO_PM4_PM47_SHIFT (7u) +#define GPIO_PM4_PM48_SHIFT (8u) +#define GPIO_PM4_PM49_SHIFT (9u) +#define GPIO_PM4_PM410_SHIFT (10u) +#define GPIO_PM4_PM411_SHIFT (11u) +#define GPIO_PM4_PM412_SHIFT (12u) +#define GPIO_PM4_PM413_SHIFT (13u) +#define GPIO_PM4_PM414_SHIFT (14u) +#define GPIO_PM4_PM415_SHIFT (15u) + +#define GPIO_PMC4_PMC40_SHIFT (0u) +#define GPIO_PMC4_PMC41_SHIFT (1u) +#define GPIO_PMC4_PMC42_SHIFT (2u) +#define GPIO_PMC4_PMC43_SHIFT (3u) +#define GPIO_PMC4_PMC44_SHIFT (4u) +#define GPIO_PMC4_PMC45_SHIFT (5u) +#define GPIO_PMC4_PMC46_SHIFT (6u) +#define GPIO_PMC4_PMC47_SHIFT (7u) +#define GPIO_PMC4_PMC48_SHIFT (8u) +#define GPIO_PMC4_PMC49_SHIFT (9u) +#define GPIO_PMC4_PMC410_SHIFT (10u) +#define GPIO_PMC4_PMC411_SHIFT (11u) +#define GPIO_PMC4_PMC412_SHIFT (12u) +#define GPIO_PMC4_PMC413_SHIFT (13u) +#define GPIO_PMC4_PMC414_SHIFT (14u) +#define GPIO_PMC4_PMC415_SHIFT (15u) + +#define GPIO_PFC4_PFC40_SHIFT (0u) +#define GPIO_PFC4_PFC41_SHIFT (1u) +#define GPIO_PFC4_PFC42_SHIFT (2u) +#define GPIO_PFC4_PFC43_SHIFT (3u) +#define GPIO_PFC4_PFC44_SHIFT (4u) +#define GPIO_PFC4_PFC45_SHIFT (5u) +#define GPIO_PFC4_PFC46_SHIFT (6u) +#define GPIO_PFC4_PFC47_SHIFT (7u) +#define GPIO_PFC4_PFC48_SHIFT (8u) +#define GPIO_PFC4_PFC49_SHIFT (9u) +#define GPIO_PFC4_PFC410_SHIFT (10u) +#define GPIO_PFC4_PFC411_SHIFT (11u) +#define GPIO_PFC4_PFC412_SHIFT (12u) +#define GPIO_PFC4_PFC413_SHIFT (13u) +#define GPIO_PFC4_PFC414_SHIFT (14u) +#define GPIO_PFC4_PFC415_SHIFT (15u) + +#define GPIO_PFCE4_PFCE40_SHIFT (0u) +#define GPIO_PFCE4_PFCE41_SHIFT (1u) +#define GPIO_PFCE4_PFCE42_SHIFT (2u) +#define GPIO_PFCE4_PFCE43_SHIFT (3u) +#define GPIO_PFCE4_PFCE44_SHIFT (4u) +#define GPIO_PFCE4_PFCE45_SHIFT (5u) +#define GPIO_PFCE4_PFCE46_SHIFT (6u) +#define GPIO_PFCE4_PFCE47_SHIFT (7u) +#define GPIO_PFCE4_PFCE48_SHIFT (8u) +#define GPIO_PFCE4_PFCE49_SHIFT (9u) +#define GPIO_PFCE4_PFCE410_SHIFT (10u) +#define GPIO_PFCE4_PFCE411_SHIFT (11u) +#define GPIO_PFCE4_PFCE412_SHIFT (12u) +#define GPIO_PFCE4_PFCE413_SHIFT (13u) +#define GPIO_PFCE4_PFCE414_SHIFT (14u) +#define GPIO_PFCE4_PFCE415_SHIFT (15u) + +#define GPIO_PNOT4_PNOT40_SHIFT (0u) +#define GPIO_PNOT4_PNOT41_SHIFT (1u) +#define GPIO_PNOT4_PNOT42_SHIFT (2u) +#define GPIO_PNOT4_PNOT43_SHIFT (3u) +#define GPIO_PNOT4_PNOT44_SHIFT (4u) +#define GPIO_PNOT4_PNOT45_SHIFT (5u) +#define GPIO_PNOT4_PNOT46_SHIFT (6u) +#define GPIO_PNOT4_PNOT47_SHIFT (7u) +#define GPIO_PNOT4_PNOT48_SHIFT (8u) +#define GPIO_PNOT4_PNOT49_SHIFT (9u) +#define GPIO_PNOT4_PNOT410_SHIFT (10u) +#define GPIO_PNOT4_PNOT411_SHIFT (11u) +#define GPIO_PNOT4_PNOT412_SHIFT (12u) +#define GPIO_PNOT4_PNOT413_SHIFT (13u) +#define GPIO_PNOT4_PNOT414_SHIFT (14u) +#define GPIO_PNOT4_PNOT415_SHIFT (15u) + +#define GPIO_PMSR4_PMSR40_SHIFT (0u) +#define GPIO_PMSR4_PMSR41_SHIFT (1u) +#define GPIO_PMSR4_PMSR42_SHIFT (2u) +#define GPIO_PMSR4_PMSR43_SHIFT (3u) +#define GPIO_PMSR4_PMSR44_SHIFT (4u) +#define GPIO_PMSR4_PMSR45_SHIFT (5u) +#define GPIO_PMSR4_PMSR46_SHIFT (6u) +#define GPIO_PMSR4_PMSR47_SHIFT (7u) +#define GPIO_PMSR4_PMSR48_SHIFT (8u) +#define GPIO_PMSR4_PMSR49_SHIFT (9u) +#define GPIO_PMSR4_PMSR410_SHIFT (10u) +#define GPIO_PMSR4_PMSR411_SHIFT (11u) +#define GPIO_PMSR4_PMSR412_SHIFT (12u) +#define GPIO_PMSR4_PMSR413_SHIFT (13u) +#define GPIO_PMSR4_PMSR414_SHIFT (14u) +#define GPIO_PMSR4_PMSR415_SHIFT (15u) +#define GPIO_PMSR4_PMSR416_SHIFT (16u) +#define GPIO_PMSR4_PMSR417_SHIFT (17u) +#define GPIO_PMSR4_PMSR418_SHIFT (18u) +#define GPIO_PMSR4_PMSR419_SHIFT (19u) +#define GPIO_PMSR4_PMSR420_SHIFT (20u) +#define GPIO_PMSR4_PMSR421_SHIFT (21u) +#define GPIO_PMSR4_PMSR422_SHIFT (22u) +#define GPIO_PMSR4_PMSR423_SHIFT (23u) +#define GPIO_PMSR4_PMSR424_SHIFT (24u) +#define GPIO_PMSR4_PMSR425_SHIFT (25u) +#define GPIO_PMSR4_PMSR426_SHIFT (26u) +#define GPIO_PMSR4_PMSR427_SHIFT (27u) +#define GPIO_PMSR4_PMSR428_SHIFT (28u) +#define GPIO_PMSR4_PMSR429_SHIFT (29u) +#define GPIO_PMSR4_PMSR430_SHIFT (30u) +#define GPIO_PMSR4_PMSR431_SHIFT (31u) + +#define GPIO_PMCSR4_PMCSR40_SHIFT (0u) +#define GPIO_PMCSR4_PMCSR41_SHIFT (1u) +#define GPIO_PMCSR4_PMCSR42_SHIFT (2u) +#define GPIO_PMCSR4_PMCSR43_SHIFT (3u) +#define GPIO_PMCSR4_PMCSR44_SHIFT (4u) +#define GPIO_PMCSR4_PMCSR45_SHIFT (5u) +#define GPIO_PMCSR4_PMCSR46_SHIFT (6u) +#define GPIO_PMCSR4_PMCSR47_SHIFT (7u) +#define GPIO_PMCSR4_PMCSR48_SHIFT (8u) +#define GPIO_PMCSR4_PMCSR49_SHIFT (9u) +#define GPIO_PMCSR4_PMCSR410_SHIFT (10u) +#define GPIO_PMCSR4_PMCSR411_SHIFT (11u) +#define GPIO_PMCSR4_PMCSR412_SHIFT (12u) +#define GPIO_PMCSR4_PMCSR413_SHIFT (13u) +#define GPIO_PMCSR4_PMCSR414_SHIFT (14u) +#define GPIO_PMCSR4_PMCSR415_SHIFT (15u) +#define GPIO_PMCSR4_PMCSR416_SHIFT (16u) +#define GPIO_PMCSR4_PMCSR417_SHIFT (17u) +#define GPIO_PMCSR4_PMCSR418_SHIFT (18u) +#define GPIO_PMCSR4_PMCSR419_SHIFT (19u) +#define GPIO_PMCSR4_PMCSR420_SHIFT (20u) +#define GPIO_PMCSR4_PMCSR421_SHIFT (21u) +#define GPIO_PMCSR4_PMCSR422_SHIFT (22u) +#define GPIO_PMCSR4_PMCSR423_SHIFT (23u) +#define GPIO_PMCSR4_PMCSR424_SHIFT (24u) +#define GPIO_PMCSR4_PMCSR425_SHIFT (25u) +#define GPIO_PMCSR4_PMCSR426_SHIFT (26u) +#define GPIO_PMCSR4_PMCSR427_SHIFT (27u) +#define GPIO_PMCSR4_PMCSR428_SHIFT (28u) +#define GPIO_PMCSR4_PMCSR429_SHIFT (29u) +#define GPIO_PMCSR4_PMCSR430_SHIFT (30u) +#define GPIO_PMCSR4_PMCSR431_SHIFT (31u) + +#define GPIO_PFCAE4_PFCAE40_SHIFT (0u) +#define GPIO_PFCAE4_PFCAE41_SHIFT (1u) +#define GPIO_PFCAE4_PFCAE42_SHIFT (2u) +#define GPIO_PFCAE4_PFCAE43_SHIFT (3u) +#define GPIO_PFCAE4_PFCAE44_SHIFT (4u) +#define GPIO_PFCAE4_PFCAE45_SHIFT (5u) +#define GPIO_PFCAE4_PFCAE46_SHIFT (6u) +#define GPIO_PFCAE4_PFCAE47_SHIFT (7u) +#define GPIO_PFCAE4_PFCAE48_SHIFT (8u) +#define GPIO_PFCAE4_PFCAE49_SHIFT (9u) +#define GPIO_PFCAE4_PFCAE410_SHIFT (10u) +#define GPIO_PFCAE4_PFCAE411_SHIFT (11u) +#define GPIO_PFCAE4_PFCAE412_SHIFT (12u) +#define GPIO_PFCAE4_PFCAE413_SHIFT (13u) +#define GPIO_PFCAE4_PFCAE414_SHIFT (14u) +#define GPIO_PFCAE4_PFCAE415_SHIFT (15u) + +#define GPIO_PIBC4_PIBC40_SHIFT (0u) +#define GPIO_PIBC4_PIBC41_SHIFT (1u) +#define GPIO_PIBC4_PIBC42_SHIFT (2u) +#define GPIO_PIBC4_PIBC43_SHIFT (3u) +#define GPIO_PIBC4_PIBC44_SHIFT (4u) +#define GPIO_PIBC4_PIBC45_SHIFT (5u) +#define GPIO_PIBC4_PIBC46_SHIFT (6u) +#define GPIO_PIBC4_PIBC47_SHIFT (7u) +#define GPIO_PIBC4_PIBC48_SHIFT (8u) +#define GPIO_PIBC4_PIBC49_SHIFT (9u) +#define GPIO_PIBC4_PIBC410_SHIFT (10u) +#define GPIO_PIBC4_PIBC411_SHIFT (11u) +#define GPIO_PIBC4_PIBC412_SHIFT (12u) +#define GPIO_PIBC4_PIBC413_SHIFT (13u) +#define GPIO_PIBC4_PIBC414_SHIFT (14u) +#define GPIO_PIBC4_PIBC415_SHIFT (15u) + +#define GPIO_PBDC4_PBDC40_SHIFT (0u) +#define GPIO_PBDC4_PBDC41_SHIFT (1u) +#define GPIO_PBDC4_PBDC42_SHIFT (2u) +#define GPIO_PBDC4_PBDC43_SHIFT (3u) +#define GPIO_PBDC4_PBDC44_SHIFT (4u) +#define GPIO_PBDC4_PBDC45_SHIFT (5u) +#define GPIO_PBDC4_PBDC46_SHIFT (6u) +#define GPIO_PBDC4_PBDC47_SHIFT (7u) +#define GPIO_PBDC4_PBDC48_SHIFT (8u) +#define GPIO_PBDC4_PBDC49_SHIFT (9u) +#define GPIO_PBDC4_PBDC410_SHIFT (10u) +#define GPIO_PBDC4_PBDC411_SHIFT (11u) +#define GPIO_PBDC4_PBDC412_SHIFT (12u) +#define GPIO_PBDC4_PBDC413_SHIFT (13u) +#define GPIO_PBDC4_PBDC414_SHIFT (14u) +#define GPIO_PBDC4_PBDC415_SHIFT (15u) + +#define GPIO_PIPC4_PIPC40_SHIFT (0u) +#define GPIO_PIPC4_PIPC41_SHIFT (1u) +#define GPIO_PIPC4_PIPC42_SHIFT (2u) +#define GPIO_PIPC4_PIPC43_SHIFT (3u) +#define GPIO_PIPC4_PIPC44_SHIFT (4u) +#define GPIO_PIPC4_PIPC45_SHIFT (5u) +#define GPIO_PIPC4_PIPC46_SHIFT (6u) +#define GPIO_PIPC4_PIPC47_SHIFT (7u) +#define GPIO_PIPC4_PIPC48_SHIFT (8u) +#define GPIO_PIPC4_PIPC49_SHIFT (9u) +#define GPIO_PIPC4_PIPC410_SHIFT (10u) +#define GPIO_PIPC4_PIPC411_SHIFT (11u) +#define GPIO_PIPC4_PIPC412_SHIFT (12u) +#define GPIO_PIPC4_PIPC413_SHIFT (13u) +#define GPIO_PIPC4_PIPC414_SHIFT (14u) +#define GPIO_PIPC4_PIPC415_SHIFT (15u) + +/* ---- P5 ---- */ +#define GPIO_P5_P50_SHIFT (0u) +#define GPIO_P5_P51_SHIFT (1u) +#define GPIO_P5_P52_SHIFT (2u) +#define GPIO_P5_P53_SHIFT (3u) +#define GPIO_P5_P54_SHIFT (4u) +#define GPIO_P5_P55_SHIFT (5u) +#define GPIO_P5_P56_SHIFT (6u) +#define GPIO_P5_P57_SHIFT (7u) +#define GPIO_P5_P58_SHIFT (8u) +#define GPIO_P5_P59_SHIFT (9u) +#define GPIO_P5_P510_SHIFT (10u) + +#define GPIO_PSR5_PSR50_SHIFT (0u) +#define GPIO_PSR5_PSR51_SHIFT (1u) +#define GPIO_PSR5_PSR52_SHIFT (2u) +#define GPIO_PSR5_PSR53_SHIFT (3u) +#define GPIO_PSR5_PSR54_SHIFT (4u) +#define GPIO_PSR5_PSR55_SHIFT (5u) +#define GPIO_PSR5_PSR56_SHIFT (6u) +#define GPIO_PSR5_PSR57_SHIFT (7u) +#define GPIO_PSR5_PSR58_SHIFT (8u) +#define GPIO_PSR5_PSR59_SHIFT (9u) +#define GPIO_PSR5_PSR510_SHIFT (10u) +#define GPIO_PSR5_PSR516_SHIFT (16u) +#define GPIO_PSR5_PSR517_SHIFT (17u) +#define GPIO_PSR5_PSR518_SHIFT (18u) +#define GPIO_PSR5_PSR519_SHIFT (19u) +#define GPIO_PSR5_PSR520_SHIFT (20u) +#define GPIO_PSR5_PSR521_SHIFT (21u) +#define GPIO_PSR5_PSR522_SHIFT (22u) +#define GPIO_PSR5_PSR523_SHIFT (23u) +#define GPIO_PSR5_PSR524_SHIFT (24u) +#define GPIO_PSR5_PSR525_SHIFT (25u) +#define GPIO_PSR5_PSR526_SHIFT (26u) + +#define GPIO_PPR5_PPR50_SHIFT (0u) +#define GPIO_PPR5_PPR51_SHIFT (1u) +#define GPIO_PPR5_PPR52_SHIFT (2u) +#define GPIO_PPR5_PPR53_SHIFT (3u) +#define GPIO_PPR5_PPR54_SHIFT (4u) +#define GPIO_PPR5_PPR55_SHIFT (5u) +#define GPIO_PPR5_PPR56_SHIFT (6u) +#define GPIO_PPR5_PPR57_SHIFT (7u) +#define GPIO_PPR5_PPR58_SHIFT (8u) +#define GPIO_PPR5_PPR59_SHIFT (9u) +#define GPIO_PPR5_PPR510_SHIFT (10u) + +#define GPIO_PM5_PM50_SHIFT (0u) +#define GPIO_PM5_PM51_SHIFT (1u) +#define GPIO_PM5_PM52_SHIFT (2u) +#define GPIO_PM5_PM53_SHIFT (3u) +#define GPIO_PM5_PM54_SHIFT (4u) +#define GPIO_PM5_PM55_SHIFT (5u) +#define GPIO_PM5_PM56_SHIFT (6u) +#define GPIO_PM5_PM57_SHIFT (7u) +#define GPIO_PM5_PM58_SHIFT (8u) +#define GPIO_PM5_PM59_SHIFT (9u) +#define GPIO_PM5_PM510_SHIFT (10u) + +#define GPIO_PMC5_PMC50_SHIFT (0u) +#define GPIO_PMC5_PMC51_SHIFT (1u) +#define GPIO_PMC5_PMC52_SHIFT (2u) +#define GPIO_PMC5_PMC53_SHIFT (3u) +#define GPIO_PMC5_PMC54_SHIFT (4u) +#define GPIO_PMC5_PMC55_SHIFT (5u) +#define GPIO_PMC5_PMC56_SHIFT (6u) +#define GPIO_PMC5_PMC57_SHIFT (7u) +#define GPIO_PMC5_PMC58_SHIFT (8u) +#define GPIO_PMC5_PMC59_SHIFT (9u) +#define GPIO_PMC5_PMC510_SHIFT (10u) + +#define GPIO_PFC5_PFC50_SHIFT (0u) +#define GPIO_PFC5_PFC51_SHIFT (1u) +#define GPIO_PFC5_PFC52_SHIFT (2u) +#define GPIO_PFC5_PFC53_SHIFT (3u) +#define GPIO_PFC5_PFC54_SHIFT (4u) +#define GPIO_PFC5_PFC55_SHIFT (5u) +#define GPIO_PFC5_PFC56_SHIFT (6u) +#define GPIO_PFC5_PFC57_SHIFT (7u) +#define GPIO_PFC5_PFC58_SHIFT (8u) +#define GPIO_PFC5_PFC59_SHIFT (9u) +#define GPIO_PFC5_PFC510_SHIFT (10u) + +#define GPIO_PFCE5_PFCE50_SHIFT (0u) +#define GPIO_PFCE5_PFCE51_SHIFT (1u) +#define GPIO_PFCE5_PFCE52_SHIFT (2u) +#define GPIO_PFCE5_PFCE53_SHIFT (3u) +#define GPIO_PFCE5_PFCE54_SHIFT (4u) +#define GPIO_PFCE5_PFCE55_SHIFT (5u) +#define GPIO_PFCE5_PFCE56_SHIFT (6u) +#define GPIO_PFCE5_PFCE57_SHIFT (7u) +#define GPIO_PFCE5_PFCE58_SHIFT (8u) +#define GPIO_PFCE5_PFCE59_SHIFT (9u) +#define GPIO_PFCE5_PFCE510_SHIFT (10u) + +#define GPIO_PNOT5_PNOT50_SHIFT (0u) +#define GPIO_PNOT5_PNOT51_SHIFT (1u) +#define GPIO_PNOT5_PNOT52_SHIFT (2u) +#define GPIO_PNOT5_PNOT53_SHIFT (3u) +#define GPIO_PNOT5_PNOT54_SHIFT (4u) +#define GPIO_PNOT5_PNOT55_SHIFT (5u) +#define GPIO_PNOT5_PNOT56_SHIFT (6u) +#define GPIO_PNOT5_PNOT57_SHIFT (7u) +#define GPIO_PNOT5_PNOT58_SHIFT (8u) +#define GPIO_PNOT5_PNOT59_SHIFT (9u) +#define GPIO_PNOT5_PNOT510_SHIFT (10u) + +#define GPIO_PMSR5_PMSR50_SHIFT (0u) +#define GPIO_PMSR5_PMSR51_SHIFT (1u) +#define GPIO_PMSR5_PMSR52_SHIFT (2u) +#define GPIO_PMSR5_PMSR53_SHIFT (3u) +#define GPIO_PMSR5_PMSR54_SHIFT (4u) +#define GPIO_PMSR5_PMSR55_SHIFT (5u) +#define GPIO_PMSR5_PMSR56_SHIFT (6u) +#define GPIO_PMSR5_PMSR57_SHIFT (7u) +#define GPIO_PMSR5_PMSR58_SHIFT (8u) +#define GPIO_PMSR5_PMSR59_SHIFT (9u) +#define GPIO_PMSR5_PMSR510_SHIFT (10u) +#define GPIO_PMSR5_PMSR516_SHIFT (16u) +#define GPIO_PMSR5_PMSR517_SHIFT (17u) +#define GPIO_PMSR5_PMSR518_SHIFT (18u) +#define GPIO_PMSR5_PMSR519_SHIFT (19u) +#define GPIO_PMSR5_PMSR520_SHIFT (20u) +#define GPIO_PMSR5_PMSR521_SHIFT (21u) +#define GPIO_PMSR5_PMSR522_SHIFT (22u) +#define GPIO_PMSR5_PMSR523_SHIFT (23u) +#define GPIO_PMSR5_PMSR524_SHIFT (24u) +#define GPIO_PMSR5_PMSR525_SHIFT (25u) +#define GPIO_PMSR5_PMSR526_SHIFT (26u) + +#define GPIO_PMCSR5_PMCSR50_SHIFT (0u) +#define GPIO_PMCSR5_PMCSR51_SHIFT (1u) +#define GPIO_PMCSR5_PMCSR52_SHIFT (2u) +#define GPIO_PMCSR5_PMCSR53_SHIFT (3u) +#define GPIO_PMCSR5_PMCSR54_SHIFT (4u) +#define GPIO_PMCSR5_PMCSR55_SHIFT (5u) +#define GPIO_PMCSR5_PMCSR56_SHIFT (6u) +#define GPIO_PMCSR5_PMCSR57_SHIFT (7u) +#define GPIO_PMCSR5_PMCSR58_SHIFT (8u) +#define GPIO_PMCSR5_PMCSR59_SHIFT (9u) +#define GPIO_PMCSR5_PMCSR510_SHIFT (10u) +#define GPIO_PMCSR5_PMCSR516_SHIFT (16u) +#define GPIO_PMCSR5_PMCSR517_SHIFT (17u) +#define GPIO_PMCSR5_PMCSR518_SHIFT (18u) +#define GPIO_PMCSR5_PMCSR519_SHIFT (19u) +#define GPIO_PMCSR5_PMCSR520_SHIFT (20u) +#define GPIO_PMCSR5_PMCSR521_SHIFT (21u) +#define GPIO_PMCSR5_PMCSR522_SHIFT (22u) +#define GPIO_PMCSR5_PMCSR523_SHIFT (23u) +#define GPIO_PMCSR5_PMCSR524_SHIFT (24u) +#define GPIO_PMCSR5_PMCSR525_SHIFT (25u) +#define GPIO_PMCSR5_PMCSR526_SHIFT (26u) + +#define GPIO_PFCAE5_PFCAE50_SHIFT (0u) +#define GPIO_PFCAE5_PFCAE51_SHIFT (1u) +#define GPIO_PFCAE5_PFCAE52_SHIFT (2u) +#define GPIO_PFCAE5_PFCAE53_SHIFT (3u) +#define GPIO_PFCAE5_PFCAE54_SHIFT (4u) +#define GPIO_PFCAE5_PFCAE55_SHIFT (5u) +#define GPIO_PFCAE5_PFCAE56_SHIFT (6u) +#define GPIO_PFCAE5_PFCAE57_SHIFT (7u) +#define GPIO_PFCAE5_PFCAE58_SHIFT (8u) +#define GPIO_PFCAE5_PFCAE59_SHIFT (9u) +#define GPIO_PFCAE5_PFCAE510_SHIFT (10u) + +#define GPIO_PIBC5_PIBC50_SHIFT (0u) +#define GPIO_PIBC5_PIBC51_SHIFT (1u) +#define GPIO_PIBC5_PIBC52_SHIFT (2u) +#define GPIO_PIBC5_PIBC53_SHIFT (3u) +#define GPIO_PIBC5_PIBC54_SHIFT (4u) +#define GPIO_PIBC5_PIBC55_SHIFT (5u) +#define GPIO_PIBC5_PIBC56_SHIFT (6u) +#define GPIO_PIBC5_PIBC57_SHIFT (7u) +#define GPIO_PIBC5_PIBC58_SHIFT (8u) +#define GPIO_PIBC5_PIBC59_SHIFT (9u) +#define GPIO_PIBC5_PIBC510_SHIFT (10u) + +#define GPIO_PBDC5_PBDC50_SHIFT (0u) +#define GPIO_PBDC5_PBDC51_SHIFT (1u) +#define GPIO_PBDC5_PBDC52_SHIFT (2u) +#define GPIO_PBDC5_PBDC53_SHIFT (3u) +#define GPIO_PBDC5_PBDC54_SHIFT (4u) +#define GPIO_PBDC5_PBDC55_SHIFT (5u) +#define GPIO_PBDC5_PBDC56_SHIFT (6u) +#define GPIO_PBDC5_PBDC57_SHIFT (7u) +#define GPIO_PBDC5_PBDC58_SHIFT (8u) +#define GPIO_PBDC5_PBDC59_SHIFT (9u) +#define GPIO_PBDC5_PBDC510_SHIFT (10u) + +#define GPIO_PIPC5_PIPC50_SHIFT (0u) +#define GPIO_PIPC5_PIPC51_SHIFT (1u) +#define GPIO_PIPC5_PIPC52_SHIFT (2u) +#define GPIO_PIPC5_PIPC53_SHIFT (3u) +#define GPIO_PIPC5_PIPC54_SHIFT (4u) +#define GPIO_PIPC5_PIPC55_SHIFT (5u) +#define GPIO_PIPC5_PIPC56_SHIFT (6u) +#define GPIO_PIPC5_PIPC57_SHIFT (7u) +#define GPIO_PIPC5_PIPC58_SHIFT (8u) +#define GPIO_PIPC5_PIPC59_SHIFT (9u) +#define GPIO_PIPC5_PIPC510_SHIFT (10u) + +/* ---- P6 ---- */ +#define GPIO_P6_P60_SHIFT (0u) +#define GPIO_P6_P61_SHIFT (1u) +#define GPIO_P6_P62_SHIFT (2u) +#define GPIO_P6_P63_SHIFT (3u) +#define GPIO_P6_P64_SHIFT (4u) +#define GPIO_P6_P65_SHIFT (5u) +#define GPIO_P6_P66_SHIFT (6u) +#define GPIO_P6_P67_SHIFT (7u) +#define GPIO_P6_P68_SHIFT (8u) +#define GPIO_P6_P69_SHIFT (9u) +#define GPIO_P6_P610_SHIFT (10u) +#define GPIO_P6_P611_SHIFT (11u) +#define GPIO_P6_P612_SHIFT (12u) +#define GPIO_P6_P613_SHIFT (13u) +#define GPIO_P6_P614_SHIFT (14u) +#define GPIO_P6_P615_SHIFT (15u) + +#define GPIO_PSR6_PSR60_SHIFT (0u) +#define GPIO_PSR6_PSR61_SHIFT (1u) +#define GPIO_PSR6_PSR62_SHIFT (2u) +#define GPIO_PSR6_PSR63_SHIFT (3u) +#define GPIO_PSR6_PSR64_SHIFT (4u) +#define GPIO_PSR6_PSR65_SHIFT (5u) +#define GPIO_PSR6_PSR66_SHIFT (6u) +#define GPIO_PSR6_PSR67_SHIFT (7u) +#define GPIO_PSR6_PSR68_SHIFT (8u) +#define GPIO_PSR6_PSR69_SHIFT (9u) +#define GPIO_PSR6_PSR610_SHIFT (10u) +#define GPIO_PSR6_PSR611_SHIFT (11u) +#define GPIO_PSR6_PSR612_SHIFT (12u) +#define GPIO_PSR6_PSR613_SHIFT (13u) +#define GPIO_PSR6_PSR614_SHIFT (14u) +#define GPIO_PSR6_PSR615_SHIFT (15u) +#define GPIO_PSR6_PSR616_SHIFT (16u) +#define GPIO_PSR6_PSR617_SHIFT (17u) +#define GPIO_PSR6_PSR618_SHIFT (18u) +#define GPIO_PSR6_PSR619_SHIFT (19u) +#define GPIO_PSR6_PSR620_SHIFT (20u) +#define GPIO_PSR6_PSR621_SHIFT (21u) +#define GPIO_PSR6_PSR622_SHIFT (22u) +#define GPIO_PSR6_PSR623_SHIFT (23u) +#define GPIO_PSR6_PSR624_SHIFT (24u) +#define GPIO_PSR6_PSR625_SHIFT (25u) +#define GPIO_PSR6_PSR626_SHIFT (26u) +#define GPIO_PSR6_PSR627_SHIFT (27u) +#define GPIO_PSR6_PSR628_SHIFT (28u) +#define GPIO_PSR6_PSR629_SHIFT (29u) +#define GPIO_PSR6_PSR630_SHIFT (30u) +#define GPIO_PSR6_PSR631_SHIFT (31u) + +#define GPIO_PPR6_PPR60_SHIFT (0u) +#define GPIO_PPR6_PPR61_SHIFT (1u) +#define GPIO_PPR6_PPR62_SHIFT (2u) +#define GPIO_PPR6_PPR63_SHIFT (3u) +#define GPIO_PPR6_PPR64_SHIFT (4u) +#define GPIO_PPR6_PPR65_SHIFT (5u) +#define GPIO_PPR6_PPR66_SHIFT (6u) +#define GPIO_PPR6_PPR67_SHIFT (7u) +#define GPIO_PPR6_PPR68_SHIFT (8u) +#define GPIO_PPR6_PPR69_SHIFT (9u) +#define GPIO_PPR6_PPR610_SHIFT (10u) +#define GPIO_PPR6_PPR611_SHIFT (11u) +#define GPIO_PPR6_PPR612_SHIFT (12u) +#define GPIO_PPR6_PPR613_SHIFT (13u) +#define GPIO_PPR6_PPR614_SHIFT (14u) +#define GPIO_PPR6_PPR615_SHIFT (15u) + +#define GPIO_PM6_PM60_SHIFT (0u) +#define GPIO_PM6_PM61_SHIFT (1u) +#define GPIO_PM6_PM62_SHIFT (2u) +#define GPIO_PM6_PM63_SHIFT (3u) +#define GPIO_PM6_PM64_SHIFT (4u) +#define GPIO_PM6_PM65_SHIFT (5u) +#define GPIO_PM6_PM66_SHIFT (6u) +#define GPIO_PM6_PM67_SHIFT (7u) +#define GPIO_PM6_PM68_SHIFT (8u) +#define GPIO_PM6_PM69_SHIFT (9u) +#define GPIO_PM6_PM610_SHIFT (10u) +#define GPIO_PM6_PM611_SHIFT (11u) +#define GPIO_PM6_PM612_SHIFT (12u) +#define GPIO_PM6_PM613_SHIFT (13u) +#define GPIO_PM6_PM614_SHIFT (14u) +#define GPIO_PM6_PM615_SHIFT (15u) + +#define GPIO_PMC6_PMC60_SHIFT (0u) +#define GPIO_PMC6_PMC61_SHIFT (1u) +#define GPIO_PMC6_PMC62_SHIFT (2u) +#define GPIO_PMC6_PMC63_SHIFT (3u) +#define GPIO_PMC6_PMC64_SHIFT (4u) +#define GPIO_PMC6_PMC65_SHIFT (5u) +#define GPIO_PMC6_PMC66_SHIFT (6u) +#define GPIO_PMC6_PMC67_SHIFT (7u) +#define GPIO_PMC6_PMC68_SHIFT (8u) +#define GPIO_PMC6_PMC69_SHIFT (9u) +#define GPIO_PMC6_PMC610_SHIFT (10u) +#define GPIO_PMC6_PMC611_SHIFT (11u) +#define GPIO_PMC6_PMC612_SHIFT (12u) +#define GPIO_PMC6_PMC613_SHIFT (13u) +#define GPIO_PMC6_PMC614_SHIFT (14u) +#define GPIO_PMC6_PMC615_SHIFT (15u) + +#define GPIO_PFC6_PFC60_SHIFT (0u) +#define GPIO_PFC6_PFC61_SHIFT (1u) +#define GPIO_PFC6_PFC62_SHIFT (2u) +#define GPIO_PFC6_PFC63_SHIFT (3u) +#define GPIO_PFC6_PFC64_SHIFT (4u) +#define GPIO_PFC6_PFC65_SHIFT (5u) +#define GPIO_PFC6_PFC66_SHIFT (6u) +#define GPIO_PFC6_PFC67_SHIFT (7u) +#define GPIO_PFC6_PFC68_SHIFT (8u) +#define GPIO_PFC6_PFC69_SHIFT (9u) +#define GPIO_PFC6_PFC610_SHIFT (10u) +#define GPIO_PFC6_PFC611_SHIFT (11u) +#define GPIO_PFC6_PFC612_SHIFT (12u) +#define GPIO_PFC6_PFC613_SHIFT (13u) +#define GPIO_PFC6_PFC614_SHIFT (14u) +#define GPIO_PFC6_PFC615_SHIFT (15u) + +#define GPIO_PFCE6_PFCE60_SHIFT (0u) +#define GPIO_PFCE6_PFCE61_SHIFT (1u) +#define GPIO_PFCE6_PFCE62_SHIFT (2u) +#define GPIO_PFCE6_PFCE63_SHIFT (3u) +#define GPIO_PFCE6_PFCE64_SHIFT (4u) +#define GPIO_PFCE6_PFCE65_SHIFT (5u) +#define GPIO_PFCE6_PFCE66_SHIFT (6u) +#define GPIO_PFCE6_PFCE67_SHIFT (7u) +#define GPIO_PFCE6_PFCE68_SHIFT (8u) +#define GPIO_PFCE6_PFCE69_SHIFT (9u) +#define GPIO_PFCE6_PFCE610_SHIFT (10u) +#define GPIO_PFCE6_PFCE611_SHIFT (11u) +#define GPIO_PFCE6_PFCE612_SHIFT (12u) +#define GPIO_PFCE6_PFCE613_SHIFT (13u) +#define GPIO_PFCE6_PFCE614_SHIFT (14u) +#define GPIO_PFCE6_PFCE615_SHIFT (15u) + +#define GPIO_PNOT6_PNOT60_SHIFT (0u) +#define GPIO_PNOT6_PNOT61_SHIFT (1u) +#define GPIO_PNOT6_PNOT62_SHIFT (2u) +#define GPIO_PNOT6_PNOT63_SHIFT (3u) +#define GPIO_PNOT6_PNOT64_SHIFT (4u) +#define GPIO_PNOT6_PNOT65_SHIFT (5u) +#define GPIO_PNOT6_PNOT66_SHIFT (6u) +#define GPIO_PNOT6_PNOT67_SHIFT (7u) +#define GPIO_PNOT6_PNOT68_SHIFT (8u) +#define GPIO_PNOT6_PNOT69_SHIFT (9u) +#define GPIO_PNOT6_PNOT610_SHIFT (10u) +#define GPIO_PNOT6_PNOT611_SHIFT (11u) +#define GPIO_PNOT6_PNOT612_SHIFT (12u) +#define GPIO_PNOT6_PNOT613_SHIFT (13u) +#define GPIO_PNOT6_PNOT614_SHIFT (14u) +#define GPIO_PNOT6_PNOT615_SHIFT (15u) + +#define GPIO_PMSR6_PMSR60_SHIFT (0u) +#define GPIO_PMSR6_PMSR61_SHIFT (1u) +#define GPIO_PMSR6_PMSR62_SHIFT (2u) +#define GPIO_PMSR6_PMSR63_SHIFT (3u) +#define GPIO_PMSR6_PMSR64_SHIFT (4u) +#define GPIO_PMSR6_PMSR65_SHIFT (5u) +#define GPIO_PMSR6_PMSR66_SHIFT (6u) +#define GPIO_PMSR6_PMSR67_SHIFT (7u) +#define GPIO_PMSR6_PMSR68_SHIFT (8u) +#define GPIO_PMSR6_PMSR69_SHIFT (9u) +#define GPIO_PMSR6_PMSR610_SHIFT (10u) +#define GPIO_PMSR6_PMSR611_SHIFT (11u) +#define GPIO_PMSR6_PMSR612_SHIFT (12u) +#define GPIO_PMSR6_PMSR613_SHIFT (13u) +#define GPIO_PMSR6_PMSR614_SHIFT (14u) +#define GPIO_PMSR6_PMSR615_SHIFT (15u) +#define GPIO_PMSR6_PMSR616_SHIFT (16u) +#define GPIO_PMSR6_PMSR617_SHIFT (17u) +#define GPIO_PMSR6_PMSR618_SHIFT (18u) +#define GPIO_PMSR6_PMSR619_SHIFT (19u) +#define GPIO_PMSR6_PMSR620_SHIFT (20u) +#define GPIO_PMSR6_PMSR621_SHIFT (21u) +#define GPIO_PMSR6_PMSR622_SHIFT (22u) +#define GPIO_PMSR6_PMSR623_SHIFT (23u) +#define GPIO_PMSR6_PMSR624_SHIFT (24u) +#define GPIO_PMSR6_PMSR625_SHIFT (25u) +#define GPIO_PMSR6_PMSR626_SHIFT (26u) +#define GPIO_PMSR6_PMSR627_SHIFT (27u) +#define GPIO_PMSR6_PMSR628_SHIFT (28u) +#define GPIO_PMSR6_PMSR629_SHIFT (29u) +#define GPIO_PMSR6_PMSR630_SHIFT (30u) +#define GPIO_PMSR6_PMSR631_SHIFT (31u) + +#define GPIO_PMCSR6_PMCSR60_SHIFT (0u) +#define GPIO_PMCSR6_PMCSR61_SHIFT (1u) +#define GPIO_PMCSR6_PMCSR62_SHIFT (2u) +#define GPIO_PMCSR6_PMCSR63_SHIFT (3u) +#define GPIO_PMCSR6_PMCSR64_SHIFT (4u) +#define GPIO_PMCSR6_PMCSR65_SHIFT (5u) +#define GPIO_PMCSR6_PMCSR66_SHIFT (6u) +#define GPIO_PMCSR6_PMCSR67_SHIFT (7u) +#define GPIO_PMCSR6_PMCSR68_SHIFT (8u) +#define GPIO_PMCSR6_PMCSR69_SHIFT (9u) +#define GPIO_PMCSR6_PMCSR610_SHIFT (10u) +#define GPIO_PMCSR6_PMCSR611_SHIFT (11u) +#define GPIO_PMCSR6_PMCSR612_SHIFT (12u) +#define GPIO_PMCSR6_PMCSR613_SHIFT (13u) +#define GPIO_PMCSR6_PMCSR614_SHIFT (14u) +#define GPIO_PMCSR6_PMCSR615_SHIFT (15u) +#define GPIO_PMCSR6_PMCSR616_SHIFT (16u) +#define GPIO_PMCSR6_PMCSR617_SHIFT (17u) +#define GPIO_PMCSR6_PMCSR618_SHIFT (18u) +#define GPIO_PMCSR6_PMCSR619_SHIFT (19u) +#define GPIO_PMCSR6_PMCSR620_SHIFT (20u) +#define GPIO_PMCSR6_PMCSR621_SHIFT (21u) +#define GPIO_PMCSR6_PMCSR622_SHIFT (22u) +#define GPIO_PMCSR6_PMCSR623_SHIFT (23u) +#define GPIO_PMCSR6_PMCSR624_SHIFT (24u) +#define GPIO_PMCSR6_PMCSR625_SHIFT (25u) +#define GPIO_PMCSR6_PMCSR626_SHIFT (26u) +#define GPIO_PMCSR6_PMCSR627_SHIFT (27u) +#define GPIO_PMCSR6_PMCSR628_SHIFT (28u) +#define GPIO_PMCSR6_PMCSR629_SHIFT (29u) +#define GPIO_PMCSR6_PMCSR630_SHIFT (30u) +#define GPIO_PMCSR6_PMCSR631_SHIFT (31u) + +#define GPIO_PFCAE6_PFCAE60_SHIFT (0u) +#define GPIO_PFCAE6_PFCAE61_SHIFT (1u) +#define GPIO_PFCAE6_PFCAE62_SHIFT (2u) +#define GPIO_PFCAE6_PFCAE63_SHIFT (3u) +#define GPIO_PFCAE6_PFCAE64_SHIFT (4u) +#define GPIO_PFCAE6_PFCAE65_SHIFT (5u) +#define GPIO_PFCAE6_PFCAE66_SHIFT (6u) +#define GPIO_PFCAE6_PFCAE67_SHIFT (7u) +#define GPIO_PFCAE6_PFCAE68_SHIFT (8u) +#define GPIO_PFCAE6_PFCAE69_SHIFT (9u) +#define GPIO_PFCAE6_PFCAE610_SHIFT (10u) +#define GPIO_PFCAE6_PFCAE611_SHIFT (11u) +#define GPIO_PFCAE6_PFCAE612_SHIFT (12u) +#define GPIO_PFCAE6_PFCAE613_SHIFT (13u) +#define GPIO_PFCAE6_PFCAE614_SHIFT (14u) +#define GPIO_PFCAE6_PFCAE615_SHIFT (15u) + +#define GPIO_PIBC6_PIBC60_SHIFT (0u) +#define GPIO_PIBC6_PIBC61_SHIFT (1u) +#define GPIO_PIBC6_PIBC62_SHIFT (2u) +#define GPIO_PIBC6_PIBC63_SHIFT (3u) +#define GPIO_PIBC6_PIBC64_SHIFT (4u) +#define GPIO_PIBC6_PIBC65_SHIFT (5u) +#define GPIO_PIBC6_PIBC66_SHIFT (6u) +#define GPIO_PIBC6_PIBC67_SHIFT (7u) +#define GPIO_PIBC6_PIBC68_SHIFT (8u) +#define GPIO_PIBC6_PIBC69_SHIFT (9u) +#define GPIO_PIBC6_PIBC610_SHIFT (10u) +#define GPIO_PIBC6_PIBC611_SHIFT (11u) +#define GPIO_PIBC6_PIBC612_SHIFT (12u) +#define GPIO_PIBC6_PIBC613_SHIFT (13u) +#define GPIO_PIBC6_PIBC614_SHIFT (14u) +#define GPIO_PIBC6_PIBC615_SHIFT (15u) + +#define GPIO_PBDC6_PBDC60_SHIFT (0u) +#define GPIO_PBDC6_PBDC61_SHIFT (1u) +#define GPIO_PBDC6_PBDC62_SHIFT (2u) +#define GPIO_PBDC6_PBDC63_SHIFT (3u) +#define GPIO_PBDC6_PBDC64_SHIFT (4u) +#define GPIO_PBDC6_PBDC65_SHIFT (5u) +#define GPIO_PBDC6_PBDC66_SHIFT (6u) +#define GPIO_PBDC6_PBDC67_SHIFT (7u) +#define GPIO_PBDC6_PBDC68_SHIFT (8u) +#define GPIO_PBDC6_PBDC69_SHIFT (9u) +#define GPIO_PBDC6_PBDC610_SHIFT (10u) +#define GPIO_PBDC6_PBDC611_SHIFT (11u) +#define GPIO_PBDC6_PBDC612_SHIFT (12u) +#define GPIO_PBDC6_PBDC613_SHIFT (13u) +#define GPIO_PBDC6_PBDC614_SHIFT (14u) +#define GPIO_PBDC6_PBDC615_SHIFT (15u) + +#define GPIO_PIPC6_PIPC60_SHIFT (0u) +#define GPIO_PIPC6_PIPC61_SHIFT (1u) +#define GPIO_PIPC6_PIPC62_SHIFT (2u) +#define GPIO_PIPC6_PIPC63_SHIFT (3u) +#define GPIO_PIPC6_PIPC64_SHIFT (4u) +#define GPIO_PIPC6_PIPC65_SHIFT (5u) +#define GPIO_PIPC6_PIPC66_SHIFT (6u) +#define GPIO_PIPC6_PIPC67_SHIFT (7u) +#define GPIO_PIPC6_PIPC68_SHIFT (8u) +#define GPIO_PIPC6_PIPC69_SHIFT (9u) +#define GPIO_PIPC6_PIPC610_SHIFT (10u) +#define GPIO_PIPC6_PIPC611_SHIFT (11u) +#define GPIO_PIPC6_PIPC612_SHIFT (12u) +#define GPIO_PIPC6_PIPC613_SHIFT (13u) +#define GPIO_PIPC6_PIPC614_SHIFT (14u) +#define GPIO_PIPC6_PIPC615_SHIFT (15u) + +/* ---- P7 ---- */ +#define GPIO_P7_P70_SHIFT (0u) +#define GPIO_P7_P71_SHIFT (1u) +#define GPIO_P7_P72_SHIFT (2u) +#define GPIO_P7_P73_SHIFT (3u) +#define GPIO_P7_P74_SHIFT (4u) +#define GPIO_P7_P75_SHIFT (5u) +#define GPIO_P7_P76_SHIFT (6u) +#define GPIO_P7_P77_SHIFT (7u) +#define GPIO_P7_P78_SHIFT (8u) +#define GPIO_P7_P79_SHIFT (9u) +#define GPIO_P7_P710_SHIFT (10u) +#define GPIO_P7_P711_SHIFT (11u) +#define GPIO_P7_P712_SHIFT (12u) +#define GPIO_P7_P713_SHIFT (13u) +#define GPIO_P7_P714_SHIFT (14u) +#define GPIO_P7_P715_SHIFT (15u) + +#define GPIO_PSR7_PSR70_SHIFT (0u) +#define GPIO_PSR7_PSR71_SHIFT (1u) +#define GPIO_PSR7_PSR72_SHIFT (2u) +#define GPIO_PSR7_PSR73_SHIFT (3u) +#define GPIO_PSR7_PSR74_SHIFT (4u) +#define GPIO_PSR7_PSR75_SHIFT (5u) +#define GPIO_PSR7_PSR76_SHIFT (6u) +#define GPIO_PSR7_PSR77_SHIFT (7u) +#define GPIO_PSR7_PSR78_SHIFT (8u) +#define GPIO_PSR7_PSR79_SHIFT (9u) +#define GPIO_PSR7_PSR710_SHIFT (10u) +#define GPIO_PSR7_PSR711_SHIFT (11u) +#define GPIO_PSR7_PSR712_SHIFT (12u) +#define GPIO_PSR7_PSR713_SHIFT (13u) +#define GPIO_PSR7_PSR714_SHIFT (14u) +#define GPIO_PSR7_PSR715_SHIFT (15u) +#define GPIO_PSR7_PSR716_SHIFT (16u) +#define GPIO_PSR7_PSR717_SHIFT (17u) +#define GPIO_PSR7_PSR718_SHIFT (18u) +#define GPIO_PSR7_PSR719_SHIFT (19u) +#define GPIO_PSR7_PSR720_SHIFT (20u) +#define GPIO_PSR7_PSR721_SHIFT (21u) +#define GPIO_PSR7_PSR722_SHIFT (22u) +#define GPIO_PSR7_PSR723_SHIFT (23u) +#define GPIO_PSR7_PSR724_SHIFT (24u) +#define GPIO_PSR7_PSR725_SHIFT (25u) +#define GPIO_PSR7_PSR726_SHIFT (26u) +#define GPIO_PSR7_PSR727_SHIFT (27u) +#define GPIO_PSR7_PSR728_SHIFT (28u) +#define GPIO_PSR7_PSR729_SHIFT (29u) +#define GPIO_PSR7_PSR730_SHIFT (30u) +#define GPIO_PSR7_PSR731_SHIFT (31u) + +#define GPIO_PPR7_PPR70_SHIFT (0u) +#define GPIO_PPR7_PPR71_SHIFT (1u) +#define GPIO_PPR7_PPR72_SHIFT (2u) +#define GPIO_PPR7_PPR73_SHIFT (3u) +#define GPIO_PPR7_PPR74_SHIFT (4u) +#define GPIO_PPR7_PPR75_SHIFT (5u) +#define GPIO_PPR7_PPR76_SHIFT (6u) +#define GPIO_PPR7_PPR77_SHIFT (7u) +#define GPIO_PPR7_PPR78_SHIFT (8u) +#define GPIO_PPR7_PPR79_SHIFT (9u) +#define GPIO_PPR7_PPR710_SHIFT (10u) +#define GPIO_PPR7_PPR711_SHIFT (11u) +#define GPIO_PPR7_PPR712_SHIFT (12u) +#define GPIO_PPR7_PPR713_SHIFT (13u) +#define GPIO_PPR7_PPR714_SHIFT (14u) +#define GPIO_PPR7_PPR715_SHIFT (15u) + +#define GPIO_PM7_PM70_SHIFT (0u) +#define GPIO_PM7_PM71_SHIFT (1u) +#define GPIO_PM7_PM72_SHIFT (2u) +#define GPIO_PM7_PM73_SHIFT (3u) +#define GPIO_PM7_PM74_SHIFT (4u) +#define GPIO_PM7_PM75_SHIFT (5u) +#define GPIO_PM7_PM76_SHIFT (6u) +#define GPIO_PM7_PM77_SHIFT (7u) +#define GPIO_PM7_PM78_SHIFT (8u) +#define GPIO_PM7_PM79_SHIFT (9u) +#define GPIO_PM7_PM710_SHIFT (10u) +#define GPIO_PM7_PM711_SHIFT (11u) +#define GPIO_PM7_PM712_SHIFT (12u) +#define GPIO_PM7_PM713_SHIFT (13u) +#define GPIO_PM7_PM714_SHIFT (14u) +#define GPIO_PM7_PM715_SHIFT (15u) + +#define GPIO_PMC7_PMC70_SHIFT (0u) +#define GPIO_PMC7_PMC71_SHIFT (1u) +#define GPIO_PMC7_PMC72_SHIFT (2u) +#define GPIO_PMC7_PMC73_SHIFT (3u) +#define GPIO_PMC7_PMC74_SHIFT (4u) +#define GPIO_PMC7_PMC75_SHIFT (5u) +#define GPIO_PMC7_PMC76_SHIFT (6u) +#define GPIO_PMC7_PMC77_SHIFT (7u) +#define GPIO_PMC7_PMC78_SHIFT (8u) +#define GPIO_PMC7_PMC79_SHIFT (9u) +#define GPIO_PMC7_PMC710_SHIFT (10u) +#define GPIO_PMC7_PMC711_SHIFT (11u) +#define GPIO_PMC7_PMC712_SHIFT (12u) +#define GPIO_PMC7_PMC713_SHIFT (13u) +#define GPIO_PMC7_PMC714_SHIFT (14u) +#define GPIO_PMC7_PMC715_SHIFT (15u) + +#define GPIO_PFC7_PFC70_SHIFT (0u) +#define GPIO_PFC7_PFC71_SHIFT (1u) +#define GPIO_PFC7_PFC72_SHIFT (2u) +#define GPIO_PFC7_PFC73_SHIFT (3u) +#define GPIO_PFC7_PFC74_SHIFT (4u) +#define GPIO_PFC7_PFC75_SHIFT (5u) +#define GPIO_PFC7_PFC76_SHIFT (6u) +#define GPIO_PFC7_PFC77_SHIFT (7u) +#define GPIO_PFC7_PFC78_SHIFT (8u) +#define GPIO_PFC7_PFC79_SHIFT (9u) +#define GPIO_PFC7_PFC710_SHIFT (10u) +#define GPIO_PFC7_PFC711_SHIFT (11u) +#define GPIO_PFC7_PFC712_SHIFT (12u) +#define GPIO_PFC7_PFC713_SHIFT (13u) +#define GPIO_PFC7_PFC714_SHIFT (14u) +#define GPIO_PFC7_PFC715_SHIFT (15u) + +#define GPIO_PFCE7_PFCE70_SHIFT (0u) +#define GPIO_PFCE7_PFCE71_SHIFT (1u) +#define GPIO_PFCE7_PFCE72_SHIFT (2u) +#define GPIO_PFCE7_PFCE73_SHIFT (3u) +#define GPIO_PFCE7_PFCE74_SHIFT (4u) +#define GPIO_PFCE7_PFCE75_SHIFT (5u) +#define GPIO_PFCE7_PFCE76_SHIFT (6u) +#define GPIO_PFCE7_PFCE77_SHIFT (7u) +#define GPIO_PFCE7_PFCE78_SHIFT (8u) +#define GPIO_PFCE7_PFCE79_SHIFT (9u) +#define GPIO_PFCE7_PFCE710_SHIFT (10u) +#define GPIO_PFCE7_PFCE711_SHIFT (11u) +#define GPIO_PFCE7_PFCE712_SHIFT (12u) +#define GPIO_PFCE7_PFCE713_SHIFT (13u) +#define GPIO_PFCE7_PFCE714_SHIFT (14u) +#define GPIO_PFCE7_PFCE715_SHIFT (15u) + +#define GPIO_PNOT7_PNOT70_SHIFT (0u) +#define GPIO_PNOT7_PNOT71_SHIFT (1u) +#define GPIO_PNOT7_PNOT72_SHIFT (2u) +#define GPIO_PNOT7_PNOT73_SHIFT (3u) +#define GPIO_PNOT7_PNOT74_SHIFT (4u) +#define GPIO_PNOT7_PNOT75_SHIFT (5u) +#define GPIO_PNOT7_PNOT76_SHIFT (6u) +#define GPIO_PNOT7_PNOT77_SHIFT (7u) +#define GPIO_PNOT7_PNOT78_SHIFT (8u) +#define GPIO_PNOT7_PNOT79_SHIFT (9u) +#define GPIO_PNOT7_PNOT710_SHIFT (10u) +#define GPIO_PNOT7_PNOT711_SHIFT (11u) +#define GPIO_PNOT7_PNOT712_SHIFT (12u) +#define GPIO_PNOT7_PNOT713_SHIFT (13u) +#define GPIO_PNOT7_PNOT714_SHIFT (14u) +#define GPIO_PNOT7_PNOT715_SHIFT (15u) + +#define GPIO_PMSR7_PMSR70_SHIFT (0u) +#define GPIO_PMSR7_PMSR71_SHIFT (1u) +#define GPIO_PMSR7_PMSR72_SHIFT (2u) +#define GPIO_PMSR7_PMSR73_SHIFT (3u) +#define GPIO_PMSR7_PMSR74_SHIFT (4u) +#define GPIO_PMSR7_PMSR75_SHIFT (5u) +#define GPIO_PMSR7_PMSR76_SHIFT (6u) +#define GPIO_PMSR7_PMSR77_SHIFT (7u) +#define GPIO_PMSR7_PMSR78_SHIFT (8u) +#define GPIO_PMSR7_PMSR79_SHIFT (9u) +#define GPIO_PMSR7_PMSR710_SHIFT (10u) +#define GPIO_PMSR7_PMSR711_SHIFT (11u) +#define GPIO_PMSR7_PMSR712_SHIFT (12u) +#define GPIO_PMSR7_PMSR713_SHIFT (13u) +#define GPIO_PMSR7_PMSR714_SHIFT (14u) +#define GPIO_PMSR7_PMSR715_SHIFT (15u) +#define GPIO_PMSR7_PMSR716_SHIFT (16u) +#define GPIO_PMSR7_PMSR717_SHIFT (17u) +#define GPIO_PMSR7_PMSR718_SHIFT (18u) +#define GPIO_PMSR7_PMSR719_SHIFT (19u) +#define GPIO_PMSR7_PMSR720_SHIFT (20u) +#define GPIO_PMSR7_PMSR721_SHIFT (21u) +#define GPIO_PMSR7_PMSR722_SHIFT (22u) +#define GPIO_PMSR7_PMSR723_SHIFT (23u) +#define GPIO_PMSR7_PMSR724_SHIFT (24u) +#define GPIO_PMSR7_PMSR725_SHIFT (25u) +#define GPIO_PMSR7_PMSR726_SHIFT (26u) +#define GPIO_PMSR7_PMSR727_SHIFT (27u) +#define GPIO_PMSR7_PMSR728_SHIFT (28u) +#define GPIO_PMSR7_PMSR729_SHIFT (29u) +#define GPIO_PMSR7_PMSR730_SHIFT (30u) +#define GPIO_PMSR7_PMSR731_SHIFT (31u) + +#define GPIO_PMCSR7_PMCSR70_SHIFT (0u) +#define GPIO_PMCSR7_PMCSR71_SHIFT (1u) +#define GPIO_PMCSR7_PMCSR72_SHIFT (2u) +#define GPIO_PMCSR7_PMCSR73_SHIFT (3u) +#define GPIO_PMCSR7_PMCSR74_SHIFT (4u) +#define GPIO_PMCSR7_PMCSR75_SHIFT (5u) +#define GPIO_PMCSR7_PMCSR76_SHIFT (6u) +#define GPIO_PMCSR7_PMCSR77_SHIFT (7u) +#define GPIO_PMCSR7_PMCSR78_SHIFT (8u) +#define GPIO_PMCSR7_PMCSR79_SHIFT (9u) +#define GPIO_PMCSR7_PMCSR710_SHIFT (10u) +#define GPIO_PMCSR7_PMCSR711_SHIFT (11u) +#define GPIO_PMCSR7_PMCSR712_SHIFT (12u) +#define GPIO_PMCSR7_PMCSR713_SHIFT (13u) +#define GPIO_PMCSR7_PMCSR714_SHIFT (14u) +#define GPIO_PMCSR7_PMCSR715_SHIFT (15u) +#define GPIO_PMCSR7_PMCSR716_SHIFT (16u) +#define GPIO_PMCSR7_PMCSR717_SHIFT (17u) +#define GPIO_PMCSR7_PMCSR718_SHIFT (18u) +#define GPIO_PMCSR7_PMCSR719_SHIFT (19u) +#define GPIO_PMCSR7_PMCSR720_SHIFT (20u) +#define GPIO_PMCSR7_PMCSR721_SHIFT (21u) +#define GPIO_PMCSR7_PMCSR722_SHIFT (22u) +#define GPIO_PMCSR7_PMCSR723_SHIFT (23u) +#define GPIO_PMCSR7_PMCSR724_SHIFT (24u) +#define GPIO_PMCSR7_PMCSR725_SHIFT (25u) +#define GPIO_PMCSR7_PMCSR726_SHIFT (26u) +#define GPIO_PMCSR7_PMCSR727_SHIFT (27u) +#define GPIO_PMCSR7_PMCSR728_SHIFT (28u) +#define GPIO_PMCSR7_PMCSR729_SHIFT (29u) +#define GPIO_PMCSR7_PMCSR730_SHIFT (30u) +#define GPIO_PMCSR7_PMCSR731_SHIFT (31u) + +#define GPIO_PFCAE7_PFCAE70_SHIFT (0u) +#define GPIO_PFCAE7_PFCAE71_SHIFT (1u) +#define GPIO_PFCAE7_PFCAE72_SHIFT (2u) +#define GPIO_PFCAE7_PFCAE73_SHIFT (3u) +#define GPIO_PFCAE7_PFCAE74_SHIFT (4u) +#define GPIO_PFCAE7_PFCAE75_SHIFT (5u) +#define GPIO_PFCAE7_PFCAE76_SHIFT (6u) +#define GPIO_PFCAE7_PFCAE77_SHIFT (7u) +#define GPIO_PFCAE7_PFCAE78_SHIFT (8u) +#define GPIO_PFCAE7_PFCAE79_SHIFT (9u) +#define GPIO_PFCAE7_PFCAE710_SHIFT (10u) +#define GPIO_PFCAE7_PFCAE711_SHIFT (11u) +#define GPIO_PFCAE7_PFCAE712_SHIFT (12u) +#define GPIO_PFCAE7_PFCAE713_SHIFT (13u) +#define GPIO_PFCAE7_PFCAE714_SHIFT (14u) +#define GPIO_PFCAE7_PFCAE715_SHIFT (15u) + +#define GPIO_PIBC7_PIBC70_SHIFT (0u) +#define GPIO_PIBC7_PIBC71_SHIFT (1u) +#define GPIO_PIBC7_PIBC72_SHIFT (2u) +#define GPIO_PIBC7_PIBC73_SHIFT (3u) +#define GPIO_PIBC7_PIBC74_SHIFT (4u) +#define GPIO_PIBC7_PIBC75_SHIFT (5u) +#define GPIO_PIBC7_PIBC76_SHIFT (6u) +#define GPIO_PIBC7_PIBC77_SHIFT (7u) +#define GPIO_PIBC7_PIBC78_SHIFT (8u) +#define GPIO_PIBC7_PIBC79_SHIFT (9u) +#define GPIO_PIBC7_PIBC710_SHIFT (10u) +#define GPIO_PIBC7_PIBC711_SHIFT (11u) +#define GPIO_PIBC7_PIBC712_SHIFT (12u) +#define GPIO_PIBC7_PIBC713_SHIFT (13u) +#define GPIO_PIBC7_PIBC714_SHIFT (14u) +#define GPIO_PIBC7_PIBC715_SHIFT (15u) + +#define GPIO_PBDC7_PBDC70_SHIFT (0u) +#define GPIO_PBDC7_PBDC71_SHIFT (1u) +#define GPIO_PBDC7_PBDC72_SHIFT (2u) +#define GPIO_PBDC7_PBDC73_SHIFT (3u) +#define GPIO_PBDC7_PBDC74_SHIFT (4u) +#define GPIO_PBDC7_PBDC75_SHIFT (5u) +#define GPIO_PBDC7_PBDC76_SHIFT (6u) +#define GPIO_PBDC7_PBDC77_SHIFT (7u) +#define GPIO_PBDC7_PBDC78_SHIFT (8u) +#define GPIO_PBDC7_PBDC79_SHIFT (9u) +#define GPIO_PBDC7_PBDC710_SHIFT (10u) +#define GPIO_PBDC7_PBDC711_SHIFT (11u) +#define GPIO_PBDC7_PBDC712_SHIFT (12u) +#define GPIO_PBDC7_PBDC713_SHIFT (13u) +#define GPIO_PBDC7_PBDC714_SHIFT (14u) +#define GPIO_PBDC7_PBDC715_SHIFT (15u) + +#define GPIO_PIPC7_PIPC70_SHIFT (0u) +#define GPIO_PIPC7_PIPC71_SHIFT (1u) +#define GPIO_PIPC7_PIPC72_SHIFT (2u) +#define GPIO_PIPC7_PIPC73_SHIFT (3u) +#define GPIO_PIPC7_PIPC74_SHIFT (4u) +#define GPIO_PIPC7_PIPC75_SHIFT (5u) +#define GPIO_PIPC7_PIPC76_SHIFT (6u) +#define GPIO_PIPC7_PIPC77_SHIFT (7u) +#define GPIO_PIPC7_PIPC78_SHIFT (8u) +#define GPIO_PIPC7_PIPC79_SHIFT (9u) +#define GPIO_PIPC7_PIPC710_SHIFT (10u) +#define GPIO_PIPC7_PIPC711_SHIFT (11u) +#define GPIO_PIPC7_PIPC712_SHIFT (12u) +#define GPIO_PIPC7_PIPC713_SHIFT (13u) +#define GPIO_PIPC7_PIPC714_SHIFT (14u) +#define GPIO_PIPC7_PIPC715_SHIFT (15u) + +/* ---- P8 ---- */ +#define GPIO_P8_P80_SHIFT (0u) +#define GPIO_P8_P81_SHIFT (1u) +#define GPIO_P8_P82_SHIFT (2u) +#define GPIO_P8_P83_SHIFT (3u) +#define GPIO_P8_P84_SHIFT (4u) +#define GPIO_P8_P85_SHIFT (5u) +#define GPIO_P8_P86_SHIFT (6u) +#define GPIO_P8_P87_SHIFT (7u) +#define GPIO_P8_P88_SHIFT (8u) +#define GPIO_P8_P89_SHIFT (9u) +#define GPIO_P8_P810_SHIFT (10u) +#define GPIO_P8_P811_SHIFT (11u) +#define GPIO_P8_P812_SHIFT (12u) +#define GPIO_P8_P813_SHIFT (13u) +#define GPIO_P8_P814_SHIFT (14u) +#define GPIO_P8_P815_SHIFT (15u) + +#define GPIO_PSR8_PSR80_SHIFT (0u) +#define GPIO_PSR8_PSR81_SHIFT (1u) +#define GPIO_PSR8_PSR82_SHIFT (2u) +#define GPIO_PSR8_PSR83_SHIFT (3u) +#define GPIO_PSR8_PSR84_SHIFT (4u) +#define GPIO_PSR8_PSR85_SHIFT (5u) +#define GPIO_PSR8_PSR86_SHIFT (6u) +#define GPIO_PSR8_PSR87_SHIFT (7u) +#define GPIO_PSR8_PSR88_SHIFT (8u) +#define GPIO_PSR8_PSR89_SHIFT (9u) +#define GPIO_PSR8_PSR810_SHIFT (10u) +#define GPIO_PSR8_PSR811_SHIFT (11u) +#define GPIO_PSR8_PSR812_SHIFT (12u) +#define GPIO_PSR8_PSR813_SHIFT (13u) +#define GPIO_PSR8_PSR814_SHIFT (14u) +#define GPIO_PSR8_PSR815_SHIFT (15u) +#define GPIO_PSR8_PSR816_SHIFT (16u) +#define GPIO_PSR8_PSR817_SHIFT (17u) +#define GPIO_PSR8_PSR818_SHIFT (18u) +#define GPIO_PSR8_PSR819_SHIFT (19u) +#define GPIO_PSR8_PSR820_SHIFT (20u) +#define GPIO_PSR8_PSR821_SHIFT (21u) +#define GPIO_PSR8_PSR822_SHIFT (22u) +#define GPIO_PSR8_PSR823_SHIFT (23u) +#define GPIO_PSR8_PSR824_SHIFT (24u) +#define GPIO_PSR8_PSR825_SHIFT (25u) +#define GPIO_PSR8_PSR826_SHIFT (26u) +#define GPIO_PSR8_PSR827_SHIFT (27u) +#define GPIO_PSR8_PSR828_SHIFT (28u) +#define GPIO_PSR8_PSR829_SHIFT (29u) +#define GPIO_PSR8_PSR830_SHIFT (30u) +#define GPIO_PSR8_PSR831_SHIFT (31u) + +#define GPIO_PPR8_PPR80_SHIFT (0u) +#define GPIO_PPR8_PPR81_SHIFT (1u) +#define GPIO_PPR8_PPR82_SHIFT (2u) +#define GPIO_PPR8_PPR83_SHIFT (3u) +#define GPIO_PPR8_PPR84_SHIFT (4u) +#define GPIO_PPR8_PPR85_SHIFT (5u) +#define GPIO_PPR8_PPR86_SHIFT (6u) +#define GPIO_PPR8_PPR87_SHIFT (7u) +#define GPIO_PPR8_PPR88_SHIFT (8u) +#define GPIO_PPR8_PPR89_SHIFT (9u) +#define GPIO_PPR8_PPR810_SHIFT (10u) +#define GPIO_PPR8_PPR811_SHIFT (11u) +#define GPIO_PPR8_PPR812_SHIFT (12u) +#define GPIO_PPR8_PPR813_SHIFT (13u) +#define GPIO_PPR8_PPR814_SHIFT (14u) +#define GPIO_PPR8_PPR815_SHIFT (15u) + +#define GPIO_PM8_PM80_SHIFT (0u) +#define GPIO_PM8_PM81_SHIFT (1u) +#define GPIO_PM8_PM82_SHIFT (2u) +#define GPIO_PM8_PM83_SHIFT (3u) +#define GPIO_PM8_PM84_SHIFT (4u) +#define GPIO_PM8_PM85_SHIFT (5u) +#define GPIO_PM8_PM86_SHIFT (6u) +#define GPIO_PM8_PM87_SHIFT (7u) +#define GPIO_PM8_PM88_SHIFT (8u) +#define GPIO_PM8_PM89_SHIFT (9u) +#define GPIO_PM8_PM810_SHIFT (10u) +#define GPIO_PM8_PM811_SHIFT (11u) +#define GPIO_PM8_PM812_SHIFT (12u) +#define GPIO_PM8_PM813_SHIFT (13u) +#define GPIO_PM8_PM814_SHIFT (14u) +#define GPIO_PM8_PM815_SHIFT (15u) + +#define GPIO_PMC8_PMC80_SHIFT (0u) +#define GPIO_PMC8_PMC81_SHIFT (1u) +#define GPIO_PMC8_PMC82_SHIFT (2u) +#define GPIO_PMC8_PMC83_SHIFT (3u) +#define GPIO_PMC8_PMC84_SHIFT (4u) +#define GPIO_PMC8_PMC85_SHIFT (5u) +#define GPIO_PMC8_PMC86_SHIFT (6u) +#define GPIO_PMC8_PMC87_SHIFT (7u) +#define GPIO_PMC8_PMC88_SHIFT (8u) +#define GPIO_PMC8_PMC89_SHIFT (9u) +#define GPIO_PMC8_PMC810_SHIFT (10u) +#define GPIO_PMC8_PMC811_SHIFT (11u) +#define GPIO_PMC8_PMC812_SHIFT (12u) +#define GPIO_PMC8_PMC813_SHIFT (13u) +#define GPIO_PMC8_PMC814_SHIFT (14u) +#define GPIO_PMC8_PMC815_SHIFT (15u) + +#define GPIO_PFC8_PFC80_SHIFT (0u) +#define GPIO_PFC8_PFC81_SHIFT (1u) +#define GPIO_PFC8_PFC82_SHIFT (2u) +#define GPIO_PFC8_PFC83_SHIFT (3u) +#define GPIO_PFC8_PFC84_SHIFT (4u) +#define GPIO_PFC8_PFC85_SHIFT (5u) +#define GPIO_PFC8_PFC86_SHIFT (6u) +#define GPIO_PFC8_PFC87_SHIFT (7u) +#define GPIO_PFC8_PFC88_SHIFT (8u) +#define GPIO_PFC8_PFC89_SHIFT (9u) +#define GPIO_PFC8_PFC810_SHIFT (10u) +#define GPIO_PFC8_PFC811_SHIFT (11u) +#define GPIO_PFC8_PFC812_SHIFT (12u) +#define GPIO_PFC8_PFC813_SHIFT (13u) +#define GPIO_PFC8_PFC814_SHIFT (14u) +#define GPIO_PFC8_PFC815_SHIFT (15u) + +#define GPIO_PFCE8_PFCE80_SHIFT (0u) +#define GPIO_PFCE8_PFCE81_SHIFT (1u) +#define GPIO_PFCE8_PFCE82_SHIFT (2u) +#define GPIO_PFCE8_PFCE83_SHIFT (3u) +#define GPIO_PFCE8_PFCE84_SHIFT (4u) +#define GPIO_PFCE8_PFCE85_SHIFT (5u) +#define GPIO_PFCE8_PFCE86_SHIFT (6u) +#define GPIO_PFCE8_PFCE87_SHIFT (7u) +#define GPIO_PFCE8_PFCE88_SHIFT (8u) +#define GPIO_PFCE8_PFCE89_SHIFT (9u) +#define GPIO_PFCE8_PFCE810_SHIFT (10u) +#define GPIO_PFCE8_PFCE811_SHIFT (11u) +#define GPIO_PFCE8_PFCE812_SHIFT (12u) +#define GPIO_PFCE8_PFCE813_SHIFT (13u) +#define GPIO_PFCE8_PFCE814_SHIFT (14u) +#define GPIO_PFCE8_PFCE815_SHIFT (15u) + +#define GPIO_PNOT8_PNOT80_SHIFT (0u) +#define GPIO_PNOT8_PNOT81_SHIFT (1u) +#define GPIO_PNOT8_PNOT82_SHIFT (2u) +#define GPIO_PNOT8_PNOT83_SHIFT (3u) +#define GPIO_PNOT8_PNOT84_SHIFT (4u) +#define GPIO_PNOT8_PNOT85_SHIFT (5u) +#define GPIO_PNOT8_PNOT86_SHIFT (6u) +#define GPIO_PNOT8_PNOT87_SHIFT (7u) +#define GPIO_PNOT8_PNOT88_SHIFT (8u) +#define GPIO_PNOT8_PNOT89_SHIFT (9u) +#define GPIO_PNOT8_PNOT810_SHIFT (10u) +#define GPIO_PNOT8_PNOT811_SHIFT (11u) +#define GPIO_PNOT8_PNOT812_SHIFT (12u) +#define GPIO_PNOT8_PNOT813_SHIFT (13u) +#define GPIO_PNOT8_PNOT814_SHIFT (14u) +#define GPIO_PNOT8_PNOT815_SHIFT (15u) + +#define GPIO_PMSR8_PMSR80_SHIFT (0u) +#define GPIO_PMSR8_PMSR81_SHIFT (1u) +#define GPIO_PMSR8_PMSR82_SHIFT (2u) +#define GPIO_PMSR8_PMSR83_SHIFT (3u) +#define GPIO_PMSR8_PMSR84_SHIFT (4u) +#define GPIO_PMSR8_PMSR85_SHIFT (5u) +#define GPIO_PMSR8_PMSR86_SHIFT (6u) +#define GPIO_PMSR8_PMSR87_SHIFT (7u) +#define GPIO_PMSR8_PMSR88_SHIFT (8u) +#define GPIO_PMSR8_PMSR89_SHIFT (9u) +#define GPIO_PMSR8_PMSR810_SHIFT (10u) +#define GPIO_PMSR8_PMSR811_SHIFT (11u) +#define GPIO_PMSR8_PMSR812_SHIFT (12u) +#define GPIO_PMSR8_PMSR813_SHIFT (13u) +#define GPIO_PMSR8_PMSR814_SHIFT (14u) +#define GPIO_PMSR8_PMSR815_SHIFT (15u) +#define GPIO_PMSR8_PMSR816_SHIFT (16u) +#define GPIO_PMSR8_PMSR817_SHIFT (17u) +#define GPIO_PMSR8_PMSR818_SHIFT (18u) +#define GPIO_PMSR8_PMSR819_SHIFT (19u) +#define GPIO_PMSR8_PMSR820_SHIFT (20u) +#define GPIO_PMSR8_PMSR821_SHIFT (21u) +#define GPIO_PMSR8_PMSR822_SHIFT (22u) +#define GPIO_PMSR8_PMSR823_SHIFT (23u) +#define GPIO_PMSR8_PMSR824_SHIFT (24u) +#define GPIO_PMSR8_PMSR825_SHIFT (25u) +#define GPIO_PMSR8_PMSR826_SHIFT (26u) +#define GPIO_PMSR8_PMSR827_SHIFT (27u) +#define GPIO_PMSR8_PMSR828_SHIFT (28u) +#define GPIO_PMSR8_PMSR829_SHIFT (29u) +#define GPIO_PMSR8_PMSR830_SHIFT (30u) +#define GPIO_PMSR8_PMSR831_SHIFT (31u) + +#define GPIO_PMCSR8_PMCSR80_SHIFT (0u) +#define GPIO_PMCSR8_PMCSR81_SHIFT (1u) +#define GPIO_PMCSR8_PMCSR82_SHIFT (2u) +#define GPIO_PMCSR8_PMCSR83_SHIFT (3u) +#define GPIO_PMCSR8_PMCSR84_SHIFT (4u) +#define GPIO_PMCSR8_PMCSR85_SHIFT (5u) +#define GPIO_PMCSR8_PMCSR86_SHIFT (6u) +#define GPIO_PMCSR8_PMCSR87_SHIFT (7u) +#define GPIO_PMCSR8_PMCSR88_SHIFT (8u) +#define GPIO_PMCSR8_PMCSR89_SHIFT (9u) +#define GPIO_PMCSR8_PMCSR810_SHIFT (10u) +#define GPIO_PMCSR8_PMCSR811_SHIFT (11u) +#define GPIO_PMCSR8_PMCSR812_SHIFT (12u) +#define GPIO_PMCSR8_PMCSR813_SHIFT (13u) +#define GPIO_PMCSR8_PMCSR814_SHIFT (14u) +#define GPIO_PMCSR8_PMCSR815_SHIFT (15u) +#define GPIO_PMCSR8_PMCSR816_SHIFT (16u) +#define GPIO_PMCSR8_PMCSR817_SHIFT (17u) +#define GPIO_PMCSR8_PMCSR818_SHIFT (18u) +#define GPIO_PMCSR8_PMCSR819_SHIFT (19u) +#define GPIO_PMCSR8_PMCSR820_SHIFT (20u) +#define GPIO_PMCSR8_PMCSR821_SHIFT (21u) +#define GPIO_PMCSR8_PMCSR822_SHIFT (22u) +#define GPIO_PMCSR8_PMCSR823_SHIFT (23u) +#define GPIO_PMCSR8_PMCSR824_SHIFT (24u) +#define GPIO_PMCSR8_PMCSR825_SHIFT (25u) +#define GPIO_PMCSR8_PMCSR826_SHIFT (26u) +#define GPIO_PMCSR8_PMCSR827_SHIFT (27u) +#define GPIO_PMCSR8_PMCSR828_SHIFT (28u) +#define GPIO_PMCSR8_PMCSR829_SHIFT (29u) +#define GPIO_PMCSR8_PMCSR830_SHIFT (30u) +#define GPIO_PMCSR8_PMCSR831_SHIFT (31u) + +#define GPIO_PFCAE8_PFCAE80_SHIFT (0u) +#define GPIO_PFCAE8_PFCAE81_SHIFT (1u) +#define GPIO_PFCAE8_PFCAE82_SHIFT (2u) +#define GPIO_PFCAE8_PFCAE83_SHIFT (3u) +#define GPIO_PFCAE8_PFCAE84_SHIFT (4u) +#define GPIO_PFCAE8_PFCAE85_SHIFT (5u) +#define GPIO_PFCAE8_PFCAE86_SHIFT (6u) +#define GPIO_PFCAE8_PFCAE87_SHIFT (7u) +#define GPIO_PFCAE8_PFCAE88_SHIFT (8u) +#define GPIO_PFCAE8_PFCAE89_SHIFT (9u) +#define GPIO_PFCAE8_PFCAE810_SHIFT (10u) +#define GPIO_PFCAE8_PFCAE811_SHIFT (11u) +#define GPIO_PFCAE8_PFCAE812_SHIFT (12u) +#define GPIO_PFCAE8_PFCAE813_SHIFT (13u) +#define GPIO_PFCAE8_PFCAE814_SHIFT (14u) +#define GPIO_PFCAE8_PFCAE815_SHIFT (15u) + +#define GPIO_PIBC8_PIBC80_SHIFT (0u) +#define GPIO_PIBC8_PIBC81_SHIFT (1u) +#define GPIO_PIBC8_PIBC82_SHIFT (2u) +#define GPIO_PIBC8_PIBC83_SHIFT (3u) +#define GPIO_PIBC8_PIBC84_SHIFT (4u) +#define GPIO_PIBC8_PIBC85_SHIFT (5u) +#define GPIO_PIBC8_PIBC86_SHIFT (6u) +#define GPIO_PIBC8_PIBC87_SHIFT (7u) +#define GPIO_PIBC8_PIBC88_SHIFT (8u) +#define GPIO_PIBC8_PIBC89_SHIFT (9u) +#define GPIO_PIBC8_PIBC810_SHIFT (10u) +#define GPIO_PIBC8_PIBC811_SHIFT (11u) +#define GPIO_PIBC8_PIBC812_SHIFT (12u) +#define GPIO_PIBC8_PIBC813_SHIFT (13u) +#define GPIO_PIBC8_PIBC814_SHIFT (14u) +#define GPIO_PIBC8_PIBC815_SHIFT (15u) + +#define GPIO_PBDC8_PBDC80_SHIFT (0u) +#define GPIO_PBDC8_PBDC81_SHIFT (1u) +#define GPIO_PBDC8_PBDC82_SHIFT (2u) +#define GPIO_PBDC8_PBDC83_SHIFT (3u) +#define GPIO_PBDC8_PBDC84_SHIFT (4u) +#define GPIO_PBDC8_PBDC85_SHIFT (5u) +#define GPIO_PBDC8_PBDC86_SHIFT (6u) +#define GPIO_PBDC8_PBDC87_SHIFT (7u) +#define GPIO_PBDC8_PBDC88_SHIFT (8u) +#define GPIO_PBDC8_PBDC89_SHIFT (9u) +#define GPIO_PBDC8_PBDC810_SHIFT (10u) +#define GPIO_PBDC8_PBDC811_SHIFT (11u) +#define GPIO_PBDC8_PBDC812_SHIFT (12u) +#define GPIO_PBDC8_PBDC813_SHIFT (13u) +#define GPIO_PBDC8_PBDC814_SHIFT (14u) +#define GPIO_PBDC8_PBDC815_SHIFT (15u) + +#define GPIO_PIPC8_PIPC80_SHIFT (0u) +#define GPIO_PIPC8_PIPC81_SHIFT (1u) +#define GPIO_PIPC8_PIPC82_SHIFT (2u) +#define GPIO_PIPC8_PIPC83_SHIFT (3u) +#define GPIO_PIPC8_PIPC84_SHIFT (4u) +#define GPIO_PIPC8_PIPC85_SHIFT (5u) +#define GPIO_PIPC8_PIPC86_SHIFT (6u) +#define GPIO_PIPC8_PIPC87_SHIFT (7u) +#define GPIO_PIPC8_PIPC88_SHIFT (8u) +#define GPIO_PIPC8_PIPC89_SHIFT (9u) +#define GPIO_PIPC8_PIPC810_SHIFT (10u) +#define GPIO_PIPC8_PIPC811_SHIFT (11u) +#define GPIO_PIPC8_PIPC812_SHIFT (12u) +#define GPIO_PIPC8_PIPC813_SHIFT (13u) +#define GPIO_PIPC8_PIPC814_SHIFT (14u) +#define GPIO_PIPC8_PIPC815_SHIFT (15u) + +/* ---- P9 ---- */ +#define GPIO_P9_P90_SHIFT (0u) +#define GPIO_P9_P91_SHIFT (1u) +#define GPIO_P9_P92_SHIFT (2u) +#define GPIO_P9_P93_SHIFT (3u) +#define GPIO_P9_P94_SHIFT (4u) +#define GPIO_P9_P95_SHIFT (5u) +#define GPIO_P9_P96_SHIFT (6u) +#define GPIO_P9_P97_SHIFT (7u) + +#define GPIO_PSR9_PSR90_SHIFT (0u) +#define GPIO_PSR9_PSR91_SHIFT (1u) +#define GPIO_PSR9_PSR92_SHIFT (2u) +#define GPIO_PSR9_PSR93_SHIFT (3u) +#define GPIO_PSR9_PSR94_SHIFT (4u) +#define GPIO_PSR9_PSR95_SHIFT (5u) +#define GPIO_PSR9_PSR96_SHIFT (6u) +#define GPIO_PSR9_PSR97_SHIFT (7u) +#define GPIO_PSR9_PSR916_SHIFT (16u) +#define GPIO_PSR9_PSR917_SHIFT (17u) +#define GPIO_PSR9_PSR918_SHIFT (18u) +#define GPIO_PSR9_PSR919_SHIFT (19u) +#define GPIO_PSR9_PSR920_SHIFT (20u) +#define GPIO_PSR9_PSR921_SHIFT (21u) +#define GPIO_PSR9_PSR922_SHIFT (22u) +#define GPIO_PSR9_PSR923_SHIFT (23u) + +#define GPIO_PPR9_PPR90_SHIFT (0u) +#define GPIO_PPR9_PPR91_SHIFT (1u) +#define GPIO_PPR9_PPR92_SHIFT (2u) +#define GPIO_PPR9_PPR93_SHIFT (3u) +#define GPIO_PPR9_PPR94_SHIFT (4u) +#define GPIO_PPR9_PPR95_SHIFT (5u) +#define GPIO_PPR9_PPR96_SHIFT (6u) +#define GPIO_PPR9_PPR97_SHIFT (7u) + +#define GPIO_PM9_PM90_SHIFT (0u) +#define GPIO_PM9_PM91_SHIFT (1u) +#define GPIO_PM9_PM92_SHIFT (2u) +#define GPIO_PM9_PM93_SHIFT (3u) +#define GPIO_PM9_PM94_SHIFT (4u) +#define GPIO_PM9_PM95_SHIFT (5u) +#define GPIO_PM9_PM96_SHIFT (6u) +#define GPIO_PM9_PM97_SHIFT (7u) + +#define GPIO_PMC9_PMC90_SHIFT (0u) +#define GPIO_PMC9_PMC91_SHIFT (1u) +#define GPIO_PMC9_PMC92_SHIFT (2u) +#define GPIO_PMC9_PMC93_SHIFT (3u) +#define GPIO_PMC9_PMC94_SHIFT (4u) +#define GPIO_PMC9_PMC95_SHIFT (5u) +#define GPIO_PMC9_PMC96_SHIFT (6u) +#define GPIO_PMC9_PMC97_SHIFT (7u) + +#define GPIO_PFC9_PFC90_SHIFT (0u) +#define GPIO_PFC9_PFC91_SHIFT (1u) +#define GPIO_PFC9_PFC92_SHIFT (2u) +#define GPIO_PFC9_PFC93_SHIFT (3u) +#define GPIO_PFC9_PFC94_SHIFT (4u) +#define GPIO_PFC9_PFC95_SHIFT (5u) +#define GPIO_PFC9_PFC96_SHIFT (6u) +#define GPIO_PFC9_PFC97_SHIFT (7u) + +#define GPIO_PFCE9_PFCE90_SHIFT (0u) +#define GPIO_PFCE9_PFCE91_SHIFT (1u) +#define GPIO_PFCE9_PFCE92_SHIFT (2u) +#define GPIO_PFCE9_PFCE93_SHIFT (3u) +#define GPIO_PFCE9_PFCE94_SHIFT (4u) +#define GPIO_PFCE9_PFCE95_SHIFT (5u) +#define GPIO_PFCE9_PFCE96_SHIFT (6u) +#define GPIO_PFCE9_PFCE97_SHIFT (7u) + +#define GPIO_PNOT9_PNOT90_SHIFT (0u) +#define GPIO_PNOT9_PNOT91_SHIFT (1u) +#define GPIO_PNOT9_PNOT92_SHIFT (2u) +#define GPIO_PNOT9_PNOT93_SHIFT (3u) +#define GPIO_PNOT9_PNOT94_SHIFT (4u) +#define GPIO_PNOT9_PNOT95_SHIFT (5u) +#define GPIO_PNOT9_PNOT96_SHIFT (6u) +#define GPIO_PNOT9_PNOT97_SHIFT (7u) + +#define GPIO_PMSR9_PMSR90_SHIFT (0u) +#define GPIO_PMSR9_PMSR91_SHIFT (1u) +#define GPIO_PMSR9_PMSR92_SHIFT (2u) +#define GPIO_PMSR9_PMSR93_SHIFT (3u) +#define GPIO_PMSR9_PMSR94_SHIFT (4u) +#define GPIO_PMSR9_PMSR95_SHIFT (5u) +#define GPIO_PMSR9_PMSR96_SHIFT (6u) +#define GPIO_PMSR9_PMSR97_SHIFT (7u) +#define GPIO_PMSR9_PMSR916_SHIFT (16u) +#define GPIO_PMSR9_PMSR917_SHIFT (17u) +#define GPIO_PMSR9_PMSR918_SHIFT (18u) +#define GPIO_PMSR9_PMSR919_SHIFT (19u) +#define GPIO_PMSR9_PMSR920_SHIFT (20u) +#define GPIO_PMSR9_PMSR921_SHIFT (21u) +#define GPIO_PMSR9_PMSR922_SHIFT (22u) +#define GPIO_PMSR9_PMSR923_SHIFT (23u) + +#define GPIO_PMCSR9_PMCSR90_SHIFT (0u) +#define GPIO_PMCSR9_PMCSR91_SHIFT (1u) +#define GPIO_PMCSR9_PMCSR92_SHIFT (2u) +#define GPIO_PMCSR9_PMCSR93_SHIFT (3u) +#define GPIO_PMCSR9_PMCSR94_SHIFT (4u) +#define GPIO_PMCSR9_PMCSR95_SHIFT (5u) +#define GPIO_PMCSR9_PMCSR96_SHIFT (6u) +#define GPIO_PMCSR9_PMCSR97_SHIFT (7u) +#define GPIO_PMCSR9_PMCSR916_SHIFT (16u) +#define GPIO_PMCSR9_PMCSR917_SHIFT (17u) +#define GPIO_PMCSR9_PMCSR918_SHIFT (18u) +#define GPIO_PMCSR9_PMCSR919_SHIFT (19u) +#define GPIO_PMCSR9_PMCSR920_SHIFT (20u) +#define GPIO_PMCSR9_PMCSR921_SHIFT (21u) +#define GPIO_PMCSR9_PMCSR922_SHIFT (22u) +#define GPIO_PMCSR9_PMCSR923_SHIFT (23u) + +#define GPIO_PFCAE9_PFCAE90_SHIFT (0u) +#define GPIO_PFCAE9_PFCAE91_SHIFT (1u) +#define GPIO_PFCAE9_PFCAE92_SHIFT (2u) +#define GPIO_PFCAE9_PFCAE93_SHIFT (3u) +#define GPIO_PFCAE9_PFCAE94_SHIFT (4u) +#define GPIO_PFCAE9_PFCAE95_SHIFT (5u) +#define GPIO_PFCAE9_PFCAE96_SHIFT (6u) +#define GPIO_PFCAE9_PFCAE97_SHIFT (7u) + +#define GPIO_PIBC9_PIBC90_SHIFT (0u) +#define GPIO_PIBC9_PIBC91_SHIFT (1u) +#define GPIO_PIBC9_PIBC92_SHIFT (2u) +#define GPIO_PIBC9_PIBC93_SHIFT (3u) +#define GPIO_PIBC9_PIBC94_SHIFT (4u) +#define GPIO_PIBC9_PIBC95_SHIFT (5u) +#define GPIO_PIBC9_PIBC96_SHIFT (6u) +#define GPIO_PIBC9_PIBC97_SHIFT (7u) + +#define GPIO_PBDC9_PBDC90_SHIFT (0u) +#define GPIO_PBDC9_PBDC91_SHIFT (1u) +#define GPIO_PBDC9_PBDC92_SHIFT (2u) +#define GPIO_PBDC9_PBDC93_SHIFT (3u) +#define GPIO_PBDC9_PBDC94_SHIFT (4u) +#define GPIO_PBDC9_PBDC95_SHIFT (5u) +#define GPIO_PBDC9_PBDC96_SHIFT (6u) +#define GPIO_PBDC9_PBDC97_SHIFT (7u) + +#define GPIO_PIPC9_PIPC90_SHIFT (0u) +#define GPIO_PIPC9_PIPC91_SHIFT (1u) +#define GPIO_PIPC9_PIPC92_SHIFT (2u) +#define GPIO_PIPC9_PIPC93_SHIFT (3u) +#define GPIO_PIPC9_PIPC94_SHIFT (4u) +#define GPIO_PIPC9_PIPC95_SHIFT (5u) +#define GPIO_PIPC9_PIPC96_SHIFT (6u) +#define GPIO_PIPC9_PIPC97_SHIFT (7u) + +/* ---- P10 ---- */ +#define GPIO_P10_P100_SHIFT (0u) +#define GPIO_P10_P101_SHIFT (1u) +#define GPIO_P10_P102_SHIFT (2u) +#define GPIO_P10_P103_SHIFT (3u) +#define GPIO_P10_P104_SHIFT (4u) +#define GPIO_P10_P105_SHIFT (5u) +#define GPIO_P10_P106_SHIFT (6u) +#define GPIO_P10_P107_SHIFT (7u) +#define GPIO_P10_P108_SHIFT (8u) +#define GPIO_P10_P109_SHIFT (9u) +#define GPIO_P10_P1010_SHIFT (10u) +#define GPIO_P10_P1011_SHIFT (11u) +#define GPIO_P10_P1012_SHIFT (12u) +#define GPIO_P10_P1013_SHIFT (13u) +#define GPIO_P10_P1014_SHIFT (14u) +#define GPIO_P10_P1015_SHIFT (15u) + +#define GPIO_PSR10_PSR100_SHIFT (0u) +#define GPIO_PSR10_PSR101_SHIFT (1u) +#define GPIO_PSR10_PSR102_SHIFT (2u) +#define GPIO_PSR10_PSR103_SHIFT (3u) +#define GPIO_PSR10_PSR104_SHIFT (4u) +#define GPIO_PSR10_PSR105_SHIFT (5u) +#define GPIO_PSR10_PSR106_SHIFT (6u) +#define GPIO_PSR10_PSR107_SHIFT (7u) +#define GPIO_PSR10_PSR108_SHIFT (8u) +#define GPIO_PSR10_PSR109_SHIFT (9u) +#define GPIO_PSR10_PSR1010_SHIFT (10u) +#define GPIO_PSR10_PSR1011_SHIFT (11u) +#define GPIO_PSR10_PSR1012_SHIFT (12u) +#define GPIO_PSR10_PSR1013_SHIFT (13u) +#define GPIO_PSR10_PSR1014_SHIFT (14u) +#define GPIO_PSR10_PSR1015_SHIFT (15u) +#define GPIO_PSR10_PSR1016_SHIFT (16u) +#define GPIO_PSR10_PSR1017_SHIFT (17u) +#define GPIO_PSR10_PSR1018_SHIFT (18u) +#define GPIO_PSR10_PSR1019_SHIFT (19u) +#define GPIO_PSR10_PSR1020_SHIFT (20u) +#define GPIO_PSR10_PSR1021_SHIFT (21u) +#define GPIO_PSR10_PSR1022_SHIFT (22u) +#define GPIO_PSR10_PSR1023_SHIFT (23u) +#define GPIO_PSR10_PSR1024_SHIFT (24u) +#define GPIO_PSR10_PSR1025_SHIFT (25u) +#define GPIO_PSR10_PSR1026_SHIFT (26u) +#define GPIO_PSR10_PSR1027_SHIFT (27u) +#define GPIO_PSR10_PSR1028_SHIFT (28u) +#define GPIO_PSR10_PSR1029_SHIFT (29u) +#define GPIO_PSR10_PSR1030_SHIFT (30u) +#define GPIO_PSR10_PSR1031_SHIFT (31u) + +#define GPIO_PPR10_PPR100_SHIFT (0u) +#define GPIO_PPR10_PPR101_SHIFT (1u) +#define GPIO_PPR10_PPR102_SHIFT (2u) +#define GPIO_PPR10_PPR103_SHIFT (3u) +#define GPIO_PPR10_PPR104_SHIFT (4u) +#define GPIO_PPR10_PPR105_SHIFT (5u) +#define GPIO_PPR10_PPR106_SHIFT (6u) +#define GPIO_PPR10_PPR107_SHIFT (7u) +#define GPIO_PPR10_PPR108_SHIFT (8u) +#define GPIO_PPR10_PPR109_SHIFT (9u) +#define GPIO_PPR10_PPR1010_SHIFT (10u) +#define GPIO_PPR10_PPR1011_SHIFT (11u) +#define GPIO_PPR10_PPR1012_SHIFT (12u) +#define GPIO_PPR10_PPR1013_SHIFT (13u) +#define GPIO_PPR10_PPR1014_SHIFT (14u) +#define GPIO_PPR10_PPR1015_SHIFT (15u) + +#define GPIO_PM10_PM100_SHIFT (0u) +#define GPIO_PM10_PM101_SHIFT (1u) +#define GPIO_PM10_PM102_SHIFT (2u) +#define GPIO_PM10_PM103_SHIFT (3u) +#define GPIO_PM10_PM104_SHIFT (4u) +#define GPIO_PM10_PM105_SHIFT (5u) +#define GPIO_PM10_PM106_SHIFT (6u) +#define GPIO_PM10_PM107_SHIFT (7u) +#define GPIO_PM10_PM108_SHIFT (8u) +#define GPIO_PM10_PM109_SHIFT (9u) +#define GPIO_PM10_PM1010_SHIFT (10u) +#define GPIO_PM10_PM1011_SHIFT (11u) +#define GPIO_PM10_PM1012_SHIFT (12u) +#define GPIO_PM10_PM1013_SHIFT (13u) +#define GPIO_PM10_PM1014_SHIFT (14u) +#define GPIO_PM10_PM1015_SHIFT (15u) + +#define GPIO_PMC10_PMC100_SHIFT (0u) +#define GPIO_PMC10_PMC101_SHIFT (1u) +#define GPIO_PMC10_PMC102_SHIFT (2u) +#define GPIO_PMC10_PMC103_SHIFT (3u) +#define GPIO_PMC10_PMC104_SHIFT (4u) +#define GPIO_PMC10_PMC105_SHIFT (5u) +#define GPIO_PMC10_PMC106_SHIFT (6u) +#define GPIO_PMC10_PMC107_SHIFT (7u) +#define GPIO_PMC10_PMC108_SHIFT (8u) +#define GPIO_PMC10_PMC109_SHIFT (9u) +#define GPIO_PMC10_PMC1010_SHIFT (10u) +#define GPIO_PMC10_PMC1011_SHIFT (11u) +#define GPIO_PMC10_PMC1012_SHIFT (12u) +#define GPIO_PMC10_PMC1013_SHIFT (13u) +#define GPIO_PMC10_PMC1014_SHIFT (14u) +#define GPIO_PMC10_PMC1015_SHIFT (15u) + +#define GPIO_PFC10_PFC100_SHIFT (0u) +#define GPIO_PFC10_PFC101_SHIFT (1u) +#define GPIO_PFC10_PFC102_SHIFT (2u) +#define GPIO_PFC10_PFC103_SHIFT (3u) +#define GPIO_PFC10_PFC104_SHIFT (4u) +#define GPIO_PFC10_PFC105_SHIFT (5u) +#define GPIO_PFC10_PFC106_SHIFT (6u) +#define GPIO_PFC10_PFC107_SHIFT (7u) +#define GPIO_PFC10_PFC108_SHIFT (8u) +#define GPIO_PFC10_PFC109_SHIFT (9u) +#define GPIO_PFC10_PFC1010_SHIFT (10u) +#define GPIO_PFC10_PFC1011_SHIFT (11u) +#define GPIO_PFC10_PFC1012_SHIFT (12u) +#define GPIO_PFC10_PFC1013_SHIFT (13u) +#define GPIO_PFC10_PFC1014_SHIFT (14u) +#define GPIO_PFC10_PFC1015_SHIFT (15u) + +#define GPIO_PFCE10_PFCE100_SHIFT (0u) +#define GPIO_PFCE10_PFCE101_SHIFT (1u) +#define GPIO_PFCE10_PFCE102_SHIFT (2u) +#define GPIO_PFCE10_PFCE103_SHIFT (3u) +#define GPIO_PFCE10_PFCE104_SHIFT (4u) +#define GPIO_PFCE10_PFCE105_SHIFT (5u) +#define GPIO_PFCE10_PFCE106_SHIFT (6u) +#define GPIO_PFCE10_PFCE107_SHIFT (7u) +#define GPIO_PFCE10_PFCE108_SHIFT (8u) +#define GPIO_PFCE10_PFCE109_SHIFT (9u) +#define GPIO_PFCE10_PFCE1010_SHIFT (10u) +#define GPIO_PFCE10_PFCE1011_SHIFT (11u) +#define GPIO_PFCE10_PFCE1012_SHIFT (12u) +#define GPIO_PFCE10_PFCE1013_SHIFT (13u) +#define GPIO_PFCE10_PFCE1014_SHIFT (14u) +#define GPIO_PFCE10_PFCE1015_SHIFT (15u) + +#define GPIO_PNOT10_PNOT100_SHIFT (0u) +#define GPIO_PNOT10_PNOT101_SHIFT (1u) +#define GPIO_PNOT10_PNOT102_SHIFT (2u) +#define GPIO_PNOT10_PNOT103_SHIFT (3u) +#define GPIO_PNOT10_PNOT104_SHIFT (4u) +#define GPIO_PNOT10_PNOT105_SHIFT (5u) +#define GPIO_PNOT10_PNOT106_SHIFT (6u) +#define GPIO_PNOT10_PNOT107_SHIFT (7u) +#define GPIO_PNOT10_PNOT108_SHIFT (8u) +#define GPIO_PNOT10_PNOT109_SHIFT (9u) +#define GPIO_PNOT10_PNOT1010_SHIFT (10u) +#define GPIO_PNOT10_PNOT1011_SHIFT (11u) +#define GPIO_PNOT10_PNOT1012_SHIFT (12u) +#define GPIO_PNOT10_PNOT1013_SHIFT (13u) +#define GPIO_PNOT10_PNOT1014_SHIFT (14u) +#define GPIO_PNOT10_PNOT1015_SHIFT (15u) + +#define GPIO_PMSR10_PMSR100_SHIFT (0u) +#define GPIO_PMSR10_PMSR101_SHIFT (1u) +#define GPIO_PMSR10_PMSR102_SHIFT (2u) +#define GPIO_PMSR10_PMSR103_SHIFT (3u) +#define GPIO_PMSR10_PMSR104_SHIFT (4u) +#define GPIO_PMSR10_PMSR105_SHIFT (5u) +#define GPIO_PMSR10_PMSR106_SHIFT (6u) +#define GPIO_PMSR10_PMSR107_SHIFT (7u) +#define GPIO_PMSR10_PMSR108_SHIFT (8u) +#define GPIO_PMSR10_PMSR109_SHIFT (9u) +#define GPIO_PMSR10_PMSR1010_SHIFT (10u) +#define GPIO_PMSR10_PMSR1011_SHIFT (11u) +#define GPIO_PMSR10_PMSR1012_SHIFT (12u) +#define GPIO_PMSR10_PMSR1013_SHIFT (13u) +#define GPIO_PMSR10_PMSR1014_SHIFT (14u) +#define GPIO_PMSR10_PMSR1015_SHIFT (15u) +#define GPIO_PMSR10_PMSR1016_SHIFT (16u) +#define GPIO_PMSR10_PMSR1017_SHIFT (17u) +#define GPIO_PMSR10_PMSR1018_SHIFT (18u) +#define GPIO_PMSR10_PMSR1019_SHIFT (19u) +#define GPIO_PMSR10_PMSR1020_SHIFT (20u) +#define GPIO_PMSR10_PMSR1021_SHIFT (21u) +#define GPIO_PMSR10_PMSR1022_SHIFT (22u) +#define GPIO_PMSR10_PMSR1023_SHIFT (23u) +#define GPIO_PMSR10_PMSR1024_SHIFT (24u) +#define GPIO_PMSR10_PMSR1025_SHIFT (25u) +#define GPIO_PMSR10_PMSR1026_SHIFT (26u) +#define GPIO_PMSR10_PMSR1027_SHIFT (27u) +#define GPIO_PMSR10_PMSR1028_SHIFT (28u) +#define GPIO_PMSR10_PMSR1029_SHIFT (29u) +#define GPIO_PMSR10_PMSR1030_SHIFT (30u) +#define GPIO_PMSR10_PMSR1031_SHIFT (31u) + +#define GPIO_PMCSR10_PMCSR100_SHIFT (0u) +#define GPIO_PMCSR10_PMCSR101_SHIFT (1u) +#define GPIO_PMCSR10_PMCSR102_SHIFT (2u) +#define GPIO_PMCSR10_PMCSR103_SHIFT (3u) +#define GPIO_PMCSR10_PMCSR104_SHIFT (4u) +#define GPIO_PMCSR10_PMCSR105_SHIFT (5u) +#define GPIO_PMCSR10_PMCSR106_SHIFT (6u) +#define GPIO_PMCSR10_PMCSR107_SHIFT (7u) +#define GPIO_PMCSR10_PMCSR108_SHIFT (8u) +#define GPIO_PMCSR10_PMCSR109_SHIFT (9u) +#define GPIO_PMCSR10_PMCSR1010_SHIFT (10u) +#define GPIO_PMCSR10_PMCSR1011_SHIFT (11u) +#define GPIO_PMCSR10_PMCSR1012_SHIFT (12u) +#define GPIO_PMCSR10_PMCSR1013_SHIFT (13u) +#define GPIO_PMCSR10_PMCSR1014_SHIFT (14u) +#define GPIO_PMCSR10_PMCSR1015_SHIFT (15u) +#define GPIO_PMCSR10_PMCSR1016_SHIFT (16u) +#define GPIO_PMCSR10_PMCSR1017_SHIFT (17u) +#define GPIO_PMCSR10_PMCSR1018_SHIFT (18u) +#define GPIO_PMCSR10_PMCSR1019_SHIFT (19u) +#define GPIO_PMCSR10_PMCSR1020_SHIFT (20u) +#define GPIO_PMCSR10_PMCSR1021_SHIFT (21u) +#define GPIO_PMCSR10_PMCSR1022_SHIFT (22u) +#define GPIO_PMCSR10_PMCSR1023_SHIFT (23u) +#define GPIO_PMCSR10_PMCSR1024_SHIFT (24u) +#define GPIO_PMCSR10_PMCSR1025_SHIFT (25u) +#define GPIO_PMCSR10_PMCSR1026_SHIFT (26u) +#define GPIO_PMCSR10_PMCSR1027_SHIFT (27u) +#define GPIO_PMCSR10_PMCSR1028_SHIFT (28u) +#define GPIO_PMCSR10_PMCSR1029_SHIFT (29u) +#define GPIO_PMCSR10_PMCSR1030_SHIFT (30u) +#define GPIO_PMCSR10_PMCSR1031_SHIFT (31u) + +#define GPIO_PFCAE10_PFCAE100_SHIFT (0u) +#define GPIO_PFCAE10_PFCAE101_SHIFT (1u) +#define GPIO_PFCAE10_PFCAE102_SHIFT (2u) +#define GPIO_PFCAE10_PFCAE103_SHIFT (3u) +#define GPIO_PFCAE10_PFCAE104_SHIFT (4u) +#define GPIO_PFCAE10_PFCAE105_SHIFT (5u) +#define GPIO_PFCAE10_PFCAE106_SHIFT (6u) +#define GPIO_PFCAE10_PFCAE107_SHIFT (7u) +#define GPIO_PFCAE10_PFCAE108_SHIFT (8u) +#define GPIO_PFCAE10_PFCAE109_SHIFT (9u) +#define GPIO_PFCAE10_PFCAE1010_SHIFT (10u) +#define GPIO_PFCAE10_PFCAE1011_SHIFT (11u) +#define GPIO_PFCAE10_PFCAE1012_SHIFT (12u) +#define GPIO_PFCAE10_PFCAE1013_SHIFT (13u) +#define GPIO_PFCAE10_PFCAE1014_SHIFT (14u) +#define GPIO_PFCAE10_PFCAE1015_SHIFT (15u) + +#define GPIO_PIBC10_PIBC100_SHIFT (0u) +#define GPIO_PIBC10_PIBC101_SHIFT (1u) +#define GPIO_PIBC10_PIBC102_SHIFT (2u) +#define GPIO_PIBC10_PIBC103_SHIFT (3u) +#define GPIO_PIBC10_PIBC104_SHIFT (4u) +#define GPIO_PIBC10_PIBC105_SHIFT (5u) +#define GPIO_PIBC10_PIBC106_SHIFT (6u) +#define GPIO_PIBC10_PIBC107_SHIFT (7u) +#define GPIO_PIBC10_PIBC108_SHIFT (8u) +#define GPIO_PIBC10_PIBC109_SHIFT (9u) +#define GPIO_PIBC10_PIBC1010_SHIFT (10u) +#define GPIO_PIBC10_PIBC1011_SHIFT (11u) +#define GPIO_PIBC10_PIBC1012_SHIFT (12u) +#define GPIO_PIBC10_PIBC1013_SHIFT (13u) +#define GPIO_PIBC10_PIBC1014_SHIFT (14u) +#define GPIO_PIBC10_PIBC1015_SHIFT (15u) + +#define GPIO_PBDC10_PBDC100_SHIFT (0u) +#define GPIO_PBDC10_PBDC101_SHIFT (1u) +#define GPIO_PBDC10_PBDC102_SHIFT (2u) +#define GPIO_PBDC10_PBDC103_SHIFT (3u) +#define GPIO_PBDC10_PBDC104_SHIFT (4u) +#define GPIO_PBDC10_PBDC105_SHIFT (5u) +#define GPIO_PBDC10_PBDC106_SHIFT (6u) +#define GPIO_PBDC10_PBDC107_SHIFT (7u) +#define GPIO_PBDC10_PBDC108_SHIFT (8u) +#define GPIO_PBDC10_PBDC109_SHIFT (9u) +#define GPIO_PBDC10_PBDC1010_SHIFT (10u) +#define GPIO_PBDC10_PBDC1011_SHIFT (11u) +#define GPIO_PBDC10_PBDC1012_SHIFT (12u) +#define GPIO_PBDC10_PBDC1013_SHIFT (13u) +#define GPIO_PBDC10_PBDC1014_SHIFT (14u) +#define GPIO_PBDC10_PBDC1015_SHIFT (15u) + +#define GPIO_PIPC10_PIPC100_SHIFT (0u) +#define GPIO_PIPC10_PIPC101_SHIFT (1u) +#define GPIO_PIPC10_PIPC102_SHIFT (2u) +#define GPIO_PIPC10_PIPC103_SHIFT (3u) +#define GPIO_PIPC10_PIPC104_SHIFT (4u) +#define GPIO_PIPC10_PIPC105_SHIFT (5u) +#define GPIO_PIPC10_PIPC106_SHIFT (6u) +#define GPIO_PIPC10_PIPC107_SHIFT (7u) +#define GPIO_PIPC10_PIPC108_SHIFT (8u) +#define GPIO_PIPC10_PIPC109_SHIFT (9u) +#define GPIO_PIPC10_PIPC1010_SHIFT (10u) +#define GPIO_PIPC10_PIPC1011_SHIFT (11u) +#define GPIO_PIPC10_PIPC1012_SHIFT (12u) +#define GPIO_PIPC10_PIPC1013_SHIFT (13u) +#define GPIO_PIPC10_PIPC1014_SHIFT (14u) +#define GPIO_PIPC10_PIPC1015_SHIFT (15u) + +/* ---- P11 ---- */ +#define GPIO_P11_P110_SHIFT (0u) +#define GPIO_P11_P111_SHIFT (1u) +#define GPIO_P11_P112_SHIFT (2u) +#define GPIO_P11_P113_SHIFT (3u) +#define GPIO_P11_P114_SHIFT (4u) +#define GPIO_P11_P115_SHIFT (5u) +#define GPIO_P11_P116_SHIFT (6u) +#define GPIO_P11_P117_SHIFT (7u) +#define GPIO_P11_P118_SHIFT (8u) +#define GPIO_P11_P119_SHIFT (9u) +#define GPIO_P11_P1110_SHIFT (10u) +#define GPIO_P11_P1111_SHIFT (11u) +#define GPIO_P11_P1112_SHIFT (12u) +#define GPIO_P11_P1113_SHIFT (13u) +#define GPIO_P11_P1114_SHIFT (14u) +#define GPIO_P11_P1115_SHIFT (15u) + +#define GPIO_PSR11_PSR110_SHIFT (0u) +#define GPIO_PSR11_PSR111_SHIFT (1u) +#define GPIO_PSR11_PSR112_SHIFT (2u) +#define GPIO_PSR11_PSR113_SHIFT (3u) +#define GPIO_PSR11_PSR114_SHIFT (4u) +#define GPIO_PSR11_PSR115_SHIFT (5u) +#define GPIO_PSR11_PSR116_SHIFT (6u) +#define GPIO_PSR11_PSR117_SHIFT (7u) +#define GPIO_PSR11_PSR118_SHIFT (8u) +#define GPIO_PSR11_PSR119_SHIFT (9u) +#define GPIO_PSR11_PSR1110_SHIFT (10u) +#define GPIO_PSR11_PSR1111_SHIFT (11u) +#define GPIO_PSR11_PSR1112_SHIFT (12u) +#define GPIO_PSR11_PSR1113_SHIFT (13u) +#define GPIO_PSR11_PSR1114_SHIFT (14u) +#define GPIO_PSR11_PSR1115_SHIFT (15u) +#define GPIO_PSR11_PSR1116_SHIFT (16u) +#define GPIO_PSR11_PSR1117_SHIFT (17u) +#define GPIO_PSR11_PSR1118_SHIFT (18u) +#define GPIO_PSR11_PSR1119_SHIFT (19u) +#define GPIO_PSR11_PSR1120_SHIFT (20u) +#define GPIO_PSR11_PSR1121_SHIFT (21u) +#define GPIO_PSR11_PSR1122_SHIFT (22u) +#define GPIO_PSR11_PSR1123_SHIFT (23u) +#define GPIO_PSR11_PSR1124_SHIFT (24u) +#define GPIO_PSR11_PSR1125_SHIFT (25u) +#define GPIO_PSR11_PSR1126_SHIFT (26u) +#define GPIO_PSR11_PSR1127_SHIFT (27u) +#define GPIO_PSR11_PSR1128_SHIFT (28u) +#define GPIO_PSR11_PSR1129_SHIFT (29u) +#define GPIO_PSR11_PSR1130_SHIFT (30u) +#define GPIO_PSR11_PSR1131_SHIFT (31u) + +#define GPIO_PPR11_PPR110_SHIFT (0u) +#define GPIO_PPR11_PPR111_SHIFT (1u) +#define GPIO_PPR11_PPR112_SHIFT (2u) +#define GPIO_PPR11_PPR113_SHIFT (3u) +#define GPIO_PPR11_PPR114_SHIFT (4u) +#define GPIO_PPR11_PPR115_SHIFT (5u) +#define GPIO_PPR11_PPR116_SHIFT (6u) +#define GPIO_PPR11_PPR117_SHIFT (7u) +#define GPIO_PPR11_PPR118_SHIFT (8u) +#define GPIO_PPR11_PPR119_SHIFT (9u) +#define GPIO_PPR11_PPR1110_SHIFT (10u) +#define GPIO_PPR11_PPR1111_SHIFT (11u) +#define GPIO_PPR11_PPR1112_SHIFT (12u) +#define GPIO_PPR11_PPR1113_SHIFT (13u) +#define GPIO_PPR11_PPR1114_SHIFT (14u) +#define GPIO_PPR11_PPR1115_SHIFT (15u) + +#define GPIO_PM11_PM110_SHIFT (0u) +#define GPIO_PM11_PM111_SHIFT (1u) +#define GPIO_PM11_PM112_SHIFT (2u) +#define GPIO_PM11_PM113_SHIFT (3u) +#define GPIO_PM11_PM114_SHIFT (4u) +#define GPIO_PM11_PM115_SHIFT (5u) +#define GPIO_PM11_PM116_SHIFT (6u) +#define GPIO_PM11_PM117_SHIFT (7u) +#define GPIO_PM11_PM118_SHIFT (8u) +#define GPIO_PM11_PM119_SHIFT (9u) +#define GPIO_PM11_PM1110_SHIFT (10u) +#define GPIO_PM11_PM1111_SHIFT (11u) +#define GPIO_PM11_PM1112_SHIFT (12u) +#define GPIO_PM11_PM1113_SHIFT (13u) +#define GPIO_PM11_PM1114_SHIFT (14u) +#define GPIO_PM11_PM1115_SHIFT (15u) + +#define GPIO_PMC11_PMC110_SHIFT (0u) +#define GPIO_PMC11_PMC111_SHIFT (1u) +#define GPIO_PMC11_PMC112_SHIFT (2u) +#define GPIO_PMC11_PMC113_SHIFT (3u) +#define GPIO_PMC11_PMC114_SHIFT (4u) +#define GPIO_PMC11_PMC115_SHIFT (5u) +#define GPIO_PMC11_PMC116_SHIFT (6u) +#define GPIO_PMC11_PMC117_SHIFT (7u) +#define GPIO_PMC11_PMC118_SHIFT (8u) +#define GPIO_PMC11_PMC119_SHIFT (9u) +#define GPIO_PMC11_PMC1110_SHIFT (10u) +#define GPIO_PMC11_PMC1111_SHIFT (11u) +#define GPIO_PMC11_PMC1112_SHIFT (12u) +#define GPIO_PMC11_PMC1113_SHIFT (13u) +#define GPIO_PMC11_PMC1114_SHIFT (14u) +#define GPIO_PMC11_PMC1115_SHIFT (15u) + +#define GPIO_PFC11_PFC110_SHIFT (0u) +#define GPIO_PFC11_PFC111_SHIFT (1u) +#define GPIO_PFC11_PFC112_SHIFT (2u) +#define GPIO_PFC11_PFC113_SHIFT (3u) +#define GPIO_PFC11_PFC114_SHIFT (4u) +#define GPIO_PFC11_PFC115_SHIFT (5u) +#define GPIO_PFC11_PFC116_SHIFT (6u) +#define GPIO_PFC11_PFC117_SHIFT (7u) +#define GPIO_PFC11_PFC118_SHIFT (8u) +#define GPIO_PFC11_PFC119_SHIFT (9u) +#define GPIO_PFC11_PFC1110_SHIFT (10u) +#define GPIO_PFC11_PFC1111_SHIFT (11u) +#define GPIO_PFC11_PFC1112_SHIFT (12u) +#define GPIO_PFC11_PFC1113_SHIFT (13u) +#define GPIO_PFC11_PFC1114_SHIFT (14u) +#define GPIO_PFC11_PFC1115_SHIFT (15u) + +#define GPIO_PFCE11_PFCE110_SHIFT (0u) +#define GPIO_PFCE11_PFCE111_SHIFT (1u) +#define GPIO_PFCE11_PFCE112_SHIFT (2u) +#define GPIO_PFCE11_PFCE113_SHIFT (3u) +#define GPIO_PFCE11_PFCE114_SHIFT (4u) +#define GPIO_PFCE11_PFCE115_SHIFT (5u) +#define GPIO_PFCE11_PFCE116_SHIFT (6u) +#define GPIO_PFCE11_PFCE117_SHIFT (7u) +#define GPIO_PFCE11_PFCE118_SHIFT (8u) +#define GPIO_PFCE11_PFCE119_SHIFT (9u) +#define GPIO_PFCE11_PFCE1110_SHIFT (10u) +#define GPIO_PFCE11_PFCE1111_SHIFT (11u) +#define GPIO_PFCE11_PFCE1112_SHIFT (12u) +#define GPIO_PFCE11_PFCE1113_SHIFT (13u) +#define GPIO_PFCE11_PFCE1114_SHIFT (14u) +#define GPIO_PFCE11_PFCE1115_SHIFT (15u) + +#define GPIO_PNOT11_PNOT110_SHIFT (0u) +#define GPIO_PNOT11_PNOT111_SHIFT (1u) +#define GPIO_PNOT11_PNOT112_SHIFT (2u) +#define GPIO_PNOT11_PNOT113_SHIFT (3u) +#define GPIO_PNOT11_PNOT114_SHIFT (4u) +#define GPIO_PNOT11_PNOT115_SHIFT (5u) +#define GPIO_PNOT11_PNOT116_SHIFT (6u) +#define GPIO_PNOT11_PNOT117_SHIFT (7u) +#define GPIO_PNOT11_PNOT118_SHIFT (8u) +#define GPIO_PNOT11_PNOT119_SHIFT (9u) +#define GPIO_PNOT11_PNOT1110_SHIFT (10u) +#define GPIO_PNOT11_PNOT1111_SHIFT (11u) +#define GPIO_PNOT11_PNOT1112_SHIFT (12u) +#define GPIO_PNOT11_PNOT1113_SHIFT (13u) +#define GPIO_PNOT11_PNOT1114_SHIFT (14u) +#define GPIO_PNOT11_PNOT1115_SHIFT (15u) + +#define GPIO_PMSR11_PMSR110_SHIFT (0u) +#define GPIO_PMSR11_PMSR111_SHIFT (1u) +#define GPIO_PMSR11_PMSR112_SHIFT (2u) +#define GPIO_PMSR11_PMSR113_SHIFT (3u) +#define GPIO_PMSR11_PMSR114_SHIFT (4u) +#define GPIO_PMSR11_PMSR115_SHIFT (5u) +#define GPIO_PMSR11_PMSR116_SHIFT (6u) +#define GPIO_PMSR11_PMSR117_SHIFT (7u) +#define GPIO_PMSR11_PMSR118_SHIFT (8u) +#define GPIO_PMSR11_PMSR119_SHIFT (9u) +#define GPIO_PMSR11_PMSR1110_SHIFT (10u) +#define GPIO_PMSR11_PMSR1111_SHIFT (11u) +#define GPIO_PMSR11_PMSR1112_SHIFT (12u) +#define GPIO_PMSR11_PMSR1113_SHIFT (13u) +#define GPIO_PMSR11_PMSR1114_SHIFT (14u) +#define GPIO_PMSR11_PMSR1115_SHIFT (15u) +#define GPIO_PMSR11_PMSR1116_SHIFT (16u) +#define GPIO_PMSR11_PMSR1117_SHIFT (17u) +#define GPIO_PMSR11_PMSR1118_SHIFT (18u) +#define GPIO_PMSR11_PMSR1119_SHIFT (19u) +#define GPIO_PMSR11_PMSR1120_SHIFT (20u) +#define GPIO_PMSR11_PMSR1121_SHIFT (21u) +#define GPIO_PMSR11_PMSR1122_SHIFT (22u) +#define GPIO_PMSR11_PMSR1123_SHIFT (23u) +#define GPIO_PMSR11_PMSR1124_SHIFT (24u) +#define GPIO_PMSR11_PMSR1125_SHIFT (25u) +#define GPIO_PMSR11_PMSR1126_SHIFT (26u) +#define GPIO_PMSR11_PMSR1127_SHIFT (27u) +#define GPIO_PMSR11_PMSR1128_SHIFT (28u) +#define GPIO_PMSR11_PMSR1129_SHIFT (29u) +#define GPIO_PMSR11_PMSR1130_SHIFT (30u) +#define GPIO_PMSR11_PMSR1131_SHIFT (31u) + +#define GPIO_PMCSR11_PMCSR110_SHIFT (0u) +#define GPIO_PMCSR11_PMCSR111_SHIFT (1u) +#define GPIO_PMCSR11_PMCSR112_SHIFT (2u) +#define GPIO_PMCSR11_PMCSR113_SHIFT (3u) +#define GPIO_PMCSR11_PMCSR114_SHIFT (4u) +#define GPIO_PMCSR11_PMCSR115_SHIFT (5u) +#define GPIO_PMCSR11_PMCSR116_SHIFT (6u) +#define GPIO_PMCSR11_PMCSR117_SHIFT (7u) +#define GPIO_PMCSR11_PMCSR118_SHIFT (8u) +#define GPIO_PMCSR11_PMCSR119_SHIFT (9u) +#define GPIO_PMCSR11_PMCSR1110_SHIFT (10u) +#define GPIO_PMCSR11_PMCSR1111_SHIFT (11u) +#define GPIO_PMCSR11_PMCSR1112_SHIFT (12u) +#define GPIO_PMCSR11_PMCSR1113_SHIFT (13u) +#define GPIO_PMCSR11_PMCSR1114_SHIFT (14u) +#define GPIO_PMCSR11_PMCSR1115_SHIFT (15u) +#define GPIO_PMCSR11_PMCSR1116_SHIFT (16u) +#define GPIO_PMCSR11_PMCSR1117_SHIFT (17u) +#define GPIO_PMCSR11_PMCSR1118_SHIFT (18u) +#define GPIO_PMCSR11_PMCSR1119_SHIFT (19u) +#define GPIO_PMCSR11_PMCSR1120_SHIFT (20u) +#define GPIO_PMCSR11_PMCSR1121_SHIFT (21u) +#define GPIO_PMCSR11_PMCSR1122_SHIFT (22u) +#define GPIO_PMCSR11_PMCSR1123_SHIFT (23u) +#define GPIO_PMCSR11_PMCSR1124_SHIFT (24u) +#define GPIO_PMCSR11_PMCSR1125_SHIFT (25u) +#define GPIO_PMCSR11_PMCSR1126_SHIFT (26u) +#define GPIO_PMCSR11_PMCSR1127_SHIFT (27u) +#define GPIO_PMCSR11_PMCSR1128_SHIFT (28u) +#define GPIO_PMCSR11_PMCSR1129_SHIFT (29u) +#define GPIO_PMCSR11_PMCSR1130_SHIFT (30u) +#define GPIO_PMCSR11_PMCSR1131_SHIFT (31u) + +#define GPIO_PFCAE11_PFCAE110_SHIFT (0u) +#define GPIO_PFCAE11_PFCAE111_SHIFT (1u) +#define GPIO_PFCAE11_PFCAE112_SHIFT (2u) +#define GPIO_PFCAE11_PFCAE113_SHIFT (3u) +#define GPIO_PFCAE11_PFCAE114_SHIFT (4u) +#define GPIO_PFCAE11_PFCAE115_SHIFT (5u) +#define GPIO_PFCAE11_PFCAE116_SHIFT (6u) +#define GPIO_PFCAE11_PFCAE117_SHIFT (7u) +#define GPIO_PFCAE11_PFCAE118_SHIFT (8u) +#define GPIO_PFCAE11_PFCAE119_SHIFT (9u) +#define GPIO_PFCAE11_PFCAE1110_SHIFT (10u) +#define GPIO_PFCAE11_PFCAE1111_SHIFT (11u) +#define GPIO_PFCAE11_PFCAE1112_SHIFT (12u) +#define GPIO_PFCAE11_PFCAE1113_SHIFT (13u) +#define GPIO_PFCAE11_PFCAE1114_SHIFT (14u) +#define GPIO_PFCAE11_PFCAE1115_SHIFT (15u) + +#define GPIO_PIBC11_PIBC110_SHIFT (0u) +#define GPIO_PIBC11_PIBC111_SHIFT (1u) +#define GPIO_PIBC11_PIBC112_SHIFT (2u) +#define GPIO_PIBC11_PIBC113_SHIFT (3u) +#define GPIO_PIBC11_PIBC114_SHIFT (4u) +#define GPIO_PIBC11_PIBC115_SHIFT (5u) +#define GPIO_PIBC11_PIBC116_SHIFT (6u) +#define GPIO_PIBC11_PIBC117_SHIFT (7u) +#define GPIO_PIBC11_PIBC118_SHIFT (8u) +#define GPIO_PIBC11_PIBC119_SHIFT (9u) +#define GPIO_PIBC11_PIBC1110_SHIFT (10u) +#define GPIO_PIBC11_PIBC1111_SHIFT (11u) +#define GPIO_PIBC11_PIBC1112_SHIFT (12u) +#define GPIO_PIBC11_PIBC1113_SHIFT (13u) +#define GPIO_PIBC11_PIBC1114_SHIFT (14u) +#define GPIO_PIBC11_PIBC1115_SHIFT (15u) + +#define GPIO_PBDC11_PBDC110_SHIFT (0u) +#define GPIO_PBDC11_PBDC111_SHIFT (1u) +#define GPIO_PBDC11_PBDC112_SHIFT (2u) +#define GPIO_PBDC11_PBDC113_SHIFT (3u) +#define GPIO_PBDC11_PBDC114_SHIFT (4u) +#define GPIO_PBDC11_PBDC115_SHIFT (5u) +#define GPIO_PBDC11_PBDC116_SHIFT (6u) +#define GPIO_PBDC11_PBDC117_SHIFT (7u) +#define GPIO_PBDC11_PBDC118_SHIFT (8u) +#define GPIO_PBDC11_PBDC119_SHIFT (9u) +#define GPIO_PBDC11_PBDC1110_SHIFT (10u) +#define GPIO_PBDC11_PBDC1111_SHIFT (11u) +#define GPIO_PBDC11_PBDC1112_SHIFT (12u) +#define GPIO_PBDC11_PBDC1113_SHIFT (13u) +#define GPIO_PBDC11_PBDC1114_SHIFT (14u) +#define GPIO_PBDC11_PBDC1115_SHIFT (15u) + +#define GPIO_PIPC11_PIPC110_SHIFT (0u) +#define GPIO_PIPC11_PIPC111_SHIFT (1u) +#define GPIO_PIPC11_PIPC112_SHIFT (2u) +#define GPIO_PIPC11_PIPC113_SHIFT (3u) +#define GPIO_PIPC11_PIPC114_SHIFT (4u) +#define GPIO_PIPC11_PIPC115_SHIFT (5u) +#define GPIO_PIPC11_PIPC116_SHIFT (6u) +#define GPIO_PIPC11_PIPC117_SHIFT (7u) +#define GPIO_PIPC11_PIPC118_SHIFT (8u) +#define GPIO_PIPC11_PIPC119_SHIFT (9u) +#define GPIO_PIPC11_PIPC1110_SHIFT (10u) +#define GPIO_PIPC11_PIPC1111_SHIFT (11u) +#define GPIO_PIPC11_PIPC1112_SHIFT (12u) +#define GPIO_PIPC11_PIPC1113_SHIFT (13u) +#define GPIO_PIPC11_PIPC1114_SHIFT (14u) +#define GPIO_PIPC11_PIPC1115_SHIFT (15u) + + +#endif /* GPIO_IOBITMASK_H */ + +/* End of File */ diff --git a/targets/TARGET_RENESAS/TARGET_RZ_A1XX/TARGET_GR_LYCHEE/device/inc/iobitmasks/intc_iobitmask.h b/targets/TARGET_RENESAS/TARGET_RZ_A1XX/TARGET_GR_LYCHEE/device/inc/iobitmasks/intc_iobitmask.h new file mode 100644 index 0000000..e1b95cb --- /dev/null +++ b/targets/TARGET_RENESAS/TARGET_RZ_A1XX/TARGET_GR_LYCHEE/device/inc/iobitmasks/intc_iobitmask.h @@ -0,0 +1,11236 @@ +/******************************************************************************* +* DISCLAIMER +* This software is supplied by Renesas Electronics Corporation and is only +* intended for use with Renesas products. No other uses are authorized. This +* software is owned by Renesas Electronics Corporation and is protected under +* all applicable laws, including copyright laws. +* THIS SOFTWARE IS PROVIDED "AS IS" AND RENESAS MAKES NO WARRANTIES REGARDING +* THIS SOFTWARE, WHETHER EXPRESS, IMPLIED OR STATUTORY, INCLUDING BUT NOT +* LIMITED TO WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE +* AND NON-INFRINGEMENT. ALL SUCH WARRANTIES ARE EXPRESSLY DISCLAIMED. +* TO THE MAXIMUM EXTENT PERMITTED NOT PROHIBITED BY LAW, NEITHER RENESAS +* ELECTRONICS CORPORATION NOR ANY OF ITS AFFILIATED COMPANIES SHALL BE LIABLE +* FOR ANY DIRECT, INDIRECT, SPECIAL, INCIDENTAL OR CONSEQUENTIAL DAMAGES FOR +* ANY REASON RELATED TO THIS SOFTWARE, EVEN IF RENESAS OR ITS AFFILIATES HAVE +* BEEN ADVISED OF THE POSSIBILITY OF SUCH DAMAGES. +* Renesas reserves the right, without notice, to make changes to this software +* and to discontinue the availability of this software. By using this software, +* you agree to the additional terms and conditions found by accessing the +* following link: +* http://www.renesas.com/disclaimer +* Copyright (C) 2012 - 2014 Renesas Electronics Corporation. All rights reserved. +*******************************************************************************/ +/******************************************************************************* +* File Name : intc_iobitmask.h +* $Rev: 1115 $ +* $Date:: 2014-07-09 15:35:02 +0900#$ +* Description : INTC register define header +*******************************************************************************/ +#ifndef INTC_IOBITMASK_H +#define INTC_IOBITMASK_H + +/* ==== Mask values for IO registers ==== */ +#define INTC_ICDDCR_Enable (0x00000001uL) + +#define INTC_ICDICTR_ITLinesNumber (0x0000001FuL) +#define INTC_ICDICTR_CPUNumber (0x000000E0uL) +#define INTC_ICDICTR_SecurityExtn (0x00000400uL) +#define INTC_ICDICTR_LSPI (0x0000F800uL) + +#define INTC_ICDIIDR_Implementer (0x00000FFFuL) +#define INTC_ICDIIDR_Revision (0x0000F000uL) +#define INTC_ICDIIDR_Variant (0x000F0000uL) +#define INTC_ICDIIDR_ProductID (0xFF000000uL) + +#define INTC_ICDISR0_SW0 (0x00000001uL) +#define INTC_ICDISR0_SW1 (0x00000002uL) +#define INTC_ICDISR0_SW2 (0x00000004uL) +#define INTC_ICDISR0_SW3 (0x00000008uL) +#define INTC_ICDISR0_SW4 (0x00000010uL) +#define INTC_ICDISR0_SW5 (0x00000020uL) +#define INTC_ICDISR0_SW6 (0x00000040uL) +#define INTC_ICDISR0_SW7 (0x00000080uL) +#define INTC_ICDISR0_SW8 (0x00000100uL) +#define INTC_ICDISR0_SW9 (0x00000200uL) +#define INTC_ICDISR0_SW10 (0x00000400uL) +#define INTC_ICDISR0_SW11 (0x00000800uL) +#define INTC_ICDISR0_SW12 (0x00001000uL) +#define INTC_ICDISR0_SW13 (0x00002000uL) +#define INTC_ICDISR0_SW14 (0x00004000uL) +#define INTC_ICDISR0_SW15 (0x00008000uL) +#define INTC_ICDISR0_PMUIRQ0 (0x00010000uL) +#define INTC_ICDISR0_COMMRX0 (0x00020000uL) +#define INTC_ICDISR0_COMMTX0 (0x00040000uL) +#define INTC_ICDISR0_CTIIRQ0 (0x00080000uL) + +#define INTC_ICDISR1_IRQ0 (0x00000001uL) +#define INTC_ICDISR1_IRQ1 (0x00000002uL) +#define INTC_ICDISR1_IRQ2 (0x00000004uL) +#define INTC_ICDISR1_IRQ3 (0x00000008uL) +#define INTC_ICDISR1_IRQ4 (0x00000010uL) +#define INTC_ICDISR1_IRQ5 (0x00000020uL) +#define INTC_ICDISR1_IRQ6 (0x00000040uL) +#define INTC_ICDISR1_IRQ7 (0x00000080uL) +#define INTC_ICDISR1_PL310ERR (0x00000100uL) +#define INTC_ICDISR1_DMAINT0 (0x00000200uL) +#define INTC_ICDISR1_DMAINT1 (0x00000400uL) +#define INTC_ICDISR1_DMAINT2 (0x00000800uL) +#define INTC_ICDISR1_DMAINT3 (0x00001000uL) +#define INTC_ICDISR1_DMAINT4 (0x00002000uL) +#define INTC_ICDISR1_DMAINT5 (0x00004000uL) +#define INTC_ICDISR1_DMAINT6 (0x00008000uL) +#define INTC_ICDISR1_DMAINT7 (0x00010000uL) +#define INTC_ICDISR1_DMAINT8 (0x00020000uL) +#define INTC_ICDISR1_DMAINT9 (0x00040000uL) +#define INTC_ICDISR1_DMAINT10 (0x00080000uL) +#define INTC_ICDISR1_DMAINT11 (0x00100000uL) +#define INTC_ICDISR1_DMAINT12 (0x00200000uL) +#define INTC_ICDISR1_DMAINT13 (0x00400000uL) +#define INTC_ICDISR1_DMAINT14 (0x00800000uL) +#define INTC_ICDISR1_DMAINT15 (0x01000000uL) +#define INTC_ICDISR1_DMAERR (0x02000000uL) + +#define INTC_ICDISR2_USBI0 (0x00000200uL) +#define INTC_ICDISR2_USBI1 (0x00000400uL) +#define INTC_ICDISR2_S0_VI_VSYNC0 (0x00000800uL) +#define INTC_ICDISR2_S0_LO_VSYNC0 (0x00001000uL) +#define INTC_ICDISR2_S0_VSYNCERR0 (0x00002000uL) +#define INTC_ICDISR2_GR3_VLINE0 (0x00004000uL) +#define INTC_ICDISR2_S0_VFIELD0 (0x00008000uL) +#define INTC_ICDISR2_IV1_VBUFERR0 (0x00010000uL) +#define INTC_ICDISR2_IV3_VBUFERR0 (0x00020000uL) +#define INTC_ICDISR2_IV5_VBUFERR0 (0x00040000uL) +#define INTC_ICDISR2_IV6_VBUFERR0 (0x00080000uL) +#define INTC_ICDISR2_S0_WLINE0 (0x00100000uL) +#define INTC_ICDISR2_S1_VI_VSYNC0 (0x00200000uL) +#define INTC_ICDISR2_S1_LO_VSYNC0 (0x00400000uL) +#define INTC_ICDISR2_S1_VSYNCERR0 (0x00800000uL) +#define INTC_ICDISR2_S1_VFIELD0 (0x01000000uL) +#define INTC_ICDISR2_IV2_VBUFERR0 (0x02000000uL) +#define INTC_ICDISR2_IV4_VBUFERR0 (0x04000000uL) +#define INTC_ICDISR2_S1_WLINE0 (0x08000000uL) +#define INTC_ICDISR2_OIR_VI_VSYNC0 (0x10000000uL) +#define INTC_ICDISR2_OIR_LO_VSYNC0 (0x20000000uL) +#define INTC_ICDISR2_OIR_VSYNCERR0 (0x40000000uL) +#define INTC_ICDISR2_OIR_VFIELD0 (0x80000000uL) + +#define INTC_ICDISR3_IV7_VBUFERR0 (0x00000001uL) +#define INTC_ICDISR3_IV8_VBUFERR0 (0x00000002uL) +#define INTC_ICDISR3_S0_VI_VSYNC1 (0x00000008uL) +#define INTC_ICDISR3_S0_LO_VSYNC1 (0x00000010uL) +#define INTC_ICDISR3_S0_VSYNCERR1 (0x00000020uL) +#define INTC_ICDISR3_GR3_VLINE1 (0x00000040uL) +#define INTC_ICDISR3_S0_VFIELD1 (0x00000080uL) +#define INTC_ICDISR3_IV1_VBUFERR1 (0x00000100uL) +#define INTC_ICDISR3_IV3_VBUFERR1 (0x00000200uL) +#define INTC_ICDISR3_IV5_VBUFERR1 (0x00000400uL) +#define INTC_ICDISR3_IV6_VBUFERR1 (0x00000800uL) +#define INTC_ICDISR3_S0_WLINE1 (0x00001000uL) +#define INTC_ICDISR3_S1_VI_VSYNC1 (0x00002000uL) +#define INTC_ICDISR3_S1_LO_VSYNC1 (0x00004000uL) +#define INTC_ICDISR3_S1_VSYNCERR1 (0x00008000uL) +#define INTC_ICDISR3_S1_VFIELD1 (0x00010000uL) +#define INTC_ICDISR3_IV2_VBUFERR1 (0x00020000uL) +#define INTC_ICDISR3_IV4_VBUFERR1 (0x00040000uL) +#define INTC_ICDISR3_S1_WLINE1 (0x00080000uL) +#define INTC_ICDISR3_OIR_VI_VSYNC1 (0x00100000uL) +#define INTC_ICDISR3_OIR_LO_VSYNC1 (0x00200000uL) +#define INTC_ICDISR3_OIR_VLINE1 (0x00400000uL) +#define INTC_ICDISR3_OIR_VFIELD1 (0x00800000uL) +#define INTC_ICDISR3_IV7_VBUFERR1 (0x01000000uL) +#define INTC_ICDISR3_IV8_VBUFERR1 (0x02000000uL) +#define INTC_ICDISR3_IMRDI (0x08000000uL) +#define INTC_ICDISR3_IMR2I0 (0x10000000uL) +#define INTC_ICDISR3_IMR2I1 (0x20000000uL) +#define INTC_ICDISR3_JEDI (0x40000000uL) +#define INTC_ICDISR3_JDTI (0x80000000uL) + +#define INTC_ICDISR4_CMP0 (0x00000001uL) +#define INTC_ICDISR4_CMP1 (0x00000002uL) +#define INTC_ICDISR4_INT0 (0x00000004uL) +#define INTC_ICDISR4_INT1 (0x00000008uL) +#define INTC_ICDISR4_INT2 (0x00000010uL) +#define INTC_ICDISR4_INT3 (0x00000020uL) +#define INTC_ICDISR4_OSTM0TINT (0x00000040uL) +#define INTC_ICDISR4_OSTM1TINT (0x00000080uL) +#define INTC_ICDISR4_CMI (0x00000100uL) +#define INTC_ICDISR4_WTOUT (0x00000200uL) +#define INTC_ICDISR4_ITI (0x00000400uL) +#define INTC_ICDISR4_TGI0A (0x00000800uL) +#define INTC_ICDISR4_TGI0B (0x00001000uL) +#define INTC_ICDISR4_TGI0C (0x00002000uL) +#define INTC_ICDISR4_TGI0D (0x00004000uL) +#define INTC_ICDISR4_TGI0V (0x00008000uL) +#define INTC_ICDISR4_TGI0E (0x00010000uL) +#define INTC_ICDISR4_TGI0F (0x00020000uL) +#define INTC_ICDISR4_TGI1A (0x00040000uL) +#define INTC_ICDISR4_TGI1B (0x00080000uL) +#define INTC_ICDISR4_TGI1V (0x00100000uL) +#define INTC_ICDISR4_TGI1U (0x00200000uL) +#define INTC_ICDISR4_TGI2A (0x00400000uL) +#define INTC_ICDISR4_TGI2B (0x00800000uL) +#define INTC_ICDISR4_TGI2V (0x01000000uL) +#define INTC_ICDISR4_TGI2U (0x02000000uL) +#define INTC_ICDISR4_TGI3A (0x04000000uL) +#define INTC_ICDISR4_TGI3B (0x08000000uL) +#define INTC_ICDISR4_TGI3C (0x10000000uL) +#define INTC_ICDISR4_TGI3D (0x20000000uL) +#define INTC_ICDISR4_TGI3V (0x40000000uL) +#define INTC_ICDISR4_TGI4A (0x80000000uL) + +#define INTC_ICDISR5_TGI4B (0x00000001uL) +#define INTC_ICDISR5_TGI4C (0x00000002uL) +#define INTC_ICDISR5_TGI4D (0x00000004uL) +#define INTC_ICDISR5_TGI4V (0x00000008uL) +#define INTC_ICDISR5_CMI1 (0x00000010uL) +#define INTC_ICDISR5_CMI2 (0x00000020uL) +#define INTC_ICDISR5_SGDEI0 (0x00000040uL) +#define INTC_ICDISR5_SGDEI1 (0x00000080uL) +#define INTC_ICDISR5_SGDEI2 (0x00000100uL) +#define INTC_ICDISR5_SGDEI3 (0x00000200uL) +#define INTC_ICDISR5_ADI (0x00000400uL) +#define INTC_ICDISR5_LMTI (0x00000800uL) +#define INTC_ICDISR5_SSII0 (0x00001000uL) +#define INTC_ICDISR5_SSIRXI0 (0x00002000uL) +#define INTC_ICDISR5_SSITXI0 (0x00004000uL) +#define INTC_ICDISR5_SSII1 (0x00008000uL) +#define INTC_ICDISR5_SSIRXI1 (0x00010000uL) +#define INTC_ICDISR5_SSITXI1 (0x00020000uL) +#define INTC_ICDISR5_SSII2 (0x00040000uL) +#define INTC_ICDISR5_SSIRTI2 (0x00080000uL) +#define INTC_ICDISR5_SSII3 (0x00100000uL) +#define INTC_ICDISR5_SSIRXI3 (0x00200000uL) +#define INTC_ICDISR5_SSITXI3 (0x00400000uL) +#define INTC_ICDISR5_SSII4 (0x00800000uL) +#define INTC_ICDISR5_SSIRTI4 (0x01000000uL) +#define INTC_ICDISR5_SSII5 (0x02000000uL) +#define INTC_ICDISR5_SSIRXI5 (0x04000000uL) +#define INTC_ICDISR5_SSITXI5 (0x08000000uL) +#define INTC_ICDISR5_SPDIFI (0x10000000uL) +#define INTC_ICDISR5_INTIICTEI0 (0x20000000uL) +#define INTC_ICDISR5_INTIICRI0 (0x40000000uL) +#define INTC_ICDISR5_INTIICTI0 (0x80000000uL) + +#define INTC_ICDISR6_INTIICSPI0 (0x00000001uL) +#define INTC_ICDISR6_INTIICSTI0 (0x00000002uL) +#define INTC_ICDISR6_INTIICNAKI0 (0x00000004uL) +#define INTC_ICDISR6_INTIICALI0 (0x00000008uL) +#define INTC_ICDISR6_INTIICTMOI0 (0x00000010uL) +#define INTC_ICDISR6_INTIICTEI1 (0x00000020uL) +#define INTC_ICDISR6_INTIICRI1 (0x00000040uL) +#define INTC_ICDISR6_INTIICTI1 (0x00000080uL) +#define INTC_ICDISR6_INTIICSPI1 (0x00000100uL) +#define INTC_ICDISR6_INTIICSTI1 (0x00000200uL) +#define INTC_ICDISR6_INTIICNAKI1 (0x00000400uL) +#define INTC_ICDISR6_INTIICALI1 (0x00000800uL) +#define INTC_ICDISR6_INTIICTMOI1 (0x00001000uL) +#define INTC_ICDISR6_INTIICTEI2 (0x00002000uL) +#define INTC_ICDISR6_INTIICRI2 (0x00004000uL) +#define INTC_ICDISR6_INTIICTI2 (0x00008000uL) +#define INTC_ICDISR6_INTIICSPI2 (0x00010000uL) +#define INTC_ICDISR6_INTIICSTI2 (0x00020000uL) +#define INTC_ICDISR6_INTIICNAKI2 (0x00040000uL) +#define INTC_ICDISR6_INTIICALI2 (0x00080000uL) +#define INTC_ICDISR6_INTIICTMOI2 (0x00100000uL) +#define INTC_ICDISR6_INTIICTEI3 (0x00200000uL) +#define INTC_ICDISR6_INTIICRI3 (0x00400000uL) +#define INTC_ICDISR6_INTIICTI3 (0x00800000uL) +#define INTC_ICDISR6_INTIICSPI3 (0x01000000uL) +#define INTC_ICDISR6_INTIICSTI3 (0x02000000uL) +#define INTC_ICDISR6_INTIICNAKI3 (0x04000000uL) +#define INTC_ICDISR6_INTIICALI3 (0x08000000uL) +#define INTC_ICDISR6_INTIICTMOI3 (0x10000000uL) +#define INTC_ICDISR6_BRI0 (0x20000000uL) +#define INTC_ICDISR6_ERI0 (0x40000000uL) +#define INTC_ICDISR6_RXI0 (0x80000000uL) + +#define INTC_ICDISR7_TXI0 (0x00000001uL) +#define INTC_ICDISR7_BRI1 (0x00000002uL) +#define INTC_ICDISR7_ERI1 (0x00000004uL) +#define INTC_ICDISR7_RXI1 (0x00000008uL) +#define INTC_ICDISR7_TXI1 (0x00000010uL) +#define INTC_ICDISR7_BRI2 (0x00000020uL) +#define INTC_ICDISR7_ERI2 (0x00000040uL) +#define INTC_ICDISR7_RXI2 (0x00000080uL) +#define INTC_ICDISR7_TXI2 (0x00000100uL) +#define INTC_ICDISR7_BRI3 (0x00000200uL) +#define INTC_ICDISR7_ERI3 (0x00000400uL) +#define INTC_ICDISR7_RXI3 (0x00000800uL) +#define INTC_ICDISR7_TXI3 (0x00001000uL) +#define INTC_ICDISR7_BRI4 (0x00002000uL) +#define INTC_ICDISR7_ERI4 (0x00004000uL) +#define INTC_ICDISR7_RXI4 (0x00008000uL) +#define INTC_ICDISR7_TXI4 (0x00010000uL) +#define INTC_ICDISR7_BRI5 (0x00020000uL) +#define INTC_ICDISR7_ERI5 (0x00040000uL) +#define INTC_ICDISR7_RXI5 (0x00080000uL) +#define INTC_ICDISR7_TXI5 (0x00100000uL) +#define INTC_ICDISR7_BRI6 (0x00200000uL) +#define INTC_ICDISR7_ERI6 (0x00400000uL) +#define INTC_ICDISR7_RXI6 (0x00800000uL) +#define INTC_ICDISR7_TXI6 (0x01000000uL) +#define INTC_ICDISR7_BRI7 (0x02000000uL) +#define INTC_ICDISR7_ERI7 (0x04000000uL) +#define INTC_ICDISR7_RXI7 (0x08000000uL) +#define INTC_ICDISR7_TXI7 (0x10000000uL) +#define INTC_ICDISR7_INTRCANGERR (0x20000000uL) +#define INTC_ICDISR7_INTRCANGRECC (0x40000000uL) +#define INTC_ICDISR7_INTRCAN0REC (0x80000000uL) + +#define INTC_ICDISR8_INTRCAN0ERR (0x00000001uL) +#define INTC_ICDISR8_INTRCAN0TRX (0x00000002uL) +#define INTC_ICDISR8_INTRCAN1REC (0x00000004uL) +#define INTC_ICDISR8_INTRCAN1ERR (0x00000008uL) +#define INTC_ICDISR8_INTRCAN1TRX (0x00000010uL) +#define INTC_ICDISR8_INTRCAN2REC (0x00000020uL) +#define INTC_ICDISR8_INTRCAN2ERR (0x00000040uL) +#define INTC_ICDISR8_INTRCAN2TRX (0x00000080uL) +#define INTC_ICDISR8_INTRCAN3REC (0x00000100uL) +#define INTC_ICDISR8_INTRCAN3ERR (0x00000200uL) +#define INTC_ICDISR8_INTRCAN3TRX (0x00000400uL) +#define INTC_ICDISR8_INTRCAN4REC (0x00000800uL) +#define INTC_ICDISR8_INTRCAN4ERR (0x00001000uL) +#define INTC_ICDISR8_INTRCAN4TRX (0x00002000uL) +#define INTC_ICDISR8_SPEI0 (0x00004000uL) +#define INTC_ICDISR8_SPRI0 (0x00008000uL) +#define INTC_ICDISR8_SPTI0 (0x00010000uL) +#define INTC_ICDISR8_SPEI1 (0x00020000uL) +#define INTC_ICDISR8_SPRI1 (0x00040000uL) +#define INTC_ICDISR8_SPTI1 (0x00080000uL) +#define INTC_ICDISR8_SPEI2 (0x00100000uL) +#define INTC_ICDISR8_SPRI2 (0x00200000uL) +#define INTC_ICDISR8_SPTI2 (0x00400000uL) +#define INTC_ICDISR8_SPEI3 (0x00800000uL) +#define INTC_ICDISR8_SPRI3 (0x01000000uL) +#define INTC_ICDISR8_SPTI3 (0x02000000uL) +#define INTC_ICDISR8_SPEI4 (0x04000000uL) +#define INTC_ICDISR8_SPRI4 (0x08000000uL) +#define INTC_ICDISR8_SPTI4 (0x10000000uL) +#define INTC_ICDISR8_IEBBTD (0x20000000uL) +#define INTC_ICDISR8_IEBBTERR (0x40000000uL) +#define INTC_ICDISR8_IEBBTSTA (0x80000000uL) + +#define INTC_ICDISR9_IEBBTV (0x00000001uL) +#define INTC_ICDISR9_ISY (0x00000002uL) +#define INTC_ICDISR9_IERR (0x00000004uL) +#define INTC_ICDISR9_ITARG (0x00000008uL) +#define INTC_ICDISR9_ISEC (0x00000010uL) +#define INTC_ICDISR9_IBUF (0x00000020uL) +#define INTC_ICDISR9_IREADY (0x00000040uL) +#define INTC_ICDISR9_FLSTE (0x00000080uL) +#define INTC_ICDISR9_FLTENDI (0x00000100uL) +#define INTC_ICDISR9_FLTREQ0I (0x00000200uL) +#define INTC_ICDISR9_FLTREQ1I (0x00000400uL) +#define INTC_ICDISR9_MMC0 (0x00000800uL) +#define INTC_ICDISR9_MMC1 (0x00001000uL) +#define INTC_ICDISR9_MMC2 (0x00002000uL) +#define INTC_ICDISR9_SDHI0_3 (0x00004000uL) +#define INTC_ICDISR9_SDHI0_0 (0x00008000uL) +#define INTC_ICDISR9_SDHI0_1 (0x00010000uL) +#define INTC_ICDISR9_SDHI1_3 (0x00020000uL) +#define INTC_ICDISR9_SDHI1_0 (0x00040000uL) +#define INTC_ICDISR9_SDHI1_1 (0x00080000uL) +#define INTC_ICDISR9_ARM (0x00100000uL) +#define INTC_ICDISR9_PRD (0x00200000uL) +#define INTC_ICDISR9_CUP (0x00400000uL) +#define INTC_ICDISR9_SCUAI0 (0x00800000uL) +#define INTC_ICDISR9_SCUAI1 (0x01000000uL) +#define INTC_ICDISR9_SCUFDI0 (0x02000000uL) +#define INTC_ICDISR9_SCUFDI1 (0x04000000uL) +#define INTC_ICDISR9_SCUFDI2 (0x08000000uL) +#define INTC_ICDISR9_SCUFDI3 (0x10000000uL) +#define INTC_ICDISR9_SCUFUI0 (0x20000000uL) +#define INTC_ICDISR9_SCUFUI1 (0x40000000uL) +#define INTC_ICDISR9_SCUFUI2 (0x80000000uL) + +#define INTC_ICDISR10_SCUFUI3 (0x00000001uL) +#define INTC_ICDISR10_SCUDVI0 (0x00000002uL) +#define INTC_ICDISR10_SCUDVI1 (0x00000004uL) +#define INTC_ICDISR10_SCUDVI2 (0x00000008uL) +#define INTC_ICDISR10_SCUDVI3 (0x00000010uL) +#define INTC_ICDISR10_MLB_CINT (0x00000020uL) +#define INTC_ICDISR10_MLB_SINT (0x00000040uL) +#define INTC_ICDISR10_DRC0 (0x00000080uL) +#define INTC_ICDISR10_DRC1 (0x00000100uL) +#define INTC_ICDISR10_LINI0_INT_T (0x00000800uL) +#define INTC_ICDISR10_LINI0_INT_R (0x00001000uL) +#define INTC_ICDISR10_LINI0_INT_S (0x00002000uL) +#define INTC_ICDISR10_LINI0_INT_M (0x00004000uL) +#define INTC_ICDISR10_LINI1_INT_T (0x00008000uL) +#define INTC_ICDISR10_LINI1_INT_R (0x00010000uL) +#define INTC_ICDISR10_LINI1_INT_S (0x00020000uL) +#define INTC_ICDISR10_LINI1_INT_M (0x00040000uL) +#define INTC_ICDISR10_ERI0 (0x08000000uL) +#define INTC_ICDISR10_RXI0 (0x10000000uL) +#define INTC_ICDISR10_TXI0 (0x20000000uL) +#define INTC_ICDISR10_TEI0 (0x40000000uL) +#define INTC_ICDISR10_ERI1 (0x80000000uL) + +#define INTC_ICDISR11_RXI1 (0x00000001uL) +#define INTC_ICDISR11_TXI1 (0x00000002uL) +#define INTC_ICDISR11_TEI1 (0x00000004uL) +#define INTC_ICDISR11_AVBI_DATA (0x00000008uL) +#define INTC_ICDISR11_AVBI_ERROR (0x00000010uL) +#define INTC_ICDISR11_AVBI_MANAGE (0x00000020uL) +#define INTC_ICDISR11_AVBI_MAC (0x00000040uL) +#define INTC_ICDISR11_ETHERI (0x00000080uL) +#define INTC_ICDISR11_CEUI (0x00001000uL) +#define INTC_ICDISR11_H2XMLB_ERRINT (0x20000000uL) +#define INTC_ICDISR11_H2XIC1_ERRINT (0x40000000uL) +#define INTC_ICDISR11_X2HPERI1_ERRINT (0x80000000uL) + +#define INTC_ICDISR12_X2HPERI2_ERRINT (0x00000001uL) +#define INTC_ICDISR12_X2HPERI34_ERRINT (0x00000002uL) +#define INTC_ICDISR12_X2HPERI5_ERRINT (0x00000004uL) +#define INTC_ICDISR12_X2HPERI67_ERRINT (0x00000008uL) +#define INTC_ICDISR12_X2HDBGR_ERRINT (0x00000010uL) +#define INTC_ICDISR12_X2HBSC_ERRINT (0x00000020uL) +#define INTC_ICDISR12_X2HSPI1_ERRINT (0x00000040uL) +#define INTC_ICDISR12_X2HSPI2_ERRINT (0x00000080uL) +#define INTC_ICDISR12_PRRI (0x00000100uL) +#define INTC_ICDISR12_IFEI0 (0x00000200uL) +#define INTC_ICDISR12_OFFI0 (0x00000400uL) +#define INTC_ICDISR12_PFVEI0 (0x00000800uL) +#define INTC_ICDISR12_IFEI1 (0x00001000uL) +#define INTC_ICDISR12_OFFI1 (0x00002000uL) +#define INTC_ICDISR12_PFVEI1 (0x00004000uL) + +#define INTC_ICDISR13_TINT0 (0x00000001uL) +#define INTC_ICDISR13_TINT1 (0x00000002uL) +#define INTC_ICDISR13_TINT2 (0x00000004uL) +#define INTC_ICDISR13_TINT3 (0x00000008uL) +#define INTC_ICDISR13_TINT4 (0x00000010uL) +#define INTC_ICDISR13_TINT5 (0x00000020uL) +#define INTC_ICDISR13_TINT6 (0x00000040uL) +#define INTC_ICDISR13_TINT7 (0x00000080uL) +#define INTC_ICDISR13_TINT8 (0x00000100uL) +#define INTC_ICDISR13_TINT9 (0x00000200uL) +#define INTC_ICDISR13_TINT10 (0x00000400uL) +#define INTC_ICDISR13_TINT11 (0x00000800uL) +#define INTC_ICDISR13_TINT12 (0x00001000uL) +#define INTC_ICDISR13_TINT13 (0x00002000uL) +#define INTC_ICDISR13_TINT14 (0x00004000uL) +#define INTC_ICDISR13_TINT15 (0x00008000uL) +#define INTC_ICDISR13_TINT16 (0x00010000uL) +#define INTC_ICDISR13_TINT17 (0x00020000uL) +#define INTC_ICDISR13_TINT18 (0x00040000uL) +#define INTC_ICDISR13_TINT19 (0x00080000uL) +#define INTC_ICDISR13_TINT20 (0x00100000uL) +#define INTC_ICDISR13_TINT21 (0x00200000uL) +#define INTC_ICDISR13_TINT22 (0x00400000uL) +#define INTC_ICDISR13_TINT23 (0x00800000uL) +#define INTC_ICDISR13_TINT24 (0x01000000uL) +#define INTC_ICDISR13_TINT25 (0x02000000uL) +#define INTC_ICDISR13_TINT26 (0x04000000uL) +#define INTC_ICDISR13_TINT27 (0x08000000uL) +#define INTC_ICDISR13_TINT28 (0x10000000uL) +#define INTC_ICDISR13_TINT29 (0x20000000uL) +#define INTC_ICDISR13_TINT30 (0x40000000uL) +#define INTC_ICDISR13_TINT31 (0x80000000uL) + +#define INTC_ICDISR14_TINT32 (0x00000001uL) +#define INTC_ICDISR14_TINT33 (0x00000002uL) +#define INTC_ICDISR14_TINT34 (0x00000004uL) +#define INTC_ICDISR14_TINT35 (0x00000008uL) +#define INTC_ICDISR14_TINT36 (0x00000010uL) +#define INTC_ICDISR14_TINT37 (0x00000020uL) +#define INTC_ICDISR14_TINT38 (0x00000040uL) +#define INTC_ICDISR14_TINT39 (0x00000080uL) +#define INTC_ICDISR14_TINT40 (0x00000100uL) +#define INTC_ICDISR14_TINT41 (0x00000200uL) +#define INTC_ICDISR14_TINT42 (0x00000400uL) +#define INTC_ICDISR14_TINT43 (0x00000800uL) +#define INTC_ICDISR14_TINT44 (0x00001000uL) +#define INTC_ICDISR14_TINT45 (0x00002000uL) +#define INTC_ICDISR14_TINT46 (0x00004000uL) +#define INTC_ICDISR14_TINT47 (0x00008000uL) +#define INTC_ICDISR14_TINT48 (0x00010000uL) +#define INTC_ICDISR14_TINT49 (0x00020000uL) +#define INTC_ICDISR14_TINT50 (0x00040000uL) +#define INTC_ICDISR14_TINT51 (0x00080000uL) +#define INTC_ICDISR14_TINT52 (0x00100000uL) +#define INTC_ICDISR14_TINT53 (0x00200000uL) +#define INTC_ICDISR14_TINT54 (0x00400000uL) +#define INTC_ICDISR14_TINT55 (0x00800000uL) +#define INTC_ICDISR14_TINT56 (0x01000000uL) +#define INTC_ICDISR14_TINT57 (0x02000000uL) +#define INTC_ICDISR14_TINT58 (0x04000000uL) +#define INTC_ICDISR14_TINT59 (0x08000000uL) +#define INTC_ICDISR14_TINT60 (0x10000000uL) +#define INTC_ICDISR14_TINT61 (0x20000000uL) +#define INTC_ICDISR14_TINT62 (0x40000000uL) +#define INTC_ICDISR14_TINT63 (0x80000000uL) + +#define INTC_ICDISR15_TINT64 (0x00000001uL) +#define INTC_ICDISR15_TINT65 (0x00000002uL) +#define INTC_ICDISR15_TINT66 (0x00000004uL) +#define INTC_ICDISR15_TINT67 (0x00000008uL) +#define INTC_ICDISR15_TINT68 (0x00000010uL) +#define INTC_ICDISR15_TINT69 (0x00000020uL) +#define INTC_ICDISR15_TINT70 (0x00000040uL) +#define INTC_ICDISR15_TINT71 (0x00000080uL) +#define INTC_ICDISR15_TINT72 (0x00000100uL) +#define INTC_ICDISR15_TINT73 (0x00000200uL) +#define INTC_ICDISR15_TINT74 (0x00000400uL) +#define INTC_ICDISR15_TINT75 (0x00000800uL) +#define INTC_ICDISR15_TINT76 (0x00001000uL) +#define INTC_ICDISR15_TINT77 (0x00002000uL) +#define INTC_ICDISR15_TINT78 (0x00004000uL) +#define INTC_ICDISR15_TINT79 (0x00008000uL) +#define INTC_ICDISR15_TINT80 (0x00010000uL) +#define INTC_ICDISR15_TINT81 (0x00020000uL) +#define INTC_ICDISR15_TINT82 (0x00040000uL) +#define INTC_ICDISR15_TINT83 (0x00080000uL) +#define INTC_ICDISR15_TINT84 (0x00100000uL) +#define INTC_ICDISR15_TINT85 (0x00200000uL) +#define INTC_ICDISR15_TINT86 (0x00400000uL) +#define INTC_ICDISR15_TINT87 (0x00800000uL) +#define INTC_ICDISR15_TINT88 (0x01000000uL) +#define INTC_ICDISR15_TINT89 (0x02000000uL) +#define INTC_ICDISR15_TINT90 (0x04000000uL) +#define INTC_ICDISR15_TINT91 (0x08000000uL) +#define INTC_ICDISR15_TINT92 (0x10000000uL) +#define INTC_ICDISR15_TINT93 (0x20000000uL) +#define INTC_ICDISR15_TINT94 (0x40000000uL) +#define INTC_ICDISR15_TINT95 (0x80000000uL) + +#define INTC_ICDISR16_TINT96 (0x00000001uL) +#define INTC_ICDISR16_TINT97 (0x00000002uL) +#define INTC_ICDISR16_TINT98 (0x00000004uL) +#define INTC_ICDISR16_TINT99 (0x00000008uL) +#define INTC_ICDISR16_TINT100 (0x00000010uL) +#define INTC_ICDISR16_TINT101 (0x00000020uL) +#define INTC_ICDISR16_TINT102 (0x00000040uL) +#define INTC_ICDISR16_TINT103 (0x00000080uL) +#define INTC_ICDISR16_TINT104 (0x00000100uL) +#define INTC_ICDISR16_TINT105 (0x00000200uL) +#define INTC_ICDISR16_TINT106 (0x00000400uL) +#define INTC_ICDISR16_TINT107 (0x00000800uL) +#define INTC_ICDISR16_TINT108 (0x00001000uL) +#define INTC_ICDISR16_TINT109 (0x00002000uL) +#define INTC_ICDISR16_TINT110 (0x00004000uL) +#define INTC_ICDISR16_TINT111 (0x00008000uL) +#define INTC_ICDISR16_TINT112 (0x00010000uL) +#define INTC_ICDISR16_TINT113 (0x00020000uL) +#define INTC_ICDISR16_TINT114 (0x00040000uL) +#define INTC_ICDISR16_TINT115 (0x00080000uL) +#define INTC_ICDISR16_TINT116 (0x00100000uL) +#define INTC_ICDISR16_TINT117 (0x00200000uL) +#define INTC_ICDISR16_TINT118 (0x00400000uL) +#define INTC_ICDISR16_TINT119 (0x00800000uL) +#define INTC_ICDISR16_TINT120 (0x01000000uL) +#define INTC_ICDISR16_TINT121 (0x02000000uL) +#define INTC_ICDISR16_TINT122 (0x04000000uL) +#define INTC_ICDISR16_TINT123 (0x08000000uL) +#define INTC_ICDISR16_TINT124 (0x10000000uL) +#define INTC_ICDISR16_TINT125 (0x20000000uL) +#define INTC_ICDISR16_TINT126 (0x40000000uL) +#define INTC_ICDISR16_TINT127 (0x80000000uL) + +#define INTC_ICDISR17_TINT128 (0x00000001uL) +#define INTC_ICDISR17_TINT129 (0x00000002uL) +#define INTC_ICDISR17_TINT130 (0x00000004uL) +#define INTC_ICDISR17_TINT131 (0x00000008uL) +#define INTC_ICDISR17_TINT132 (0x00000010uL) +#define INTC_ICDISR17_TINT133 (0x00000020uL) +#define INTC_ICDISR17_TINT134 (0x00000040uL) +#define INTC_ICDISR17_TINT135 (0x00000080uL) +#define INTC_ICDISR17_TINT136 (0x00000100uL) +#define INTC_ICDISR17_TINT137 (0x00000200uL) +#define INTC_ICDISR17_TINT138 (0x00000400uL) +#define INTC_ICDISR17_TINT139 (0x00000800uL) +#define INTC_ICDISR17_TINT140 (0x00001000uL) +#define INTC_ICDISR17_TINT141 (0x00002000uL) +#define INTC_ICDISR17_TINT142 (0x00004000uL) +#define INTC_ICDISR17_TINT143 (0x00008000uL) +#define INTC_ICDISR17_TINT144 (0x00010000uL) +#define INTC_ICDISR17_TINT145 (0x00020000uL) +#define INTC_ICDISR17_TINT146 (0x00040000uL) +#define INTC_ICDISR17_TINT147 (0x00080000uL) +#define INTC_ICDISR17_TINT148 (0x00100000uL) +#define INTC_ICDISR17_TINT149 (0x00200000uL) +#define INTC_ICDISR17_TINT150 (0x00400000uL) +#define INTC_ICDISR17_TINT151 (0x00800000uL) +#define INTC_ICDISR17_TINT152 (0x01000000uL) +#define INTC_ICDISR17_TINT153 (0x02000000uL) +#define INTC_ICDISR17_TINT154 (0x04000000uL) +#define INTC_ICDISR17_TINT155 (0x08000000uL) +#define INTC_ICDISR17_TINT156 (0x10000000uL) +#define INTC_ICDISR17_TINT157 (0x20000000uL) +#define INTC_ICDISR17_TINT158 (0x40000000uL) +#define INTC_ICDISR17_TINT159 (0x80000000uL) + +#define INTC_ICDISR18_TINT160 (0x00000001uL) +#define INTC_ICDISR18_TINT161 (0x00000002uL) +#define INTC_ICDISR18_TINT162 (0x00000004uL) +#define INTC_ICDISR18_TINT163 (0x00000008uL) +#define INTC_ICDISR18_TINT164 (0x00000010uL) +#define INTC_ICDISR18_TINT165 (0x00000020uL) +#define INTC_ICDISR18_TINT166 (0x00000040uL) +#define INTC_ICDISR18_TINT167 (0x00000080uL) +#define INTC_ICDISR18_TINT168 (0x00000100uL) +#define INTC_ICDISR18_TINT169 (0x00000200uL) +#define INTC_ICDISR18_TINT170 (0x00000400uL) + +#define INTC_ICDISER0_SW0 (0x00000001uL) +#define INTC_ICDISER0_SW1 (0x00000002uL) +#define INTC_ICDISER0_SW2 (0x00000004uL) +#define INTC_ICDISER0_SW3 (0x00000008uL) +#define INTC_ICDISER0_SW4 (0x00000010uL) +#define INTC_ICDISER0_SW5 (0x00000020uL) +#define INTC_ICDISER0_SW6 (0x00000040uL) +#define INTC_ICDISER0_SW7 (0x00000080uL) +#define INTC_ICDISER0_SW8 (0x00000100uL) +#define INTC_ICDISER0_SW9 (0x00000200uL) +#define INTC_ICDISER0_SW10 (0x00000400uL) +#define INTC_ICDISER0_SW11 (0x00000800uL) +#define INTC_ICDISER0_SW12 (0x00001000uL) +#define INTC_ICDISER0_SW13 (0x00002000uL) +#define INTC_ICDISER0_SW14 (0x00004000uL) +#define INTC_ICDISER0_SW15 (0x00008000uL) +#define INTC_ICDISER0_PMUIRQ0 (0x00010000uL) +#define INTC_ICDISER0_COMMRX0 (0x00020000uL) +#define INTC_ICDISER0_COMMTX0 (0x00040000uL) +#define INTC_ICDISER0_CTIIRQ0 (0x00080000uL) + +#define INTC_ICDISER1_IRQ0 (0x00000001uL) +#define INTC_ICDISER1_IRQ1 (0x00000002uL) +#define INTC_ICDISER1_IRQ2 (0x00000004uL) +#define INTC_ICDISER1_IRQ3 (0x00000008uL) +#define INTC_ICDISER1_IRQ4 (0x00000010uL) +#define INTC_ICDISER1_IRQ5 (0x00000020uL) +#define INTC_ICDISER1_IRQ6 (0x00000040uL) +#define INTC_ICDISER1_IRQ7 (0x00000080uL) +#define INTC_ICDISER1_PL310ERR (0x00000100uL) +#define INTC_ICDISER1_DMAINT0 (0x00000200uL) +#define INTC_ICDISER1_DMAINT1 (0x00000400uL) +#define INTC_ICDISER1_DMAINT2 (0x00000800uL) +#define INTC_ICDISER1_DMAINT3 (0x00001000uL) +#define INTC_ICDISER1_DMAINT4 (0x00002000uL) +#define INTC_ICDISER1_DMAINT5 (0x00004000uL) +#define INTC_ICDISER1_DMAINT6 (0x00008000uL) +#define INTC_ICDISER1_DMAINT7 (0x00010000uL) +#define INTC_ICDISER1_DMAINT8 (0x00020000uL) +#define INTC_ICDISER1_DMAINT9 (0x00040000uL) +#define INTC_ICDISER1_DMAINT10 (0x00080000uL) +#define INTC_ICDISER1_DMAINT11 (0x00100000uL) +#define INTC_ICDISER1_DMAINT12 (0x00200000uL) +#define INTC_ICDISER1_DMAINT13 (0x00400000uL) +#define INTC_ICDISER1_DMAINT14 (0x00800000uL) +#define INTC_ICDISER1_DMAINT15 (0x01000000uL) +#define INTC_ICDISER1_DMAERR (0x02000000uL) + +#define INTC_ICDISER2_USBI0 (0x00000200uL) +#define INTC_ICDISER2_USBI1 (0x00000400uL) +#define INTC_ICDISER2_S0_VI_VSYNC0 (0x00000800uL) +#define INTC_ICDISER2_S0_LO_VSYNC0 (0x00001000uL) +#define INTC_ICDISER2_S0_VSYNCERR0 (0x00002000uL) +#define INTC_ICDISER2_GR3_VLINE0 (0x00004000uL) +#define INTC_ICDISER2_S0_VFIELD0 (0x00008000uL) +#define INTC_ICDISER2_IV1_VBUFERR0 (0x00010000uL) +#define INTC_ICDISER2_IV3_VBUFERR0 (0x00020000uL) +#define INTC_ICDISER2_IV5_VBUFERR0 (0x00040000uL) +#define INTC_ICDISER2_IV6_VBUFERR0 (0x00080000uL) +#define INTC_ICDISER2_S0_WLINE0 (0x00100000uL) +#define INTC_ICDISER2_S1_VI_VSYNC0 (0x00200000uL) +#define INTC_ICDISER2_S1_LO_VSYNC0 (0x00400000uL) +#define INTC_ICDISER2_S1_VSYNCERR0 (0x00800000uL) +#define INTC_ICDISER2_S1_VFIELD0 (0x01000000uL) +#define INTC_ICDISER2_IV2_VBUFERR0 (0x02000000uL) +#define INTC_ICDISER2_IV4_VBUFERR0 (0x04000000uL) +#define INTC_ICDISER2_S1_WLINE0 (0x08000000uL) +#define INTC_ICDISER2_OIR_VI_VSYNC0 (0x10000000uL) +#define INTC_ICDISER2_OIR_LO_VSYNC0 (0x20000000uL) +#define INTC_ICDISER2_OIR_VSYNCERR0 (0x40000000uL) +#define INTC_ICDISER2_OIR_VFIELD0 (0x80000000uL) + +#define INTC_ICDISER3_IV7_VBUFERR0 (0x00000001uL) +#define INTC_ICDISER3_IV8_VBUFERR0 (0x00000002uL) +#define INTC_ICDISER3_S0_VI_VSYNC1 (0x00000008uL) +#define INTC_ICDISER3_S0_LO_VSYNC1 (0x00000010uL) +#define INTC_ICDISER3_S0_VSYNCERR1 (0x00000020uL) +#define INTC_ICDISER3_GR3_VLINE1 (0x00000040uL) +#define INTC_ICDISER3_S0_VFIELD1 (0x00000080uL) +#define INTC_ICDISER3_IV1_VBUFERR1 (0x00000100uL) +#define INTC_ICDISER3_IV3_VBUFERR1 (0x00000200uL) +#define INTC_ICDISER3_IV5_VBUFERR1 (0x00000400uL) +#define INTC_ICDISER3_IV6_VBUFERR1 (0x00000800uL) +#define INTC_ICDISER3_S0_WLINE1 (0x00001000uL) +#define INTC_ICDISER3_S1_VI_VSYNC1 (0x00002000uL) +#define INTC_ICDISER3_S1_LO_VSYNC1 (0x00004000uL) +#define INTC_ICDISER3_S1_VSYNCERR1 (0x00008000uL) +#define INTC_ICDISER3_S1_VFIELD1 (0x00010000uL) +#define INTC_ICDISER3_IV2_VBUFERR1 (0x00020000uL) +#define INTC_ICDISER3_IV4_VBUFERR1 (0x00040000uL) +#define INTC_ICDISER3_S1_WLINE1 (0x00080000uL) +#define INTC_ICDISER3_OIR_VI_VSYNC1 (0x00100000uL) +#define INTC_ICDISER3_OIR_LO_VSYNC1 (0x00200000uL) +#define INTC_ICDISER3_OIR_VLINE1 (0x00400000uL) +#define INTC_ICDISER3_OIR_VFIELD1 (0x00800000uL) +#define INTC_ICDISER3_IV7_VBUFERR1 (0x01000000uL) +#define INTC_ICDISER3_IV8_VBUFERR1 (0x02000000uL) +#define INTC_ICDISER3_IMRDI (0x08000000uL) +#define INTC_ICDISER3_IMR2I0 (0x10000000uL) +#define INTC_ICDISER3_IMR2I1 (0x20000000uL) +#define INTC_ICDISER3_JEDI (0x40000000uL) +#define INTC_ICDISER3_JDTI (0x80000000uL) + +#define INTC_ICDISER4_CMP0 (0x00000001uL) +#define INTC_ICDISER4_CMP1 (0x00000002uL) +#define INTC_ICDISER4_INT0 (0x00000004uL) +#define INTC_ICDISER4_INT1 (0x00000008uL) +#define INTC_ICDISER4_INT2 (0x00000010uL) +#define INTC_ICDISER4_INT3 (0x00000020uL) +#define INTC_ICDISER4_OSTM0TINT (0x00000040uL) +#define INTC_ICDISER4_OSTM1TINT (0x00000080uL) +#define INTC_ICDISER4_CMI (0x00000100uL) +#define INTC_ICDISER4_WTOUT (0x00000200uL) +#define INTC_ICDISER4_ITI (0x00000400uL) +#define INTC_ICDISER4_TGI0A (0x00000800uL) +#define INTC_ICDISER4_TGI0B (0x00001000uL) +#define INTC_ICDISER4_TGI0C (0x00002000uL) +#define INTC_ICDISER4_TGI0D (0x00004000uL) +#define INTC_ICDISER4_TGI0V (0x00008000uL) +#define INTC_ICDISER4_TGI0E (0x00010000uL) +#define INTC_ICDISER4_TGI0F (0x00020000uL) +#define INTC_ICDISER4_TGI1A (0x00040000uL) +#define INTC_ICDISER4_TGI1B (0x00080000uL) +#define INTC_ICDISER4_TGI1V (0x00100000uL) +#define INTC_ICDISER4_TGI1U (0x00200000uL) +#define INTC_ICDISER4_TGI2A (0x00400000uL) +#define INTC_ICDISER4_TGI2B (0x00800000uL) +#define INTC_ICDISER4_TGI2V (0x01000000uL) +#define INTC_ICDISER4_TGI2U (0x02000000uL) +#define INTC_ICDISER4_TGI3A (0x04000000uL) +#define INTC_ICDISER4_TGI3B (0x08000000uL) +#define INTC_ICDISER4_TGI3C (0x10000000uL) +#define INTC_ICDISER4_TGI3D (0x20000000uL) +#define INTC_ICDISER4_TGI3V (0x40000000uL) +#define INTC_ICDISER4_TGI4A (0x80000000uL) + +#define INTC_ICDISER5_TGI4B (0x00000001uL) +#define INTC_ICDISER5_TGI4C (0x00000002uL) +#define INTC_ICDISER5_TGI4D (0x00000004uL) +#define INTC_ICDISER5_TGI4V (0x00000008uL) +#define INTC_ICDISER5_CMI1 (0x00000010uL) +#define INTC_ICDISER5_CMI2 (0x00000020uL) +#define INTC_ICDISER5_SGDEI0 (0x00000040uL) +#define INTC_ICDISER5_SGDEI1 (0x00000080uL) +#define INTC_ICDISER5_SGDEI2 (0x00000100uL) +#define INTC_ICDISER5_SGDEI3 (0x00000200uL) +#define INTC_ICDISER5_ADI (0x00000400uL) +#define INTC_ICDISER5_LMTI (0x00000800uL) +#define INTC_ICDISER5_SSII0 (0x00001000uL) +#define INTC_ICDISER5_SSIRXI0 (0x00002000uL) +#define INTC_ICDISER5_SSITXI0 (0x00004000uL) +#define INTC_ICDISER5_SSII1 (0x00008000uL) +#define INTC_ICDISER5_SSIRXI1 (0x00010000uL) +#define INTC_ICDISER5_SSITXI1 (0x00020000uL) +#define INTC_ICDISER5_SSII2 (0x00040000uL) +#define INTC_ICDISER5_SSIRTI2 (0x00080000uL) +#define INTC_ICDISER5_SSII3 (0x00100000uL) +#define INTC_ICDISER5_SSIRXI3 (0x00200000uL) +#define INTC_ICDISER5_SSITXI3 (0x00400000uL) +#define INTC_ICDISER5_SSII4 (0x00800000uL) +#define INTC_ICDISER5_SSIRTI4 (0x01000000uL) +#define INTC_ICDISER5_SSII5 (0x02000000uL) +#define INTC_ICDISER5_SSIRXI5 (0x04000000uL) +#define INTC_ICDISER5_SSITXI5 (0x08000000uL) +#define INTC_ICDISER5_SPDIFI (0x10000000uL) +#define INTC_ICDISER5_INTIICTEI0 (0x20000000uL) +#define INTC_ICDISER5_INTIICRI0 (0x40000000uL) +#define INTC_ICDISER5_INTIICTI0 (0x80000000uL) + +#define INTC_ICDISER6_INTIICSPI0 (0x00000001uL) +#define INTC_ICDISER6_INTIICSTI0 (0x00000002uL) +#define INTC_ICDISER6_INTIICNAKI0 (0x00000004uL) +#define INTC_ICDISER6_INTIICALI0 (0x00000008uL) +#define INTC_ICDISER6_INTIICTMOI0 (0x00000010uL) +#define INTC_ICDISER6_INTIICTEI1 (0x00000020uL) +#define INTC_ICDISER6_INTIICRI1 (0x00000040uL) +#define INTC_ICDISER6_INTIICTI1 (0x00000080uL) +#define INTC_ICDISER6_INTIICSPI1 (0x00000100uL) +#define INTC_ICDISER6_INTIICSTI1 (0x00000200uL) +#define INTC_ICDISER6_INTIICNAKI1 (0x00000400uL) +#define INTC_ICDISER6_INTIICALI1 (0x00000800uL) +#define INTC_ICDISER6_INTIICTMOI1 (0x00001000uL) +#define INTC_ICDISER6_INTIICTEI2 (0x00002000uL) +#define INTC_ICDISER6_INTIICRI2 (0x00004000uL) +#define INTC_ICDISER6_INTIICTI2 (0x00008000uL) +#define INTC_ICDISER6_INTIICSPI2 (0x00010000uL) +#define INTC_ICDISER6_INTIICSTI2 (0x00020000uL) +#define INTC_ICDISER6_INTIICNAKI2 (0x00040000uL) +#define INTC_ICDISER6_INTIICALI2 (0x00080000uL) +#define INTC_ICDISER6_INTIICTMOI2 (0x00100000uL) +#define INTC_ICDISER6_INTIICTEI3 (0x00200000uL) +#define INTC_ICDISER6_INTIICRI3 (0x00400000uL) +#define INTC_ICDISER6_INTIICTI3 (0x00800000uL) +#define INTC_ICDISER6_INTIICSPI3 (0x01000000uL) +#define INTC_ICDISER6_INTIICSTI3 (0x02000000uL) +#define INTC_ICDISER6_INTIICNAKI3 (0x04000000uL) +#define INTC_ICDISER6_INTIICALI3 (0x08000000uL) +#define INTC_ICDISER6_INTIICTMOI3 (0x10000000uL) +#define INTC_ICDISER6_BRI0 (0x20000000uL) +#define INTC_ICDISER6_ERI0 (0x40000000uL) +#define INTC_ICDISER6_RXI0 (0x80000000uL) + +#define INTC_ICDISER7_TXI0 (0x00000001uL) +#define INTC_ICDISER7_BRI1 (0x00000002uL) +#define INTC_ICDISER7_ERI1 (0x00000004uL) +#define INTC_ICDISER7_RXI1 (0x00000008uL) +#define INTC_ICDISER7_TXI1 (0x00000010uL) +#define INTC_ICDISER7_BRI2 (0x00000020uL) +#define INTC_ICDISER7_ERI2 (0x00000040uL) +#define INTC_ICDISER7_RXI2 (0x00000080uL) +#define INTC_ICDISER7_TXI2 (0x00000100uL) +#define INTC_ICDISER7_BRI3 (0x00000200uL) +#define INTC_ICDISER7_ERI3 (0x00000400uL) +#define INTC_ICDISER7_RXI3 (0x00000800uL) +#define INTC_ICDISER7_TXI3 (0x00001000uL) +#define INTC_ICDISER7_BRI4 (0x00002000uL) +#define INTC_ICDISER7_ERI4 (0x00004000uL) +#define INTC_ICDISER7_RXI4 (0x00008000uL) +#define INTC_ICDISER7_TXI4 (0x00010000uL) +#define INTC_ICDISER7_BRI5 (0x00020000uL) +#define INTC_ICDISER7_ERI5 (0x00040000uL) +#define INTC_ICDISER7_RXI5 (0x00080000uL) +#define INTC_ICDISER7_TXI5 (0x00100000uL) +#define INTC_ICDISER7_BRI6 (0x00200000uL) +#define INTC_ICDISER7_ERI6 (0x00400000uL) +#define INTC_ICDISER7_RXI6 (0x00800000uL) +#define INTC_ICDISER7_TXI6 (0x01000000uL) +#define INTC_ICDISER7_BRI7 (0x02000000uL) +#define INTC_ICDISER7_ERI7 (0x04000000uL) +#define INTC_ICDISER7_RXI7 (0x08000000uL) +#define INTC_ICDISER7_TXI7 (0x10000000uL) +#define INTC_ICDISER7_INTRCANGERR (0x20000000uL) +#define INTC_ICDISER7_INTRCANGRECC (0x40000000uL) +#define INTC_ICDISER7_INTRCAN0REC (0x80000000uL) + +#define INTC_ICDISER8_INTRCAN0ERR (0x00000001uL) +#define INTC_ICDISER8_INTRCAN0TRX (0x00000002uL) +#define INTC_ICDISER8_INTRCAN1REC (0x00000004uL) +#define INTC_ICDISER8_INTRCAN1ERR (0x00000008uL) +#define INTC_ICDISER8_INTRCAN1TRX (0x00000010uL) +#define INTC_ICDISER8_INTRCAN2REC (0x00000020uL) +#define INTC_ICDISER8_INTRCAN2ERR (0x00000040uL) +#define INTC_ICDISER8_INTRCAN2TRX (0x00000080uL) +#define INTC_ICDISER8_INTRCAN3REC (0x00000100uL) +#define INTC_ICDISER8_INTRCAN3ERR (0x00000200uL) +#define INTC_ICDISER8_INTRCAN3TRX (0x00000400uL) +#define INTC_ICDISER8_INTRCAN4REC (0x00000800uL) +#define INTC_ICDISER8_INTRCAN4ERR (0x00001000uL) +#define INTC_ICDISER8_INTRCAN4TRX (0x00002000uL) +#define INTC_ICDISER8_SPEI0 (0x00004000uL) +#define INTC_ICDISER8_SPRI0 (0x00008000uL) +#define INTC_ICDISER8_SPTI0 (0x00010000uL) +#define INTC_ICDISER8_SPEI1 (0x00020000uL) +#define INTC_ICDISER8_SPRI1 (0x00040000uL) +#define INTC_ICDISER8_SPTI1 (0x00080000uL) +#define INTC_ICDISER8_SPEI2 (0x00100000uL) +#define INTC_ICDISER8_SPRI2 (0x00200000uL) +#define INTC_ICDISER8_SPTI2 (0x00400000uL) +#define INTC_ICDISER8_SPEI3 (0x00800000uL) +#define INTC_ICDISER8_SPRI3 (0x01000000uL) +#define INTC_ICDISER8_SPTI3 (0x02000000uL) +#define INTC_ICDISER8_SPEI4 (0x04000000uL) +#define INTC_ICDISER8_SPRI4 (0x08000000uL) +#define INTC_ICDISER8_SPTI4 (0x10000000uL) +#define INTC_ICDISER8_IEBBTD (0x20000000uL) +#define INTC_ICDISER8_IEBBTERR (0x40000000uL) +#define INTC_ICDISER8_IEBBTSTA (0x80000000uL) + +#define INTC_ICDISER9_IEBBTV (0x00000001uL) +#define INTC_ICDISER9_ISY (0x00000002uL) +#define INTC_ICDISER9_IERR (0x00000004uL) +#define INTC_ICDISER9_ITARG (0x00000008uL) +#define INTC_ICDISER9_ISEC (0x00000010uL) +#define INTC_ICDISER9_IBUF (0x00000020uL) +#define INTC_ICDISER9_IREADY (0x00000040uL) +#define INTC_ICDISER9_FLSTE (0x00000080uL) +#define INTC_ICDISER9_FLTENDI (0x00000100uL) +#define INTC_ICDISER9_FLTREQ0I (0x00000200uL) +#define INTC_ICDISER9_FLTREQ1I (0x00000400uL) +#define INTC_ICDISER9_MMC0 (0x00000800uL) +#define INTC_ICDISER9_MMC1 (0x00001000uL) +#define INTC_ICDISER9_MMC2 (0x00002000uL) +#define INTC_ICDISER9_SDHI0_3 (0x00004000uL) +#define INTC_ICDISER9_SDHI0_0 (0x00008000uL) +#define INTC_ICDISER9_SDHI0_1 (0x00010000uL) +#define INTC_ICDISER9_SDHI1_3 (0x00020000uL) +#define INTC_ICDISER9_SDHI1_0 (0x00040000uL) +#define INTC_ICDISER9_SDHI1_1 (0x00080000uL) +#define INTC_ICDISER9_ARM (0x00100000uL) +#define INTC_ICDISER9_PRD (0x00200000uL) +#define INTC_ICDISER9_CUP (0x00400000uL) +#define INTC_ICDISER9_SCUAI0 (0x00800000uL) +#define INTC_ICDISER9_SCUAI1 (0x01000000uL) +#define INTC_ICDISER9_SCUFDI0 (0x02000000uL) +#define INTC_ICDISER9_SCUFDI1 (0x04000000uL) +#define INTC_ICDISER9_SCUFDI2 (0x08000000uL) +#define INTC_ICDISER9_SCUFDI3 (0x10000000uL) +#define INTC_ICDISER9_SCUFUI0 (0x20000000uL) +#define INTC_ICDISER9_SCUFUI1 (0x40000000uL) +#define INTC_ICDISER9_SCUFUI2 (0x80000000uL) + +#define INTC_ICDISER10_SCUFUI3 (0x00000001uL) +#define INTC_ICDISER10_SCUDVI0 (0x00000002uL) +#define INTC_ICDISER10_SCUDVI1 (0x00000004uL) +#define INTC_ICDISER10_SCUDVI2 (0x00000008uL) +#define INTC_ICDISER10_SCUDVI3 (0x00000010uL) +#define INTC_ICDISER10_MLB_CINT (0x00000020uL) +#define INTC_ICDISER10_MLB_SINT (0x00000040uL) +#define INTC_ICDISER10_DRC0 (0x00000080uL) +#define INTC_ICDISER10_DRC1 (0x00000100uL) +#define INTC_ICDISER10_LINI0_INT_T (0x00000800uL) +#define INTC_ICDISER10_LINI0_INT_R (0x00001000uL) +#define INTC_ICDISER10_LINI0_INT_S (0x00002000uL) +#define INTC_ICDISER10_LINI0_INT_M (0x00004000uL) +#define INTC_ICDISER10_LINI1_INT_T (0x00008000uL) +#define INTC_ICDISER10_LINI1_INT_R (0x00010000uL) +#define INTC_ICDISER10_LINI1_INT_S (0x00020000uL) +#define INTC_ICDISER10_LINI1_INT_M (0x00040000uL) +#define INTC_ICDISER10_ERI0 (0x08000000uL) +#define INTC_ICDISER10_RXI0 (0x10000000uL) +#define INTC_ICDISER10_TXI0 (0x20000000uL) +#define INTC_ICDISER10_TEI0 (0x40000000uL) +#define INTC_ICDISER10_ERI1 (0x80000000uL) + +#define INTC_ICDISER11_RXI1 (0x00000001uL) +#define INTC_ICDISER11_TXI1 (0x00000002uL) +#define INTC_ICDISER11_TEI1 (0x00000004uL) +#define INTC_ICDISER11_AVBI_DATA (0x00000008uL) +#define INTC_ICDISER11_AVBI_ERROR (0x00000010uL) +#define INTC_ICDISER11_AVBI_MANAGE (0x00000020uL) +#define INTC_ICDISER11_AVBI_MAC (0x00000040uL) +#define INTC_ICDISER11_ETHERI (0x00000080uL) +#define INTC_ICDISER11_CEUI (0x00001000uL) +#define INTC_ICDISER11_H2XMLB_ERRINT (0x20000000uL) +#define INTC_ICDISER11_H2XIC1_ERRINT (0x40000000uL) +#define INTC_ICDISER11_X2HPERI1_ERRINT (0x80000000uL) + +#define INTC_ICDISER12_X2HPERI2_ERRINT (0x00000001uL) +#define INTC_ICDISER12_X2HPERI34_ERRINT (0x00000002uL) +#define INTC_ICDISER12_X2HPERI5_ERRINT (0x00000004uL) +#define INTC_ICDISER12_X2HPERI67_ERRINT (0x00000008uL) +#define INTC_ICDISER12_X2HDBGR_ERRINT (0x00000010uL) +#define INTC_ICDISER12_X2HBSC_ERRINT (0x00000020uL) +#define INTC_ICDISER12_X2HSPI1_ERRINT (0x00000040uL) +#define INTC_ICDISER12_X2HSPI2_ERRINT (0x00000080uL) +#define INTC_ICDISER12_PRRI (0x00000100uL) +#define INTC_ICDISER12_IFEI0 (0x00000200uL) +#define INTC_ICDISER12_OFFI0 (0x00000400uL) +#define INTC_ICDISER12_PFVEI0 (0x00000800uL) +#define INTC_ICDISER12_IFEI1 (0x00001000uL) +#define INTC_ICDISER12_OFFI1 (0x00002000uL) +#define INTC_ICDISER12_PFVEI1 (0x00004000uL) + +#define INTC_ICDISER13_TINT0 (0x00000001uL) +#define INTC_ICDISER13_TINT1 (0x00000002uL) +#define INTC_ICDISER13_TINT2 (0x00000004uL) +#define INTC_ICDISER13_TINT3 (0x00000008uL) +#define INTC_ICDISER13_TINT4 (0x00000010uL) +#define INTC_ICDISER13_TINT5 (0x00000020uL) +#define INTC_ICDISER13_TINT6 (0x00000040uL) +#define INTC_ICDISER13_TINT7 (0x00000080uL) +#define INTC_ICDISER13_TINT8 (0x00000100uL) +#define INTC_ICDISER13_TINT9 (0x00000200uL) +#define INTC_ICDISER13_TINT10 (0x00000400uL) +#define INTC_ICDISER13_TINT11 (0x00000800uL) +#define INTC_ICDISER13_TINT12 (0x00001000uL) +#define INTC_ICDISER13_TINT13 (0x00002000uL) +#define INTC_ICDISER13_TINT14 (0x00004000uL) +#define INTC_ICDISER13_TINT15 (0x00008000uL) +#define INTC_ICDISER13_TINT16 (0x00010000uL) +#define INTC_ICDISER13_TINT17 (0x00020000uL) +#define INTC_ICDISER13_TINT18 (0x00040000uL) +#define INTC_ICDISER13_TINT19 (0x00080000uL) +#define INTC_ICDISER13_TINT20 (0x00100000uL) +#define INTC_ICDISER13_TINT21 (0x00200000uL) +#define INTC_ICDISER13_TINT22 (0x00400000uL) +#define INTC_ICDISER13_TINT23 (0x00800000uL) +#define INTC_ICDISER13_TINT24 (0x01000000uL) +#define INTC_ICDISER13_TINT25 (0x02000000uL) +#define INTC_ICDISER13_TINT26 (0x04000000uL) +#define INTC_ICDISER13_TINT27 (0x08000000uL) +#define INTC_ICDISER13_TINT28 (0x10000000uL) +#define INTC_ICDISER13_TINT29 (0x20000000uL) +#define INTC_ICDISER13_TINT30 (0x40000000uL) +#define INTC_ICDISER13_TINT31 (0x80000000uL) + +#define INTC_ICDISER14_TINT32 (0x00000001uL) +#define INTC_ICDISER14_TINT33 (0x00000002uL) +#define INTC_ICDISER14_TINT34 (0x00000004uL) +#define INTC_ICDISER14_TINT35 (0x00000008uL) +#define INTC_ICDISER14_TINT36 (0x00000010uL) +#define INTC_ICDISER14_TINT37 (0x00000020uL) +#define INTC_ICDISER14_TINT38 (0x00000040uL) +#define INTC_ICDISER14_TINT39 (0x00000080uL) +#define INTC_ICDISER14_TINT40 (0x00000100uL) +#define INTC_ICDISER14_TINT41 (0x00000200uL) +#define INTC_ICDISER14_TINT42 (0x00000400uL) +#define INTC_ICDISER14_TINT43 (0x00000800uL) +#define INTC_ICDISER14_TINT44 (0x00001000uL) +#define INTC_ICDISER14_TINT45 (0x00002000uL) +#define INTC_ICDISER14_TINT46 (0x00004000uL) +#define INTC_ICDISER14_TINT47 (0x00008000uL) +#define INTC_ICDISER14_TINT48 (0x00010000uL) +#define INTC_ICDISER14_TINT49 (0x00020000uL) +#define INTC_ICDISER14_TINT50 (0x00040000uL) +#define INTC_ICDISER14_TINT51 (0x00080000uL) +#define INTC_ICDISER14_TINT52 (0x00100000uL) +#define INTC_ICDISER14_TINT53 (0x00200000uL) +#define INTC_ICDISER14_TINT54 (0x00400000uL) +#define INTC_ICDISER14_TINT55 (0x00800000uL) +#define INTC_ICDISER14_TINT56 (0x01000000uL) +#define INTC_ICDISER14_TINT57 (0x02000000uL) +#define INTC_ICDISER14_TINT58 (0x04000000uL) +#define INTC_ICDISER14_TINT59 (0x08000000uL) +#define INTC_ICDISER14_TINT60 (0x10000000uL) +#define INTC_ICDISER14_TINT61 (0x20000000uL) +#define INTC_ICDISER14_TINT62 (0x40000000uL) +#define INTC_ICDISER14_TINT63 (0x80000000uL) + +#define INTC_ICDISER15_TINT64 (0x00000001uL) +#define INTC_ICDISER15_TINT65 (0x00000002uL) +#define INTC_ICDISER15_TINT66 (0x00000004uL) +#define INTC_ICDISER15_TINT67 (0x00000008uL) +#define INTC_ICDISER15_TINT68 (0x00000010uL) +#define INTC_ICDISER15_TINT69 (0x00000020uL) +#define INTC_ICDISER15_TINT70 (0x00000040uL) +#define INTC_ICDISER15_TINT71 (0x00000080uL) +#define INTC_ICDISER15_TINT72 (0x00000100uL) +#define INTC_ICDISER15_TINT73 (0x00000200uL) +#define INTC_ICDISER15_TINT74 (0x00000400uL) +#define INTC_ICDISER15_TINT75 (0x00000800uL) +#define INTC_ICDISER15_TINT76 (0x00001000uL) +#define INTC_ICDISER15_TINT77 (0x00002000uL) +#define INTC_ICDISER15_TINT78 (0x00004000uL) +#define INTC_ICDISER15_TINT79 (0x00008000uL) +#define INTC_ICDISER15_TINT80 (0x00010000uL) +#define INTC_ICDISER15_TINT81 (0x00020000uL) +#define INTC_ICDISER15_TINT82 (0x00040000uL) +#define INTC_ICDISER15_TINT83 (0x00080000uL) +#define INTC_ICDISER15_TINT84 (0x00100000uL) +#define INTC_ICDISER15_TINT85 (0x00200000uL) +#define INTC_ICDISER15_TINT86 (0x00400000uL) +#define INTC_ICDISER15_TINT87 (0x00800000uL) +#define INTC_ICDISER15_TINT88 (0x01000000uL) +#define INTC_ICDISER15_TINT89 (0x02000000uL) +#define INTC_ICDISER15_TINT90 (0x04000000uL) +#define INTC_ICDISER15_TINT91 (0x08000000uL) +#define INTC_ICDISER15_TINT92 (0x10000000uL) +#define INTC_ICDISER15_TINT93 (0x20000000uL) +#define INTC_ICDISER15_TINT94 (0x40000000uL) +#define INTC_ICDISER15_TINT95 (0x80000000uL) + +#define INTC_ICDISER16_TINT96 (0x00000001uL) +#define INTC_ICDISER16_TINT97 (0x00000002uL) +#define INTC_ICDISER16_TINT98 (0x00000004uL) +#define INTC_ICDISER16_TINT99 (0x00000008uL) +#define INTC_ICDISER16_TINT100 (0x00000010uL) +#define INTC_ICDISER16_TINT101 (0x00000020uL) +#define INTC_ICDISER16_TINT102 (0x00000040uL) +#define INTC_ICDISER16_TINT103 (0x00000080uL) +#define INTC_ICDISER16_TINT104 (0x00000100uL) +#define INTC_ICDISER16_TINT105 (0x00000200uL) +#define INTC_ICDISER16_TINT106 (0x00000400uL) +#define INTC_ICDISER16_TINT107 (0x00000800uL) +#define INTC_ICDISER16_TINT108 (0x00001000uL) +#define INTC_ICDISER16_TINT109 (0x00002000uL) +#define INTC_ICDISER16_TINT110 (0x00004000uL) +#define INTC_ICDISER16_TINT111 (0x00008000uL) +#define INTC_ICDISER16_TINT112 (0x00010000uL) +#define INTC_ICDISER16_TINT113 (0x00020000uL) +#define INTC_ICDISER16_TINT114 (0x00040000uL) +#define INTC_ICDISER16_TINT115 (0x00080000uL) +#define INTC_ICDISER16_TINT116 (0x00100000uL) +#define INTC_ICDISER16_TINT117 (0x00200000uL) +#define INTC_ICDISER16_TINT118 (0x00400000uL) +#define INTC_ICDISER16_TINT119 (0x00800000uL) +#define INTC_ICDISER16_TINT120 (0x01000000uL) +#define INTC_ICDISER16_TINT121 (0x02000000uL) +#define INTC_ICDISER16_TINT122 (0x04000000uL) +#define INTC_ICDISER16_TINT123 (0x08000000uL) +#define INTC_ICDISER16_TINT124 (0x10000000uL) +#define INTC_ICDISER16_TINT125 (0x20000000uL) +#define INTC_ICDISER16_TINT126 (0x40000000uL) +#define INTC_ICDISER16_TINT127 (0x80000000uL) + +#define INTC_ICDISER17_TINT128 (0x00000001uL) +#define INTC_ICDISER17_TINT129 (0x00000002uL) +#define INTC_ICDISER17_TINT130 (0x00000004uL) +#define INTC_ICDISER17_TINT131 (0x00000008uL) +#define INTC_ICDISER17_TINT132 (0x00000010uL) +#define INTC_ICDISER17_TINT133 (0x00000020uL) +#define INTC_ICDISER17_TINT134 (0x00000040uL) +#define INTC_ICDISER17_TINT135 (0x00000080uL) +#define INTC_ICDISER17_TINT136 (0x00000100uL) +#define INTC_ICDISER17_TINT137 (0x00000200uL) +#define INTC_ICDISER17_TINT138 (0x00000400uL) +#define INTC_ICDISER17_TINT139 (0x00000800uL) +#define INTC_ICDISER17_TINT140 (0x00001000uL) +#define INTC_ICDISER17_TINT141 (0x00002000uL) +#define INTC_ICDISER17_TINT142 (0x00004000uL) +#define INTC_ICDISER17_TINT143 (0x00008000uL) +#define INTC_ICDISER17_TINT144 (0x00010000uL) +#define INTC_ICDISER17_TINT145 (0x00020000uL) +#define INTC_ICDISER17_TINT146 (0x00040000uL) +#define INTC_ICDISER17_TINT147 (0x00080000uL) +#define INTC_ICDISER17_TINT148 (0x00100000uL) +#define INTC_ICDISER17_TINT149 (0x00200000uL) +#define INTC_ICDISER17_TINT150 (0x00400000uL) +#define INTC_ICDISER17_TINT151 (0x00800000uL) +#define INTC_ICDISER17_TINT152 (0x01000000uL) +#define INTC_ICDISER17_TINT153 (0x02000000uL) +#define INTC_ICDISER17_TINT154 (0x04000000uL) +#define INTC_ICDISER17_TINT155 (0x08000000uL) +#define INTC_ICDISER17_TINT156 (0x10000000uL) +#define INTC_ICDISER17_TINT157 (0x20000000uL) +#define INTC_ICDISER17_TINT158 (0x40000000uL) +#define INTC_ICDISER17_TINT159 (0x80000000uL) + +#define INTC_ICDISER18_TINT160 (0x00000001uL) +#define INTC_ICDISER18_TINT161 (0x00000002uL) +#define INTC_ICDISER18_TINT162 (0x00000004uL) +#define INTC_ICDISER18_TINT163 (0x00000008uL) +#define INTC_ICDISER18_TINT164 (0x00000010uL) +#define INTC_ICDISER18_TINT165 (0x00000020uL) +#define INTC_ICDISER18_TINT166 (0x00000040uL) +#define INTC_ICDISER18_TINT167 (0x00000080uL) +#define INTC_ICDISER18_TINT168 (0x00000100uL) +#define INTC_ICDISER18_TINT169 (0x00000200uL) +#define INTC_ICDISER18_TINT170 (0x00000400uL) + +#define INTC_ICDICER0_SW0 (0x00000001uL) +#define INTC_ICDICER0_SW1 (0x00000002uL) +#define INTC_ICDICER0_SW2 (0x00000004uL) +#define INTC_ICDICER0_SW3 (0x00000008uL) +#define INTC_ICDICER0_SW4 (0x00000010uL) +#define INTC_ICDICER0_SW5 (0x00000020uL) +#define INTC_ICDICER0_SW6 (0x00000040uL) +#define INTC_ICDICER0_SW7 (0x00000080uL) +#define INTC_ICDICER0_SW8 (0x00000100uL) +#define INTC_ICDICER0_SW9 (0x00000200uL) +#define INTC_ICDICER0_SW10 (0x00000400uL) +#define INTC_ICDICER0_SW11 (0x00000800uL) +#define INTC_ICDICER0_SW12 (0x00001000uL) +#define INTC_ICDICER0_SW13 (0x00002000uL) +#define INTC_ICDICER0_SW14 (0x00004000uL) +#define INTC_ICDICER0_SW15 (0x00008000uL) +#define INTC_ICDICER0_PMUIRQ0 (0x00010000uL) +#define INTC_ICDICER0_COMMRX0 (0x00020000uL) +#define INTC_ICDICER0_COMMTX0 (0x00040000uL) +#define INTC_ICDICER0_CTIIRQ0 (0x00080000uL) + +#define INTC_ICDICER1_IRQ0 (0x00000001uL) +#define INTC_ICDICER1_IRQ1 (0x00000002uL) +#define INTC_ICDICER1_IRQ2 (0x00000004uL) +#define INTC_ICDICER1_IRQ3 (0x00000008uL) +#define INTC_ICDICER1_IRQ4 (0x00000010uL) +#define INTC_ICDICER1_IRQ5 (0x00000020uL) +#define INTC_ICDICER1_IRQ6 (0x00000040uL) +#define INTC_ICDICER1_IRQ7 (0x00000080uL) +#define INTC_ICDICER1_PL310ERR (0x00000100uL) +#define INTC_ICDICER1_DMAINT0 (0x00000200uL) +#define INTC_ICDICER1_DMAINT1 (0x00000400uL) +#define INTC_ICDICER1_DMAINT2 (0x00000800uL) +#define INTC_ICDICER1_DMAINT3 (0x00001000uL) +#define INTC_ICDICER1_DMAINT4 (0x00002000uL) +#define INTC_ICDICER1_DMAINT5 (0x00004000uL) +#define INTC_ICDICER1_DMAINT6 (0x00008000uL) +#define INTC_ICDICER1_DMAINT7 (0x00010000uL) +#define INTC_ICDICER1_DMAINT8 (0x00020000uL) +#define INTC_ICDICER1_DMAINT9 (0x00040000uL) +#define INTC_ICDICER1_DMAINT10 (0x00080000uL) +#define INTC_ICDICER1_DMAINT11 (0x00100000uL) +#define INTC_ICDICER1_DMAINT12 (0x00200000uL) +#define INTC_ICDICER1_DMAINT13 (0x00400000uL) +#define INTC_ICDICER1_DMAINT14 (0x00800000uL) +#define INTC_ICDICER1_DMAINT15 (0x01000000uL) +#define INTC_ICDICER1_DMAERR (0x02000000uL) + +#define INTC_ICDICER2_USBI0 (0x00000200uL) +#define INTC_ICDICER2_USBI1 (0x00000400uL) +#define INTC_ICDICER2_S0_VI_VSYNC0 (0x00000800uL) +#define INTC_ICDICER2_S0_LO_VSYNC0 (0x00001000uL) +#define INTC_ICDICER2_S0_VSYNCERR0 (0x00002000uL) +#define INTC_ICDICER2_GR3_VLINE0 (0x00004000uL) +#define INTC_ICDICER2_S0_VFIELD0 (0x00008000uL) +#define INTC_ICDICER2_IV1_VBUFERR0 (0x00010000uL) +#define INTC_ICDICER2_IV3_VBUFERR0 (0x00020000uL) +#define INTC_ICDICER2_IV5_VBUFERR0 (0x00040000uL) +#define INTC_ICDICER2_IV6_VBUFERR0 (0x00080000uL) +#define INTC_ICDICER2_S0_WLINE0 (0x00100000uL) +#define INTC_ICDICER2_S1_VI_VSYNC0 (0x00200000uL) +#define INTC_ICDICER2_S1_LO_VSYNC0 (0x00400000uL) +#define INTC_ICDICER2_S1_VSYNCERR0 (0x00800000uL) +#define INTC_ICDICER2_S1_VFIELD0 (0x01000000uL) +#define INTC_ICDICER2_IV2_VBUFERR0 (0x02000000uL) +#define INTC_ICDICER2_IV4_VBUFERR0 (0x04000000uL) +#define INTC_ICDICER2_S1_WLINE0 (0x08000000uL) +#define INTC_ICDICER2_OIR_VI_VSYNC0 (0x10000000uL) +#define INTC_ICDICER2_OIR_LO_VSYNC0 (0x20000000uL) +#define INTC_ICDICER2_OIR_VSYNCERR0 (0x40000000uL) +#define INTC_ICDICER2_OIR_VFIELD0 (0x80000000uL) + +#define INTC_ICDICER3_IV7_VBUFERR0 (0x00000001uL) +#define INTC_ICDICER3_IV8_VBUFERR0 (0x00000002uL) +#define INTC_ICDICER3_S0_VI_VSYNC1 (0x00000008uL) +#define INTC_ICDICER3_S0_LO_VSYNC1 (0x00000010uL) +#define INTC_ICDICER3_S0_VSYNCERR1 (0x00000020uL) +#define INTC_ICDICER3_GR3_VLINE1 (0x00000040uL) +#define INTC_ICDICER3_S0_VFIELD1 (0x00000080uL) +#define INTC_ICDICER3_IV1_VBUFERR1 (0x00000100uL) +#define INTC_ICDICER3_IV3_VBUFERR1 (0x00000200uL) +#define INTC_ICDICER3_IV5_VBUFERR1 (0x00000400uL) +#define INTC_ICDICER3_IV6_VBUFERR1 (0x00000800uL) +#define INTC_ICDICER3_S0_WLINE1 (0x00001000uL) +#define INTC_ICDICER3_S1_VI_VSYNC1 (0x00002000uL) +#define INTC_ICDICER3_S1_LO_VSYNC1 (0x00004000uL) +#define INTC_ICDICER3_S1_VSYNCERR1 (0x00008000uL) +#define INTC_ICDICER3_S1_VFIELD1 (0x00010000uL) +#define INTC_ICDICER3_IV2_VBUFERR1 (0x00020000uL) +#define INTC_ICDICER3_IV4_VBUFERR1 (0x00040000uL) +#define INTC_ICDICER3_S1_WLINE1 (0x00080000uL) +#define INTC_ICDICER3_OIR_VI_VSYNC1 (0x00100000uL) +#define INTC_ICDICER3_OIR_LO_VSYNC1 (0x00200000uL) +#define INTC_ICDICER3_OIR_VLINE1 (0x00400000uL) +#define INTC_ICDICER3_OIR_VFIELD1 (0x00800000uL) +#define INTC_ICDICER3_IV7_VBUFERR1 (0x01000000uL) +#define INTC_ICDICER3_IV8_VBUFERR1 (0x02000000uL) +#define INTC_ICDICER3_IMRDI (0x08000000uL) +#define INTC_ICDICER3_IMR2I0 (0x10000000uL) +#define INTC_ICDICER3_IMR2I1 (0x20000000uL) +#define INTC_ICDICER3_JEDI (0x40000000uL) +#define INTC_ICDICER3_JDTI (0x80000000uL) + +#define INTC_ICDICER4_CMP0 (0x00000001uL) +#define INTC_ICDICER4_CMP1 (0x00000002uL) +#define INTC_ICDICER4_INT0 (0x00000004uL) +#define INTC_ICDICER4_INT1 (0x00000008uL) +#define INTC_ICDICER4_INT2 (0x00000010uL) +#define INTC_ICDICER4_INT3 (0x00000020uL) +#define INTC_ICDICER4_OSTM0TINT (0x00000040uL) +#define INTC_ICDICER4_OSTM1TINT (0x00000080uL) +#define INTC_ICDICER4_CMI (0x00000100uL) +#define INTC_ICDICER4_WTOUT (0x00000200uL) +#define INTC_ICDICER4_ITI (0x00000400uL) +#define INTC_ICDICER4_TGI0A (0x00000800uL) +#define INTC_ICDICER4_TGI0B (0x00001000uL) +#define INTC_ICDICER4_TGI0C (0x00002000uL) +#define INTC_ICDICER4_TGI0D (0x00004000uL) +#define INTC_ICDICER4_TGI0V (0x00008000uL) +#define INTC_ICDICER4_TGI0E (0x00010000uL) +#define INTC_ICDICER4_TGI0F (0x00020000uL) +#define INTC_ICDICER4_TGI1A (0x00040000uL) +#define INTC_ICDICER4_TGI1B (0x00080000uL) +#define INTC_ICDICER4_TGI1V (0x00100000uL) +#define INTC_ICDICER4_TGI1U (0x00200000uL) +#define INTC_ICDICER4_TGI2A (0x00400000uL) +#define INTC_ICDICER4_TGI2B (0x00800000uL) +#define INTC_ICDICER4_TGI2V (0x01000000uL) +#define INTC_ICDICER4_TGI2U (0x02000000uL) +#define INTC_ICDICER4_TGI3A (0x04000000uL) +#define INTC_ICDICER4_TGI3B (0x08000000uL) +#define INTC_ICDICER4_TGI3C (0x10000000uL) +#define INTC_ICDICER4_TGI3D (0x20000000uL) +#define INTC_ICDICER4_TGI3V (0x40000000uL) +#define INTC_ICDICER4_TGI4A (0x80000000uL) + +#define INTC_ICDICER5_TGI4B (0x00000001uL) +#define INTC_ICDICER5_TGI4C (0x00000002uL) +#define INTC_ICDICER5_TGI4D (0x00000004uL) +#define INTC_ICDICER5_TGI4V (0x00000008uL) +#define INTC_ICDICER5_CMI1 (0x00000010uL) +#define INTC_ICDICER5_CMI2 (0x00000020uL) +#define INTC_ICDICER5_SGDEI0 (0x00000040uL) +#define INTC_ICDICER5_SGDEI1 (0x00000080uL) +#define INTC_ICDICER5_SGDEI2 (0x00000100uL) +#define INTC_ICDICER5_SGDEI3 (0x00000200uL) +#define INTC_ICDICER5_ADI (0x00000400uL) +#define INTC_ICDICER5_LMTI (0x00000800uL) +#define INTC_ICDICER5_SSII0 (0x00001000uL) +#define INTC_ICDICER5_SSIRXI0 (0x00002000uL) +#define INTC_ICDICER5_SSITXI0 (0x00004000uL) +#define INTC_ICDICER5_SSII1 (0x00008000uL) +#define INTC_ICDICER5_SSIRXI1 (0x00010000uL) +#define INTC_ICDICER5_SSITXI1 (0x00020000uL) +#define INTC_ICDICER5_SSII2 (0x00040000uL) +#define INTC_ICDICER5_SSIRTI2 (0x00080000uL) +#define INTC_ICDICER5_SSII3 (0x00100000uL) +#define INTC_ICDICER5_SSIRXI3 (0x00200000uL) +#define INTC_ICDICER5_SSITXI3 (0x00400000uL) +#define INTC_ICDICER5_SSII4 (0x00800000uL) +#define INTC_ICDICER5_SSIRTI4 (0x01000000uL) +#define INTC_ICDICER5_SSII5 (0x02000000uL) +#define INTC_ICDICER5_SSIRXI5 (0x04000000uL) +#define INTC_ICDICER5_SSITXI5 (0x08000000uL) +#define INTC_ICDICER5_SPDIFI (0x10000000uL) +#define INTC_ICDICER5_INTIICTEI0 (0x20000000uL) +#define INTC_ICDICER5_INTIICRI0 (0x40000000uL) +#define INTC_ICDICER5_INTIICTI0 (0x80000000uL) + +#define INTC_ICDICER6_INTIICSPI0 (0x00000001uL) +#define INTC_ICDICER6_INTIICSTI0 (0x00000002uL) +#define INTC_ICDICER6_INTIICNAKI0 (0x00000004uL) +#define INTC_ICDICER6_INTIICALI0 (0x00000008uL) +#define INTC_ICDICER6_INTIICTMOI0 (0x00000010uL) +#define INTC_ICDICER6_INTIICTEI1 (0x00000020uL) +#define INTC_ICDICER6_INTIICRI1 (0x00000040uL) +#define INTC_ICDICER6_INTIICTI1 (0x00000080uL) +#define INTC_ICDICER6_INTIICSPI1 (0x00000100uL) +#define INTC_ICDICER6_INTIICSTI1 (0x00000200uL) +#define INTC_ICDICER6_INTIICNAKI1 (0x00000400uL) +#define INTC_ICDICER6_INTIICALI1 (0x00000800uL) +#define INTC_ICDICER6_INTIICTMOI1 (0x00001000uL) +#define INTC_ICDICER6_INTIICTEI2 (0x00002000uL) +#define INTC_ICDICER6_INTIICRI2 (0x00004000uL) +#define INTC_ICDICER6_INTIICTI2 (0x00008000uL) +#define INTC_ICDICER6_INTIICSPI2 (0x00010000uL) +#define INTC_ICDICER6_INTIICSTI2 (0x00020000uL) +#define INTC_ICDICER6_INTIICNAKI2 (0x00040000uL) +#define INTC_ICDICER6_INTIICALI2 (0x00080000uL) +#define INTC_ICDICER6_INTIICTMOI2 (0x00100000uL) +#define INTC_ICDICER6_INTIICTEI3 (0x00200000uL) +#define INTC_ICDICER6_INTIICRI3 (0x00400000uL) +#define INTC_ICDICER6_INTIICTI3 (0x00800000uL) +#define INTC_ICDICER6_INTIICSPI3 (0x01000000uL) +#define INTC_ICDICER6_INTIICSTI3 (0x02000000uL) +#define INTC_ICDICER6_INTIICNAKI3 (0x04000000uL) +#define INTC_ICDICER6_INTIICALI3 (0x08000000uL) +#define INTC_ICDICER6_INTIICTMOI3 (0x10000000uL) +#define INTC_ICDICER6_BRI0 (0x20000000uL) +#define INTC_ICDICER6_ERI0 (0x40000000uL) +#define INTC_ICDICER6_RXI0 (0x80000000uL) + +#define INTC_ICDICER7_TXI0 (0x00000001uL) +#define INTC_ICDICER7_BRI1 (0x00000002uL) +#define INTC_ICDICER7_ERI1 (0x00000004uL) +#define INTC_ICDICER7_RXI1 (0x00000008uL) +#define INTC_ICDICER7_TXI1 (0x00000010uL) +#define INTC_ICDICER7_BRI2 (0x00000020uL) +#define INTC_ICDICER7_ERI2 (0x00000040uL) +#define INTC_ICDICER7_RXI2 (0x00000080uL) +#define INTC_ICDICER7_TXI2 (0x00000100uL) +#define INTC_ICDICER7_BRI3 (0x00000200uL) +#define INTC_ICDICER7_ERI3 (0x00000400uL) +#define INTC_ICDICER7_RXI3 (0x00000800uL) +#define INTC_ICDICER7_TXI3 (0x00001000uL) +#define INTC_ICDICER7_BRI4 (0x00002000uL) +#define INTC_ICDICER7_ERI4 (0x00004000uL) +#define INTC_ICDICER7_RXI4 (0x00008000uL) +#define INTC_ICDICER7_TXI4 (0x00010000uL) +#define INTC_ICDICER7_BRI5 (0x00020000uL) +#define INTC_ICDICER7_ERI5 (0x00040000uL) +#define INTC_ICDICER7_RXI5 (0x00080000uL) +#define INTC_ICDICER7_TXI5 (0x00100000uL) +#define INTC_ICDICER7_BRI6 (0x00200000uL) +#define INTC_ICDICER7_ERI6 (0x00400000uL) +#define INTC_ICDICER7_RXI6 (0x00800000uL) +#define INTC_ICDICER7_TXI6 (0x01000000uL) +#define INTC_ICDICER7_BRI7 (0x02000000uL) +#define INTC_ICDICER7_ERI7 (0x04000000uL) +#define INTC_ICDICER7_RXI7 (0x08000000uL) +#define INTC_ICDICER7_TXI7 (0x10000000uL) +#define INTC_ICDICER7_INTRCANGERR (0x20000000uL) +#define INTC_ICDICER7_INTRCANGRECC (0x40000000uL) +#define INTC_ICDICER7_INTRCAN0REC (0x80000000uL) + +#define INTC_ICDICER8_INTRCAN0ERR (0x00000001uL) +#define INTC_ICDICER8_INTRCAN0TRX (0x00000002uL) +#define INTC_ICDICER8_INTRCAN1REC (0x00000004uL) +#define INTC_ICDICER8_INTRCAN1ERR (0x00000008uL) +#define INTC_ICDICER8_INTRCAN1TRX (0x00000010uL) +#define INTC_ICDICER8_INTRCAN2REC (0x00000020uL) +#define INTC_ICDICER8_INTRCAN2ERR (0x00000040uL) +#define INTC_ICDICER8_INTRCAN2TRX (0x00000080uL) +#define INTC_ICDICER8_INTRCAN3REC (0x00000100uL) +#define INTC_ICDICER8_INTRCAN3ERR (0x00000200uL) +#define INTC_ICDICER8_INTRCAN3TRX (0x00000400uL) +#define INTC_ICDICER8_INTRCAN4REC (0x00000800uL) +#define INTC_ICDICER8_INTRCAN4ERR (0x00001000uL) +#define INTC_ICDICER8_INTRCAN4TRX (0x00002000uL) +#define INTC_ICDICER8_SPEI0 (0x00004000uL) +#define INTC_ICDICER8_SPRI0 (0x00008000uL) +#define INTC_ICDICER8_SPTI0 (0x00010000uL) +#define INTC_ICDICER8_SPEI1 (0x00020000uL) +#define INTC_ICDICER8_SPRI1 (0x00040000uL) +#define INTC_ICDICER8_SPTI1 (0x00080000uL) +#define INTC_ICDICER8_SPEI2 (0x00100000uL) +#define INTC_ICDICER8_SPRI2 (0x00200000uL) +#define INTC_ICDICER8_SPTI2 (0x00400000uL) +#define INTC_ICDICER8_SPEI3 (0x00800000uL) +#define INTC_ICDICER8_SPRI3 (0x01000000uL) +#define INTC_ICDICER8_SPTI3 (0x02000000uL) +#define INTC_ICDICER8_SPEI4 (0x04000000uL) +#define INTC_ICDICER8_SPRI4 (0x08000000uL) +#define INTC_ICDICER8_SPTI4 (0x10000000uL) +#define INTC_ICDICER8_IEBBTD (0x20000000uL) +#define INTC_ICDICER8_IEBBTERR (0x40000000uL) +#define INTC_ICDICER8_IEBBTSTA (0x80000000uL) + +#define INTC_ICDICER9_IEBBTV (0x00000001uL) +#define INTC_ICDICER9_ISY (0x00000002uL) +#define INTC_ICDICER9_IERR (0x00000004uL) +#define INTC_ICDICER9_ITARG (0x00000008uL) +#define INTC_ICDICER9_ISEC (0x00000010uL) +#define INTC_ICDICER9_IBUF (0x00000020uL) +#define INTC_ICDICER9_IREADY (0x00000040uL) +#define INTC_ICDICER9_FLSTE (0x00000080uL) +#define INTC_ICDICER9_FLTENDI (0x00000100uL) +#define INTC_ICDICER9_FLTREQ0I (0x00000200uL) +#define INTC_ICDICER9_FLTREQ1I (0x00000400uL) +#define INTC_ICDICER9_MMC0 (0x00000800uL) +#define INTC_ICDICER9_MMC1 (0x00001000uL) +#define INTC_ICDICER9_MMC2 (0x00002000uL) +#define INTC_ICDICER9_SDHI0_3 (0x00004000uL) +#define INTC_ICDICER9_SDHI0_0 (0x00008000uL) +#define INTC_ICDICER9_SDHI0_1 (0x00010000uL) +#define INTC_ICDICER9_SDHI1_3 (0x00020000uL) +#define INTC_ICDICER9_SDHI1_0 (0x00040000uL) +#define INTC_ICDICER9_SDHI1_1 (0x00080000uL) +#define INTC_ICDICER9_ARM (0x00100000uL) +#define INTC_ICDICER9_PRD (0x00200000uL) +#define INTC_ICDICER9_CUP (0x00400000uL) +#define INTC_ICDICER9_SCUAI0 (0x00800000uL) +#define INTC_ICDICER9_SCUAI1 (0x01000000uL) +#define INTC_ICDICER9_SCUFDI0 (0x02000000uL) +#define INTC_ICDICER9_SCUFDI1 (0x04000000uL) +#define INTC_ICDICER9_SCUFDI2 (0x08000000uL) +#define INTC_ICDICER9_SCUFDI3 (0x10000000uL) +#define INTC_ICDICER9_SCUFUI0 (0x20000000uL) +#define INTC_ICDICER9_SCUFUI1 (0x40000000uL) +#define INTC_ICDICER9_SCUFUI2 (0x80000000uL) + +#define INTC_ICDICER10_SCUFUI3 (0x00000001uL) +#define INTC_ICDICER10_SCUDVI0 (0x00000002uL) +#define INTC_ICDICER10_SCUDVI1 (0x00000004uL) +#define INTC_ICDICER10_SCUDVI2 (0x00000008uL) +#define INTC_ICDICER10_SCUDVI3 (0x00000010uL) +#define INTC_ICDICER10_MLB_CINT (0x00000020uL) +#define INTC_ICDICER10_MLB_SINT (0x00000040uL) +#define INTC_ICDICER10_DRC0 (0x00000080uL) +#define INTC_ICDICER10_DRC1 (0x00000100uL) +#define INTC_ICDICER10_LINI0_INT_T (0x00000800uL) +#define INTC_ICDICER10_LINI0_INT_R (0x00001000uL) +#define INTC_ICDICER10_LINI0_INT_S (0x00002000uL) +#define INTC_ICDICER10_LINI0_INT_M (0x00004000uL) +#define INTC_ICDICER10_LINI1_INT_T (0x00008000uL) +#define INTC_ICDICER10_LINI1_INT_R (0x00010000uL) +#define INTC_ICDICER10_LINI1_INT_S (0x00020000uL) +#define INTC_ICDICER10_LINI1_INT_M (0x00040000uL) +#define INTC_ICDICER10_ERI0 (0x08000000uL) +#define INTC_ICDICER10_RXI0 (0x10000000uL) +#define INTC_ICDICER10_TXI0 (0x20000000uL) +#define INTC_ICDICER10_TEI0 (0x40000000uL) +#define INTC_ICDICER10_ERI1 (0x80000000uL) + +#define INTC_ICDICER11_RXI1 (0x00000001uL) +#define INTC_ICDICER11_TXI1 (0x00000002uL) +#define INTC_ICDICER11_TEI1 (0x00000004uL) +#define INTC_ICDICER11_AVBI_DATA (0x00000008uL) +#define INTC_ICDICER11_AVBI_ERROR (0x00000010uL) +#define INTC_ICDICER11_AVBI_MANAGE (0x00000020uL) +#define INTC_ICDICER11_AVBI_MAC (0x00000040uL) +#define INTC_ICDICER11_ETHERI (0x00000080uL) +#define INTC_ICDICER11_CEUI (0x00001000uL) +#define INTC_ICDICER11_H2XMLB_ERRINT (0x20000000uL) +#define INTC_ICDICER11_H2XIC1_ERRINT (0x40000000uL) +#define INTC_ICDICER11_X2HPERI1_ERRINT (0x80000000uL) + +#define INTC_ICDICER12_X2HPERI2_ERRINT (0x00000001uL) +#define INTC_ICDICER12_X2HPERI34_ERRINT (0x00000002uL) +#define INTC_ICDICER12_X2HPERI5_ERRINT (0x00000004uL) +#define INTC_ICDICER12_X2HPERI67_ERRINT (0x00000008uL) +#define INTC_ICDICER12_X2HDBGR_ERRINT (0x00000010uL) +#define INTC_ICDICER12_X2HBSC_ERRINT (0x00000020uL) +#define INTC_ICDICER12_X2HSPI1_ERRINT (0x00000040uL) +#define INTC_ICDICER12_X2HSPI2_ERRINT (0x00000080uL) +#define INTC_ICDICER12_PRRI (0x00000100uL) +#define INTC_ICDICER12_IFEI0 (0x00000200uL) +#define INTC_ICDICER12_OFFI0 (0x00000400uL) +#define INTC_ICDICER12_PFVEI0 (0x00000800uL) +#define INTC_ICDICER12_IFEI1 (0x00001000uL) +#define INTC_ICDICER12_OFFI1 (0x00002000uL) +#define INTC_ICDICER12_PFVEI1 (0x00004000uL) + +#define INTC_ICDICER13_TINT0 (0x00000001uL) +#define INTC_ICDICER13_TINT1 (0x00000002uL) +#define INTC_ICDICER13_TINT2 (0x00000004uL) +#define INTC_ICDICER13_TINT3 (0x00000008uL) +#define INTC_ICDICER13_TINT4 (0x00000010uL) +#define INTC_ICDICER13_TINT5 (0x00000020uL) +#define INTC_ICDICER13_TINT6 (0x00000040uL) +#define INTC_ICDICER13_TINT7 (0x00000080uL) +#define INTC_ICDICER13_TINT8 (0x00000100uL) +#define INTC_ICDICER13_TINT9 (0x00000200uL) +#define INTC_ICDICER13_TINT10 (0x00000400uL) +#define INTC_ICDICER13_TINT11 (0x00000800uL) +#define INTC_ICDICER13_TINT12 (0x00001000uL) +#define INTC_ICDICER13_TINT13 (0x00002000uL) +#define INTC_ICDICER13_TINT14 (0x00004000uL) +#define INTC_ICDICER13_TINT15 (0x00008000uL) +#define INTC_ICDICER13_TINT16 (0x00010000uL) +#define INTC_ICDICER13_TINT17 (0x00020000uL) +#define INTC_ICDICER13_TINT18 (0x00040000uL) +#define INTC_ICDICER13_TINT19 (0x00080000uL) +#define INTC_ICDICER13_TINT20 (0x00100000uL) +#define INTC_ICDICER13_TINT21 (0x00200000uL) +#define INTC_ICDICER13_TINT22 (0x00400000uL) +#define INTC_ICDICER13_TINT23 (0x00800000uL) +#define INTC_ICDICER13_TINT24 (0x01000000uL) +#define INTC_ICDICER13_TINT25 (0x02000000uL) +#define INTC_ICDICER13_TINT26 (0x04000000uL) +#define INTC_ICDICER13_TINT27 (0x08000000uL) +#define INTC_ICDICER13_TINT28 (0x10000000uL) +#define INTC_ICDICER13_TINT29 (0x20000000uL) +#define INTC_ICDICER13_TINT30 (0x40000000uL) +#define INTC_ICDICER13_TINT31 (0x80000000uL) + +#define INTC_ICDICER14_TINT32 (0x00000001uL) +#define INTC_ICDICER14_TINT33 (0x00000002uL) +#define INTC_ICDICER14_TINT34 (0x00000004uL) +#define INTC_ICDICER14_TINT35 (0x00000008uL) +#define INTC_ICDICER14_TINT36 (0x00000010uL) +#define INTC_ICDICER14_TINT37 (0x00000020uL) +#define INTC_ICDICER14_TINT38 (0x00000040uL) +#define INTC_ICDICER14_TINT39 (0x00000080uL) +#define INTC_ICDICER14_TINT40 (0x00000100uL) +#define INTC_ICDICER14_TINT41 (0x00000200uL) +#define INTC_ICDICER14_TINT42 (0x00000400uL) +#define INTC_ICDICER14_TINT43 (0x00000800uL) +#define INTC_ICDICER14_TINT44 (0x00001000uL) +#define INTC_ICDICER14_TINT45 (0x00002000uL) +#define INTC_ICDICER14_TINT46 (0x00004000uL) +#define INTC_ICDICER14_TINT47 (0x00008000uL) +#define INTC_ICDICER14_TINT48 (0x00010000uL) +#define INTC_ICDICER14_TINT49 (0x00020000uL) +#define INTC_ICDICER14_TINT50 (0x00040000uL) +#define INTC_ICDICER14_TINT51 (0x00080000uL) +#define INTC_ICDICER14_TINT52 (0x00100000uL) +#define INTC_ICDICER14_TINT53 (0x00200000uL) +#define INTC_ICDICER14_TINT54 (0x00400000uL) +#define INTC_ICDICER14_TINT55 (0x00800000uL) +#define INTC_ICDICER14_TINT56 (0x01000000uL) +#define INTC_ICDICER14_TINT57 (0x02000000uL) +#define INTC_ICDICER14_TINT58 (0x04000000uL) +#define INTC_ICDICER14_TINT59 (0x08000000uL) +#define INTC_ICDICER14_TINT60 (0x10000000uL) +#define INTC_ICDICER14_TINT61 (0x20000000uL) +#define INTC_ICDICER14_TINT62 (0x40000000uL) +#define INTC_ICDICER14_TINT63 (0x80000000uL) + +#define INTC_ICDICER15_TINT64 (0x00000001uL) +#define INTC_ICDICER15_TINT65 (0x00000002uL) +#define INTC_ICDICER15_TINT66 (0x00000004uL) +#define INTC_ICDICER15_TINT67 (0x00000008uL) +#define INTC_ICDICER15_TINT68 (0x00000010uL) +#define INTC_ICDICER15_TINT69 (0x00000020uL) +#define INTC_ICDICER15_TINT70 (0x00000040uL) +#define INTC_ICDICER15_TINT71 (0x00000080uL) +#define INTC_ICDICER15_TINT72 (0x00000100uL) +#define INTC_ICDICER15_TINT73 (0x00000200uL) +#define INTC_ICDICER15_TINT74 (0x00000400uL) +#define INTC_ICDICER15_TINT75 (0x00000800uL) +#define INTC_ICDICER15_TINT76 (0x00001000uL) +#define INTC_ICDICER15_TINT77 (0x00002000uL) +#define INTC_ICDICER15_TINT78 (0x00004000uL) +#define INTC_ICDICER15_TINT79 (0x00008000uL) +#define INTC_ICDICER15_TINT80 (0x00010000uL) +#define INTC_ICDICER15_TINT81 (0x00020000uL) +#define INTC_ICDICER15_TINT82 (0x00040000uL) +#define INTC_ICDICER15_TINT83 (0x00080000uL) +#define INTC_ICDICER15_TINT84 (0x00100000uL) +#define INTC_ICDICER15_TINT85 (0x00200000uL) +#define INTC_ICDICER15_TINT86 (0x00400000uL) +#define INTC_ICDICER15_TINT87 (0x00800000uL) +#define INTC_ICDICER15_TINT88 (0x01000000uL) +#define INTC_ICDICER15_TINT89 (0x02000000uL) +#define INTC_ICDICER15_TINT90 (0x04000000uL) +#define INTC_ICDICER15_TINT91 (0x08000000uL) +#define INTC_ICDICER15_TINT92 (0x10000000uL) +#define INTC_ICDICER15_TINT93 (0x20000000uL) +#define INTC_ICDICER15_TINT94 (0x40000000uL) +#define INTC_ICDICER15_TINT95 (0x80000000uL) + +#define INTC_ICDICER16_TINT96 (0x00000001uL) +#define INTC_ICDICER16_TINT97 (0x00000002uL) +#define INTC_ICDICER16_TINT98 (0x00000004uL) +#define INTC_ICDICER16_TINT99 (0x00000008uL) +#define INTC_ICDICER16_TINT100 (0x00000010uL) +#define INTC_ICDICER16_TINT101 (0x00000020uL) +#define INTC_ICDICER16_TINT102 (0x00000040uL) +#define INTC_ICDICER16_TINT103 (0x00000080uL) +#define INTC_ICDICER16_TINT104 (0x00000100uL) +#define INTC_ICDICER16_TINT105 (0x00000200uL) +#define INTC_ICDICER16_TINT106 (0x00000400uL) +#define INTC_ICDICER16_TINT107 (0x00000800uL) +#define INTC_ICDICER16_TINT108 (0x00001000uL) +#define INTC_ICDICER16_TINT109 (0x00002000uL) +#define INTC_ICDICER16_TINT110 (0x00004000uL) +#define INTC_ICDICER16_TINT111 (0x00008000uL) +#define INTC_ICDICER16_TINT112 (0x00010000uL) +#define INTC_ICDICER16_TINT113 (0x00020000uL) +#define INTC_ICDICER16_TINT114 (0x00040000uL) +#define INTC_ICDICER16_TINT115 (0x00080000uL) +#define INTC_ICDICER16_TINT116 (0x00100000uL) +#define INTC_ICDICER16_TINT117 (0x00200000uL) +#define INTC_ICDICER16_TINT118 (0x00400000uL) +#define INTC_ICDICER16_TINT119 (0x00800000uL) +#define INTC_ICDICER16_TINT120 (0x01000000uL) +#define INTC_ICDICER16_TINT121 (0x02000000uL) +#define INTC_ICDICER16_TINT122 (0x04000000uL) +#define INTC_ICDICER16_TINT123 (0x08000000uL) +#define INTC_ICDICER16_TINT124 (0x10000000uL) +#define INTC_ICDICER16_TINT125 (0x20000000uL) +#define INTC_ICDICER16_TINT126 (0x40000000uL) +#define INTC_ICDICER16_TINT127 (0x80000000uL) + +#define INTC_ICDICER17_TINT128 (0x00000001uL) +#define INTC_ICDICER17_TINT129 (0x00000002uL) +#define INTC_ICDICER17_TINT130 (0x00000004uL) +#define INTC_ICDICER17_TINT131 (0x00000008uL) +#define INTC_ICDICER17_TINT132 (0x00000010uL) +#define INTC_ICDICER17_TINT133 (0x00000020uL) +#define INTC_ICDICER17_TINT134 (0x00000040uL) +#define INTC_ICDICER17_TINT135 (0x00000080uL) +#define INTC_ICDICER17_TINT136 (0x00000100uL) +#define INTC_ICDICER17_TINT137 (0x00000200uL) +#define INTC_ICDICER17_TINT138 (0x00000400uL) +#define INTC_ICDICER17_TINT139 (0x00000800uL) +#define INTC_ICDICER17_TINT140 (0x00001000uL) +#define INTC_ICDICER17_TINT141 (0x00002000uL) +#define INTC_ICDICER17_TINT142 (0x00004000uL) +#define INTC_ICDICER17_TINT143 (0x00008000uL) +#define INTC_ICDICER17_TINT144 (0x00010000uL) +#define INTC_ICDICER17_TINT145 (0x00020000uL) +#define INTC_ICDICER17_TINT146 (0x00040000uL) +#define INTC_ICDICER17_TINT147 (0x00080000uL) +#define INTC_ICDICER17_TINT148 (0x00100000uL) +#define INTC_ICDICER17_TINT149 (0x00200000uL) +#define INTC_ICDICER17_TINT150 (0x00400000uL) +#define INTC_ICDICER17_TINT151 (0x00800000uL) +#define INTC_ICDICER17_TINT152 (0x01000000uL) +#define INTC_ICDICER17_TINT153 (0x02000000uL) +#define INTC_ICDICER17_TINT154 (0x04000000uL) +#define INTC_ICDICER17_TINT155 (0x08000000uL) +#define INTC_ICDICER17_TINT156 (0x10000000uL) +#define INTC_ICDICER17_TINT157 (0x20000000uL) +#define INTC_ICDICER17_TINT158 (0x40000000uL) +#define INTC_ICDICER17_TINT159 (0x80000000uL) + +#define INTC_ICDICER18_TINT160 (0x00000001uL) +#define INTC_ICDICER18_TINT161 (0x00000002uL) +#define INTC_ICDICER18_TINT162 (0x00000004uL) +#define INTC_ICDICER18_TINT163 (0x00000008uL) +#define INTC_ICDICER18_TINT164 (0x00000010uL) +#define INTC_ICDICER18_TINT165 (0x00000020uL) +#define INTC_ICDICER18_TINT166 (0x00000040uL) +#define INTC_ICDICER18_TINT167 (0x00000080uL) +#define INTC_ICDICER18_TINT168 (0x00000100uL) +#define INTC_ICDICER18_TINT169 (0x00000200uL) +#define INTC_ICDICER18_TINT170 (0x00000400uL) + +#define INTC_ICDISPR0_SW0 (0x00000001uL) +#define INTC_ICDISPR0_SW1 (0x00000002uL) +#define INTC_ICDISPR0_SW2 (0x00000004uL) +#define INTC_ICDISPR0_SW3 (0x00000008uL) +#define INTC_ICDISPR0_SW4 (0x00000010uL) +#define INTC_ICDISPR0_SW5 (0x00000020uL) +#define INTC_ICDISPR0_SW6 (0x00000040uL) +#define INTC_ICDISPR0_SW7 (0x00000080uL) +#define INTC_ICDISPR0_SW8 (0x00000100uL) +#define INTC_ICDISPR0_SW9 (0x00000200uL) +#define INTC_ICDISPR0_SW10 (0x00000400uL) +#define INTC_ICDISPR0_SW11 (0x00000800uL) +#define INTC_ICDISPR0_SW12 (0x00001000uL) +#define INTC_ICDISPR0_SW13 (0x00002000uL) +#define INTC_ICDISPR0_SW14 (0x00004000uL) +#define INTC_ICDISPR0_SW15 (0x00008000uL) +#define INTC_ICDISPR0_PMUIRQ0 (0x00010000uL) +#define INTC_ICDISPR0_COMMRX0 (0x00020000uL) +#define INTC_ICDISPR0_COMMTX0 (0x00040000uL) +#define INTC_ICDISPR0_CTIIRQ0 (0x00080000uL) + +#define INTC_ICDISPR1_IRQ0 (0x00000001uL) +#define INTC_ICDISPR1_IRQ1 (0x00000002uL) +#define INTC_ICDISPR1_IRQ2 (0x00000004uL) +#define INTC_ICDISPR1_IRQ3 (0x00000008uL) +#define INTC_ICDISPR1_IRQ4 (0x00000010uL) +#define INTC_ICDISPR1_IRQ5 (0x00000020uL) +#define INTC_ICDISPR1_IRQ6 (0x00000040uL) +#define INTC_ICDISPR1_IRQ7 (0x00000080uL) +#define INTC_ICDISPR1_PL310ERR (0x00000100uL) +#define INTC_ICDISPR1_DMAINT0 (0x00000200uL) +#define INTC_ICDISPR1_DMAINT1 (0x00000400uL) +#define INTC_ICDISPR1_DMAINT2 (0x00000800uL) +#define INTC_ICDISPR1_DMAINT3 (0x00001000uL) +#define INTC_ICDISPR1_DMAINT4 (0x00002000uL) +#define INTC_ICDISPR1_DMAINT5 (0x00004000uL) +#define INTC_ICDISPR1_DMAINT6 (0x00008000uL) +#define INTC_ICDISPR1_DMAINT7 (0x00010000uL) +#define INTC_ICDISPR1_DMAINT8 (0x00020000uL) +#define INTC_ICDISPR1_DMAINT9 (0x00040000uL) +#define INTC_ICDISPR1_DMAINT10 (0x00080000uL) +#define INTC_ICDISPR1_DMAINT11 (0x00100000uL) +#define INTC_ICDISPR1_DMAINT12 (0x00200000uL) +#define INTC_ICDISPR1_DMAINT13 (0x00400000uL) +#define INTC_ICDISPR1_DMAINT14 (0x00800000uL) +#define INTC_ICDISPR1_DMAINT15 (0x01000000uL) +#define INTC_ICDISPR1_DMAERR (0x02000000uL) + +#define INTC_ICDISPR2_USBI0 (0x00000200uL) +#define INTC_ICDISPR2_USBI1 (0x00000400uL) +#define INTC_ICDISPR2_S0_VI_VSYNC0 (0x00000800uL) +#define INTC_ICDISPR2_S0_LO_VSYNC0 (0x00001000uL) +#define INTC_ICDISPR2_S0_VSYNCERR0 (0x00002000uL) +#define INTC_ICDISPR2_GR3_VLINE0 (0x00004000uL) +#define INTC_ICDISPR2_S0_VFIELD0 (0x00008000uL) +#define INTC_ICDISPR2_IV1_VBUFERR0 (0x00010000uL) +#define INTC_ICDISPR2_IV3_VBUFERR0 (0x00020000uL) +#define INTC_ICDISPR2_IV5_VBUFERR0 (0x00040000uL) +#define INTC_ICDISPR2_IV6_VBUFERR0 (0x00080000uL) +#define INTC_ICDISPR2_S0_WLINE0 (0x00100000uL) +#define INTC_ICDISPR2_S1_VI_VSYNC0 (0x00200000uL) +#define INTC_ICDISPR2_S1_LO_VSYNC0 (0x00400000uL) +#define INTC_ICDISPR2_S1_VSYNCERR0 (0x00800000uL) +#define INTC_ICDISPR2_S1_VFIELD0 (0x01000000uL) +#define INTC_ICDISPR2_IV2_VBUFERR0 (0x02000000uL) +#define INTC_ICDISPR2_IV4_VBUFERR0 (0x04000000uL) +#define INTC_ICDISPR2_S1_WLINE0 (0x08000000uL) +#define INTC_ICDISPR2_OIR_VI_VSYNC0 (0x10000000uL) +#define INTC_ICDISPR2_OIR_LO_VSYNC0 (0x20000000uL) +#define INTC_ICDISPR2_OIR_VSYNCERR0 (0x40000000uL) +#define INTC_ICDISPR2_OIR_VFIELD0 (0x80000000uL) + +#define INTC_ICDISPR3_IV7_VBUFERR0 (0x00000001uL) +#define INTC_ICDISPR3_IV8_VBUFERR0 (0x00000002uL) +#define INTC_ICDISPR3_S0_VI_VSYNC1 (0x00000008uL) +#define INTC_ICDISPR3_S0_LO_VSYNC1 (0x00000010uL) +#define INTC_ICDISPR3_S0_VSYNCERR1 (0x00000020uL) +#define INTC_ICDISPR3_GR3_VLINE1 (0x00000040uL) +#define INTC_ICDISPR3_S0_VFIELD1 (0x00000080uL) +#define INTC_ICDISPR3_IV1_VBUFERR1 (0x00000100uL) +#define INTC_ICDISPR3_IV3_VBUFERR1 (0x00000200uL) +#define INTC_ICDISPR3_IV5_VBUFERR1 (0x00000400uL) +#define INTC_ICDISPR3_IV6_VBUFERR1 (0x00000800uL) +#define INTC_ICDISPR3_S0_WLINE1 (0x00001000uL) +#define INTC_ICDISPR3_S1_VI_VSYNC1 (0x00002000uL) +#define INTC_ICDISPR3_S1_LO_VSYNC1 (0x00004000uL) +#define INTC_ICDISPR3_S1_VSYNCERR1 (0x00008000uL) +#define INTC_ICDISPR3_S1_VFIELD1 (0x00010000uL) +#define INTC_ICDISPR3_IV2_VBUFERR1 (0x00020000uL) +#define INTC_ICDISPR3_IV4_VBUFERR1 (0x00040000uL) +#define INTC_ICDISPR3_S1_WLINE1 (0x00080000uL) +#define INTC_ICDISPR3_OIR_VI_VSYNC1 (0x00100000uL) +#define INTC_ICDISPR3_OIR_LO_VSYNC1 (0x00200000uL) +#define INTC_ICDISPR3_OIR_VLINE1 (0x00400000uL) +#define INTC_ICDISPR3_OIR_VFIELD1 (0x00800000uL) +#define INTC_ICDISPR3_IV7_VBUFERR1 (0x01000000uL) +#define INTC_ICDISPR3_IV8_VBUFERR1 (0x02000000uL) +#define INTC_ICDISPR3_IMRDI (0x08000000uL) +#define INTC_ICDISPR3_IMR2I0 (0x10000000uL) +#define INTC_ICDISPR3_IMR2I1 (0x20000000uL) +#define INTC_ICDISPR3_JEDI (0x40000000uL) +#define INTC_ICDISPR3_JDTI (0x80000000uL) + +#define INTC_ICDISPR4_CMP0 (0x00000001uL) +#define INTC_ICDISPR4_CMP1 (0x00000002uL) +#define INTC_ICDISPR4_INT0 (0x00000004uL) +#define INTC_ICDISPR4_INT1 (0x00000008uL) +#define INTC_ICDISPR4_INT2 (0x00000010uL) +#define INTC_ICDISPR4_INT3 (0x00000020uL) +#define INTC_ICDISPR4_OSTM0TINT (0x00000040uL) +#define INTC_ICDISPR4_OSTM1TINT (0x00000080uL) +#define INTC_ICDISPR4_CMI (0x00000100uL) +#define INTC_ICDISPR4_WTOUT (0x00000200uL) +#define INTC_ICDISPR4_ITI (0x00000400uL) +#define INTC_ICDISPR4_TGI0A (0x00000800uL) +#define INTC_ICDISPR4_TGI0B (0x00001000uL) +#define INTC_ICDISPR4_TGI0C (0x00002000uL) +#define INTC_ICDISPR4_TGI0D (0x00004000uL) +#define INTC_ICDISPR4_TGI0V (0x00008000uL) +#define INTC_ICDISPR4_TGI0E (0x00010000uL) +#define INTC_ICDISPR4_TGI0F (0x00020000uL) +#define INTC_ICDISPR4_TGI1A (0x00040000uL) +#define INTC_ICDISPR4_TGI1B (0x00080000uL) +#define INTC_ICDISPR4_TGI1V (0x00100000uL) +#define INTC_ICDISPR4_TGI1U (0x00200000uL) +#define INTC_ICDISPR4_TGI2A (0x00400000uL) +#define INTC_ICDISPR4_TGI2B (0x00800000uL) +#define INTC_ICDISPR4_TGI2V (0x01000000uL) +#define INTC_ICDISPR4_TGI2U (0x02000000uL) +#define INTC_ICDISPR4_TGI3A (0x04000000uL) +#define INTC_ICDISPR4_TGI3B (0x08000000uL) +#define INTC_ICDISPR4_TGI3C (0x10000000uL) +#define INTC_ICDISPR4_TGI3D (0x20000000uL) +#define INTC_ICDISPR4_TGI3V (0x40000000uL) +#define INTC_ICDISPR4_TGI4A (0x80000000uL) + +#define INTC_ICDISPR5_TGI4B (0x00000001uL) +#define INTC_ICDISPR5_TGI4C (0x00000002uL) +#define INTC_ICDISPR5_TGI4D (0x00000004uL) +#define INTC_ICDISPR5_TGI4V (0x00000008uL) +#define INTC_ICDISPR5_CMI1 (0x00000010uL) +#define INTC_ICDISPR5_CMI2 (0x00000020uL) +#define INTC_ICDISPR5_SGDEI0 (0x00000040uL) +#define INTC_ICDISPR5_SGDEI1 (0x00000080uL) +#define INTC_ICDISPR5_SGDEI2 (0x00000100uL) +#define INTC_ICDISPR5_SGDEI3 (0x00000200uL) +#define INTC_ICDISPR5_ADI (0x00000400uL) +#define INTC_ICDISPR5_LMTI (0x00000800uL) +#define INTC_ICDISPR5_SSII0 (0x00001000uL) +#define INTC_ICDISPR5_SSIRXI0 (0x00002000uL) +#define INTC_ICDISPR5_SSITXI0 (0x00004000uL) +#define INTC_ICDISPR5_SSII1 (0x00008000uL) +#define INTC_ICDISPR5_SSIRXI1 (0x00010000uL) +#define INTC_ICDISPR5_SSITXI1 (0x00020000uL) +#define INTC_ICDISPR5_SSII2 (0x00040000uL) +#define INTC_ICDISPR5_SSIRTI2 (0x00080000uL) +#define INTC_ICDISPR5_SSII3 (0x00100000uL) +#define INTC_ICDISPR5_SSIRXI3 (0x00200000uL) +#define INTC_ICDISPR5_SSITXI3 (0x00400000uL) +#define INTC_ICDISPR5_SSII4 (0x00800000uL) +#define INTC_ICDISPR5_SSIRTI4 (0x01000000uL) +#define INTC_ICDISPR5_SSII5 (0x02000000uL) +#define INTC_ICDISPR5_SSIRXI5 (0x04000000uL) +#define INTC_ICDISPR5_SSITXI5 (0x08000000uL) +#define INTC_ICDISPR5_SPDIFI (0x10000000uL) +#define INTC_ICDISPR5_INTIICTEI0 (0x20000000uL) +#define INTC_ICDISPR5_INTIICRI0 (0x40000000uL) +#define INTC_ICDISPR5_INTIICTI0 (0x80000000uL) + +#define INTC_ICDISPR6_INTIICSPI0 (0x00000001uL) +#define INTC_ICDISPR6_INTIICSTI0 (0x00000002uL) +#define INTC_ICDISPR6_INTIICNAKI0 (0x00000004uL) +#define INTC_ICDISPR6_INTIICALI0 (0x00000008uL) +#define INTC_ICDISPR6_INTIICTMOI0 (0x00000010uL) +#define INTC_ICDISPR6_INTIICTEI1 (0x00000020uL) +#define INTC_ICDISPR6_INTIICRI1 (0x00000040uL) +#define INTC_ICDISPR6_INTIICTI1 (0x00000080uL) +#define INTC_ICDISPR6_INTIICSPI1 (0x00000100uL) +#define INTC_ICDISPR6_INTIICSTI1 (0x00000200uL) +#define INTC_ICDISPR6_INTIICNAKI1 (0x00000400uL) +#define INTC_ICDISPR6_INTIICALI1 (0x00000800uL) +#define INTC_ICDISPR6_INTIICTMOI1 (0x00001000uL) +#define INTC_ICDISPR6_INTIICTEI2 (0x00002000uL) +#define INTC_ICDISPR6_INTIICRI2 (0x00004000uL) +#define INTC_ICDISPR6_INTIICTI2 (0x00008000uL) +#define INTC_ICDISPR6_INTIICSPI2 (0x00010000uL) +#define INTC_ICDISPR6_INTIICSTI2 (0x00020000uL) +#define INTC_ICDISPR6_INTIICNAKI2 (0x00040000uL) +#define INTC_ICDISPR6_INTIICALI2 (0x00080000uL) +#define INTC_ICDISPR6_INTIICTMOI2 (0x00100000uL) +#define INTC_ICDISPR6_INTIICTEI3 (0x00200000uL) +#define INTC_ICDISPR6_INTIICRI3 (0x00400000uL) +#define INTC_ICDISPR6_INTIICTI3 (0x00800000uL) +#define INTC_ICDISPR6_INTIICSPI3 (0x01000000uL) +#define INTC_ICDISPR6_INTIICSTI3 (0x02000000uL) +#define INTC_ICDISPR6_INTIICNAKI3 (0x04000000uL) +#define INTC_ICDISPR6_INTIICALI3 (0x08000000uL) +#define INTC_ICDISPR6_INTIICTMOI3 (0x10000000uL) +#define INTC_ICDISPR6_BRI0 (0x20000000uL) +#define INTC_ICDISPR6_ERI0 (0x40000000uL) +#define INTC_ICDISPR6_RXI0 (0x80000000uL) + +#define INTC_ICDISPR7_TXI0 (0x00000001uL) +#define INTC_ICDISPR7_BRI1 (0x00000002uL) +#define INTC_ICDISPR7_ERI1 (0x00000004uL) +#define INTC_ICDISPR7_RXI1 (0x00000008uL) +#define INTC_ICDISPR7_TXI1 (0x00000010uL) +#define INTC_ICDISPR7_BRI2 (0x00000020uL) +#define INTC_ICDISPR7_ERI2 (0x00000040uL) +#define INTC_ICDISPR7_RXI2 (0x00000080uL) +#define INTC_ICDISPR7_TXI2 (0x00000100uL) +#define INTC_ICDISPR7_BRI3 (0x00000200uL) +#define INTC_ICDISPR7_ERI3 (0x00000400uL) +#define INTC_ICDISPR7_RXI3 (0x00000800uL) +#define INTC_ICDISPR7_TXI3 (0x00001000uL) +#define INTC_ICDISPR7_BRI4 (0x00002000uL) +#define INTC_ICDISPR7_ERI4 (0x00004000uL) +#define INTC_ICDISPR7_RXI4 (0x00008000uL) +#define INTC_ICDISPR7_TXI4 (0x00010000uL) +#define INTC_ICDISPR7_BRI5 (0x00020000uL) +#define INTC_ICDISPR7_ERI5 (0x00040000uL) +#define INTC_ICDISPR7_RXI5 (0x00080000uL) +#define INTC_ICDISPR7_TXI5 (0x00100000uL) +#define INTC_ICDISPR7_BRI6 (0x00200000uL) +#define INTC_ICDISPR7_ERI6 (0x00400000uL) +#define INTC_ICDISPR7_RXI6 (0x00800000uL) +#define INTC_ICDISPR7_TXI6 (0x01000000uL) +#define INTC_ICDISPR7_BRI7 (0x02000000uL) +#define INTC_ICDISPR7_ERI7 (0x04000000uL) +#define INTC_ICDISPR7_RXI7 (0x08000000uL) +#define INTC_ICDISPR7_TXI7 (0x10000000uL) +#define INTC_ICDISPR7_INTRCANGERR (0x20000000uL) +#define INTC_ICDISPR7_INTRCANGRECC (0x40000000uL) +#define INTC_ICDISPR7_INTRCAN0REC (0x80000000uL) + +#define INTC_ICDISPR8_INTRCAN0ERR (0x00000001uL) +#define INTC_ICDISPR8_INTRCAN0TRX (0x00000002uL) +#define INTC_ICDISPR8_INTRCAN1REC (0x00000004uL) +#define INTC_ICDISPR8_INTRCAN1ERR (0x00000008uL) +#define INTC_ICDISPR8_INTRCAN1TRX (0x00000010uL) +#define INTC_ICDISPR8_INTRCAN2REC (0x00000020uL) +#define INTC_ICDISPR8_INTRCAN2ERR (0x00000040uL) +#define INTC_ICDISPR8_INTRCAN2TRX (0x00000080uL) +#define INTC_ICDISPR8_INTRCAN3REC (0x00000100uL) +#define INTC_ICDISPR8_INTRCAN3ERR (0x00000200uL) +#define INTC_ICDISPR8_INTRCAN3TRX (0x00000400uL) +#define INTC_ICDISPR8_INTRCAN4REC (0x00000800uL) +#define INTC_ICDISPR8_INTRCAN4ERR (0x00001000uL) +#define INTC_ICDISPR8_INTRCAN4TRX (0x00002000uL) +#define INTC_ICDISPR8_SPEI0 (0x00004000uL) +#define INTC_ICDISPR8_SPRI0 (0x00008000uL) +#define INTC_ICDISPR8_SPTI0 (0x00010000uL) +#define INTC_ICDISPR8_SPEI1 (0x00020000uL) +#define INTC_ICDISPR8_SPRI1 (0x00040000uL) +#define INTC_ICDISPR8_SPTI1 (0x00080000uL) +#define INTC_ICDISPR8_SPEI2 (0x00100000uL) +#define INTC_ICDISPR8_SPRI2 (0x00200000uL) +#define INTC_ICDISPR8_SPTI2 (0x00400000uL) +#define INTC_ICDISPR8_SPEI3 (0x00800000uL) +#define INTC_ICDISPR8_SPRI3 (0x01000000uL) +#define INTC_ICDISPR8_SPTI3 (0x02000000uL) +#define INTC_ICDISPR8_SPEI4 (0x04000000uL) +#define INTC_ICDISPR8_SPRI4 (0x08000000uL) +#define INTC_ICDISPR8_SPTI4 (0x10000000uL) +#define INTC_ICDISPR8_IEBBTD (0x20000000uL) +#define INTC_ICDISPR8_IEBBTERR (0x40000000uL) +#define INTC_ICDISPR8_IEBBTSTA (0x80000000uL) + +#define INTC_ICDISPR9_IEBBTV (0x00000001uL) +#define INTC_ICDISPR9_ISY (0x00000002uL) +#define INTC_ICDISPR9_IERR (0x00000004uL) +#define INTC_ICDISPR9_ITARG (0x00000008uL) +#define INTC_ICDISPR9_ISEC (0x00000010uL) +#define INTC_ICDISPR9_IBUF (0x00000020uL) +#define INTC_ICDISPR9_IREADY (0x00000040uL) +#define INTC_ICDISPR9_FLSTE (0x00000080uL) +#define INTC_ICDISPR9_FLTENDI (0x00000100uL) +#define INTC_ICDISPR9_FLTREQ0I (0x00000200uL) +#define INTC_ICDISPR9_FLTREQ1I (0x00000400uL) +#define INTC_ICDISPR9_MMC0 (0x00000800uL) +#define INTC_ICDISPR9_MMC1 (0x00001000uL) +#define INTC_ICDISPR9_MMC2 (0x00002000uL) +#define INTC_ICDISPR9_SDHI0_3 (0x00004000uL) +#define INTC_ICDISPR9_SDHI0_0 (0x00008000uL) +#define INTC_ICDISPR9_SDHI0_1 (0x00010000uL) +#define INTC_ICDISPR9_SDHI1_3 (0x00020000uL) +#define INTC_ICDISPR9_SDHI1_0 (0x00040000uL) +#define INTC_ICDISPR9_SDHI1_1 (0x00080000uL) +#define INTC_ICDISPR9_ARM (0x00100000uL) +#define INTC_ICDISPR9_PRD (0x00200000uL) +#define INTC_ICDISPR9_CUP (0x00400000uL) +#define INTC_ICDISPR9_SCUAI0 (0x00800000uL) +#define INTC_ICDISPR9_SCUAI1 (0x01000000uL) +#define INTC_ICDISPR9_SCUFDI0 (0x02000000uL) +#define INTC_ICDISPR9_SCUFDI1 (0x04000000uL) +#define INTC_ICDISPR9_SCUFDI2 (0x08000000uL) +#define INTC_ICDISPR9_SCUFDI3 (0x10000000uL) +#define INTC_ICDISPR9_SCUFUI0 (0x20000000uL) +#define INTC_ICDISPR9_SCUFUI1 (0x40000000uL) +#define INTC_ICDISPR9_SCUFUI2 (0x80000000uL) + +#define INTC_ICDISPR10_SCUFUI3 (0x00000001uL) +#define INTC_ICDISPR10_SCUDVI0 (0x00000002uL) +#define INTC_ICDISPR10_SCUDVI1 (0x00000004uL) +#define INTC_ICDISPR10_SCUDVI2 (0x00000008uL) +#define INTC_ICDISPR10_SCUDVI3 (0x00000010uL) +#define INTC_ICDISPR10_MLB_CINT (0x00000020uL) +#define INTC_ICDISPR10_MLB_SINT (0x00000040uL) +#define INTC_ICDISPR10_DRC0 (0x00000080uL) +#define INTC_ICDISPR10_DRC1 (0x00000100uL) +#define INTC_ICDISPR10_LINI0_INT_T (0x00000800uL) +#define INTC_ICDISPR10_LINI0_INT_R (0x00001000uL) +#define INTC_ICDISPR10_LINI0_INT_S (0x00002000uL) +#define INTC_ICDISPR10_LINI0_INT_M (0x00004000uL) +#define INTC_ICDISPR10_LINI1_INT_T (0x00008000uL) +#define INTC_ICDISPR10_LINI1_INT_R (0x00010000uL) +#define INTC_ICDISPR10_LINI1_INT_S (0x00020000uL) +#define INTC_ICDISPR10_LINI1_INT_M (0x00040000uL) +#define INTC_ICDISPR10_ERI0 (0x08000000uL) +#define INTC_ICDISPR10_RXI0 (0x10000000uL) +#define INTC_ICDISPR10_TXI0 (0x20000000uL) +#define INTC_ICDISPR10_TEI0 (0x40000000uL) +#define INTC_ICDISPR10_ERI1 (0x80000000uL) + +#define INTC_ICDISPR11_RXI1 (0x00000001uL) +#define INTC_ICDISPR11_TXI1 (0x00000002uL) +#define INTC_ICDISPR11_TEI1 (0x00000004uL) +#define INTC_ICDISPR11_AVBI_DATA (0x00000008uL) +#define INTC_ICDISPR11_AVBI_ERROR (0x00000010uL) +#define INTC_ICDISPR11_AVBI_MANAGE (0x00000020uL) +#define INTC_ICDISPR11_AVBI_MAC (0x00000040uL) +#define INTC_ICDISPR11_ETHERI (0x00000080uL) +#define INTC_ICDISPR11_CEUI (0x00001000uL) +#define INTC_ICDISPR11_H2XMLB_ERRINT (0x20000000uL) +#define INTC_ICDISPR11_H2XIC1_ERRINT (0x40000000uL) +#define INTC_ICDISPR11_X2HPERI1_ERRINT (0x80000000uL) + +#define INTC_ICDISPR12_X2HPERI2_ERRINT (0x00000001uL) +#define INTC_ICDISPR12_X2HPERI34_ERRINT (0x00000002uL) +#define INTC_ICDISPR12_X2HPERI5_ERRINT (0x00000004uL) +#define INTC_ICDISPR12_X2HPERI67_ERRINT (0x00000008uL) +#define INTC_ICDISPR12_X2HDBGR_ERRINT (0x00000010uL) +#define INTC_ICDISPR12_X2HBSC_ERRINT (0x00000020uL) +#define INTC_ICDISPR12_X2HSPI1_ERRINT (0x00000040uL) +#define INTC_ICDISPR12_X2HSPI2_ERRINT (0x00000080uL) +#define INTC_ICDISPR12_PRRI (0x00000100uL) +#define INTC_ICDISPR12_IFEI0 (0x00000200uL) +#define INTC_ICDISPR12_OFFI0 (0x00000400uL) +#define INTC_ICDISPR12_PFVEI0 (0x00000800uL) +#define INTC_ICDISPR12_IFEI1 (0x00001000uL) +#define INTC_ICDISPR12_OFFI1 (0x00002000uL) +#define INTC_ICDISPR12_PFVEI1 (0x00004000uL) + +#define INTC_ICDISPR13_TINT0 (0x00000001uL) +#define INTC_ICDISPR13_TINT1 (0x00000002uL) +#define INTC_ICDISPR13_TINT2 (0x00000004uL) +#define INTC_ICDISPR13_TINT3 (0x00000008uL) +#define INTC_ICDISPR13_TINT4 (0x00000010uL) +#define INTC_ICDISPR13_TINT5 (0x00000020uL) +#define INTC_ICDISPR13_TINT6 (0x00000040uL) +#define INTC_ICDISPR13_TINT7 (0x00000080uL) +#define INTC_ICDISPR13_TINT8 (0x00000100uL) +#define INTC_ICDISPR13_TINT9 (0x00000200uL) +#define INTC_ICDISPR13_TINT10 (0x00000400uL) +#define INTC_ICDISPR13_TINT11 (0x00000800uL) +#define INTC_ICDISPR13_TINT12 (0x00001000uL) +#define INTC_ICDISPR13_TINT13 (0x00002000uL) +#define INTC_ICDISPR13_TINT14 (0x00004000uL) +#define INTC_ICDISPR13_TINT15 (0x00008000uL) +#define INTC_ICDISPR13_TINT16 (0x00010000uL) +#define INTC_ICDISPR13_TINT17 (0x00020000uL) +#define INTC_ICDISPR13_TINT18 (0x00040000uL) +#define INTC_ICDISPR13_TINT19 (0x00080000uL) +#define INTC_ICDISPR13_TINT20 (0x00100000uL) +#define INTC_ICDISPR13_TINT21 (0x00200000uL) +#define INTC_ICDISPR13_TINT22 (0x00400000uL) +#define INTC_ICDISPR13_TINT23 (0x00800000uL) +#define INTC_ICDISPR13_TINT24 (0x01000000uL) +#define INTC_ICDISPR13_TINT25 (0x02000000uL) +#define INTC_ICDISPR13_TINT26 (0x04000000uL) +#define INTC_ICDISPR13_TINT27 (0x08000000uL) +#define INTC_ICDISPR13_TINT28 (0x10000000uL) +#define INTC_ICDISPR13_TINT29 (0x20000000uL) +#define INTC_ICDISPR13_TINT30 (0x40000000uL) +#define INTC_ICDISPR13_TINT31 (0x80000000uL) + +#define INTC_ICDISPR14_TINT32 (0x00000001uL) +#define INTC_ICDISPR14_TINT33 (0x00000002uL) +#define INTC_ICDISPR14_TINT34 (0x00000004uL) +#define INTC_ICDISPR14_TINT35 (0x00000008uL) +#define INTC_ICDISPR14_TINT36 (0x00000010uL) +#define INTC_ICDISPR14_TINT37 (0x00000020uL) +#define INTC_ICDISPR14_TINT38 (0x00000040uL) +#define INTC_ICDISPR14_TINT39 (0x00000080uL) +#define INTC_ICDISPR14_TINT40 (0x00000100uL) +#define INTC_ICDISPR14_TINT41 (0x00000200uL) +#define INTC_ICDISPR14_TINT42 (0x00000400uL) +#define INTC_ICDISPR14_TINT43 (0x00000800uL) +#define INTC_ICDISPR14_TINT44 (0x00001000uL) +#define INTC_ICDISPR14_TINT45 (0x00002000uL) +#define INTC_ICDISPR14_TINT46 (0x00004000uL) +#define INTC_ICDISPR14_TINT47 (0x00008000uL) +#define INTC_ICDISPR14_TINT48 (0x00010000uL) +#define INTC_ICDISPR14_TINT49 (0x00020000uL) +#define INTC_ICDISPR14_TINT50 (0x00040000uL) +#define INTC_ICDISPR14_TINT51 (0x00080000uL) +#define INTC_ICDISPR14_TINT52 (0x00100000uL) +#define INTC_ICDISPR14_TINT53 (0x00200000uL) +#define INTC_ICDISPR14_TINT54 (0x00400000uL) +#define INTC_ICDISPR14_TINT55 (0x00800000uL) +#define INTC_ICDISPR14_TINT56 (0x01000000uL) +#define INTC_ICDISPR14_TINT57 (0x02000000uL) +#define INTC_ICDISPR14_TINT58 (0x04000000uL) +#define INTC_ICDISPR14_TINT59 (0x08000000uL) +#define INTC_ICDISPR14_TINT60 (0x10000000uL) +#define INTC_ICDISPR14_TINT61 (0x20000000uL) +#define INTC_ICDISPR14_TINT62 (0x40000000uL) +#define INTC_ICDISPR14_TINT63 (0x80000000uL) + +#define INTC_ICDISPR15_TINT64 (0x00000001uL) +#define INTC_ICDISPR15_TINT65 (0x00000002uL) +#define INTC_ICDISPR15_TINT66 (0x00000004uL) +#define INTC_ICDISPR15_TINT67 (0x00000008uL) +#define INTC_ICDISPR15_TINT68 (0x00000010uL) +#define INTC_ICDISPR15_TINT69 (0x00000020uL) +#define INTC_ICDISPR15_TINT70 (0x00000040uL) +#define INTC_ICDISPR15_TINT71 (0x00000080uL) +#define INTC_ICDISPR15_TINT72 (0x00000100uL) +#define INTC_ICDISPR15_TINT73 (0x00000200uL) +#define INTC_ICDISPR15_TINT74 (0x00000400uL) +#define INTC_ICDISPR15_TINT75 (0x00000800uL) +#define INTC_ICDISPR15_TINT76 (0x00001000uL) +#define INTC_ICDISPR15_TINT77 (0x00002000uL) +#define INTC_ICDISPR15_TINT78 (0x00004000uL) +#define INTC_ICDISPR15_TINT79 (0x00008000uL) +#define INTC_ICDISPR15_TINT80 (0x00010000uL) +#define INTC_ICDISPR15_TINT81 (0x00020000uL) +#define INTC_ICDISPR15_TINT82 (0x00040000uL) +#define INTC_ICDISPR15_TINT83 (0x00080000uL) +#define INTC_ICDISPR15_TINT84 (0x00100000uL) +#define INTC_ICDISPR15_TINT85 (0x00200000uL) +#define INTC_ICDISPR15_TINT86 (0x00400000uL) +#define INTC_ICDISPR15_TINT87 (0x00800000uL) +#define INTC_ICDISPR15_TINT88 (0x01000000uL) +#define INTC_ICDISPR15_TINT89 (0x02000000uL) +#define INTC_ICDISPR15_TINT90 (0x04000000uL) +#define INTC_ICDISPR15_TINT91 (0x08000000uL) +#define INTC_ICDISPR15_TINT92 (0x10000000uL) +#define INTC_ICDISPR15_TINT93 (0x20000000uL) +#define INTC_ICDISPR15_TINT94 (0x40000000uL) +#define INTC_ICDISPR15_TINT95 (0x80000000uL) + +#define INTC_ICDISPR16_TINT96 (0x00000001uL) +#define INTC_ICDISPR16_TINT97 (0x00000002uL) +#define INTC_ICDISPR16_TINT98 (0x00000004uL) +#define INTC_ICDISPR16_TINT99 (0x00000008uL) +#define INTC_ICDISPR16_TINT100 (0x00000010uL) +#define INTC_ICDISPR16_TINT101 (0x00000020uL) +#define INTC_ICDISPR16_TINT102 (0x00000040uL) +#define INTC_ICDISPR16_TINT103 (0x00000080uL) +#define INTC_ICDISPR16_TINT104 (0x00000100uL) +#define INTC_ICDISPR16_TINT105 (0x00000200uL) +#define INTC_ICDISPR16_TINT106 (0x00000400uL) +#define INTC_ICDISPR16_TINT107 (0x00000800uL) +#define INTC_ICDISPR16_TINT108 (0x00001000uL) +#define INTC_ICDISPR16_TINT109 (0x00002000uL) +#define INTC_ICDISPR16_TINT110 (0x00004000uL) +#define INTC_ICDISPR16_TINT111 (0x00008000uL) +#define INTC_ICDISPR16_TINT112 (0x00010000uL) +#define INTC_ICDISPR16_TINT113 (0x00020000uL) +#define INTC_ICDISPR16_TINT114 (0x00040000uL) +#define INTC_ICDISPR16_TINT115 (0x00080000uL) +#define INTC_ICDISPR16_TINT116 (0x00100000uL) +#define INTC_ICDISPR16_TINT117 (0x00200000uL) +#define INTC_ICDISPR16_TINT118 (0x00400000uL) +#define INTC_ICDISPR16_TINT119 (0x00800000uL) +#define INTC_ICDISPR16_TINT120 (0x01000000uL) +#define INTC_ICDISPR16_TINT121 (0x02000000uL) +#define INTC_ICDISPR16_TINT122 (0x04000000uL) +#define INTC_ICDISPR16_TINT123 (0x08000000uL) +#define INTC_ICDISPR16_TINT124 (0x10000000uL) +#define INTC_ICDISPR16_TINT125 (0x20000000uL) +#define INTC_ICDISPR16_TINT126 (0x40000000uL) +#define INTC_ICDISPR16_TINT127 (0x80000000uL) + +#define INTC_ICDISPR17_TINT128 (0x00000001uL) +#define INTC_ICDISPR17_TINT129 (0x00000002uL) +#define INTC_ICDISPR17_TINT130 (0x00000004uL) +#define INTC_ICDISPR17_TINT131 (0x00000008uL) +#define INTC_ICDISPR17_TINT132 (0x00000010uL) +#define INTC_ICDISPR17_TINT133 (0x00000020uL) +#define INTC_ICDISPR17_TINT134 (0x00000040uL) +#define INTC_ICDISPR17_TINT135 (0x00000080uL) +#define INTC_ICDISPR17_TINT136 (0x00000100uL) +#define INTC_ICDISPR17_TINT137 (0x00000200uL) +#define INTC_ICDISPR17_TINT138 (0x00000400uL) +#define INTC_ICDISPR17_TINT139 (0x00000800uL) +#define INTC_ICDISPR17_TINT140 (0x00001000uL) +#define INTC_ICDISPR17_TINT141 (0x00002000uL) +#define INTC_ICDISPR17_TINT142 (0x00004000uL) +#define INTC_ICDISPR17_TINT143 (0x00008000uL) +#define INTC_ICDISPR17_TINT144 (0x00010000uL) +#define INTC_ICDISPR17_TINT145 (0x00020000uL) +#define INTC_ICDISPR17_TINT146 (0x00040000uL) +#define INTC_ICDISPR17_TINT147 (0x00080000uL) +#define INTC_ICDISPR17_TINT148 (0x00100000uL) +#define INTC_ICDISPR17_TINT149 (0x00200000uL) +#define INTC_ICDISPR17_TINT150 (0x00400000uL) +#define INTC_ICDISPR17_TINT151 (0x00800000uL) +#define INTC_ICDISPR17_TINT152 (0x01000000uL) +#define INTC_ICDISPR17_TINT153 (0x02000000uL) +#define INTC_ICDISPR17_TINT154 (0x04000000uL) +#define INTC_ICDISPR17_TINT155 (0x08000000uL) +#define INTC_ICDISPR17_TINT156 (0x10000000uL) +#define INTC_ICDISPR17_TINT157 (0x20000000uL) +#define INTC_ICDISPR17_TINT158 (0x40000000uL) +#define INTC_ICDISPR17_TINT159 (0x80000000uL) + +#define INTC_ICDISPR18_TINT160 (0x00000001uL) +#define INTC_ICDISPR18_TINT161 (0x00000002uL) +#define INTC_ICDISPR18_TINT162 (0x00000004uL) +#define INTC_ICDISPR18_TINT163 (0x00000008uL) +#define INTC_ICDISPR18_TINT164 (0x00000010uL) +#define INTC_ICDISPR18_TINT165 (0x00000020uL) +#define INTC_ICDISPR18_TINT166 (0x00000040uL) +#define INTC_ICDISPR18_TINT167 (0x00000080uL) +#define INTC_ICDISPR18_TINT168 (0x00000100uL) +#define INTC_ICDISPR18_TINT169 (0x00000200uL) +#define INTC_ICDISPR18_TINT170 (0x00000400uL) + +#define INTC_ICDICPR0_SW0 (0x00000001uL) +#define INTC_ICDICPR0_SW1 (0x00000002uL) +#define INTC_ICDICPR0_SW2 (0x00000004uL) +#define INTC_ICDICPR0_SW3 (0x00000008uL) +#define INTC_ICDICPR0_SW4 (0x00000010uL) +#define INTC_ICDICPR0_SW5 (0x00000020uL) +#define INTC_ICDICPR0_SW6 (0x00000040uL) +#define INTC_ICDICPR0_SW7 (0x00000080uL) +#define INTC_ICDICPR0_SW8 (0x00000100uL) +#define INTC_ICDICPR0_SW9 (0x00000200uL) +#define INTC_ICDICPR0_SW10 (0x00000400uL) +#define INTC_ICDICPR0_SW11 (0x00000800uL) +#define INTC_ICDICPR0_SW12 (0x00001000uL) +#define INTC_ICDICPR0_SW13 (0x00002000uL) +#define INTC_ICDICPR0_SW14 (0x00004000uL) +#define INTC_ICDICPR0_SW15 (0x00008000uL) +#define INTC_ICDICPR0_PMUIRQ0 (0x00010000uL) +#define INTC_ICDICPR0_COMMRX0 (0x00020000uL) +#define INTC_ICDICPR0_COMMTX0 (0x00040000uL) +#define INTC_ICDICPR0_CTIIRQ0 (0x00080000uL) + +#define INTC_ICDICPR1_IRQ0 (0x00000001uL) +#define INTC_ICDICPR1_IRQ1 (0x00000002uL) +#define INTC_ICDICPR1_IRQ2 (0x00000004uL) +#define INTC_ICDICPR1_IRQ3 (0x00000008uL) +#define INTC_ICDICPR1_IRQ4 (0x00000010uL) +#define INTC_ICDICPR1_IRQ5 (0x00000020uL) +#define INTC_ICDICPR1_IRQ6 (0x00000040uL) +#define INTC_ICDICPR1_IRQ7 (0x00000080uL) +#define INTC_ICDICPR1_PL310ERR (0x00000100uL) +#define INTC_ICDICPR1_DMAINT0 (0x00000200uL) +#define INTC_ICDICPR1_DMAINT1 (0x00000400uL) +#define INTC_ICDICPR1_DMAINT2 (0x00000800uL) +#define INTC_ICDICPR1_DMAINT3 (0x00001000uL) +#define INTC_ICDICPR1_DMAINT4 (0x00002000uL) +#define INTC_ICDICPR1_DMAINT5 (0x00004000uL) +#define INTC_ICDICPR1_DMAINT6 (0x00008000uL) +#define INTC_ICDICPR1_DMAINT7 (0x00010000uL) +#define INTC_ICDICPR1_DMAINT8 (0x00020000uL) +#define INTC_ICDICPR1_DMAINT9 (0x00040000uL) +#define INTC_ICDICPR1_DMAINT10 (0x00080000uL) +#define INTC_ICDICPR1_DMAINT11 (0x00100000uL) +#define INTC_ICDICPR1_DMAINT12 (0x00200000uL) +#define INTC_ICDICPR1_DMAINT13 (0x00400000uL) +#define INTC_ICDICPR1_DMAINT14 (0x00800000uL) +#define INTC_ICDICPR1_DMAINT15 (0x01000000uL) +#define INTC_ICDICPR1_DMAERR (0x02000000uL) + +#define INTC_ICDICPR2_USBI0 (0x00000200uL) +#define INTC_ICDICPR2_USBI1 (0x00000400uL) +#define INTC_ICDICPR2_S0_VI_VSYNC0 (0x00000800uL) +#define INTC_ICDICPR2_S0_LO_VSYNC0 (0x00001000uL) +#define INTC_ICDICPR2_S0_VSYNCERR0 (0x00002000uL) +#define INTC_ICDICPR2_GR3_VLINE0 (0x00004000uL) +#define INTC_ICDICPR2_S0_VFIELD0 (0x00008000uL) +#define INTC_ICDICPR2_IV1_VBUFERR0 (0x00010000uL) +#define INTC_ICDICPR2_IV3_VBUFERR0 (0x00020000uL) +#define INTC_ICDICPR2_IV5_VBUFERR0 (0x00040000uL) +#define INTC_ICDICPR2_IV6_VBUFERR0 (0x00080000uL) +#define INTC_ICDICPR2_S0_WLINE0 (0x00100000uL) +#define INTC_ICDICPR2_S1_VI_VSYNC0 (0x00200000uL) +#define INTC_ICDICPR2_S1_LO_VSYNC0 (0x00400000uL) +#define INTC_ICDICPR2_S1_VSYNCERR0 (0x00800000uL) +#define INTC_ICDICPR2_S1_VFIELD0 (0x01000000uL) +#define INTC_ICDICPR2_IV2_VBUFERR0 (0x02000000uL) +#define INTC_ICDICPR2_IV4_VBUFERR0 (0x04000000uL) +#define INTC_ICDICPR2_S1_WLINE0 (0x08000000uL) +#define INTC_ICDICPR2_OIR_VI_VSYNC0 (0x10000000uL) +#define INTC_ICDICPR2_OIR_LO_VSYNC0 (0x20000000uL) +#define INTC_ICDICPR2_OIR_VSYNCERR0 (0x40000000uL) +#define INTC_ICDICPR2_OIR_VFIELD0 (0x80000000uL) + +#define INTC_ICDICPR3_IV7_VBUFERR0 (0x00000001uL) +#define INTC_ICDICPR3_IV8_VBUFERR0 (0x00000002uL) +#define INTC_ICDICPR3_S0_VI_VSYNC1 (0x00000008uL) +#define INTC_ICDICPR3_S0_LO_VSYNC1 (0x00000010uL) +#define INTC_ICDICPR3_S0_VSYNCERR1 (0x00000020uL) +#define INTC_ICDICPR3_GR3_VLINE1 (0x00000040uL) +#define INTC_ICDICPR3_S0_VFIELD1 (0x00000080uL) +#define INTC_ICDICPR3_IV1_VBUFERR1 (0x00000100uL) +#define INTC_ICDICPR3_IV3_VBUFERR1 (0x00000200uL) +#define INTC_ICDICPR3_IV5_VBUFERR1 (0x00000400uL) +#define INTC_ICDICPR3_IV6_VBUFERR1 (0x00000800uL) +#define INTC_ICDICPR3_S0_WLINE1 (0x00001000uL) +#define INTC_ICDICPR3_S1_VI_VSYNC1 (0x00002000uL) +#define INTC_ICDICPR3_S1_LO_VSYNC1 (0x00004000uL) +#define INTC_ICDICPR3_S1_VSYNCERR1 (0x00008000uL) +#define INTC_ICDICPR3_S1_VFIELD1 (0x00010000uL) +#define INTC_ICDICPR3_IV2_VBUFERR1 (0x00020000uL) +#define INTC_ICDICPR3_IV4_VBUFERR1 (0x00040000uL) +#define INTC_ICDICPR3_S1_WLINE1 (0x00080000uL) +#define INTC_ICDICPR3_OIR_VI_VSYNC1 (0x00100000uL) +#define INTC_ICDICPR3_OIR_LO_VSYNC1 (0x00200000uL) +#define INTC_ICDICPR3_OIR_VLINE1 (0x00400000uL) +#define INTC_ICDICPR3_OIR_VFIELD1 (0x00800000uL) +#define INTC_ICDICPR3_IV7_VBUFERR1 (0x01000000uL) +#define INTC_ICDICPR3_IV8_VBUFERR1 (0x02000000uL) +#define INTC_ICDICPR3_IMRDI (0x08000000uL) +#define INTC_ICDICPR3_IMR2I0 (0x10000000uL) +#define INTC_ICDICPR3_IMR2I1 (0x20000000uL) +#define INTC_ICDICPR3_JEDI (0x40000000uL) +#define INTC_ICDICPR3_JDTI (0x80000000uL) + +#define INTC_ICDICPR4_CMP0 (0x00000001uL) +#define INTC_ICDICPR4_CMP1 (0x00000002uL) +#define INTC_ICDICPR4_INT0 (0x00000004uL) +#define INTC_ICDICPR4_INT1 (0x00000008uL) +#define INTC_ICDICPR4_INT2 (0x00000010uL) +#define INTC_ICDICPR4_INT3 (0x00000020uL) +#define INTC_ICDICPR4_OSTM0TINT (0x00000040uL) +#define INTC_ICDICPR4_OSTM1TINT (0x00000080uL) +#define INTC_ICDICPR4_CMI (0x00000100uL) +#define INTC_ICDICPR4_WTOUT (0x00000200uL) +#define INTC_ICDICPR4_ITI (0x00000400uL) +#define INTC_ICDICPR4_TGI0A (0x00000800uL) +#define INTC_ICDICPR4_TGI0B (0x00001000uL) +#define INTC_ICDICPR4_TGI0C (0x00002000uL) +#define INTC_ICDICPR4_TGI0D (0x00004000uL) +#define INTC_ICDICPR4_TGI0V (0x00008000uL) +#define INTC_ICDICPR4_TGI0E (0x00010000uL) +#define INTC_ICDICPR4_TGI0F (0x00020000uL) +#define INTC_ICDICPR4_TGI1A (0x00040000uL) +#define INTC_ICDICPR4_TGI1B (0x00080000uL) +#define INTC_ICDICPR4_TGI1V (0x00100000uL) +#define INTC_ICDICPR4_TGI1U (0x00200000uL) +#define INTC_ICDICPR4_TGI2A (0x00400000uL) +#define INTC_ICDICPR4_TGI2B (0x00800000uL) +#define INTC_ICDICPR4_TGI2V (0x01000000uL) +#define INTC_ICDICPR4_TGI2U (0x02000000uL) +#define INTC_ICDICPR4_TGI3A (0x04000000uL) +#define INTC_ICDICPR4_TGI3B (0x08000000uL) +#define INTC_ICDICPR4_TGI3C (0x10000000uL) +#define INTC_ICDICPR4_TGI3D (0x20000000uL) +#define INTC_ICDICPR4_TGI3V (0x40000000uL) +#define INTC_ICDICPR4_TGI4A (0x80000000uL) + +#define INTC_ICDICPR5_TGI4B (0x00000001uL) +#define INTC_ICDICPR5_TGI4C (0x00000002uL) +#define INTC_ICDICPR5_TGI4D (0x00000004uL) +#define INTC_ICDICPR5_TGI4V (0x00000008uL) +#define INTC_ICDICPR5_CMI1 (0x00000010uL) +#define INTC_ICDICPR5_CMI2 (0x00000020uL) +#define INTC_ICDICPR5_SGDEI0 (0x00000040uL) +#define INTC_ICDICPR5_SGDEI1 (0x00000080uL) +#define INTC_ICDICPR5_SGDEI2 (0x00000100uL) +#define INTC_ICDICPR5_SGDEI3 (0x00000200uL) +#define INTC_ICDICPR5_ADI (0x00000400uL) +#define INTC_ICDICPR5_LMTI (0x00000800uL) +#define INTC_ICDICPR5_SSII0 (0x00001000uL) +#define INTC_ICDICPR5_SSIRXI0 (0x00002000uL) +#define INTC_ICDICPR5_SSITXI0 (0x00004000uL) +#define INTC_ICDICPR5_SSII1 (0x00008000uL) +#define INTC_ICDICPR5_SSIRXI1 (0x00010000uL) +#define INTC_ICDICPR5_SSITXI1 (0x00020000uL) +#define INTC_ICDICPR5_SSII2 (0x00040000uL) +#define INTC_ICDICPR5_SSIRTI2 (0x00080000uL) +#define INTC_ICDICPR5_SSII3 (0x00100000uL) +#define INTC_ICDICPR5_SSIRXI3 (0x00200000uL) +#define INTC_ICDICPR5_SSITXI3 (0x00400000uL) +#define INTC_ICDICPR5_SSII4 (0x00800000uL) +#define INTC_ICDICPR5_SSIRTI4 (0x01000000uL) +#define INTC_ICDICPR5_SSII5 (0x02000000uL) +#define INTC_ICDICPR5_SSIRXI5 (0x04000000uL) +#define INTC_ICDICPR5_SSITXI5 (0x08000000uL) +#define INTC_ICDICPR5_SPDIFI (0x10000000uL) +#define INTC_ICDICPR5_INTIICTEI0 (0x20000000uL) +#define INTC_ICDICPR5_INTIICRI0 (0x40000000uL) +#define INTC_ICDICPR5_INTIICTI0 (0x80000000uL) + +#define INTC_ICDICPR6_INTIICSPI0 (0x00000001uL) +#define INTC_ICDICPR6_INTIICSTI0 (0x00000002uL) +#define INTC_ICDICPR6_INTIICNAKI0 (0x00000004uL) +#define INTC_ICDICPR6_INTIICALI0 (0x00000008uL) +#define INTC_ICDICPR6_INTIICTMOI0 (0x00000010uL) +#define INTC_ICDICPR6_INTIICTEI1 (0x00000020uL) +#define INTC_ICDICPR6_INTIICRI1 (0x00000040uL) +#define INTC_ICDICPR6_INTIICTI1 (0x00000080uL) +#define INTC_ICDICPR6_INTIICSPI1 (0x00000100uL) +#define INTC_ICDICPR6_INTIICSTI1 (0x00000200uL) +#define INTC_ICDICPR6_INTIICNAKI1 (0x00000400uL) +#define INTC_ICDICPR6_INTIICALI1 (0x00000800uL) +#define INTC_ICDICPR6_INTIICTMOI1 (0x00001000uL) +#define INTC_ICDICPR6_INTIICTEI2 (0x00002000uL) +#define INTC_ICDICPR6_INTIICRI2 (0x00004000uL) +#define INTC_ICDICPR6_INTIICTI2 (0x00008000uL) +#define INTC_ICDICPR6_INTIICSPI2 (0x00010000uL) +#define INTC_ICDICPR6_INTIICSTI2 (0x00020000uL) +#define INTC_ICDICPR6_INTIICNAKI2 (0x00040000uL) +#define INTC_ICDICPR6_INTIICALI2 (0x00080000uL) +#define INTC_ICDICPR6_INTIICTMOI2 (0x00100000uL) +#define INTC_ICDICPR6_INTIICTEI3 (0x00200000uL) +#define INTC_ICDICPR6_INTIICRI3 (0x00400000uL) +#define INTC_ICDICPR6_INTIICTI3 (0x00800000uL) +#define INTC_ICDICPR6_INTIICSPI3 (0x01000000uL) +#define INTC_ICDICPR6_INTIICSTI3 (0x02000000uL) +#define INTC_ICDICPR6_INTIICNAKI3 (0x04000000uL) +#define INTC_ICDICPR6_INTIICALI3 (0x08000000uL) +#define INTC_ICDICPR6_INTIICTMOI3 (0x10000000uL) +#define INTC_ICDICPR6_BRI0 (0x20000000uL) +#define INTC_ICDICPR6_ERI0 (0x40000000uL) +#define INTC_ICDICPR6_RXI0 (0x80000000uL) + +#define INTC_ICDICPR7_TXI0 (0x00000001uL) +#define INTC_ICDICPR7_BRI1 (0x00000002uL) +#define INTC_ICDICPR7_ERI1 (0x00000004uL) +#define INTC_ICDICPR7_RXI1 (0x00000008uL) +#define INTC_ICDICPR7_TXI1 (0x00000010uL) +#define INTC_ICDICPR7_BRI2 (0x00000020uL) +#define INTC_ICDICPR7_ERI2 (0x00000040uL) +#define INTC_ICDICPR7_RXI2 (0x00000080uL) +#define INTC_ICDICPR7_TXI2 (0x00000100uL) +#define INTC_ICDICPR7_BRI3 (0x00000200uL) +#define INTC_ICDICPR7_ERI3 (0x00000400uL) +#define INTC_ICDICPR7_RXI3 (0x00000800uL) +#define INTC_ICDICPR7_TXI3 (0x00001000uL) +#define INTC_ICDICPR7_BRI4 (0x00002000uL) +#define INTC_ICDICPR7_ERI4 (0x00004000uL) +#define INTC_ICDICPR7_RXI4 (0x00008000uL) +#define INTC_ICDICPR7_TXI4 (0x00010000uL) +#define INTC_ICDICPR7_BRI5 (0x00020000uL) +#define INTC_ICDICPR7_ERI5 (0x00040000uL) +#define INTC_ICDICPR7_RXI5 (0x00080000uL) +#define INTC_ICDICPR7_TXI5 (0x00100000uL) +#define INTC_ICDICPR7_BRI6 (0x00200000uL) +#define INTC_ICDICPR7_ERI6 (0x00400000uL) +#define INTC_ICDICPR7_RXI6 (0x00800000uL) +#define INTC_ICDICPR7_TXI6 (0x01000000uL) +#define INTC_ICDICPR7_BRI7 (0x02000000uL) +#define INTC_ICDICPR7_ERI7 (0x04000000uL) +#define INTC_ICDICPR7_RXI7 (0x08000000uL) +#define INTC_ICDICPR7_TXI7 (0x10000000uL) +#define INTC_ICDICPR7_INTRCANGERR (0x20000000uL) +#define INTC_ICDICPR7_INTRCANGRECC (0x40000000uL) +#define INTC_ICDICPR7_INTRCAN0REC (0x80000000uL) + +#define INTC_ICDICPR8_INTRCAN0ERR (0x00000001uL) +#define INTC_ICDICPR8_INTRCAN0TRX (0x00000002uL) +#define INTC_ICDICPR8_INTRCAN1REC (0x00000004uL) +#define INTC_ICDICPR8_INTRCAN1ERR (0x00000008uL) +#define INTC_ICDICPR8_INTRCAN1TRX (0x00000010uL) +#define INTC_ICDICPR8_INTRCAN2REC (0x00000020uL) +#define INTC_ICDICPR8_INTRCAN2ERR (0x00000040uL) +#define INTC_ICDICPR8_INTRCAN2TRX (0x00000080uL) +#define INTC_ICDICPR8_INTRCAN3REC (0x00000100uL) +#define INTC_ICDICPR8_INTRCAN3ERR (0x00000200uL) +#define INTC_ICDICPR8_INTRCAN3TRX (0x00000400uL) +#define INTC_ICDICPR8_INTRCAN4REC (0x00000800uL) +#define INTC_ICDICPR8_INTRCAN4ERR (0x00001000uL) +#define INTC_ICDICPR8_INTRCAN4TRX (0x00002000uL) +#define INTC_ICDICPR8_SPEI0 (0x00004000uL) +#define INTC_ICDICPR8_SPRI0 (0x00008000uL) +#define INTC_ICDICPR8_SPTI0 (0x00010000uL) +#define INTC_ICDICPR8_SPEI1 (0x00020000uL) +#define INTC_ICDICPR8_SPRI1 (0x00040000uL) +#define INTC_ICDICPR8_SPTI1 (0x00080000uL) +#define INTC_ICDICPR8_SPEI2 (0x00100000uL) +#define INTC_ICDICPR8_SPRI2 (0x00200000uL) +#define INTC_ICDICPR8_SPTI2 (0x00400000uL) +#define INTC_ICDICPR8_SPEI3 (0x00800000uL) +#define INTC_ICDICPR8_SPRI3 (0x01000000uL) +#define INTC_ICDICPR8_SPTI3 (0x02000000uL) +#define INTC_ICDICPR8_SPEI4 (0x04000000uL) +#define INTC_ICDICPR8_SPRI4 (0x08000000uL) +#define INTC_ICDICPR8_SPTI4 (0x10000000uL) +#define INTC_ICDICPR8_IEBBTD (0x20000000uL) +#define INTC_ICDICPR8_IEBBTERR (0x40000000uL) +#define INTC_ICDICPR8_IEBBTSTA (0x80000000uL) + +#define INTC_ICDICPR9_IEBBTV (0x00000001uL) +#define INTC_ICDICPR9_ISY (0x00000002uL) +#define INTC_ICDICPR9_IERR (0x00000004uL) +#define INTC_ICDICPR9_ITARG (0x00000008uL) +#define INTC_ICDICPR9_ISEC (0x00000010uL) +#define INTC_ICDICPR9_IBUF (0x00000020uL) +#define INTC_ICDICPR9_IREADY (0x00000040uL) +#define INTC_ICDICPR9_FLSTE (0x00000080uL) +#define INTC_ICDICPR9_FLTENDI (0x00000100uL) +#define INTC_ICDICPR9_FLTREQ0I (0x00000200uL) +#define INTC_ICDICPR9_FLTREQ1I (0x00000400uL) +#define INTC_ICDICPR9_MMC0 (0x00000800uL) +#define INTC_ICDICPR9_MMC1 (0x00001000uL) +#define INTC_ICDICPR9_MMC2 (0x00002000uL) +#define INTC_ICDICPR9_SDHI0_3 (0x00004000uL) +#define INTC_ICDICPR9_SDHI0_0 (0x00008000uL) +#define INTC_ICDICPR9_SDHI0_1 (0x00010000uL) +#define INTC_ICDICPR9_SDHI1_3 (0x00020000uL) +#define INTC_ICDICPR9_SDHI1_0 (0x00040000uL) +#define INTC_ICDICPR9_SDHI1_1 (0x00080000uL) +#define INTC_ICDICPR9_ARM (0x00100000uL) +#define INTC_ICDICPR9_PRD (0x00200000uL) +#define INTC_ICDICPR9_CUP (0x00400000uL) +#define INTC_ICDICPR9_SCUAI0 (0x00800000uL) +#define INTC_ICDICPR9_SCUAI1 (0x01000000uL) +#define INTC_ICDICPR9_SCUFDI0 (0x02000000uL) +#define INTC_ICDICPR9_SCUFDI1 (0x04000000uL) +#define INTC_ICDICPR9_SCUFDI2 (0x08000000uL) +#define INTC_ICDICPR9_SCUFDI3 (0x10000000uL) +#define INTC_ICDICPR9_SCUFUI0 (0x20000000uL) +#define INTC_ICDICPR9_SCUFUI1 (0x40000000uL) +#define INTC_ICDICPR9_SCUFUI2 (0x80000000uL) + +#define INTC_ICDICPR10_SCUFUI3 (0x00000001uL) +#define INTC_ICDICPR10_SCUDVI0 (0x00000002uL) +#define INTC_ICDICPR10_SCUDVI1 (0x00000004uL) +#define INTC_ICDICPR10_SCUDVI2 (0x00000008uL) +#define INTC_ICDICPR10_SCUDVI3 (0x00000010uL) +#define INTC_ICDICPR10_MLB_CINT (0x00000020uL) +#define INTC_ICDICPR10_MLB_SINT (0x00000040uL) +#define INTC_ICDICPR10_DRC0 (0x00000080uL) +#define INTC_ICDICPR10_DRC1 (0x00000100uL) +#define INTC_ICDICPR10_LINI0_INT_T (0x00000800uL) +#define INTC_ICDICPR10_LINI0_INT_R (0x00001000uL) +#define INTC_ICDICPR10_LINI0_INT_S (0x00002000uL) +#define INTC_ICDICPR10_LINI0_INT_M (0x00004000uL) +#define INTC_ICDICPR10_LINI1_INT_T (0x00008000uL) +#define INTC_ICDICPR10_LINI1_INT_R (0x00010000uL) +#define INTC_ICDICPR10_LINI1_INT_S (0x00020000uL) +#define INTC_ICDICPR10_LINI1_INT_M (0x00040000uL) +#define INTC_ICDICPR10_ERI0 (0x08000000uL) +#define INTC_ICDICPR10_RXI0 (0x10000000uL) +#define INTC_ICDICPR10_TXI0 (0x20000000uL) +#define INTC_ICDICPR10_TEI0 (0x40000000uL) +#define INTC_ICDICPR10_ERI1 (0x80000000uL) + +#define INTC_ICDICPR11_RXI1 (0x00000001uL) +#define INTC_ICDICPR11_TXI1 (0x00000002uL) +#define INTC_ICDICPR11_TEI1 (0x00000004uL) +#define INTC_ICDICPR11_AVBI_DATA (0x00000008uL) +#define INTC_ICDICPR11_AVBI_ERROR (0x00000010uL) +#define INTC_ICDICPR11_AVBI_MANAGE (0x00000020uL) +#define INTC_ICDICPR11_AVBI_MAC (0x00000040uL) +#define INTC_ICDICPR11_ETHERI (0x00000080uL) +#define INTC_ICDICPR11_CEUI (0x00001000uL) +#define INTC_ICDICPR11_H2XMLB_ERRINT (0x20000000uL) +#define INTC_ICDICPR11_H2XIC1_ERRINT (0x40000000uL) +#define INTC_ICDICPR11_X2HPERI1_ERRINT (0x80000000uL) + +#define INTC_ICDICPR12_X2HPERI2_ERRINT (0x00000001uL) +#define INTC_ICDICPR12_X2HPERI34_ERRINT (0x00000002uL) +#define INTC_ICDICPR12_X2HPERI5_ERRINT (0x00000004uL) +#define INTC_ICDICPR12_X2HPERI67_ERRINT (0x00000008uL) +#define INTC_ICDICPR12_X2HDBGR_ERRINT (0x00000010uL) +#define INTC_ICDICPR12_X2HBSC_ERRINT (0x00000020uL) +#define INTC_ICDICPR12_X2HSPI1_ERRINT (0x00000040uL) +#define INTC_ICDICPR12_X2HSPI2_ERRINT (0x00000080uL) +#define INTC_ICDICPR12_PRRI (0x00000100uL) +#define INTC_ICDICPR12_IFEI0 (0x00000200uL) +#define INTC_ICDICPR12_OFFI0 (0x00000400uL) +#define INTC_ICDICPR12_PFVEI0 (0x00000800uL) +#define INTC_ICDICPR12_IFEI1 (0x00001000uL) +#define INTC_ICDICPR12_OFFI1 (0x00002000uL) +#define INTC_ICDICPR12_PFVEI1 (0x00004000uL) + +#define INTC_ICDICPR13_TINT0 (0x00000001uL) +#define INTC_ICDICPR13_TINT1 (0x00000002uL) +#define INTC_ICDICPR13_TINT2 (0x00000004uL) +#define INTC_ICDICPR13_TINT3 (0x00000008uL) +#define INTC_ICDICPR13_TINT4 (0x00000010uL) +#define INTC_ICDICPR13_TINT5 (0x00000020uL) +#define INTC_ICDICPR13_TINT6 (0x00000040uL) +#define INTC_ICDICPR13_TINT7 (0x00000080uL) +#define INTC_ICDICPR13_TINT8 (0x00000100uL) +#define INTC_ICDICPR13_TINT9 (0x00000200uL) +#define INTC_ICDICPR13_TINT10 (0x00000400uL) +#define INTC_ICDICPR13_TINT11 (0x00000800uL) +#define INTC_ICDICPR13_TINT12 (0x00001000uL) +#define INTC_ICDICPR13_TINT13 (0x00002000uL) +#define INTC_ICDICPR13_TINT14 (0x00004000uL) +#define INTC_ICDICPR13_TINT15 (0x00008000uL) +#define INTC_ICDICPR13_TINT16 (0x00010000uL) +#define INTC_ICDICPR13_TINT17 (0x00020000uL) +#define INTC_ICDICPR13_TINT18 (0x00040000uL) +#define INTC_ICDICPR13_TINT19 (0x00080000uL) +#define INTC_ICDICPR13_TINT20 (0x00100000uL) +#define INTC_ICDICPR13_TINT21 (0x00200000uL) +#define INTC_ICDICPR13_TINT22 (0x00400000uL) +#define INTC_ICDICPR13_TINT23 (0x00800000uL) +#define INTC_ICDICPR13_TINT24 (0x01000000uL) +#define INTC_ICDICPR13_TINT25 (0x02000000uL) +#define INTC_ICDICPR13_TINT26 (0x04000000uL) +#define INTC_ICDICPR13_TINT27 (0x08000000uL) +#define INTC_ICDICPR13_TINT28 (0x10000000uL) +#define INTC_ICDICPR13_TINT29 (0x20000000uL) +#define INTC_ICDICPR13_TINT30 (0x40000000uL) +#define INTC_ICDICPR13_TINT31 (0x80000000uL) + +#define INTC_ICDICPR14_TINT32 (0x00000001uL) +#define INTC_ICDICPR14_TINT33 (0x00000002uL) +#define INTC_ICDICPR14_TINT34 (0x00000004uL) +#define INTC_ICDICPR14_TINT35 (0x00000008uL) +#define INTC_ICDICPR14_TINT36 (0x00000010uL) +#define INTC_ICDICPR14_TINT37 (0x00000020uL) +#define INTC_ICDICPR14_TINT38 (0x00000040uL) +#define INTC_ICDICPR14_TINT39 (0x00000080uL) +#define INTC_ICDICPR14_TINT40 (0x00000100uL) +#define INTC_ICDICPR14_TINT41 (0x00000200uL) +#define INTC_ICDICPR14_TINT42 (0x00000400uL) +#define INTC_ICDICPR14_TINT43 (0x00000800uL) +#define INTC_ICDICPR14_TINT44 (0x00001000uL) +#define INTC_ICDICPR14_TINT45 (0x00002000uL) +#define INTC_ICDICPR14_TINT46 (0x00004000uL) +#define INTC_ICDICPR14_TINT47 (0x00008000uL) +#define INTC_ICDICPR14_TINT48 (0x00010000uL) +#define INTC_ICDICPR14_TINT49 (0x00020000uL) +#define INTC_ICDICPR14_TINT50 (0x00040000uL) +#define INTC_ICDICPR14_TINT51 (0x00080000uL) +#define INTC_ICDICPR14_TINT52 (0x00100000uL) +#define INTC_ICDICPR14_TINT53 (0x00200000uL) +#define INTC_ICDICPR14_TINT54 (0x00400000uL) +#define INTC_ICDICPR14_TINT55 (0x00800000uL) +#define INTC_ICDICPR14_TINT56 (0x01000000uL) +#define INTC_ICDICPR14_TINT57 (0x02000000uL) +#define INTC_ICDICPR14_TINT58 (0x04000000uL) +#define INTC_ICDICPR14_TINT59 (0x08000000uL) +#define INTC_ICDICPR14_TINT60 (0x10000000uL) +#define INTC_ICDICPR14_TINT61 (0x20000000uL) +#define INTC_ICDICPR14_TINT62 (0x40000000uL) +#define INTC_ICDICPR14_TINT63 (0x80000000uL) + +#define INTC_ICDICPR15_TINT64 (0x00000001uL) +#define INTC_ICDICPR15_TINT65 (0x00000002uL) +#define INTC_ICDICPR15_TINT66 (0x00000004uL) +#define INTC_ICDICPR15_TINT67 (0x00000008uL) +#define INTC_ICDICPR15_TINT68 (0x00000010uL) +#define INTC_ICDICPR15_TINT69 (0x00000020uL) +#define INTC_ICDICPR15_TINT70 (0x00000040uL) +#define INTC_ICDICPR15_TINT71 (0x00000080uL) +#define INTC_ICDICPR15_TINT72 (0x00000100uL) +#define INTC_ICDICPR15_TINT73 (0x00000200uL) +#define INTC_ICDICPR15_TINT74 (0x00000400uL) +#define INTC_ICDICPR15_TINT75 (0x00000800uL) +#define INTC_ICDICPR15_TINT76 (0x00001000uL) +#define INTC_ICDICPR15_TINT77 (0x00002000uL) +#define INTC_ICDICPR15_TINT78 (0x00004000uL) +#define INTC_ICDICPR15_TINT79 (0x00008000uL) +#define INTC_ICDICPR15_TINT80 (0x00010000uL) +#define INTC_ICDICPR15_TINT81 (0x00020000uL) +#define INTC_ICDICPR15_TINT82 (0x00040000uL) +#define INTC_ICDICPR15_TINT83 (0x00080000uL) +#define INTC_ICDICPR15_TINT84 (0x00100000uL) +#define INTC_ICDICPR15_TINT85 (0x00200000uL) +#define INTC_ICDICPR15_TINT86 (0x00400000uL) +#define INTC_ICDICPR15_TINT87 (0x00800000uL) +#define INTC_ICDICPR15_TINT88 (0x01000000uL) +#define INTC_ICDICPR15_TINT89 (0x02000000uL) +#define INTC_ICDICPR15_TINT90 (0x04000000uL) +#define INTC_ICDICPR15_TINT91 (0x08000000uL) +#define INTC_ICDICPR15_TINT92 (0x10000000uL) +#define INTC_ICDICPR15_TINT93 (0x20000000uL) +#define INTC_ICDICPR15_TINT94 (0x40000000uL) +#define INTC_ICDICPR15_TINT95 (0x80000000uL) + +#define INTC_ICDICPR16_TINT96 (0x00000001uL) +#define INTC_ICDICPR16_TINT97 (0x00000002uL) +#define INTC_ICDICPR16_TINT98 (0x00000004uL) +#define INTC_ICDICPR16_TINT99 (0x00000008uL) +#define INTC_ICDICPR16_TINT100 (0x00000010uL) +#define INTC_ICDICPR16_TINT101 (0x00000020uL) +#define INTC_ICDICPR16_TINT102 (0x00000040uL) +#define INTC_ICDICPR16_TINT103 (0x00000080uL) +#define INTC_ICDICPR16_TINT104 (0x00000100uL) +#define INTC_ICDICPR16_TINT105 (0x00000200uL) +#define INTC_ICDICPR16_TINT106 (0x00000400uL) +#define INTC_ICDICPR16_TINT107 (0x00000800uL) +#define INTC_ICDICPR16_TINT108 (0x00001000uL) +#define INTC_ICDICPR16_TINT109 (0x00002000uL) +#define INTC_ICDICPR16_TINT110 (0x00004000uL) +#define INTC_ICDICPR16_TINT111 (0x00008000uL) +#define INTC_ICDICPR16_TINT112 (0x00010000uL) +#define INTC_ICDICPR16_TINT113 (0x00020000uL) +#define INTC_ICDICPR16_TINT114 (0x00040000uL) +#define INTC_ICDICPR16_TINT115 (0x00080000uL) +#define INTC_ICDICPR16_TINT116 (0x00100000uL) +#define INTC_ICDICPR16_TINT117 (0x00200000uL) +#define INTC_ICDICPR16_TINT118 (0x00400000uL) +#define INTC_ICDICPR16_TINT119 (0x00800000uL) +#define INTC_ICDICPR16_TINT120 (0x01000000uL) +#define INTC_ICDICPR16_TINT121 (0x02000000uL) +#define INTC_ICDICPR16_TINT122 (0x04000000uL) +#define INTC_ICDICPR16_TINT123 (0x08000000uL) +#define INTC_ICDICPR16_TINT124 (0x10000000uL) +#define INTC_ICDICPR16_TINT125 (0x20000000uL) +#define INTC_ICDICPR16_TINT126 (0x40000000uL) +#define INTC_ICDICPR16_TINT127 (0x80000000uL) + +#define INTC_ICDICPR17_TINT128 (0x00000001uL) +#define INTC_ICDICPR17_TINT129 (0x00000002uL) +#define INTC_ICDICPR17_TINT130 (0x00000004uL) +#define INTC_ICDICPR17_TINT131 (0x00000008uL) +#define INTC_ICDICPR17_TINT132 (0x00000010uL) +#define INTC_ICDICPR17_TINT133 (0x00000020uL) +#define INTC_ICDICPR17_TINT134 (0x00000040uL) +#define INTC_ICDICPR17_TINT135 (0x00000080uL) +#define INTC_ICDICPR17_TINT136 (0x00000100uL) +#define INTC_ICDICPR17_TINT137 (0x00000200uL) +#define INTC_ICDICPR17_TINT138 (0x00000400uL) +#define INTC_ICDICPR17_TINT139 (0x00000800uL) +#define INTC_ICDICPR17_TINT140 (0x00001000uL) +#define INTC_ICDICPR17_TINT141 (0x00002000uL) +#define INTC_ICDICPR17_TINT142 (0x00004000uL) +#define INTC_ICDICPR17_TINT143 (0x00008000uL) +#define INTC_ICDICPR17_TINT144 (0x00010000uL) +#define INTC_ICDICPR17_TINT145 (0x00020000uL) +#define INTC_ICDICPR17_TINT146 (0x00040000uL) +#define INTC_ICDICPR17_TINT147 (0x00080000uL) +#define INTC_ICDICPR17_TINT148 (0x00100000uL) +#define INTC_ICDICPR17_TINT149 (0x00200000uL) +#define INTC_ICDICPR17_TINT150 (0x00400000uL) +#define INTC_ICDICPR17_TINT151 (0x00800000uL) +#define INTC_ICDICPR17_TINT152 (0x01000000uL) +#define INTC_ICDICPR17_TINT153 (0x02000000uL) +#define INTC_ICDICPR17_TINT154 (0x04000000uL) +#define INTC_ICDICPR17_TINT155 (0x08000000uL) +#define INTC_ICDICPR17_TINT156 (0x10000000uL) +#define INTC_ICDICPR17_TINT157 (0x20000000uL) +#define INTC_ICDICPR17_TINT158 (0x40000000uL) +#define INTC_ICDICPR17_TINT159 (0x80000000uL) + +#define INTC_ICDICPR18_TINT160 (0x00000001uL) +#define INTC_ICDICPR18_TINT161 (0x00000002uL) +#define INTC_ICDICPR18_TINT162 (0x00000004uL) +#define INTC_ICDICPR18_TINT163 (0x00000008uL) +#define INTC_ICDICPR18_TINT164 (0x00000010uL) +#define INTC_ICDICPR18_TINT165 (0x00000020uL) +#define INTC_ICDICPR18_TINT166 (0x00000040uL) +#define INTC_ICDICPR18_TINT167 (0x00000080uL) +#define INTC_ICDICPR18_TINT168 (0x00000100uL) +#define INTC_ICDICPR18_TINT169 (0x00000200uL) +#define INTC_ICDICPR18_TINT170 (0x00000400uL) + +#define INTC_ICDABR0_SW0 (0x00000001uL) +#define INTC_ICDABR0_SW1 (0x00000002uL) +#define INTC_ICDABR0_SW2 (0x00000004uL) +#define INTC_ICDABR0_SW3 (0x00000008uL) +#define INTC_ICDABR0_SW4 (0x00000010uL) +#define INTC_ICDABR0_SW5 (0x00000020uL) +#define INTC_ICDABR0_SW6 (0x00000040uL) +#define INTC_ICDABR0_SW7 (0x00000080uL) +#define INTC_ICDABR0_SW8 (0x00000100uL) +#define INTC_ICDABR0_SW9 (0x00000200uL) +#define INTC_ICDABR0_SW10 (0x00000400uL) +#define INTC_ICDABR0_SW11 (0x00000800uL) +#define INTC_ICDABR0_SW12 (0x00001000uL) +#define INTC_ICDABR0_SW13 (0x00002000uL) +#define INTC_ICDABR0_SW14 (0x00004000uL) +#define INTC_ICDABR0_SW15 (0x00008000uL) +#define INTC_ICDABR0_PMUIRQ0 (0x00010000uL) +#define INTC_ICDABR0_COMMRX0 (0x00020000uL) +#define INTC_ICDABR0_COMMTX0 (0x00040000uL) +#define INTC_ICDABR0_CTIIRQ0 (0x00080000uL) + +#define INTC_ICDABR1_IRQ0 (0x00000001uL) +#define INTC_ICDABR1_IRQ1 (0x00000002uL) +#define INTC_ICDABR1_IRQ2 (0x00000004uL) +#define INTC_ICDABR1_IRQ3 (0x00000008uL) +#define INTC_ICDABR1_IRQ4 (0x00000010uL) +#define INTC_ICDABR1_IRQ5 (0x00000020uL) +#define INTC_ICDABR1_IRQ6 (0x00000040uL) +#define INTC_ICDABR1_IRQ7 (0x00000080uL) +#define INTC_ICDABR1_PL310ERR (0x00000100uL) +#define INTC_ICDABR1_DMAINT0 (0x00000200uL) +#define INTC_ICDABR1_DMAINT1 (0x00000400uL) +#define INTC_ICDABR1_DMAINT2 (0x00000800uL) +#define INTC_ICDABR1_DMAINT3 (0x00001000uL) +#define INTC_ICDABR1_DMAINT4 (0x00002000uL) +#define INTC_ICDABR1_DMAINT5 (0x00004000uL) +#define INTC_ICDABR1_DMAINT6 (0x00008000uL) +#define INTC_ICDABR1_DMAINT7 (0x00010000uL) +#define INTC_ICDABR1_DMAINT8 (0x00020000uL) +#define INTC_ICDABR1_DMAINT9 (0x00040000uL) +#define INTC_ICDABR1_DMAINT10 (0x00080000uL) +#define INTC_ICDABR1_DMAINT11 (0x00100000uL) +#define INTC_ICDABR1_DMAINT12 (0x00200000uL) +#define INTC_ICDABR1_DMAINT13 (0x00400000uL) +#define INTC_ICDABR1_DMAINT14 (0x00800000uL) +#define INTC_ICDABR1_DMAINT15 (0x01000000uL) +#define INTC_ICDABR1_DMAERR (0x02000000uL) + +#define INTC_ICDABR2_USBI0 (0x00000200uL) +#define INTC_ICDABR2_USBI1 (0x00000400uL) +#define INTC_ICDABR2_S0_VI_VSYNC0 (0x00000800uL) +#define INTC_ICDABR2_S0_LO_VSYNC0 (0x00001000uL) +#define INTC_ICDABR2_S0_VSYNCERR0 (0x00002000uL) +#define INTC_ICDABR2_GR3_VLINE0 (0x00004000uL) +#define INTC_ICDABR2_S0_VFIELD0 (0x00008000uL) +#define INTC_ICDABR2_IV1_VBUFERR0 (0x00010000uL) +#define INTC_ICDABR2_IV3_VBUFERR0 (0x00020000uL) +#define INTC_ICDABR2_IV5_VBUFERR0 (0x00040000uL) +#define INTC_ICDABR2_IV6_VBUFERR0 (0x00080000uL) +#define INTC_ICDABR2_S0_WLINE0 (0x00100000uL) +#define INTC_ICDABR2_S1_VI_VSYNC0 (0x00200000uL) +#define INTC_ICDABR2_S1_LO_VSYNC0 (0x00400000uL) +#define INTC_ICDABR2_S1_VSYNCERR0 (0x00800000uL) +#define INTC_ICDABR2_S1_VFIELD0 (0x01000000uL) +#define INTC_ICDABR2_IV2_VBUFERR0 (0x02000000uL) +#define INTC_ICDABR2_IV4_VBUFERR0 (0x04000000uL) +#define INTC_ICDABR2_S1_WLINE0 (0x08000000uL) +#define INTC_ICDABR2_OIR_VI_VSYNC0 (0x10000000uL) +#define INTC_ICDABR2_OIR_LO_VSYNC0 (0x20000000uL) +#define INTC_ICDABR2_OIR_VSYNCERR0 (0x40000000uL) +#define INTC_ICDABR2_OIR_VFIELD0 (0x80000000uL) + +#define INTC_ICDABR3_IV7_VBUFERR0 (0x00000001uL) +#define INTC_ICDABR3_IV8_VBUFERR0 (0x00000002uL) +#define INTC_ICDABR3_S0_VI_VSYNC1 (0x00000008uL) +#define INTC_ICDABR3_S0_LO_VSYNC1 (0x00000010uL) +#define INTC_ICDABR3_S0_VSYNCERR1 (0x00000020uL) +#define INTC_ICDABR3_GR3_VLINE1 (0x00000040uL) +#define INTC_ICDABR3_S0_VFIELD1 (0x00000080uL) +#define INTC_ICDABR3_IV1_VBUFERR1 (0x00000100uL) +#define INTC_ICDABR3_IV3_VBUFERR1 (0x00000200uL) +#define INTC_ICDABR3_IV5_VBUFERR1 (0x00000400uL) +#define INTC_ICDABR3_IV6_VBUFERR1 (0x00000800uL) +#define INTC_ICDABR3_S0_WLINE1 (0x00001000uL) +#define INTC_ICDABR3_S1_VI_VSYNC1 (0x00002000uL) +#define INTC_ICDABR3_S1_LO_VSYNC1 (0x00004000uL) +#define INTC_ICDABR3_S1_VSYNCERR1 (0x00008000uL) +#define INTC_ICDABR3_S1_VFIELD1 (0x00010000uL) +#define INTC_ICDABR3_IV2_VBUFERR1 (0x00020000uL) +#define INTC_ICDABR3_IV4_VBUFERR1 (0x00040000uL) +#define INTC_ICDABR3_S1_WLINE1 (0x00080000uL) +#define INTC_ICDABR3_OIR_VI_VSYNC1 (0x00100000uL) +#define INTC_ICDABR3_OIR_LO_VSYNC1 (0x00200000uL) +#define INTC_ICDABR3_OIR_VLINE1 (0x00400000uL) +#define INTC_ICDABR3_OIR_VFIELD1 (0x00800000uL) +#define INTC_ICDABR3_IV7_VBUFERR1 (0x01000000uL) +#define INTC_ICDABR3_IV8_VBUFERR1 (0x02000000uL) +#define INTC_ICDABR3_IMRDI (0x08000000uL) +#define INTC_ICDABR3_IMR2I0 (0x10000000uL) +#define INTC_ICDABR3_IMR2I1 (0x20000000uL) +#define INTC_ICDABR3_JEDI (0x40000000uL) +#define INTC_ICDABR3_JDTI (0x80000000uL) + +#define INTC_ICDABR4_CMP0 (0x00000001uL) +#define INTC_ICDABR4_CMP1 (0x00000002uL) +#define INTC_ICDABR4_INT0 (0x00000004uL) +#define INTC_ICDABR4_INT1 (0x00000008uL) +#define INTC_ICDABR4_INT2 (0x00000010uL) +#define INTC_ICDABR4_INT3 (0x00000020uL) +#define INTC_ICDABR4_OSTM0TINT (0x00000040uL) +#define INTC_ICDABR4_OSTM1TINT (0x00000080uL) +#define INTC_ICDABR4_CMI (0x00000100uL) +#define INTC_ICDABR4_WTOUT (0x00000200uL) +#define INTC_ICDABR4_ITI (0x00000400uL) +#define INTC_ICDABR4_TGI0A (0x00000800uL) +#define INTC_ICDABR4_TGI0B (0x00001000uL) +#define INTC_ICDABR4_TGI0C (0x00002000uL) +#define INTC_ICDABR4_TGI0D (0x00004000uL) +#define INTC_ICDABR4_TGI0V (0x00008000uL) +#define INTC_ICDABR4_TGI0E (0x00010000uL) +#define INTC_ICDABR4_TGI0F (0x00020000uL) +#define INTC_ICDABR4_TGI1A (0x00040000uL) +#define INTC_ICDABR4_TGI1B (0x00080000uL) +#define INTC_ICDABR4_TGI1V (0x00100000uL) +#define INTC_ICDABR4_TGI1U (0x00200000uL) +#define INTC_ICDABR4_TGI2A (0x00400000uL) +#define INTC_ICDABR4_TGI2B (0x00800000uL) +#define INTC_ICDABR4_TGI2V (0x01000000uL) +#define INTC_ICDABR4_TGI2U (0x02000000uL) +#define INTC_ICDABR4_TGI3A (0x04000000uL) +#define INTC_ICDABR4_TGI3B (0x08000000uL) +#define INTC_ICDABR4_TGI3C (0x10000000uL) +#define INTC_ICDABR4_TGI3D (0x20000000uL) +#define INTC_ICDABR4_TGI3V (0x40000000uL) +#define INTC_ICDABR4_TGI4A (0x80000000uL) + +#define INTC_ICDABR5_TGI4B (0x00000001uL) +#define INTC_ICDABR5_TGI4C (0x00000002uL) +#define INTC_ICDABR5_TGI4D (0x00000004uL) +#define INTC_ICDABR5_TGI4V (0x00000008uL) +#define INTC_ICDABR5_CMI1 (0x00000010uL) +#define INTC_ICDABR5_CMI2 (0x00000020uL) +#define INTC_ICDABR5_SGDEI0 (0x00000040uL) +#define INTC_ICDABR5_SGDEI1 (0x00000080uL) +#define INTC_ICDABR5_SGDEI2 (0x00000100uL) +#define INTC_ICDABR5_SGDEI3 (0x00000200uL) +#define INTC_ICDABR5_ADI (0x00000400uL) +#define INTC_ICDABR5_LMTI (0x00000800uL) +#define INTC_ICDABR5_SSII0 (0x00001000uL) +#define INTC_ICDABR5_SSIRXI0 (0x00002000uL) +#define INTC_ICDABR5_SSITXI0 (0x00004000uL) +#define INTC_ICDABR5_SSII1 (0x00008000uL) +#define INTC_ICDABR5_SSIRXI1 (0x00010000uL) +#define INTC_ICDABR5_SSITXI1 (0x00020000uL) +#define INTC_ICDABR5_SSII2 (0x00040000uL) +#define INTC_ICDABR5_SSIRTI2 (0x00080000uL) +#define INTC_ICDABR5_SSII3 (0x00100000uL) +#define INTC_ICDABR5_SSIRXI3 (0x00200000uL) +#define INTC_ICDABR5_SSITXI3 (0x00400000uL) +#define INTC_ICDABR5_SSII4 (0x00800000uL) +#define INTC_ICDABR5_SSIRTI4 (0x01000000uL) +#define INTC_ICDABR5_SSII5 (0x02000000uL) +#define INTC_ICDABR5_SSIRXI5 (0x04000000uL) +#define INTC_ICDABR5_SSITXI5 (0x08000000uL) +#define INTC_ICDABR5_SPDIFI (0x10000000uL) +#define INTC_ICDABR5_INTIICTEI0 (0x20000000uL) +#define INTC_ICDABR5_INTIICRI0 (0x40000000uL) +#define INTC_ICDABR5_INTIICTI0 (0x80000000uL) + +#define INTC_ICDABR6_INTIICSPI0 (0x00000001uL) +#define INTC_ICDABR6_INTIICSTI0 (0x00000002uL) +#define INTC_ICDABR6_INTIICNAKI0 (0x00000004uL) +#define INTC_ICDABR6_INTIICALI0 (0x00000008uL) +#define INTC_ICDABR6_INTIICTMOI0 (0x00000010uL) +#define INTC_ICDABR6_INTIICTEI1 (0x00000020uL) +#define INTC_ICDABR6_INTIICRI1 (0x00000040uL) +#define INTC_ICDABR6_INTIICTI1 (0x00000080uL) +#define INTC_ICDABR6_INTIICSPI1 (0x00000100uL) +#define INTC_ICDABR6_INTIICSTI1 (0x00000200uL) +#define INTC_ICDABR6_INTIICNAKI1 (0x00000400uL) +#define INTC_ICDABR6_INTIICALI1 (0x00000800uL) +#define INTC_ICDABR6_INTIICTMOI1 (0x00001000uL) +#define INTC_ICDABR6_INTIICTEI2 (0x00002000uL) +#define INTC_ICDABR6_INTIICRI2 (0x00004000uL) +#define INTC_ICDABR6_INTIICTI2 (0x00008000uL) +#define INTC_ICDABR6_INTIICSPI2 (0x00010000uL) +#define INTC_ICDABR6_INTIICSTI2 (0x00020000uL) +#define INTC_ICDABR6_INTIICNAKI2 (0x00040000uL) +#define INTC_ICDABR6_INTIICALI2 (0x00080000uL) +#define INTC_ICDABR6_INTIICTMOI2 (0x00100000uL) +#define INTC_ICDABR6_INTIICTEI3 (0x00200000uL) +#define INTC_ICDABR6_INTIICRI3 (0x00400000uL) +#define INTC_ICDABR6_INTIICTI3 (0x00800000uL) +#define INTC_ICDABR6_INTIICSPI3 (0x01000000uL) +#define INTC_ICDABR6_INTIICSTI3 (0x02000000uL) +#define INTC_ICDABR6_INTIICNAKI3 (0x04000000uL) +#define INTC_ICDABR6_INTIICALI3 (0x08000000uL) +#define INTC_ICDABR6_INTIICTMOI3 (0x10000000uL) +#define INTC_ICDABR6_BRI0 (0x20000000uL) +#define INTC_ICDABR6_ERI0 (0x40000000uL) +#define INTC_ICDABR6_RXI0 (0x80000000uL) + +#define INTC_ICDABR7_TXI0 (0x00000001uL) +#define INTC_ICDABR7_BRI1 (0x00000002uL) +#define INTC_ICDABR7_ERI1 (0x00000004uL) +#define INTC_ICDABR7_RXI1 (0x00000008uL) +#define INTC_ICDABR7_TXI1 (0x00000010uL) +#define INTC_ICDABR7_BRI2 (0x00000020uL) +#define INTC_ICDABR7_ERI2 (0x00000040uL) +#define INTC_ICDABR7_RXI2 (0x00000080uL) +#define INTC_ICDABR7_TXI2 (0x00000100uL) +#define INTC_ICDABR7_BRI3 (0x00000200uL) +#define INTC_ICDABR7_ERI3 (0x00000400uL) +#define INTC_ICDABR7_RXI3 (0x00000800uL) +#define INTC_ICDABR7_TXI3 (0x00001000uL) +#define INTC_ICDABR7_BRI4 (0x00002000uL) +#define INTC_ICDABR7_ERI4 (0x00004000uL) +#define INTC_ICDABR7_RXI4 (0x00008000uL) +#define INTC_ICDABR7_TXI4 (0x00010000uL) +#define INTC_ICDABR7_BRI5 (0x00020000uL) +#define INTC_ICDABR7_ERI5 (0x00040000uL) +#define INTC_ICDABR7_RXI5 (0x00080000uL) +#define INTC_ICDABR7_TXI5 (0x00100000uL) +#define INTC_ICDABR7_BRI6 (0x00200000uL) +#define INTC_ICDABR7_ERI6 (0x00400000uL) +#define INTC_ICDABR7_RXI6 (0x00800000uL) +#define INTC_ICDABR7_TXI6 (0x01000000uL) +#define INTC_ICDABR7_BRI7 (0x02000000uL) +#define INTC_ICDABR7_ERI7 (0x04000000uL) +#define INTC_ICDABR7_RXI7 (0x08000000uL) +#define INTC_ICDABR7_TXI7 (0x10000000uL) +#define INTC_ICDABR7_INTRCANGERR (0x20000000uL) +#define INTC_ICDABR7_INTRCANGRECC (0x40000000uL) +#define INTC_ICDABR7_INTRCAN0REC (0x80000000uL) + +#define INTC_ICDABR8_INTRCAN0ERR (0x00000001uL) +#define INTC_ICDABR8_INTRCAN0TRX (0x00000002uL) +#define INTC_ICDABR8_INTRCAN1REC (0x00000004uL) +#define INTC_ICDABR8_INTRCAN1ERR (0x00000008uL) +#define INTC_ICDABR8_INTRCAN1TRX (0x00000010uL) +#define INTC_ICDABR8_INTRCAN2REC (0x00000020uL) +#define INTC_ICDABR8_INTRCAN2ERR (0x00000040uL) +#define INTC_ICDABR8_INTRCAN2TRX (0x00000080uL) +#define INTC_ICDABR8_INTRCAN3REC (0x00000100uL) +#define INTC_ICDABR8_INTRCAN3ERR (0x00000200uL) +#define INTC_ICDABR8_INTRCAN3TRX (0x00000400uL) +#define INTC_ICDABR8_INTRCAN4REC (0x00000800uL) +#define INTC_ICDABR8_INTRCAN4ERR (0x00001000uL) +#define INTC_ICDABR8_INTRCAN4TRX (0x00002000uL) +#define INTC_ICDABR8_SPEI0 (0x00004000uL) +#define INTC_ICDABR8_SPRI0 (0x00008000uL) +#define INTC_ICDABR8_SPTI0 (0x00010000uL) +#define INTC_ICDABR8_SPEI1 (0x00020000uL) +#define INTC_ICDABR8_SPRI1 (0x00040000uL) +#define INTC_ICDABR8_SPTI1 (0x00080000uL) +#define INTC_ICDABR8_SPEI2 (0x00100000uL) +#define INTC_ICDABR8_SPRI2 (0x00200000uL) +#define INTC_ICDABR8_SPTI2 (0x00400000uL) +#define INTC_ICDABR8_SPEI3 (0x00800000uL) +#define INTC_ICDABR8_SPRI3 (0x01000000uL) +#define INTC_ICDABR8_SPTI3 (0x02000000uL) +#define INTC_ICDABR8_SPEI4 (0x04000000uL) +#define INTC_ICDABR8_SPRI4 (0x08000000uL) +#define INTC_ICDABR8_SPTI4 (0x10000000uL) +#define INTC_ICDABR8_IEBBTD (0x20000000uL) +#define INTC_ICDABR8_IEBBTERR (0x40000000uL) +#define INTC_ICDABR8_IEBBTSTA (0x80000000uL) + +#define INTC_ICDABR9_IEBBTV (0x00000001uL) +#define INTC_ICDABR9_ISY (0x00000002uL) +#define INTC_ICDABR9_IERR (0x00000004uL) +#define INTC_ICDABR9_ITARG (0x00000008uL) +#define INTC_ICDABR9_ISEC (0x00000010uL) +#define INTC_ICDABR9_IBUF (0x00000020uL) +#define INTC_ICDABR9_IREADY (0x00000040uL) +#define INTC_ICDABR9_FLSTE (0x00000080uL) +#define INTC_ICDABR9_FLTENDI (0x00000100uL) +#define INTC_ICDABR9_FLTREQ0I (0x00000200uL) +#define INTC_ICDABR9_FLTREQ1I (0x00000400uL) +#define INTC_ICDABR9_MMC0 (0x00000800uL) +#define INTC_ICDABR9_MMC1 (0x00001000uL) +#define INTC_ICDABR9_MMC2 (0x00002000uL) +#define INTC_ICDABR9_SDHI0_3 (0x00004000uL) +#define INTC_ICDABR9_SDHI0_0 (0x00008000uL) +#define INTC_ICDABR9_SDHI0_1 (0x00010000uL) +#define INTC_ICDABR9_SDHI1_3 (0x00020000uL) +#define INTC_ICDABR9_SDHI1_0 (0x00040000uL) +#define INTC_ICDABR9_SDHI1_1 (0x00080000uL) +#define INTC_ICDABR9_ARM (0x00100000uL) +#define INTC_ICDABR9_PRD (0x00200000uL) +#define INTC_ICDABR9_CUP (0x00400000uL) +#define INTC_ICDABR9_SCUAI0 (0x00800000uL) +#define INTC_ICDABR9_SCUAI1 (0x01000000uL) +#define INTC_ICDABR9_SCUFDI0 (0x02000000uL) +#define INTC_ICDABR9_SCUFDI1 (0x04000000uL) +#define INTC_ICDABR9_SCUFDI2 (0x08000000uL) +#define INTC_ICDABR9_SCUFDI3 (0x10000000uL) +#define INTC_ICDABR9_SCUFUI0 (0x20000000uL) +#define INTC_ICDABR9_SCUFUI1 (0x40000000uL) +#define INTC_ICDABR9_SCUFUI2 (0x80000000uL) + +#define INTC_ICDABR10_SCUFUI3 (0x00000001uL) +#define INTC_ICDABR10_SCUDVI0 (0x00000002uL) +#define INTC_ICDABR10_SCUDVI1 (0x00000004uL) +#define INTC_ICDABR10_SCUDVI2 (0x00000008uL) +#define INTC_ICDABR10_SCUDVI3 (0x00000010uL) +#define INTC_ICDABR10_MLB_CINT (0x00000020uL) +#define INTC_ICDABR10_MLB_SINT (0x00000040uL) +#define INTC_ICDABR10_DRC0 (0x00000080uL) +#define INTC_ICDABR10_DRC1 (0x00000100uL) +#define INTC_ICDABR10_LINI0_INT_T (0x00000800uL) +#define INTC_ICDABR10_LINI0_INT_R (0x00001000uL) +#define INTC_ICDABR10_LINI0_INT_S (0x00002000uL) +#define INTC_ICDABR10_LINI0_INT_M (0x00004000uL) +#define INTC_ICDABR10_LINI1_INT_T (0x00008000uL) +#define INTC_ICDABR10_LINI1_INT_R (0x00010000uL) +#define INTC_ICDABR10_LINI1_INT_S (0x00020000uL) +#define INTC_ICDABR10_LINI1_INT_M (0x00040000uL) +#define INTC_ICDABR10_ERI0 (0x08000000uL) +#define INTC_ICDABR10_RXI0 (0x10000000uL) +#define INTC_ICDABR10_TXI0 (0x20000000uL) +#define INTC_ICDABR10_TEI0 (0x40000000uL) +#define INTC_ICDABR10_ERI1 (0x80000000uL) + +#define INTC_ICDABR11_RXI1 (0x00000001uL) +#define INTC_ICDABR11_TXI1 (0x00000002uL) +#define INTC_ICDABR11_TEI1 (0x00000004uL) +#define INTC_ICDABR11_AVBI_DATA (0x00000008uL) +#define INTC_ICDABR11_AVBI_ERROR (0x00000010uL) +#define INTC_ICDABR11_AVBI_MANAGE (0x00000020uL) +#define INTC_ICDABR11_AVBI_MAC (0x00000040uL) +#define INTC_ICDABR11_ETHERI (0x00000080uL) +#define INTC_ICDABR11_CEUI (0x00001000uL) +#define INTC_ICDABR11_H2XMLB_ERRINT (0x20000000uL) +#define INTC_ICDABR11_H2XIC1_ERRINT (0x40000000uL) +#define INTC_ICDABR11_X2HPERI1_ERRINT (0x80000000uL) + +#define INTC_ICDABR12_X2HPERI2_ERRINT (0x00000001uL) +#define INTC_ICDABR12_X2HPERI34_ERRINT (0x00000002uL) +#define INTC_ICDABR12_X2HPERI5_ERRINT (0x00000004uL) +#define INTC_ICDABR12_X2HPERI67_ERRINT (0x00000008uL) +#define INTC_ICDABR12_X2HDBGR_ERRINT (0x00000010uL) +#define INTC_ICDABR12_X2HBSC_ERRINT (0x00000020uL) +#define INTC_ICDABR12_X2HSPI1_ERRINT (0x00000040uL) +#define INTC_ICDABR12_X2HSPI2_ERRINT (0x00000080uL) +#define INTC_ICDABR12_PRRI (0x00000100uL) +#define INTC_ICDABR12_IFEI0 (0x00000200uL) +#define INTC_ICDABR12_OFFI0 (0x00000400uL) +#define INTC_ICDABR12_PFVEI0 (0x00000800uL) +#define INTC_ICDABR12_IFEI1 (0x00001000uL) +#define INTC_ICDABR12_OFFI1 (0x00002000uL) +#define INTC_ICDABR12_PFVEI1 (0x00004000uL) + +#define INTC_ICDABR13_TINT0 (0x00000001uL) +#define INTC_ICDABR13_TINT1 (0x00000002uL) +#define INTC_ICDABR13_TINT2 (0x00000004uL) +#define INTC_ICDABR13_TINT3 (0x00000008uL) +#define INTC_ICDABR13_TINT4 (0x00000010uL) +#define INTC_ICDABR13_TINT5 (0x00000020uL) +#define INTC_ICDABR13_TINT6 (0x00000040uL) +#define INTC_ICDABR13_TINT7 (0x00000080uL) +#define INTC_ICDABR13_TINT8 (0x00000100uL) +#define INTC_ICDABR13_TINT9 (0x00000200uL) +#define INTC_ICDABR13_TINT10 (0x00000400uL) +#define INTC_ICDABR13_TINT11 (0x00000800uL) +#define INTC_ICDABR13_TINT12 (0x00001000uL) +#define INTC_ICDABR13_TINT13 (0x00002000uL) +#define INTC_ICDABR13_TINT14 (0x00004000uL) +#define INTC_ICDABR13_TINT15 (0x00008000uL) +#define INTC_ICDABR13_TINT16 (0x00010000uL) +#define INTC_ICDABR13_TINT17 (0x00020000uL) +#define INTC_ICDABR13_TINT18 (0x00040000uL) +#define INTC_ICDABR13_TINT19 (0x00080000uL) +#define INTC_ICDABR13_TINT20 (0x00100000uL) +#define INTC_ICDABR13_TINT21 (0x00200000uL) +#define INTC_ICDABR13_TINT22 (0x00400000uL) +#define INTC_ICDABR13_TINT23 (0x00800000uL) +#define INTC_ICDABR13_TINT24 (0x01000000uL) +#define INTC_ICDABR13_TINT25 (0x02000000uL) +#define INTC_ICDABR13_TINT26 (0x04000000uL) +#define INTC_ICDABR13_TINT27 (0x08000000uL) +#define INTC_ICDABR13_TINT28 (0x10000000uL) +#define INTC_ICDABR13_TINT29 (0x20000000uL) +#define INTC_ICDABR13_TINT30 (0x40000000uL) +#define INTC_ICDABR13_TINT31 (0x80000000uL) + +#define INTC_ICDABR14_TINT32 (0x00000001uL) +#define INTC_ICDABR14_TINT33 (0x00000002uL) +#define INTC_ICDABR14_TINT34 (0x00000004uL) +#define INTC_ICDABR14_TINT35 (0x00000008uL) +#define INTC_ICDABR14_TINT36 (0x00000010uL) +#define INTC_ICDABR14_TINT37 (0x00000020uL) +#define INTC_ICDABR14_TINT38 (0x00000040uL) +#define INTC_ICDABR14_TINT39 (0x00000080uL) +#define INTC_ICDABR14_TINT40 (0x00000100uL) +#define INTC_ICDABR14_TINT41 (0x00000200uL) +#define INTC_ICDABR14_TINT42 (0x00000400uL) +#define INTC_ICDABR14_TINT43 (0x00000800uL) +#define INTC_ICDABR14_TINT44 (0x00001000uL) +#define INTC_ICDABR14_TINT45 (0x00002000uL) +#define INTC_ICDABR14_TINT46 (0x00004000uL) +#define INTC_ICDABR14_TINT47 (0x00008000uL) +#define INTC_ICDABR14_TINT48 (0x00010000uL) +#define INTC_ICDABR14_TINT49 (0x00020000uL) +#define INTC_ICDABR14_TINT50 (0x00040000uL) +#define INTC_ICDABR14_TINT51 (0x00080000uL) +#define INTC_ICDABR14_TINT52 (0x00100000uL) +#define INTC_ICDABR14_TINT53 (0x00200000uL) +#define INTC_ICDABR14_TINT54 (0x00400000uL) +#define INTC_ICDABR14_TINT55 (0x00800000uL) +#define INTC_ICDABR14_TINT56 (0x01000000uL) +#define INTC_ICDABR14_TINT57 (0x02000000uL) +#define INTC_ICDABR14_TINT58 (0x04000000uL) +#define INTC_ICDABR14_TINT59 (0x08000000uL) +#define INTC_ICDABR14_TINT60 (0x10000000uL) +#define INTC_ICDABR14_TINT61 (0x20000000uL) +#define INTC_ICDABR14_TINT62 (0x40000000uL) +#define INTC_ICDABR14_TINT63 (0x80000000uL) + +#define INTC_ICDABR15_TINT64 (0x00000001uL) +#define INTC_ICDABR15_TINT65 (0x00000002uL) +#define INTC_ICDABR15_TINT66 (0x00000004uL) +#define INTC_ICDABR15_TINT67 (0x00000008uL) +#define INTC_ICDABR15_TINT68 (0x00000010uL) +#define INTC_ICDABR15_TINT69 (0x00000020uL) +#define INTC_ICDABR15_TINT70 (0x00000040uL) +#define INTC_ICDABR15_TINT71 (0x00000080uL) +#define INTC_ICDABR15_TINT72 (0x00000100uL) +#define INTC_ICDABR15_TINT73 (0x00000200uL) +#define INTC_ICDABR15_TINT74 (0x00000400uL) +#define INTC_ICDABR15_TINT75 (0x00000800uL) +#define INTC_ICDABR15_TINT76 (0x00001000uL) +#define INTC_ICDABR15_TINT77 (0x00002000uL) +#define INTC_ICDABR15_TINT78 (0x00004000uL) +#define INTC_ICDABR15_TINT79 (0x00008000uL) +#define INTC_ICDABR15_TINT80 (0x00010000uL) +#define INTC_ICDABR15_TINT81 (0x00020000uL) +#define INTC_ICDABR15_TINT82 (0x00040000uL) +#define INTC_ICDABR15_TINT83 (0x00080000uL) +#define INTC_ICDABR15_TINT84 (0x00100000uL) +#define INTC_ICDABR15_TINT85 (0x00200000uL) +#define INTC_ICDABR15_TINT86 (0x00400000uL) +#define INTC_ICDABR15_TINT87 (0x00800000uL) +#define INTC_ICDABR15_TINT88 (0x01000000uL) +#define INTC_ICDABR15_TINT89 (0x02000000uL) +#define INTC_ICDABR15_TINT90 (0x04000000uL) +#define INTC_ICDABR15_TINT91 (0x08000000uL) +#define INTC_ICDABR15_TINT92 (0x10000000uL) +#define INTC_ICDABR15_TINT93 (0x20000000uL) +#define INTC_ICDABR15_TINT94 (0x40000000uL) +#define INTC_ICDABR15_TINT95 (0x80000000uL) + +#define INTC_ICDABR16_TINT96 (0x00000001uL) +#define INTC_ICDABR16_TINT97 (0x00000002uL) +#define INTC_ICDABR16_TINT98 (0x00000004uL) +#define INTC_ICDABR16_TINT99 (0x00000008uL) +#define INTC_ICDABR16_TINT100 (0x00000010uL) +#define INTC_ICDABR16_TINT101 (0x00000020uL) +#define INTC_ICDABR16_TINT102 (0x00000040uL) +#define INTC_ICDABR16_TINT103 (0x00000080uL) +#define INTC_ICDABR16_TINT104 (0x00000100uL) +#define INTC_ICDABR16_TINT105 (0x00000200uL) +#define INTC_ICDABR16_TINT106 (0x00000400uL) +#define INTC_ICDABR16_TINT107 (0x00000800uL) +#define INTC_ICDABR16_TINT108 (0x00001000uL) +#define INTC_ICDABR16_TINT109 (0x00002000uL) +#define INTC_ICDABR16_TINT110 (0x00004000uL) +#define INTC_ICDABR16_TINT111 (0x00008000uL) +#define INTC_ICDABR16_TINT112 (0x00010000uL) +#define INTC_ICDABR16_TINT113 (0x00020000uL) +#define INTC_ICDABR16_TINT114 (0x00040000uL) +#define INTC_ICDABR16_TINT115 (0x00080000uL) +#define INTC_ICDABR16_TINT116 (0x00100000uL) +#define INTC_ICDABR16_TINT117 (0x00200000uL) +#define INTC_ICDABR16_TINT118 (0x00400000uL) +#define INTC_ICDABR16_TINT119 (0x00800000uL) +#define INTC_ICDABR16_TINT120 (0x01000000uL) +#define INTC_ICDABR16_TINT121 (0x02000000uL) +#define INTC_ICDABR16_TINT122 (0x04000000uL) +#define INTC_ICDABR16_TINT123 (0x08000000uL) +#define INTC_ICDABR16_TINT124 (0x10000000uL) +#define INTC_ICDABR16_TINT125 (0x20000000uL) +#define INTC_ICDABR16_TINT126 (0x40000000uL) +#define INTC_ICDABR16_TINT127 (0x80000000uL) + +#define INTC_ICDABR17_TINT128 (0x00000001uL) +#define INTC_ICDABR17_TINT129 (0x00000002uL) +#define INTC_ICDABR17_TINT130 (0x00000004uL) +#define INTC_ICDABR17_TINT131 (0x00000008uL) +#define INTC_ICDABR17_TINT132 (0x00000010uL) +#define INTC_ICDABR17_TINT133 (0x00000020uL) +#define INTC_ICDABR17_TINT134 (0x00000040uL) +#define INTC_ICDABR17_TINT135 (0x00000080uL) +#define INTC_ICDABR17_TINT136 (0x00000100uL) +#define INTC_ICDABR17_TINT137 (0x00000200uL) +#define INTC_ICDABR17_TINT138 (0x00000400uL) +#define INTC_ICDABR17_TINT139 (0x00000800uL) +#define INTC_ICDABR17_TINT140 (0x00001000uL) +#define INTC_ICDABR17_TINT141 (0x00002000uL) +#define INTC_ICDABR17_TINT142 (0x00004000uL) +#define INTC_ICDABR17_TINT143 (0x00008000uL) +#define INTC_ICDABR17_TINT144 (0x00010000uL) +#define INTC_ICDABR17_TINT145 (0x00020000uL) +#define INTC_ICDABR17_TINT146 (0x00040000uL) +#define INTC_ICDABR17_TINT147 (0x00080000uL) +#define INTC_ICDABR17_TINT148 (0x00100000uL) +#define INTC_ICDABR17_TINT149 (0x00200000uL) +#define INTC_ICDABR17_TINT150 (0x00400000uL) +#define INTC_ICDABR17_TINT151 (0x00800000uL) +#define INTC_ICDABR17_TINT152 (0x01000000uL) +#define INTC_ICDABR17_TINT153 (0x02000000uL) +#define INTC_ICDABR17_TINT154 (0x04000000uL) +#define INTC_ICDABR17_TINT155 (0x08000000uL) +#define INTC_ICDABR17_TINT156 (0x10000000uL) +#define INTC_ICDABR17_TINT157 (0x20000000uL) +#define INTC_ICDABR17_TINT158 (0x40000000uL) +#define INTC_ICDABR17_TINT159 (0x80000000uL) + +#define INTC_ICDABR18_TINT160 (0x00000001uL) +#define INTC_ICDABR18_TINT161 (0x00000002uL) +#define INTC_ICDABR18_TINT162 (0x00000004uL) +#define INTC_ICDABR18_TINT163 (0x00000008uL) +#define INTC_ICDABR18_TINT164 (0x00000010uL) +#define INTC_ICDABR18_TINT165 (0x00000020uL) +#define INTC_ICDABR18_TINT166 (0x00000040uL) +#define INTC_ICDABR18_TINT167 (0x00000080uL) +#define INTC_ICDABR18_TINT168 (0x00000100uL) +#define INTC_ICDABR18_TINT169 (0x00000200uL) +#define INTC_ICDABR18_TINT170 (0x00000400uL) + +#define INTC_ICDIPR0_SW0 (0x000000FFuL) +#define INTC_ICDIPR0_SW1 (0x0000FF00uL) +#define INTC_ICDIPR0_SW2 (0x00FF0000uL) +#define INTC_ICDIPR0_SW3 (0xFF000000uL) + +#define INTC_ICDIPR1_SW4 (0x000000FFuL) +#define INTC_ICDIPR1_SW5 (0x0000FF00uL) +#define INTC_ICDIPR1_SW6 (0x00FF0000uL) +#define INTC_ICDIPR1_SW7 (0xFF000000uL) + +#define INTC_ICDIPR2_SW8 (0x000000FFuL) +#define INTC_ICDIPR2_SW9 (0x0000FF00uL) +#define INTC_ICDIPR2_SW10 (0x00FF0000uL) +#define INTC_ICDIPR2_SW11 (0xFF000000uL) + +#define INTC_ICDIPR3_SW12 (0x000000FFuL) +#define INTC_ICDIPR3_SW13 (0x0000FF00uL) +#define INTC_ICDIPR3_SW14 (0x00FF0000uL) +#define INTC_ICDIPR3_SW15 (0xFF000000uL) + +#define INTC_ICDIPR4_PMUIRQ0 (0x000000FFuL) +#define INTC_ICDIPR4_COMMRX0 (0x0000FF00uL) +#define INTC_ICDIPR4_COMMTX0 (0x00FF0000uL) +#define INTC_ICDIPR4_CTIIRQ0 (0xFF000000uL) + +#define INTC_ICDIPR8_IRQ0 (0x000000FFuL) +#define INTC_ICDIPR8_IRQ1 (0x0000FF00uL) +#define INTC_ICDIPR8_IRQ2 (0x00FF0000uL) +#define INTC_ICDIPR8_IRQ3 (0xFF000000uL) + +#define INTC_ICDIPR9_IRQ4 (0x000000FFuL) +#define INTC_ICDIPR9_IRQ5 (0x0000FF00uL) +#define INTC_ICDIPR9_IRQ6 (0x00FF0000uL) +#define INTC_ICDIPR9_IRQ7 (0xFF000000uL) + +#define INTC_ICDIPR10_PL310ERR (0x000000FFuL) +#define INTC_ICDIPR10_DMAINT0 (0x0000FF00uL) +#define INTC_ICDIPR10_DMAINT1 (0x00FF0000uL) +#define INTC_ICDIPR10_DMAINT2 (0xFF000000uL) + +#define INTC_ICDIPR11_DMAINT3 (0x000000FFuL) +#define INTC_ICDIPR11_DMAINT4 (0x0000FF00uL) +#define INTC_ICDIPR11_DMAINT5 (0x00FF0000uL) +#define INTC_ICDIPR11_DMAINT6 (0xFF000000uL) + +#define INTC_ICDIPR12_DMAINT7 (0x000000FFuL) +#define INTC_ICDIPR12_DMAINT8 (0x0000FF00uL) +#define INTC_ICDIPR12_DMAINT9 (0x00FF0000uL) +#define INTC_ICDIPR12_DMAINT10 (0xFF000000uL) + +#define INTC_ICDIPR13_DMAINT11 (0x000000FFuL) +#define INTC_ICDIPR13_DMAINT12 (0x0000FF00uL) +#define INTC_ICDIPR13_DMAINT13 (0x00FF0000uL) +#define INTC_ICDIPR13_DMAINT14 (0xFF000000uL) + +#define INTC_ICDIPR14_DMAINT15 (0x000000FFuL) +#define INTC_ICDIPR14_DMAERR (0x0000FF00uL) + +#define INTC_ICDIPR18_USBI0 (0x0000FF00uL) +#define INTC_ICDIPR18_USBI1 (0x00FF0000uL) +#define INTC_ICDIPR18_S0_VI_VSYNC0 (0xFF000000uL) + +#define INTC_ICDIPR19_S0_LO_VSYNC0 (0x000000FFuL) +#define INTC_ICDIPR19_S0_VSYNCERR0 (0x0000FF00uL) +#define INTC_ICDIPR19_GR3_VLINE0 (0x00FF0000uL) +#define INTC_ICDIPR19_S0_VFIELD0 (0xFF000000uL) + +#define INTC_ICDIPR20_IV1_VBUFERR0 (0x000000FFuL) +#define INTC_ICDIPR20_IV3_VBUFERR0 (0x0000FF00uL) +#define INTC_ICDIPR20_IV5_VBUFERR0 (0x00FF0000uL) +#define INTC_ICDIPR20_IV6_VBUFERR0 (0xFF000000uL) + +#define INTC_ICDIPR21_S0_WLINE0 (0x000000FFuL) +#define INTC_ICDIPR21_S1_VI_VSYNC0 (0x0000FF00uL) +#define INTC_ICDIPR21_S1_LO_VSYNC0 (0x00FF0000uL) +#define INTC_ICDIPR21_S1_VSYNCERR0 (0xFF000000uL) + +#define INTC_ICDIPR22_S1_VFIELD0 (0x000000FFuL) +#define INTC_ICDIPR22_IV2_VBUFERR0 (0x0000FF00uL) +#define INTC_ICDIPR22_IV4_VBUFERR0 (0x00FF0000uL) +#define INTC_ICDIPR22_S1_WLINE0 (0xFF000000uL) + +#define INTC_ICDIPR23_OIR_VI_VSYNC0 (0x000000FFuL) +#define INTC_ICDIPR23_OIR_LO_VSYNC0 (0x0000FF00uL) +#define INTC_ICDIPR23_OIR_VSYNCERR0 (0x00FF0000uL) +#define INTC_ICDIPR23_OIR_VFIELD0 (0xFF000000uL) + +#define INTC_ICDIPR24_IV7_VBUFERR0 (0x000000FFuL) +#define INTC_ICDIPR24_IV8_VBUFERR0 (0x0000FF00uL) +#define INTC_ICDIPR24_S0_VI_VSYNC1 (0xFF000000uL) + +#define INTC_ICDIPR25_S0_LO_VSYNC1 (0x000000FFuL) +#define INTC_ICDIPR25_S0_VSYNCERR1 (0x0000FF00uL) +#define INTC_ICDIPR25_GR3_VLINE1 (0x00FF0000uL) +#define INTC_ICDIPR25_S0_VFIELD1 (0xFF000000uL) + +#define INTC_ICDIPR26_IV1_VBUFERR1 (0x000000FFuL) +#define INTC_ICDIPR26_IV3_VBUFERR1 (0x0000FF00uL) +#define INTC_ICDIPR26_IV5_VBUFERR1 (0x00FF0000uL) +#define INTC_ICDIPR26_IV6_VBUFERR1 (0xFF000000uL) + +#define INTC_ICDIPR27_S0_WLINE1 (0x000000FFuL) +#define INTC_ICDIPR27_S1_VI_VSYNC1 (0x0000FF00uL) +#define INTC_ICDIPR27_S1_LO_VSYNC1 (0x00FF0000uL) +#define INTC_ICDIPR27_S1_VSYNCERR1 (0xFF000000uL) + +#define INTC_ICDIPR28_S1_VFIELD1 (0x000000FFuL) +#define INTC_ICDIPR28_IV2_VBUFERR1 (0x0000FF00uL) +#define INTC_ICDIPR28_IV4_VBUFERR1 (0x00FF0000uL) +#define INTC_ICDIPR28_S1_WLINE1 (0xFF000000uL) + +#define INTC_ICDIPR29_OIR_VI_VSYNC1 (0x000000FFuL) +#define INTC_ICDIPR29_OIR_LO_VSYNC1 (0x0000FF00uL) +#define INTC_ICDIPR29_OIR_VLINE1 (0x00FF0000uL) +#define INTC_ICDIPR29_OIR_VFIELD1 (0xFF000000uL) + +#define INTC_ICDIPR30_IV7_VBUFERR1 (0x000000FFuL) +#define INTC_ICDIPR30_IV8_VBUFERR1 (0x0000FF00uL) +#define INTC_ICDIPR30_IMRDI (0xFF000000uL) + +#define INTC_ICDIPR31_IMR2I0 (0x000000FFuL) +#define INTC_ICDIPR31_IMR2I1 (0x0000FF00uL) +#define INTC_ICDIPR31_JEDI (0x00FF0000uL) +#define INTC_ICDIPR31_JDTI (0xFF000000uL) + +#define INTC_ICDIPR32_CMP0 (0x000000FFuL) +#define INTC_ICDIPR32_CMP1 (0x0000FF00uL) +#define INTC_ICDIPR32_INT0 (0x00FF0000uL) +#define INTC_ICDIPR32_INT1 (0xFF000000uL) + +#define INTC_ICDIPR33_INT2 (0x000000FFuL) +#define INTC_ICDIPR33_INT3 (0x0000FF00uL) +#define INTC_ICDIPR33_OSTM0TINT (0x00FF0000uL) +#define INTC_ICDIPR33_OSTM1TINT (0xFF000000uL) + +#define INTC_ICDIPR34_CMI (0x000000FFuL) +#define INTC_ICDIPR34_WTOUT (0x0000FF00uL) +#define INTC_ICDIPR34_ITI (0x00FF0000uL) +#define INTC_ICDIPR34_TGI0A (0xFF000000uL) + +#define INTC_ICDIPR35_TGI0B (0x000000FFuL) +#define INTC_ICDIPR35_TGI0C (0x0000FF00uL) +#define INTC_ICDIPR35_TGI0D (0x00FF0000uL) +#define INTC_ICDIPR35_TGI0V (0xFF000000uL) + +#define INTC_ICDIPR36_TGI0E (0x000000FFuL) +#define INTC_ICDIPR36_TGI0F (0x0000FF00uL) +#define INTC_ICDIPR36_TGI1A (0x00FF0000uL) +#define INTC_ICDIPR36_TGI1B (0xFF000000uL) + +#define INTC_ICDIPR37_TGI1V (0x000000FFuL) +#define INTC_ICDIPR37_TGI1U (0x0000FF00uL) +#define INTC_ICDIPR37_TGI2A (0x00FF0000uL) +#define INTC_ICDIPR37_TGI2B (0xFF000000uL) + +#define INTC_ICDIPR38_TGI2V (0x000000FFuL) +#define INTC_ICDIPR38_TGI2U (0x0000FF00uL) +#define INTC_ICDIPR38_TGI3A (0x00FF0000uL) +#define INTC_ICDIPR38_TGI3B (0xFF000000uL) + +#define INTC_ICDIPR39_TGI3C (0x000000FFuL) +#define INTC_ICDIPR39_TGI3D (0x0000FF00uL) +#define INTC_ICDIPR39_TGI3V (0x00FF0000uL) +#define INTC_ICDIPR39_TGI4A (0xFF000000uL) + +#define INTC_ICDIPR40_TGI4B (0x000000FFuL) +#define INTC_ICDIPR40_TGI4C (0x0000FF00uL) +#define INTC_ICDIPR40_TGI4D (0x00FF0000uL) +#define INTC_ICDIPR40_TGI4V (0xFF000000uL) + +#define INTC_ICDIPR41_CMI1 (0x000000FFuL) +#define INTC_ICDIPR41_CMI2 (0x0000FF00uL) +#define INTC_ICDIPR41_SGDEI0 (0x00FF0000uL) +#define INTC_ICDIPR41_SGDEI1 (0xFF000000uL) + +#define INTC_ICDIPR42_SGDEI2 (0x000000FFuL) +#define INTC_ICDIPR42_SGDEI3 (0x0000FF00uL) +#define INTC_ICDIPR42_ADI (0x00FF0000uL) +#define INTC_ICDIPR42_LMTI (0xFF000000uL) + +#define INTC_ICDIPR43_SSII0 (0x000000FFuL) +#define INTC_ICDIPR43_SSIRXI0 (0x0000FF00uL) +#define INTC_ICDIPR43_SSITXI0 (0x00FF0000uL) +#define INTC_ICDIPR43_SSII1 (0xFF000000uL) + +#define INTC_ICDIPR44_SSIRXI1 (0x000000FFuL) +#define INTC_ICDIPR44_SSITXI1 (0x0000FF00uL) +#define INTC_ICDIPR44_SSII2 (0x00FF0000uL) +#define INTC_ICDIPR44_SSIRTI2 (0xFF000000uL) + +#define INTC_ICDIPR45_SSII3 (0x000000FFuL) +#define INTC_ICDIPR45_SSIRXI3 (0x0000FF00uL) +#define INTC_ICDIPR45_SSITXI3 (0x00FF0000uL) +#define INTC_ICDIPR45_SSII4 (0xFF000000uL) + +#define INTC_ICDIPR46_SSIRTI4 (0x000000FFuL) +#define INTC_ICDIPR46_SSII5 (0x0000FF00uL) +#define INTC_ICDIPR46_SSIRXI5 (0x00FF0000uL) +#define INTC_ICDIPR46_SSITXI5 (0xFF000000uL) + +#define INTC_ICDIPR47_SPDIFI (0x000000FFuL) +#define INTC_ICDIPR47_INTIICTEI0 (0x0000FF00uL) +#define INTC_ICDIPR47_INTIICRI0 (0x00FF0000uL) +#define INTC_ICDIPR47_INTIICTI0 (0xFF000000uL) + +#define INTC_ICDIPR48_INTIICSPI0 (0x000000FFuL) +#define INTC_ICDIPR48_INTIICSTI0 (0x0000FF00uL) +#define INTC_ICDIPR48_INTIICNAKI0 (0x00FF0000uL) +#define INTC_ICDIPR48_INTIICALI0 (0xFF000000uL) + +#define INTC_ICDIPR49_INTIICTMOI0 (0x000000FFuL) +#define INTC_ICDIPR49_INTIICTEI1 (0x0000FF00uL) +#define INTC_ICDIPR49_INTIICRI1 (0x00FF0000uL) +#define INTC_ICDIPR49_INTIICTI1 (0xFF000000uL) + +#define INTC_ICDIPR50_INTIICSPI1 (0x000000FFuL) +#define INTC_ICDIPR50_INTIICSTI1 (0x0000FF00uL) +#define INTC_ICDIPR50_INTIICNAKI1 (0x00FF0000uL) +#define INTC_ICDIPR50_INTIICALI1 (0xFF000000uL) + +#define INTC_ICDIPR51_INTIICTMOI1 (0x000000FFuL) +#define INTC_ICDIPR51_INTIICTEI2 (0x0000FF00uL) +#define INTC_ICDIPR51_INTIICRI2 (0x00FF0000uL) +#define INTC_ICDIPR51_INTIICTI2 (0xFF000000uL) + +#define INTC_ICDIPR52_INTIICSPI2 (0x000000FFuL) +#define INTC_ICDIPR52_INTIICSTI2 (0x0000FF00uL) +#define INTC_ICDIPR52_INTIICNAKI2 (0x00FF0000uL) +#define INTC_ICDIPR52_INTIICALI2 (0xFF000000uL) + +#define INTC_ICDIPR53_INTIICTMOI2 (0x000000FFuL) +#define INTC_ICDIPR53_INTIICTEI3 (0x0000FF00uL) +#define INTC_ICDIPR53_INTIICRI3 (0x00FF0000uL) +#define INTC_ICDIPR53_INTIICTI3 (0xFF000000uL) + +#define INTC_ICDIPR54_INTIICSPI3 (0x000000FFuL) +#define INTC_ICDIPR54_INTIICSTI3 (0x0000FF00uL) +#define INTC_ICDIPR54_INTIICNAKI3 (0x00FF0000uL) +#define INTC_ICDIPR54_INTIICALI3 (0xFF000000uL) + +#define INTC_ICDIPR55_INTIICTMOI3 (0x000000FFuL) +#define INTC_ICDIPR55_BRI0 (0x0000FF00uL) +#define INTC_ICDIPR55_ERI0 (0x00FF0000uL) +#define INTC_ICDIPR55_RXI0 (0xFF000000uL) + +#define INTC_ICDIPR56_TXI0 (0x000000FFuL) +#define INTC_ICDIPR56_BRI1 (0x0000FF00uL) +#define INTC_ICDIPR56_ERI1 (0x00FF0000uL) +#define INTC_ICDIPR56_RXI1 (0xFF000000uL) + +#define INTC_ICDIPR57_TXI1 (0x000000FFuL) +#define INTC_ICDIPR57_BRI2 (0x0000FF00uL) +#define INTC_ICDIPR57_ERI2 (0x00FF0000uL) +#define INTC_ICDIPR57_RXI2 (0xFF000000uL) + +#define INTC_ICDIPR58_TXI2 (0x000000FFuL) +#define INTC_ICDIPR58_BRI3 (0x0000FF00uL) +#define INTC_ICDIPR58_ERI3 (0x00FF0000uL) +#define INTC_ICDIPR58_RXI3 (0xFF000000uL) + +#define INTC_ICDIPR59_TXI3 (0x000000FFuL) +#define INTC_ICDIPR59_BRI4 (0x0000FF00uL) +#define INTC_ICDIPR59_ERI4 (0x00FF0000uL) +#define INTC_ICDIPR59_RXI4 (0xFF000000uL) + +#define INTC_ICDIPR60_TXI4 (0x000000FFuL) +#define INTC_ICDIPR60_BRI5 (0x0000FF00uL) +#define INTC_ICDIPR60_ERI5 (0x00FF0000uL) +#define INTC_ICDIPR60_RXI5 (0xFF000000uL) + +#define INTC_ICDIPR61_TXI5 (0x000000FFuL) +#define INTC_ICDIPR61_BRI6 (0x0000FF00uL) +#define INTC_ICDIPR61_ERI6 (0x00FF0000uL) +#define INTC_ICDIPR61_RXI6 (0xFF000000uL) + +#define INTC_ICDIPR62_TXI6 (0x000000FFuL) +#define INTC_ICDIPR62_BRI7 (0x0000FF00uL) +#define INTC_ICDIPR62_ERI7 (0x00FF0000uL) +#define INTC_ICDIPR62_RXI7 (0xFF000000uL) + +#define INTC_ICDIPR63_TXI7 (0x000000FFuL) +#define INTC_ICDIPR63_INTRCANGERR (0x0000FF00uL) +#define INTC_ICDIPR63_INTRCANGRECC (0x00FF0000uL) +#define INTC_ICDIPR63_INTRCAN0REC (0xFF000000uL) + +#define INTC_ICDIPR64_INTRCAN0ERR (0x000000FFuL) +#define INTC_ICDIPR64_INTRCAN0TRX (0x0000FF00uL) +#define INTC_ICDIPR64_INTRCAN1REC (0x00FF0000uL) +#define INTC_ICDIPR64_INTRCAN1ERR (0xFF000000uL) + +#define INTC_ICDIPR65_INTRCAN1TRX (0x000000FFuL) +#define INTC_ICDIPR65_INTRCAN2REC (0x0000FF00uL) +#define INTC_ICDIPR65_INTRCAN2ERR (0x00FF0000uL) +#define INTC_ICDIPR65_INTRCAN2TRX (0xFF000000uL) + +#define INTC_ICDIPR66_INTRCAN3REC (0x000000FFuL) +#define INTC_ICDIPR66_INTRCAN3ERR (0x0000FF00uL) +#define INTC_ICDIPR66_INTRCAN3TRX (0x00FF0000uL) +#define INTC_ICDIPR66_INTRCAN4REC (0xFF000000uL) + +#define INTC_ICDIPR67_INTRCAN4ERR (0x000000FFuL) +#define INTC_ICDIPR67_INTRCAN4TRX (0x0000FF00uL) +#define INTC_ICDIPR67_SPEI0 (0x00FF0000uL) +#define INTC_ICDIPR67_SPRI0 (0xFF000000uL) + +#define INTC_ICDIPR68_SPTI0 (0x000000FFuL) +#define INTC_ICDIPR68_SPEI1 (0x0000FF00uL) +#define INTC_ICDIPR68_SPRI1 (0x00FF0000uL) +#define INTC_ICDIPR68_SPTI1 (0xFF000000uL) + +#define INTC_ICDIPR69_SPEI2 (0x000000FFuL) +#define INTC_ICDIPR69_SPRI2 (0x0000FF00uL) +#define INTC_ICDIPR69_SPTI2 (0x00FF0000uL) +#define INTC_ICDIPR69_SPEI3 (0xFF000000uL) + +#define INTC_ICDIPR70_SPRI3 (0x000000FFuL) +#define INTC_ICDIPR70_SPTI3 (0x0000FF00uL) +#define INTC_ICDIPR70_SPEI4 (0x00FF0000uL) +#define INTC_ICDIPR70_SPRI4 (0xFF000000uL) + +#define INTC_ICDIPR71_SPTI4 (0x000000FFuL) +#define INTC_ICDIPR71_IEBBTD (0x0000FF00uL) +#define INTC_ICDIPR71_IEBBTERR (0x00FF0000uL) +#define INTC_ICDIPR71_IEBBTSTA (0xFF000000uL) + +#define INTC_ICDIPR72_IEBBTV (0x000000FFuL) +#define INTC_ICDIPR72_ISY (0x0000FF00uL) +#define INTC_ICDIPR72_IERR (0x00FF0000uL) +#define INTC_ICDIPR72_ITARG (0xFF000000uL) + +#define INTC_ICDIPR73_ISEC (0x000000FFuL) +#define INTC_ICDIPR73_IBUF (0x0000FF00uL) +#define INTC_ICDIPR73_IREADY (0x00FF0000uL) +#define INTC_ICDIPR73_FLSTE (0xFF000000uL) + +#define INTC_ICDIPR74_FLTENDI (0x000000FFuL) +#define INTC_ICDIPR74_FLTREQ0I (0x0000FF00uL) +#define INTC_ICDIPR74_FLTREQ1I (0x00FF0000uL) +#define INTC_ICDIPR74_MMC0 (0xFF000000uL) + +#define INTC_ICDIPR75_MMC1 (0x000000FFuL) +#define INTC_ICDIPR75_MMC2 (0x0000FF00uL) +#define INTC_ICDIPR75_SDHI0_3 (0x00FF0000uL) +#define INTC_ICDIPR75_SDHI0_0 (0xFF000000uL) + +#define INTC_ICDIPR76_SDHI0_1 (0x000000FFuL) +#define INTC_ICDIPR76_SDHI1_3 (0x0000FF00uL) +#define INTC_ICDIPR76_SDHI1_0 (0x00FF0000uL) +#define INTC_ICDIPR76_SDHI1_1 (0xFF000000uL) + +#define INTC_ICDIPR77_ARM (0x000000FFuL) +#define INTC_ICDIPR77_PRD (0x0000FF00uL) +#define INTC_ICDIPR77_CUP (0x00FF0000uL) +#define INTC_ICDIPR77_SCUAI0 (0xFF000000uL) + +#define INTC_ICDIPR78_SCUAI1 (0x000000FFuL) +#define INTC_ICDIPR78_SCUFDI0 (0x0000FF00uL) +#define INTC_ICDIPR78_SCUFDI1 (0x00FF0000uL) +#define INTC_ICDIPR78_SCUFDI2 (0xFF000000uL) + +#define INTC_ICDIPR79_SCUFDI3 (0x000000FFuL) +#define INTC_ICDIPR79_SCUFUI0 (0x0000FF00uL) +#define INTC_ICDIPR79_SCUFUI1 (0x00FF0000uL) +#define INTC_ICDIPR79_SCUFUI2 (0xFF000000uL) + +#define INTC_ICDIPR80_SCUFUI3 (0x000000FFuL) +#define INTC_ICDIPR80_SCUDVI0 (0x0000FF00uL) +#define INTC_ICDIPR80_SCUDVI1 (0x00FF0000uL) +#define INTC_ICDIPR80_SCUDVI2 (0xFF000000uL) + +#define INTC_ICDIPR81_SCUDVI3 (0x000000FFuL) +#define INTC_ICDIPR81_MLB_CINT (0x0000FF00uL) +#define INTC_ICDIPR81_MLB_SINT (0x00FF0000uL) +#define INTC_ICDIPR81_DRC0 (0xFF000000uL) + +#define INTC_ICDIPR82_DRC1 (0x000000FFuL) +#define INTC_ICDIPR82_LINI0_INT_T (0xFF000000uL) + +#define INTC_ICDIPR83_LINI0_INT_R (0x000000FFuL) +#define INTC_ICDIPR83_LINI0_INT_S (0x0000FF00uL) +#define INTC_ICDIPR83_LINI0_INT_M (0x00FF0000uL) +#define INTC_ICDIPR83_LINI1_INT_T (0xFF000000uL) + +#define INTC_ICDIPR84_LINI1_INT_R (0x000000FFuL) +#define INTC_ICDIPR84_LINI1_INT_S (0x0000FF00uL) +#define INTC_ICDIPR84_LINI1_INT_M (0x00FF0000uL) + +#define INTC_ICDIPR86_ERI0 (0xFF000000uL) + +#define INTC_ICDIPR87_RXI0 (0x000000FFuL) +#define INTC_ICDIPR87_TXI0 (0x0000FF00uL) +#define INTC_ICDIPR87_TEI0 (0x00FF0000uL) +#define INTC_ICDIPR87_ERI1 (0xFF000000uL) + +#define INTC_ICDIPR88_RXI1 (0x000000FFuL) +#define INTC_ICDIPR88_TXI1 (0x0000FF00uL) +#define INTC_ICDIPR88_TEI1 (0x00FF0000uL) +#define INTC_ICDIPR88_AVBI_DATA (0xFF000000uL) + +#define INTC_ICDIPR89_AVBI_ERROR (0x000000FFuL) +#define INTC_ICDIPR89_AVBI_MANAGE (0x0000FF00uL) +#define INTC_ICDIPR89_AVBI_MAC (0x00FF0000uL) +#define INTC_ICDIPR89_ETHERI (0xFF000000uL) + +#define INTC_ICDIPR91_CEUI (0x000000FFuL) + +#define INTC_ICDIPR95_H2XMLB_ERRINT (0x0000FF00uL) +#define INTC_ICDIPR95_H2XIC1_ERRINT (0x00FF0000uL) +#define INTC_ICDIPR95_X2HPERI1_ERRINT (0xFF000000uL) + +#define INTC_ICDIPR96_X2HPERI2_ERRINT (0x000000FFuL) +#define INTC_ICDIPR96_X2HPERI34_ERRINT (0x0000FF00uL) +#define INTC_ICDIPR96_X2HPERI5_ERRINT (0x00FF0000uL) +#define INTC_ICDIPR96_X2HPERI67_ERRINT (0xFF000000uL) + +#define INTC_ICDIPR97_X2HDBGR_ERRINT (0x000000FFuL) +#define INTC_ICDIPR97_X2HBSC_ERRINT (0x0000FF00uL) +#define INTC_ICDIPR97_X2HSPI1_ERRINT (0x00FF0000uL) +#define INTC_ICDIPR97_X2HSPI2_ERRINT (0xFF000000uL) + +#define INTC_ICDIPR98_PRRI (0x000000FFuL) +#define INTC_ICDIPR98_IFEI0 (0x0000FF00uL) +#define INTC_ICDIPR98_OFFI0 (0x00FF0000uL) +#define INTC_ICDIPR98_PFVEI0 (0xFF000000uL) + +#define INTC_ICDIPR99_IFEI1 (0x000000FFuL) +#define INTC_ICDIPR99_OFFI1 (0x0000FF00uL) +#define INTC_ICDIPR99_PFVEI1 (0x00FF0000uL) + +#define INTC_ICDIPR104_TINT0 (0x000000FFuL) +#define INTC_ICDIPR104_TINT1 (0x0000FF00uL) +#define INTC_ICDIPR104_TINT2 (0x00FF0000uL) +#define INTC_ICDIPR104_TINT3 (0xFF000000uL) + +#define INTC_ICDIPR105_TINT4 (0x000000FFuL) +#define INTC_ICDIPR105_TINT5 (0x0000FF00uL) +#define INTC_ICDIPR105_TINT6 (0x00FF0000uL) +#define INTC_ICDIPR105_TINT7 (0xFF000000uL) + +#define INTC_ICDIPR106_TINT8 (0x000000FFuL) +#define INTC_ICDIPR106_TINT9 (0x0000FF00uL) +#define INTC_ICDIPR106_TINT10 (0x00FF0000uL) +#define INTC_ICDIPR106_TINT11 (0xFF000000uL) + +#define INTC_ICDIPR107_TINT12 (0x000000FFuL) +#define INTC_ICDIPR107_TINT13 (0x0000FF00uL) +#define INTC_ICDIPR107_TINT14 (0x00FF0000uL) +#define INTC_ICDIPR107_TINT15 (0xFF000000uL) + +#define INTC_ICDIPR108_TINT16 (0x000000FFuL) +#define INTC_ICDIPR108_TINT17 (0x0000FF00uL) +#define INTC_ICDIPR108_TINT18 (0x00FF0000uL) +#define INTC_ICDIPR108_TINT19 (0xFF000000uL) + +#define INTC_ICDIPR109_TINT20 (0x000000FFuL) +#define INTC_ICDIPR109_TINT21 (0x0000FF00uL) +#define INTC_ICDIPR109_TINT22 (0x00FF0000uL) +#define INTC_ICDIPR109_TINT23 (0xFF000000uL) + +#define INTC_ICDIPR110_TINT24 (0x000000FFuL) +#define INTC_ICDIPR110_TINT25 (0x0000FF00uL) +#define INTC_ICDIPR110_TINT26 (0x00FF0000uL) +#define INTC_ICDIPR110_TINT27 (0xFF000000uL) + +#define INTC_ICDIPR111_TINT28 (0x000000FFuL) +#define INTC_ICDIPR111_TINT29 (0x0000FF00uL) +#define INTC_ICDIPR111_TINT30 (0x00FF0000uL) +#define INTC_ICDIPR111_TINT31 (0xFF000000uL) + +#define INTC_ICDIPR112_TINT32 (0x000000FFuL) +#define INTC_ICDIPR112_TINT33 (0x0000FF00uL) +#define INTC_ICDIPR112_TINT34 (0x00FF0000uL) +#define INTC_ICDIPR112_TINT35 (0xFF000000uL) + +#define INTC_ICDIPR113_TINT36 (0x000000FFuL) +#define INTC_ICDIPR113_TINT37 (0x0000FF00uL) +#define INTC_ICDIPR113_TINT38 (0x00FF0000uL) +#define INTC_ICDIPR113_TINT39 (0xFF000000uL) + +#define INTC_ICDIPR114_TINT40 (0x000000FFuL) +#define INTC_ICDIPR114_TINT41 (0x0000FF00uL) +#define INTC_ICDIPR114_TINT42 (0x00FF0000uL) +#define INTC_ICDIPR114_TINT43 (0xFF000000uL) + +#define INTC_ICDIPR115_TINT44 (0x000000FFuL) +#define INTC_ICDIPR115_TINT45 (0x0000FF00uL) +#define INTC_ICDIPR115_TINT46 (0x00FF0000uL) +#define INTC_ICDIPR115_TINT47 (0xFF000000uL) + +#define INTC_ICDIPR116_TINT48 (0x000000FFuL) +#define INTC_ICDIPR116_TINT49 (0x0000FF00uL) +#define INTC_ICDIPR116_TINT50 (0x00FF0000uL) +#define INTC_ICDIPR116_TINT51 (0xFF000000uL) + +#define INTC_ICDIPR117_TINT52 (0x000000FFuL) +#define INTC_ICDIPR117_TINT53 (0x0000FF00uL) +#define INTC_ICDIPR117_TINT54 (0x00FF0000uL) +#define INTC_ICDIPR117_TINT55 (0xFF000000uL) + +#define INTC_ICDIPR118_TINT56 (0x000000FFuL) +#define INTC_ICDIPR118_TINT57 (0x0000FF00uL) +#define INTC_ICDIPR118_TINT58 (0x00FF0000uL) +#define INTC_ICDIPR118_TINT59 (0xFF000000uL) + +#define INTC_ICDIPR119_TINT60 (0x000000FFuL) +#define INTC_ICDIPR119_TINT61 (0x0000FF00uL) +#define INTC_ICDIPR119_TINT62 (0x00FF0000uL) +#define INTC_ICDIPR119_TINT63 (0xFF000000uL) + +#define INTC_ICDIPR120_TINT64 (0x000000FFuL) +#define INTC_ICDIPR120_TINT65 (0x0000FF00uL) +#define INTC_ICDIPR120_TINT66 (0x00FF0000uL) +#define INTC_ICDIPR120_TINT67 (0xFF000000uL) + +#define INTC_ICDIPR121_TINT68 (0x000000FFuL) +#define INTC_ICDIPR121_TINT69 (0x0000FF00uL) +#define INTC_ICDIPR121_TINT70 (0x00FF0000uL) +#define INTC_ICDIPR121_TINT71 (0xFF000000uL) + +#define INTC_ICDIPR122_TINT72 (0x000000FFuL) +#define INTC_ICDIPR122_TINT73 (0x0000FF00uL) +#define INTC_ICDIPR122_TINT74 (0x00FF0000uL) +#define INTC_ICDIPR122_TINT75 (0xFF000000uL) + +#define INTC_ICDIPR123_TINT76 (0x000000FFuL) +#define INTC_ICDIPR123_TINT77 (0x0000FF00uL) +#define INTC_ICDIPR123_TINT78 (0x00FF0000uL) +#define INTC_ICDIPR123_TINT79 (0xFF000000uL) + +#define INTC_ICDIPR124_TINT80 (0x000000FFuL) +#define INTC_ICDIPR124_TINT81 (0x0000FF00uL) +#define INTC_ICDIPR124_TINT82 (0x00FF0000uL) +#define INTC_ICDIPR124_TINT83 (0xFF000000uL) + +#define INTC_ICDIPR125_TINT84 (0x000000FFuL) +#define INTC_ICDIPR125_TINT85 (0x0000FF00uL) +#define INTC_ICDIPR125_TINT86 (0x00FF0000uL) +#define INTC_ICDIPR125_TINT87 (0xFF000000uL) + +#define INTC_ICDIPR126_TINT88 (0x000000FFuL) +#define INTC_ICDIPR126_TINT89 (0x0000FF00uL) +#define INTC_ICDIPR126_TINT90 (0x00FF0000uL) +#define INTC_ICDIPR126_TINT91 (0xFF000000uL) + +#define INTC_ICDIPR127_TINT92 (0x000000FFuL) +#define INTC_ICDIPR127_TINT93 (0x0000FF00uL) +#define INTC_ICDIPR127_TINT94 (0x00FF0000uL) +#define INTC_ICDIPR127_TINT95 (0xFF000000uL) + +#define INTC_ICDIPR128_TINT96 (0x000000FFuL) +#define INTC_ICDIPR128_TINT97 (0x0000FF00uL) +#define INTC_ICDIPR128_TINT98 (0x00FF0000uL) +#define INTC_ICDIPR128_TINT99 (0xFF000000uL) + +#define INTC_ICDIPR129_TINT100 (0x000000FFuL) +#define INTC_ICDIPR129_TINT101 (0x0000FF00uL) +#define INTC_ICDIPR129_TINT102 (0x00FF0000uL) +#define INTC_ICDIPR129_TINT103 (0xFF000000uL) + +#define INTC_ICDIPR130_TINT104 (0x000000FFuL) +#define INTC_ICDIPR130_TINT105 (0x0000FF00uL) +#define INTC_ICDIPR130_TINT106 (0x00FF0000uL) +#define INTC_ICDIPR130_TINT107 (0xFF000000uL) + +#define INTC_ICDIPR131_TINT108 (0x000000FFuL) +#define INTC_ICDIPR131_TINT109 (0x0000FF00uL) +#define INTC_ICDIPR131_TINT110 (0x00FF0000uL) +#define INTC_ICDIPR131_TINT111 (0xFF000000uL) + +#define INTC_ICDIPR132_TINT112 (0x000000FFuL) +#define INTC_ICDIPR132_TINT113 (0x0000FF00uL) +#define INTC_ICDIPR132_TINT114 (0x00FF0000uL) +#define INTC_ICDIPR132_TINT115 (0xFF000000uL) + +#define INTC_ICDIPR133_TINT116 (0x000000FFuL) +#define INTC_ICDIPR133_TINT117 (0x0000FF00uL) +#define INTC_ICDIPR133_TINT118 (0x00FF0000uL) +#define INTC_ICDIPR133_TINT119 (0xFF000000uL) + +#define INTC_ICDIPR134_TINT120 (0x000000FFuL) +#define INTC_ICDIPR134_TINT121 (0x0000FF00uL) +#define INTC_ICDIPR134_TINT122 (0x00FF0000uL) +#define INTC_ICDIPR134_TINT123 (0xFF000000uL) + +#define INTC_ICDIPR135_TINT124 (0x000000FFuL) +#define INTC_ICDIPR135_TINT125 (0x0000FF00uL) +#define INTC_ICDIPR135_TINT126 (0x00FF0000uL) +#define INTC_ICDIPR135_TINT127 (0xFF000000uL) + +#define INTC_ICDIPR136_TINT128 (0x000000FFuL) +#define INTC_ICDIPR136_TINT129 (0x0000FF00uL) +#define INTC_ICDIPR136_TINT130 (0x00FF0000uL) +#define INTC_ICDIPR136_TINT131 (0xFF000000uL) + +#define INTC_ICDIPR137_TINT132 (0x000000FFuL) +#define INTC_ICDIPR137_TINT133 (0x0000FF00uL) +#define INTC_ICDIPR137_TINT134 (0x00FF0000uL) +#define INTC_ICDIPR137_TINT135 (0xFF000000uL) + +#define INTC_ICDIPR138_TINT136 (0x000000FFuL) +#define INTC_ICDIPR138_TINT137 (0x0000FF00uL) +#define INTC_ICDIPR138_TINT138 (0x00FF0000uL) +#define INTC_ICDIPR138_TINT139 (0xFF000000uL) + +#define INTC_ICDIPR139_TINT140 (0x000000FFuL) +#define INTC_ICDIPR139_TINT141 (0x0000FF00uL) +#define INTC_ICDIPR139_TINT142 (0x00FF0000uL) +#define INTC_ICDIPR139_TINT143 (0xFF000000uL) + +#define INTC_ICDIPR140_TINT144 (0x000000FFuL) +#define INTC_ICDIPR140_TINT145 (0x0000FF00uL) +#define INTC_ICDIPR140_TINT146 (0x00FF0000uL) +#define INTC_ICDIPR140_TINT147 (0xFF000000uL) + +#define INTC_ICDIPR141_TINT148 (0x000000FFuL) +#define INTC_ICDIPR141_TINT149 (0x0000FF00uL) +#define INTC_ICDIPR141_TINT150 (0x00FF0000uL) +#define INTC_ICDIPR141_TINT151 (0xFF000000uL) + +#define INTC_ICDIPR142_TINT152 (0x000000FFuL) +#define INTC_ICDIPR142_TINT153 (0x0000FF00uL) +#define INTC_ICDIPR142_TINT154 (0x00FF0000uL) +#define INTC_ICDIPR142_TINT155 (0xFF000000uL) + +#define INTC_ICDIPR143_TINT156 (0x000000FFuL) +#define INTC_ICDIPR143_TINT157 (0x0000FF00uL) +#define INTC_ICDIPR143_TINT158 (0x00FF0000uL) +#define INTC_ICDIPR143_TINT159 (0xFF000000uL) + +#define INTC_ICDIPR144_TINT160 (0x000000FFuL) +#define INTC_ICDIPR144_TINT161 (0x0000FF00uL) +#define INTC_ICDIPR144_TINT162 (0x00FF0000uL) +#define INTC_ICDIPR144_TINT163 (0xFF000000uL) + +#define INTC_ICDIPR145_TINT164 (0x000000FFuL) +#define INTC_ICDIPR145_TINT165 (0x0000FF00uL) +#define INTC_ICDIPR145_TINT166 (0x00FF0000uL) +#define INTC_ICDIPR145_TINT167 (0xFF000000uL) + +#define INTC_ICDIPR146_TINT168 (0x000000FFuL) +#define INTC_ICDIPR146_TINT169 (0x0000FF00uL) +#define INTC_ICDIPR146_TINT170 (0x00FF0000uL) + +#define INTC_ICDIPTR0_SW0 (0x000000FFuL) +#define INTC_ICDIPTR0_SW1 (0x0000FF00uL) +#define INTC_ICDIPTR0_SW2 (0x00FF0000uL) +#define INTC_ICDIPTR0_SW3 (0xFF000000uL) + +#define INTC_ICDIPTR1_SW4 (0x000000FFuL) +#define INTC_ICDIPTR1_SW5 (0x0000FF00uL) +#define INTC_ICDIPTR1_SW6 (0x00FF0000uL) +#define INTC_ICDIPTR1_SW7 (0xFF000000uL) + +#define INTC_ICDIPTR2_SW8 (0x000000FFuL) +#define INTC_ICDIPTR2_SW9 (0x0000FF00uL) +#define INTC_ICDIPTR2_SW10 (0x00FF0000uL) +#define INTC_ICDIPTR2_SW11 (0xFF000000uL) + +#define INTC_ICDIPTR3_SW12 (0x000000FFuL) +#define INTC_ICDIPTR3_SW13 (0x0000FF00uL) +#define INTC_ICDIPTR3_SW14 (0x00FF0000uL) +#define INTC_ICDIPTR3_SW15 (0xFF000000uL) + +#define INTC_ICDIPTR4_PMUIRQ0 (0x000000FFuL) +#define INTC_ICDIPTR4_COMMRX0 (0x0000FF00uL) +#define INTC_ICDIPTR4_COMMTX0 (0x00FF0000uL) +#define INTC_ICDIPTR4_CTIIRQ0 (0xFF000000uL) + +#define INTC_ICDIPTR8_IRQ0 (0x000000FFuL) +#define INTC_ICDIPTR8_IRQ1 (0x0000FF00uL) +#define INTC_ICDIPTR8_IRQ2 (0x00FF0000uL) +#define INTC_ICDIPTR8_IRQ3 (0xFF000000uL) + +#define INTC_ICDIPTR9_IRQ4 (0x000000FFuL) +#define INTC_ICDIPTR9_IRQ5 (0x0000FF00uL) +#define INTC_ICDIPTR9_IRQ6 (0x00FF0000uL) +#define INTC_ICDIPTR9_IRQ7 (0xFF000000uL) + +#define INTC_ICDIPTR10_PL310ERR (0x000000FFuL) +#define INTC_ICDIPTR10_DMAINT0 (0x0000FF00uL) +#define INTC_ICDIPTR10_DMAINT1 (0x00FF0000uL) +#define INTC_ICDIPTR10_DMAINT2 (0xFF000000uL) + +#define INTC_ICDIPTR11_DMAINT3 (0x000000FFuL) +#define INTC_ICDIPTR11_DMAINT4 (0x0000FF00uL) +#define INTC_ICDIPTR11_DMAINT5 (0x00FF0000uL) +#define INTC_ICDIPTR11_DMAINT6 (0xFF000000uL) + +#define INTC_ICDIPTR12_DMAINT7 (0x000000FFuL) +#define INTC_ICDIPTR12_DMAINT8 (0x0000FF00uL) +#define INTC_ICDIPTR12_DMAINT9 (0x00FF0000uL) +#define INTC_ICDIPTR12_DMAINT10 (0xFF000000uL) + +#define INTC_ICDIPTR13_DMAINT11 (0x000000FFuL) +#define INTC_ICDIPTR13_DMAINT12 (0x0000FF00uL) +#define INTC_ICDIPTR13_DMAINT13 (0x00FF0000uL) +#define INTC_ICDIPTR13_DMAINT14 (0xFF000000uL) + +#define INTC_ICDIPTR14_DMAINT15 (0x000000FFuL) +#define INTC_ICDIPTR14_DMAERR (0x0000FF00uL) + +#define INTC_ICDIPTR18_USBI0 (0x0000FF00uL) +#define INTC_ICDIPTR18_USBI1 (0x00FF0000uL) +#define INTC_ICDIPTR18_S0_VI_VSYNC0 (0xFF000000uL) + +#define INTC_ICDIPTR19_S0_LO_VSYNC0 (0x000000FFuL) +#define INTC_ICDIPTR19_S0_VSYNCERR0 (0x0000FF00uL) +#define INTC_ICDIPTR19_GR3_VLINE0 (0x00FF0000uL) +#define INTC_ICDIPTR19_S0_VFIELD0 (0xFF000000uL) + +#define INTC_ICDIPTR20_IV1_VBUFERR0 (0x000000FFuL) +#define INTC_ICDIPTR20_IV3_VBUFERR0 (0x0000FF00uL) +#define INTC_ICDIPTR20_IV5_VBUFERR0 (0x00FF0000uL) +#define INTC_ICDIPTR20_IV6_VBUFERR0 (0xFF000000uL) + +#define INTC_ICDIPTR21_S0_WLINE0 (0x000000FFuL) +#define INTC_ICDIPTR21_S1_VI_VSYNC0 (0x0000FF00uL) +#define INTC_ICDIPTR21_S1_LO_VSYNC0 (0x00FF0000uL) +#define INTC_ICDIPTR21_S1_VSYNCERR0 (0xFF000000uL) + +#define INTC_ICDIPTR22_S1_VFIELD0 (0x000000FFuL) +#define INTC_ICDIPTR22_IV2_VBUFERR0 (0x0000FF00uL) +#define INTC_ICDIPTR22_IV4_VBUFERR0 (0x00FF0000uL) +#define INTC_ICDIPTR22_S1_WLINE0 (0xFF000000uL) + +#define INTC_ICDIPTR23_OIR_VI_VSYNC0 (0x000000FFuL) +#define INTC_ICDIPTR23_OIR_LO_VSYNC0 (0x0000FF00uL) +#define INTC_ICDIPTR23_OIR_VSYNCERR0 (0x00FF0000uL) +#define INTC_ICDIPTR23_OIR_VFIELD0 (0xFF000000uL) + +#define INTC_ICDIPTR24_IV7_VBUFERR0 (0x000000FFuL) +#define INTC_ICDIPTR24_IV8_VBUFERR0 (0x0000FF00uL) +#define INTC_ICDIPTR24_S0_VI_VSYNC1 (0xFF000000uL) + +#define INTC_ICDIPTR25_S0_LO_VSYNC1 (0x000000FFuL) +#define INTC_ICDIPTR25_S0_VSYNCERR1 (0x0000FF00uL) +#define INTC_ICDIPTR25_GR3_VLINE1 (0x00FF0000uL) +#define INTC_ICDIPTR25_S0_VFIELD1 (0xFF000000uL) + +#define INTC_ICDIPTR26_IV1_VBUFERR1 (0x000000FFuL) +#define INTC_ICDIPTR26_IV3_VBUFERR1 (0x0000FF00uL) +#define INTC_ICDIPTR26_IV5_VBUFERR1 (0x00FF0000uL) +#define INTC_ICDIPTR26_IV6_VBUFERR1 (0xFF000000uL) + +#define INTC_ICDIPTR27_S0_WLINE1 (0x000000FFuL) +#define INTC_ICDIPTR27_S1_VI_VSYNC1 (0x0000FF00uL) +#define INTC_ICDIPTR27_S1_LO_VSYNC1 (0x00FF0000uL) +#define INTC_ICDIPTR27_S1_VSYNCERR1 (0xFF000000uL) + +#define INTC_ICDIPTR28_S1_VFIELD1 (0x000000FFuL) +#define INTC_ICDIPTR28_IV2_VBUFERR1 (0x0000FF00uL) +#define INTC_ICDIPTR28_IV4_VBUFERR1 (0x00FF0000uL) +#define INTC_ICDIPTR28_S1_WLINE1 (0xFF000000uL) + +#define INTC_ICDIPTR29_OIR_VI_VSYNC1 (0x000000FFuL) +#define INTC_ICDIPTR29_OIR_LO_VSYNC1 (0x0000FF00uL) +#define INTC_ICDIPTR29_OIR_VLINE1 (0x00FF0000uL) +#define INTC_ICDIPTR29_OIR_VFIELD1 (0xFF000000uL) + +#define INTC_ICDIPTR30_IV7_VBUFERR1 (0x000000FFuL) +#define INTC_ICDIPTR30_IV8_VBUFERR1 (0x0000FF00uL) +#define INTC_ICDIPTR30_IMRDI (0xFF000000uL) + +#define INTC_ICDIPTR31_IMR2I0 (0x000000FFuL) +#define INTC_ICDIPTR31_IMR2I1 (0x0000FF00uL) +#define INTC_ICDIPTR31_JEDI (0x00FF0000uL) +#define INTC_ICDIPTR31_JDTI (0xFF000000uL) + +#define INTC_ICDIPTR32_CMP0 (0x000000FFuL) +#define INTC_ICDIPTR32_CMP1 (0x0000FF00uL) +#define INTC_ICDIPTR32_INT0 (0x00FF0000uL) +#define INTC_ICDIPTR32_INT1 (0xFF000000uL) + +#define INTC_ICDIPTR33_INT2 (0x000000FFuL) +#define INTC_ICDIPTR33_INT3 (0x0000FF00uL) +#define INTC_ICDIPTR33_OSTM0TINT (0x00FF0000uL) +#define INTC_ICDIPTR33_OSTM1TINT (0xFF000000uL) + +#define INTC_ICDIPTR34_CMI (0x000000FFuL) +#define INTC_ICDIPTR34_WTOUT (0x0000FF00uL) +#define INTC_ICDIPTR34_ITI (0x00FF0000uL) +#define INTC_ICDIPTR34_TGI0A (0xFF000000uL) + +#define INTC_ICDIPTR35_TGI0B (0x000000FFuL) +#define INTC_ICDIPTR35_TGI0C (0x0000FF00uL) +#define INTC_ICDIPTR35_TGI0D (0x00FF0000uL) +#define INTC_ICDIPTR35_TGI0V (0xFF000000uL) + +#define INTC_ICDIPTR36_TGI0E (0x000000FFuL) +#define INTC_ICDIPTR36_TGI0F (0x0000FF00uL) +#define INTC_ICDIPTR36_TGI1A (0x00FF0000uL) +#define INTC_ICDIPTR36_TGI1B (0xFF000000uL) + +#define INTC_ICDIPTR37_TGI1V (0x000000FFuL) +#define INTC_ICDIPTR37_TGI1U (0x0000FF00uL) +#define INTC_ICDIPTR37_TGI2A (0x00FF0000uL) +#define INTC_ICDIPTR37_TGI2B (0xFF000000uL) + +#define INTC_ICDIPTR38_TGI2V (0x000000FFuL) +#define INTC_ICDIPTR38_TGI2U (0x0000FF00uL) +#define INTC_ICDIPTR38_TGI3A (0x00FF0000uL) +#define INTC_ICDIPTR38_TGI3B (0xFF000000uL) + +#define INTC_ICDIPTR39_TGI3C (0x000000FFuL) +#define INTC_ICDIPTR39_TGI3D (0x0000FF00uL) +#define INTC_ICDIPTR39_TGI3V (0x00FF0000uL) +#define INTC_ICDIPTR39_TGI4A (0xFF000000uL) + +#define INTC_ICDIPTR40_TGI4B (0x000000FFuL) +#define INTC_ICDIPTR40_TGI4C (0x0000FF00uL) +#define INTC_ICDIPTR40_TGI4D (0x00FF0000uL) +#define INTC_ICDIPTR40_TGI4V (0xFF000000uL) + +#define INTC_ICDIPTR41_CMI1 (0x000000FFuL) +#define INTC_ICDIPTR41_CMI2 (0x0000FF00uL) +#define INTC_ICDIPTR41_SGDEI0 (0x00FF0000uL) +#define INTC_ICDIPTR41_SGDEI1 (0xFF000000uL) + +#define INTC_ICDIPTR42_SGDEI2 (0x000000FFuL) +#define INTC_ICDIPTR42_SGDEI3 (0x0000FF00uL) +#define INTC_ICDIPTR42_ADI (0x00FF0000uL) +#define INTC_ICDIPTR42_LMTI (0xFF000000uL) + +#define INTC_ICDIPTR43_SSII0 (0x000000FFuL) +#define INTC_ICDIPTR43_SSIRXI0 (0x0000FF00uL) +#define INTC_ICDIPTR43_SSITXI0 (0x00FF0000uL) +#define INTC_ICDIPTR43_SSII1 (0xFF000000uL) + +#define INTC_ICDIPTR44_SSIRXI1 (0x000000FFuL) +#define INTC_ICDIPTR44_SSITXI1 (0x0000FF00uL) +#define INTC_ICDIPTR44_SSII2 (0x00FF0000uL) +#define INTC_ICDIPTR44_SSIRTI2 (0xFF000000uL) + +#define INTC_ICDIPTR45_SSII3 (0x000000FFuL) +#define INTC_ICDIPTR45_SSIRXI3 (0x0000FF00uL) +#define INTC_ICDIPTR45_SSITXI3 (0x00FF0000uL) +#define INTC_ICDIPTR45_SSII4 (0xFF000000uL) + +#define INTC_ICDIPTR46_SSIRTI4 (0x000000FFuL) +#define INTC_ICDIPTR46_SSII5 (0x0000FF00uL) +#define INTC_ICDIPTR46_SSIRXI5 (0x00FF0000uL) +#define INTC_ICDIPTR46_SSITXI5 (0xFF000000uL) + +#define INTC_ICDIPTR47_SPDIFI (0x000000FFuL) +#define INTC_ICDIPTR47_INTIICTEI0 (0x0000FF00uL) +#define INTC_ICDIPTR47_INTIICRI0 (0x00FF0000uL) +#define INTC_ICDIPTR47_INTIICTI0 (0xFF000000uL) + +#define INTC_ICDIPTR48_INTIICSPI0 (0x000000FFuL) +#define INTC_ICDIPTR48_INTIICSTI0 (0x0000FF00uL) +#define INTC_ICDIPTR48_INTIICNAKI0 (0x00FF0000uL) +#define INTC_ICDIPTR48_INTIICALI0 (0xFF000000uL) + +#define INTC_ICDIPTR49_INTIICTMOI0 (0x000000FFuL) +#define INTC_ICDIPTR49_INTIICTEI1 (0x0000FF00uL) +#define INTC_ICDIPTR49_INTIICRI1 (0x00FF0000uL) +#define INTC_ICDIPTR49_INTIICTI1 (0xFF000000uL) + +#define INTC_ICDIPTR50_INTIICSPI1 (0x000000FFuL) +#define INTC_ICDIPTR50_INTIICSTI1 (0x0000FF00uL) +#define INTC_ICDIPTR50_INTIICNAKI1 (0x00FF0000uL) +#define INTC_ICDIPTR50_INTIICALI1 (0xFF000000uL) + +#define INTC_ICDIPTR51_INTIICTMOI1 (0x000000FFuL) +#define INTC_ICDIPTR51_INTIICTEI2 (0x0000FF00uL) +#define INTC_ICDIPTR51_INTIICRI2 (0x00FF0000uL) +#define INTC_ICDIPTR51_INTIICTI2 (0xFF000000uL) + +#define INTC_ICDIPTR52_INTIICSPI2 (0x000000FFuL) +#define INTC_ICDIPTR52_INTIICSTI2 (0x0000FF00uL) +#define INTC_ICDIPTR52_INTIICNAKI2 (0x00FF0000uL) +#define INTC_ICDIPTR52_INTIICALI2 (0xFF000000uL) + +#define INTC_ICDIPTR53_INTIICTMOI2 (0x000000FFuL) +#define INTC_ICDIPTR53_INTIICTEI3 (0x0000FF00uL) +#define INTC_ICDIPTR53_INTIICRI3 (0x00FF0000uL) +#define INTC_ICDIPTR53_INTIICTI3 (0xFF000000uL) + +#define INTC_ICDIPTR54_INTIICSPI3 (0x000000FFuL) +#define INTC_ICDIPTR54_INTIICSTI3 (0x0000FF00uL) +#define INTC_ICDIPTR54_INTIICNAKI3 (0x00FF0000uL) +#define INTC_ICDIPTR54_INTIICALI3 (0xFF000000uL) + +#define INTC_ICDIPTR55_INTIICTMOI3 (0x000000FFuL) +#define INTC_ICDIPTR55_BRI0 (0x0000FF00uL) +#define INTC_ICDIPTR55_ERI0 (0x00FF0000uL) +#define INTC_ICDIPTR55_RXI0 (0xFF000000uL) + +#define INTC_ICDIPTR56_TXI0 (0x000000FFuL) +#define INTC_ICDIPTR56_BRI1 (0x0000FF00uL) +#define INTC_ICDIPTR56_ERI1 (0x00FF0000uL) +#define INTC_ICDIPTR56_RXI1 (0xFF000000uL) + +#define INTC_ICDIPTR57_TXI1 (0x000000FFuL) +#define INTC_ICDIPTR57_BRI2 (0x0000FF00uL) +#define INTC_ICDIPTR57_ERI2 (0x00FF0000uL) +#define INTC_ICDIPTR57_RXI2 (0xFF000000uL) + +#define INTC_ICDIPTR58_TXI2 (0x000000FFuL) +#define INTC_ICDIPTR58_BRI3 (0x0000FF00uL) +#define INTC_ICDIPTR58_ERI3 (0x00FF0000uL) +#define INTC_ICDIPTR58_RXI3 (0xFF000000uL) + +#define INTC_ICDIPTR59_TXI3 (0x000000FFuL) +#define INTC_ICDIPTR59_BRI4 (0x0000FF00uL) +#define INTC_ICDIPTR59_ERI4 (0x00FF0000uL) +#define INTC_ICDIPTR59_RXI4 (0xFF000000uL) + +#define INTC_ICDIPTR60_TXI4 (0x000000FFuL) +#define INTC_ICDIPTR60_BRI5 (0x0000FF00uL) +#define INTC_ICDIPTR60_ERI5 (0x00FF0000uL) +#define INTC_ICDIPTR60_RXI5 (0xFF000000uL) + +#define INTC_ICDIPTR61_TXI5 (0x000000FFuL) +#define INTC_ICDIPTR61_BRI6 (0x0000FF00uL) +#define INTC_ICDIPTR61_ERI6 (0x00FF0000uL) +#define INTC_ICDIPTR61_RXI6 (0xFF000000uL) + +#define INTC_ICDIPTR62_TXI6 (0x000000FFuL) +#define INTC_ICDIPTR62_BRI7 (0x0000FF00uL) +#define INTC_ICDIPTR62_ERI7 (0x00FF0000uL) +#define INTC_ICDIPTR62_RXI7 (0xFF000000uL) + +#define INTC_ICDIPTR63_TXI7 (0x000000FFuL) +#define INTC_ICDIPTR63_INTRCANGERR (0x0000FF00uL) +#define INTC_ICDIPTR63_INTRCANGRECC (0x00FF0000uL) +#define INTC_ICDIPTR63_INTRCAN0REC (0xFF000000uL) + +#define INTC_ICDIPTR64_INTRCAN0ERR (0x000000FFuL) +#define INTC_ICDIPTR64_INTRCAN0TRX (0x0000FF00uL) +#define INTC_ICDIPTR64_INTRCAN1REC (0x00FF0000uL) +#define INTC_ICDIPTR64_INTRCAN1ERR (0xFF000000uL) + +#define INTC_ICDIPTR65_INTRCAN1TRX (0x000000FFuL) +#define INTC_ICDIPTR65_INTRCAN2REC (0x0000FF00uL) +#define INTC_ICDIPTR65_INTRCAN2ERR (0x00FF0000uL) +#define INTC_ICDIPTR65_INTRCAN2TRX (0xFF000000uL) + +#define INTC_ICDIPTR66_INTRCAN3REC (0x000000FFuL) +#define INTC_ICDIPTR66_INTRCAN3ERR (0x0000FF00uL) +#define INTC_ICDIPTR66_INTRCAN3TRX (0x00FF0000uL) +#define INTC_ICDIPTR66_INTRCAN4REC (0xFF000000uL) + +#define INTC_ICDIPTR67_INTRCAN4ERR (0x000000FFuL) +#define INTC_ICDIPTR67_INTRCAN4TRX (0x0000FF00uL) +#define INTC_ICDIPTR67_SPEI0 (0x00FF0000uL) +#define INTC_ICDIPTR67_SPRI0 (0xFF000000uL) + +#define INTC_ICDIPTR68_SPTI0 (0x000000FFuL) +#define INTC_ICDIPTR68_SPEI1 (0x0000FF00uL) +#define INTC_ICDIPTR68_SPRI1 (0x00FF0000uL) +#define INTC_ICDIPTR68_SPTI1 (0xFF000000uL) + +#define INTC_ICDIPTR69_SPEI2 (0x000000FFuL) +#define INTC_ICDIPTR69_SPRI2 (0x0000FF00uL) +#define INTC_ICDIPTR69_SPTI2 (0x00FF0000uL) +#define INTC_ICDIPTR69_SPEI3 (0xFF000000uL) + +#define INTC_ICDIPTR70_SPRI3 (0x000000FFuL) +#define INTC_ICDIPTR70_SPTI3 (0x0000FF00uL) +#define INTC_ICDIPTR70_SPEI4 (0x00FF0000uL) +#define INTC_ICDIPTR70_SPRI4 (0xFF000000uL) + +#define INTC_ICDIPTR71_SPTI4 (0x000000FFuL) +#define INTC_ICDIPTR71_IEBBTD (0x0000FF00uL) +#define INTC_ICDIPTR71_IEBBTERR (0x00FF0000uL) +#define INTC_ICDIPTR71_IEBBTSTA (0xFF000000uL) + +#define INTC_ICDIPTR72_IEBBTV (0x000000FFuL) +#define INTC_ICDIPTR72_ISY (0x0000FF00uL) +#define INTC_ICDIPTR72_IERR (0x00FF0000uL) +#define INTC_ICDIPTR72_ITARG (0xFF000000uL) + +#define INTC_ICDIPTR73_ISEC (0x000000FFuL) +#define INTC_ICDIPTR73_IBUF (0x0000FF00uL) +#define INTC_ICDIPTR73_IREADY (0x00FF0000uL) +#define INTC_ICDIPTR73_FLSTE (0xFF000000uL) + +#define INTC_ICDIPTR74_FLTENDI (0x000000FFuL) +#define INTC_ICDIPTR74_FLTREQ0I (0x0000FF00uL) +#define INTC_ICDIPTR74_FLTREQ1I (0x00FF0000uL) +#define INTC_ICDIPTR74_MMC0 (0xFF000000uL) + +#define INTC_ICDIPTR75_MMC1 (0x000000FFuL) +#define INTC_ICDIPTR75_MMC2 (0x0000FF00uL) +#define INTC_ICDIPTR75_SDHI0_3 (0x00FF0000uL) +#define INTC_ICDIPTR75_SDHI0_0 (0xFF000000uL) + +#define INTC_ICDIPTR76_SDHI0_1 (0x000000FFuL) +#define INTC_ICDIPTR76_SDHI1_3 (0x0000FF00uL) +#define INTC_ICDIPTR76_SDHI1_0 (0x00FF0000uL) +#define INTC_ICDIPTR76_SDHI1_1 (0xFF000000uL) + +#define INTC_ICDIPTR77_ARM (0x000000FFuL) +#define INTC_ICDIPTR77_PRD (0x0000FF00uL) +#define INTC_ICDIPTR77_CUP (0x00FF0000uL) +#define INTC_ICDIPTR77_SCUAI0 (0xFF000000uL) + +#define INTC_ICDIPTR78_SCUAI1 (0x000000FFuL) +#define INTC_ICDIPTR78_SCUFDI0 (0x0000FF00uL) +#define INTC_ICDIPTR78_SCUFDI1 (0x00FF0000uL) +#define INTC_ICDIPTR78_SCUFDI2 (0xFF000000uL) + +#define INTC_ICDIPTR79_SCUFDI3 (0x000000FFuL) +#define INTC_ICDIPTR79_SCUFUI0 (0x0000FF00uL) +#define INTC_ICDIPTR79_SCUFUI1 (0x00FF0000uL) +#define INTC_ICDIPTR79_SCUFUI2 (0xFF000000uL) + +#define INTC_ICDIPTR80_SCUFUI3 (0x000000FFuL) +#define INTC_ICDIPTR80_SCUDVI0 (0x0000FF00uL) +#define INTC_ICDIPTR80_SCUDVI1 (0x00FF0000uL) +#define INTC_ICDIPTR80_SCUDVI2 (0xFF000000uL) + +#define INTC_ICDIPTR81_SCUDVI3 (0x000000FFuL) +#define INTC_ICDIPTR81_MLB_CINT (0x0000FF00uL) +#define INTC_ICDIPTR81_MLB_SINT (0x00FF0000uL) +#define INTC_ICDIPTR81_DRC0 (0xFF000000uL) + +#define INTC_ICDIPTR82_DRC1 (0x000000FFuL) +#define INTC_ICDIPTR82_LINI0_INT_T (0xFF000000uL) + +#define INTC_ICDIPTR83_LINI0_INT_R (0x000000FFuL) +#define INTC_ICDIPTR83_LINI0_INT_S (0x0000FF00uL) +#define INTC_ICDIPTR83_LINI0_INT_M (0x00FF0000uL) +#define INTC_ICDIPTR83_LINI1_INT_T (0xFF000000uL) + +#define INTC_ICDIPTR84_LINI1_INT_R (0x000000FFuL) +#define INTC_ICDIPTR84_LINI1_INT_S (0x0000FF00uL) +#define INTC_ICDIPTR84_LINI1_INT_M (0x00FF0000uL) + +#define INTC_ICDIPTR86_ERI0 (0xFF000000uL) + +#define INTC_ICDIPTR87_RXI0 (0x000000FFuL) +#define INTC_ICDIPTR87_TXI0 (0x0000FF00uL) +#define INTC_ICDIPTR87_TEI0 (0x00FF0000uL) +#define INTC_ICDIPTR87_ERI1 (0xFF000000uL) + +#define INTC_ICDIPTR88_RXI1 (0x000000FFuL) +#define INTC_ICDIPTR88_TXI1 (0x0000FF00uL) +#define INTC_ICDIPTR88_TEI1 (0x00FF0000uL) +#define INTC_ICDIPTR88_AVBI_DATA (0xFF000000uL) + +#define INTC_ICDIPTR89_AVBI_ERROR (0x000000FFuL) +#define INTC_ICDIPTR89_AVBI_MANAGE (0x0000FF00uL) +#define INTC_ICDIPTR89_AVBI_MAC (0x00FF0000uL) +#define INTC_ICDIPTR89_ETHERI (0xFF000000uL) + +#define INTC_ICDIPTR91_CEUI (0x000000FFuL) + +#define INTC_ICDIPTR95_H2XMLB_ERRINT (0x0000FF00uL) +#define INTC_ICDIPTR95_H2XIC1_ERRINT (0x00FF0000uL) +#define INTC_ICDIPTR95_X2HPERI1_ERRINT (0xFF000000uL) + +#define INTC_ICDIPTR96_X2HPERI2_ERRINT (0x000000FFuL) +#define INTC_ICDIPTR96_X2HPERI34_ERRINT (0x0000FF00uL) +#define INTC_ICDIPTR96_X2HPERI5_ERRINT (0x00FF0000uL) +#define INTC_ICDIPTR96_X2HPERI67_ERRINT (0xFF000000uL) + +#define INTC_ICDIPTR97_X2HDBGR_ERRINT (0x000000FFuL) +#define INTC_ICDIPTR97_X2HBSC_ERRINT (0x0000FF00uL) +#define INTC_ICDIPTR97_X2HSPI1_ERRINT (0x00FF0000uL) +#define INTC_ICDIPTR97_X2HSPI2_ERRINT (0xFF000000uL) + +#define INTC_ICDIPTR98_PRRI (0x000000FFuL) +#define INTC_ICDIPTR98_IFEI0 (0x0000FF00uL) +#define INTC_ICDIPTR98_OFFI0 (0x00FF0000uL) +#define INTC_ICDIPTR98_PFVEI0 (0xFF000000uL) + +#define INTC_ICDIPTR99_IFEI1 (0x000000FFuL) +#define INTC_ICDIPTR99_OFFI1 (0x0000FF00uL) +#define INTC_ICDIPTR99_PFVEI1 (0x00FF0000uL) + +#define INTC_ICDIPTR104_TINT0 (0x000000FFuL) +#define INTC_ICDIPTR104_TINT1 (0x0000FF00uL) +#define INTC_ICDIPTR104_TINT2 (0x00FF0000uL) +#define INTC_ICDIPTR104_TINT3 (0xFF000000uL) + +#define INTC_ICDIPTR105_TINT4 (0x000000FFuL) +#define INTC_ICDIPTR105_TINT5 (0x0000FF00uL) +#define INTC_ICDIPTR105_TINT6 (0x00FF0000uL) +#define INTC_ICDIPTR105_TINT7 (0xFF000000uL) + +#define INTC_ICDIPTR106_TINT8 (0x000000FFuL) +#define INTC_ICDIPTR106_TINT9 (0x0000FF00uL) +#define INTC_ICDIPTR106_TINT10 (0x00FF0000uL) +#define INTC_ICDIPTR106_TINT11 (0xFF000000uL) + +#define INTC_ICDIPTR107_TINT12 (0x000000FFuL) +#define INTC_ICDIPTR107_TINT13 (0x0000FF00uL) +#define INTC_ICDIPTR107_TINT14 (0x00FF0000uL) +#define INTC_ICDIPTR107_TINT15 (0xFF000000uL) + +#define INTC_ICDIPTR108_TINT16 (0x000000FFuL) +#define INTC_ICDIPTR108_TINT17 (0x0000FF00uL) +#define INTC_ICDIPTR108_TINT18 (0x00FF0000uL) +#define INTC_ICDIPTR108_TINT19 (0xFF000000uL) + +#define INTC_ICDIPTR109_TINT20 (0x000000FFuL) +#define INTC_ICDIPTR109_TINT21 (0x0000FF00uL) +#define INTC_ICDIPTR109_TINT22 (0x00FF0000uL) +#define INTC_ICDIPTR109_TINT23 (0xFF000000uL) + +#define INTC_ICDIPTR110_TINT24 (0x000000FFuL) +#define INTC_ICDIPTR110_TINT25 (0x0000FF00uL) +#define INTC_ICDIPTR110_TINT26 (0x00FF0000uL) +#define INTC_ICDIPTR110_TINT27 (0xFF000000uL) + +#define INTC_ICDIPTR111_TINT28 (0x000000FFuL) +#define INTC_ICDIPTR111_TINT29 (0x0000FF00uL) +#define INTC_ICDIPTR111_TINT30 (0x00FF0000uL) +#define INTC_ICDIPTR111_TINT31 (0xFF000000uL) + +#define INTC_ICDIPTR112_TINT32 (0x000000FFuL) +#define INTC_ICDIPTR112_TINT33 (0x0000FF00uL) +#define INTC_ICDIPTR112_TINT34 (0x00FF0000uL) +#define INTC_ICDIPTR112_TINT35 (0xFF000000uL) + +#define INTC_ICDIPTR113_TINT36 (0x000000FFuL) +#define INTC_ICDIPTR113_TINT37 (0x0000FF00uL) +#define INTC_ICDIPTR113_TINT38 (0x00FF0000uL) +#define INTC_ICDIPTR113_TINT39 (0xFF000000uL) + +#define INTC_ICDIPTR114_TINT40 (0x000000FFuL) +#define INTC_ICDIPTR114_TINT41 (0x0000FF00uL) +#define INTC_ICDIPTR114_TINT42 (0x00FF0000uL) +#define INTC_ICDIPTR114_TINT43 (0xFF000000uL) + +#define INTC_ICDIPTR115_TINT44 (0x000000FFuL) +#define INTC_ICDIPTR115_TINT45 (0x0000FF00uL) +#define INTC_ICDIPTR115_TINT46 (0x00FF0000uL) +#define INTC_ICDIPTR115_TINT47 (0xFF000000uL) + +#define INTC_ICDIPTR116_TINT48 (0x000000FFuL) +#define INTC_ICDIPTR116_TINT49 (0x0000FF00uL) +#define INTC_ICDIPTR116_TINT50 (0x00FF0000uL) +#define INTC_ICDIPTR116_TINT51 (0xFF000000uL) + +#define INTC_ICDIPTR117_TINT52 (0x000000FFuL) +#define INTC_ICDIPTR117_TINT53 (0x0000FF00uL) +#define INTC_ICDIPTR117_TINT54 (0x00FF0000uL) +#define INTC_ICDIPTR117_TINT55 (0xFF000000uL) + +#define INTC_ICDIPTR118_TINT56 (0x000000FFuL) +#define INTC_ICDIPTR118_TINT57 (0x0000FF00uL) +#define INTC_ICDIPTR118_TINT58 (0x00FF0000uL) +#define INTC_ICDIPTR118_TINT59 (0xFF000000uL) + +#define INTC_ICDIPTR119_TINT60 (0x000000FFuL) +#define INTC_ICDIPTR119_TINT61 (0x0000FF00uL) +#define INTC_ICDIPTR119_TINT62 (0x00FF0000uL) +#define INTC_ICDIPTR119_TINT63 (0xFF000000uL) + +#define INTC_ICDIPTR120_TINT64 (0x000000FFuL) +#define INTC_ICDIPTR120_TINT65 (0x0000FF00uL) +#define INTC_ICDIPTR120_TINT66 (0x00FF0000uL) +#define INTC_ICDIPTR120_TINT67 (0xFF000000uL) + +#define INTC_ICDIPTR121_TINT68 (0x000000FFuL) +#define INTC_ICDIPTR121_TINT69 (0x0000FF00uL) +#define INTC_ICDIPTR121_TINT70 (0x00FF0000uL) +#define INTC_ICDIPTR121_TINT71 (0xFF000000uL) + +#define INTC_ICDIPTR122_TINT72 (0x000000FFuL) +#define INTC_ICDIPTR122_TINT73 (0x0000FF00uL) +#define INTC_ICDIPTR122_TINT74 (0x00FF0000uL) +#define INTC_ICDIPTR122_TINT75 (0xFF000000uL) + +#define INTC_ICDIPTR123_TINT76 (0x000000FFuL) +#define INTC_ICDIPTR123_TINT77 (0x0000FF00uL) +#define INTC_ICDIPTR123_TINT78 (0x00FF0000uL) +#define INTC_ICDIPTR123_TINT79 (0xFF000000uL) + +#define INTC_ICDIPTR124_TINT80 (0x000000FFuL) +#define INTC_ICDIPTR124_TINT81 (0x0000FF00uL) +#define INTC_ICDIPTR124_TINT82 (0x00FF0000uL) +#define INTC_ICDIPTR124_TINT83 (0xFF000000uL) + +#define INTC_ICDIPTR125_TINT84 (0x000000FFuL) +#define INTC_ICDIPTR125_TINT85 (0x0000FF00uL) +#define INTC_ICDIPTR125_TINT86 (0x00FF0000uL) +#define INTC_ICDIPTR125_TINT87 (0xFF000000uL) + +#define INTC_ICDIPTR126_TINT88 (0x000000FFuL) +#define INTC_ICDIPTR126_TINT89 (0x0000FF00uL) +#define INTC_ICDIPTR126_TINT90 (0x00FF0000uL) +#define INTC_ICDIPTR126_TINT91 (0xFF000000uL) + +#define INTC_ICDIPTR127_TINT92 (0x000000FFuL) +#define INTC_ICDIPTR127_TINT93 (0x0000FF00uL) +#define INTC_ICDIPTR127_TINT94 (0x00FF0000uL) +#define INTC_ICDIPTR127_TINT95 (0xFF000000uL) + +#define INTC_ICDIPTR128_TINT96 (0x000000FFuL) +#define INTC_ICDIPTR128_TINT97 (0x0000FF00uL) +#define INTC_ICDIPTR128_TINT98 (0x00FF0000uL) +#define INTC_ICDIPTR128_TINT99 (0xFF000000uL) + +#define INTC_ICDIPTR129_TINT100 (0x000000FFuL) +#define INTC_ICDIPTR129_TINT101 (0x0000FF00uL) +#define INTC_ICDIPTR129_TINT102 (0x00FF0000uL) +#define INTC_ICDIPTR129_TINT103 (0xFF000000uL) + +#define INTC_ICDIPTR130_TINT104 (0x000000FFuL) +#define INTC_ICDIPTR130_TINT105 (0x0000FF00uL) +#define INTC_ICDIPTR130_TINT106 (0x00FF0000uL) +#define INTC_ICDIPTR130_TINT107 (0xFF000000uL) + +#define INTC_ICDIPTR131_TINT108 (0x000000FFuL) +#define INTC_ICDIPTR131_TINT109 (0x0000FF00uL) +#define INTC_ICDIPTR131_TINT110 (0x00FF0000uL) +#define INTC_ICDIPTR131_TINT111 (0xFF000000uL) + +#define INTC_ICDIPTR132_TINT112 (0x000000FFuL) +#define INTC_ICDIPTR132_TINT113 (0x0000FF00uL) +#define INTC_ICDIPTR132_TINT114 (0x00FF0000uL) +#define INTC_ICDIPTR132_TINT115 (0xFF000000uL) + +#define INTC_ICDIPTR133_TINT116 (0x000000FFuL) +#define INTC_ICDIPTR133_TINT117 (0x0000FF00uL) +#define INTC_ICDIPTR133_TINT118 (0x00FF0000uL) +#define INTC_ICDIPTR133_TINT119 (0xFF000000uL) + +#define INTC_ICDIPTR134_TINT120 (0x000000FFuL) +#define INTC_ICDIPTR134_TINT121 (0x0000FF00uL) +#define INTC_ICDIPTR134_TINT122 (0x00FF0000uL) +#define INTC_ICDIPTR134_TINT123 (0xFF000000uL) + +#define INTC_ICDIPTR135_TINT124 (0x000000FFuL) +#define INTC_ICDIPTR135_TINT125 (0x0000FF00uL) +#define INTC_ICDIPTR135_TINT126 (0x00FF0000uL) +#define INTC_ICDIPTR135_TINT127 (0xFF000000uL) + +#define INTC_ICDIPTR136_TINT128 (0x000000FFuL) +#define INTC_ICDIPTR136_TINT129 (0x0000FF00uL) +#define INTC_ICDIPTR136_TINT130 (0x00FF0000uL) +#define INTC_ICDIPTR136_TINT131 (0xFF000000uL) + +#define INTC_ICDIPTR137_TINT132 (0x000000FFuL) +#define INTC_ICDIPTR137_TINT133 (0x0000FF00uL) +#define INTC_ICDIPTR137_TINT134 (0x00FF0000uL) +#define INTC_ICDIPTR137_TINT135 (0xFF000000uL) + +#define INTC_ICDIPTR138_TINT136 (0x000000FFuL) +#define INTC_ICDIPTR138_TINT137 (0x0000FF00uL) +#define INTC_ICDIPTR138_TINT138 (0x00FF0000uL) +#define INTC_ICDIPTR138_TINT139 (0xFF000000uL) + +#define INTC_ICDIPTR139_TINT140 (0x000000FFuL) +#define INTC_ICDIPTR139_TINT141 (0x0000FF00uL) +#define INTC_ICDIPTR139_TINT142 (0x00FF0000uL) +#define INTC_ICDIPTR139_TINT143 (0xFF000000uL) + +#define INTC_ICDIPTR140_TINT144 (0x000000FFuL) +#define INTC_ICDIPTR140_TINT145 (0x0000FF00uL) +#define INTC_ICDIPTR140_TINT146 (0x00FF0000uL) +#define INTC_ICDIPTR140_TINT147 (0xFF000000uL) + +#define INTC_ICDIPTR141_TINT148 (0x000000FFuL) +#define INTC_ICDIPTR141_TINT149 (0x0000FF00uL) +#define INTC_ICDIPTR141_TINT150 (0x00FF0000uL) +#define INTC_ICDIPTR141_TINT151 (0xFF000000uL) + +#define INTC_ICDIPTR142_TINT152 (0x000000FFuL) +#define INTC_ICDIPTR142_TINT153 (0x0000FF00uL) +#define INTC_ICDIPTR142_TINT154 (0x00FF0000uL) +#define INTC_ICDIPTR142_TINT155 (0xFF000000uL) + +#define INTC_ICDIPTR143_TINT156 (0x000000FFuL) +#define INTC_ICDIPTR143_TINT157 (0x0000FF00uL) +#define INTC_ICDIPTR143_TINT158 (0x00FF0000uL) +#define INTC_ICDIPTR143_TINT159 (0xFF000000uL) + +#define INTC_ICDIPTR144_TINT160 (0x000000FFuL) +#define INTC_ICDIPTR144_TINT161 (0x0000FF00uL) +#define INTC_ICDIPTR144_TINT162 (0x00FF0000uL) +#define INTC_ICDIPTR144_TINT163 (0xFF000000uL) + +#define INTC_ICDIPTR145_TINT164 (0x000000FFuL) +#define INTC_ICDIPTR145_TINT165 (0x0000FF00uL) +#define INTC_ICDIPTR145_TINT166 (0x00FF0000uL) +#define INTC_ICDIPTR145_TINT167 (0xFF000000uL) + +#define INTC_ICDIPTR146_TINT168 (0x000000FFuL) +#define INTC_ICDIPTR146_TINT169 (0x0000FF00uL) +#define INTC_ICDIPTR146_TINT170 (0x00FF0000uL) + +#define INTC_ICDICFR0_SW0_0 (0x00000001uL) +#define INTC_ICDICFR0_SW0_1 (0x00000002uL) +#define INTC_ICDICFR0_SW1_0 (0x00000004uL) +#define INTC_ICDICFR0_SW1_1 (0x00000008uL) +#define INTC_ICDICFR0_SW2_0 (0x00000010uL) +#define INTC_ICDICFR0_SW2_1 (0x00000020uL) +#define INTC_ICDICFR0_SW3_0 (0x00000040uL) +#define INTC_ICDICFR0_SW3_1 (0x00000080uL) +#define INTC_ICDICFR0_SW4_0 (0x00000100uL) +#define INTC_ICDICFR0_SW4_1 (0x00000200uL) +#define INTC_ICDICFR0_SW5_0 (0x00000400uL) +#define INTC_ICDICFR0_SW5_1 (0x00000800uL) +#define INTC_ICDICFR0_SW6_0 (0x00001000uL) +#define INTC_ICDICFR0_SW6_1 (0x00002000uL) +#define INTC_ICDICFR0_SW7_0 (0x00004000uL) +#define INTC_ICDICFR0_SW7_1 (0x00008000uL) +#define INTC_ICDICFR0_SW8_0 (0x00010000uL) +#define INTC_ICDICFR0_SW8_1 (0x00020000uL) +#define INTC_ICDICFR0_SW9_0 (0x00040000uL) +#define INTC_ICDICFR0_SW9_1 (0x00080000uL) +#define INTC_ICDICFR0_SW10_0 (0x00100000uL) +#define INTC_ICDICFR0_SW10_1 (0x00200000uL) +#define INTC_ICDICFR0_SW11_0 (0x00400000uL) +#define INTC_ICDICFR0_SW11_1 (0x00800000uL) +#define INTC_ICDICFR0_SW12_0 (0x01000000uL) +#define INTC_ICDICFR0_SW12_1 (0x02000000uL) +#define INTC_ICDICFR0_SW13_0 (0x04000000uL) +#define INTC_ICDICFR0_SW13_1 (0x08000000uL) +#define INTC_ICDICFR0_SW14_0 (0x10000000uL) +#define INTC_ICDICFR0_SW14_1 (0x20000000uL) +#define INTC_ICDICFR0_SW15_0 (0x40000000uL) +#define INTC_ICDICFR0_SW15_1 (0x80000000uL) + +#define INTC_ICDICFR1_PMUIRQ0_0 (0x00000001uL) +#define INTC_ICDICFR1_PMUIRQ0_1 (0x00000002uL) +#define INTC_ICDICFR1_COMMRX0_0 (0x00000004uL) +#define INTC_ICDICFR1_COMMRX0_1 (0x00000008uL) +#define INTC_ICDICFR1_COMMTX0_0 (0x00000010uL) +#define INTC_ICDICFR1_COMMTX0_1 (0x00000020uL) +#define INTC_ICDICFR1_CTIIRQ0_0 (0x00000040uL) +#define INTC_ICDICFR1_CTIIRQ0_1 (0x00000080uL) + +#define INTC_ICDICFR2_IRQ0_0 (0x00000001uL) +#define INTC_ICDICFR2_IRQ0_1 (0x00000002uL) +#define INTC_ICDICFR2_IRQ1_0 (0x00000004uL) +#define INTC_ICDICFR2_IRQ1_1 (0x00000008uL) +#define INTC_ICDICFR2_IRQ2_0 (0x00000010uL) +#define INTC_ICDICFR2_IRQ2_1 (0x00000020uL) +#define INTC_ICDICFR2_IRQ3_0 (0x00000040uL) +#define INTC_ICDICFR2_IRQ3_1 (0x00000080uL) +#define INTC_ICDICFR2_IRQ4_0 (0x00000100uL) +#define INTC_ICDICFR2_IRQ4_1 (0x00000200uL) +#define INTC_ICDICFR2_IRQ5_0 (0x00000400uL) +#define INTC_ICDICFR2_IRQ5_1 (0x00000800uL) +#define INTC_ICDICFR2_IRQ6_0 (0x00001000uL) +#define INTC_ICDICFR2_IRQ6_1 (0x00002000uL) +#define INTC_ICDICFR2_IRQ7_0 (0x00004000uL) +#define INTC_ICDICFR2_IRQ7_1 (0x00008000uL) +#define INTC_ICDICFR2_PL310ERR_0 (0x00010000uL) +#define INTC_ICDICFR2_PL310ERR_1 (0x00020000uL) +#define INTC_ICDICFR2_DMAINT0_0 (0x00040000uL) +#define INTC_ICDICFR2_DMAINT0_1 (0x00080000uL) +#define INTC_ICDICFR2_DMAINT1_0 (0x00100000uL) +#define INTC_ICDICFR2_DMAINT1_1 (0x00200000uL) +#define INTC_ICDICFR2_DMAINT2_0 (0x00400000uL) +#define INTC_ICDICFR2_DMAINT2_1 (0x00800000uL) +#define INTC_ICDICFR2_DMAINT3_0 (0x01000000uL) +#define INTC_ICDICFR2_DMAINT3_1 (0x02000000uL) +#define INTC_ICDICFR2_DMAINT4_0 (0x04000000uL) +#define INTC_ICDICFR2_DMAINT4_1 (0x08000000uL) +#define INTC_ICDICFR2_DMAINT5_0 (0x10000000uL) +#define INTC_ICDICFR2_DMAINT5_1 (0x20000000uL) +#define INTC_ICDICFR2_DMAINT6_0 (0x40000000uL) +#define INTC_ICDICFR2_DMAINT6_1 (0x80000000uL) + +#define INTC_ICDICFR3_DMAINT7_0 (0x00000001uL) +#define INTC_ICDICFR3_DMAINT7_1 (0x00000002uL) +#define INTC_ICDICFR3_DMAINT8_0 (0x00000004uL) +#define INTC_ICDICFR3_DMAINT8_1 (0x00000008uL) +#define INTC_ICDICFR3_DMAINT9_0 (0x00000010uL) +#define INTC_ICDICFR3_DMAINT9_1 (0x00000020uL) +#define INTC_ICDICFR3_DMAINT10_0 (0x00000040uL) +#define INTC_ICDICFR3_DMAINT10_1 (0x00000080uL) +#define INTC_ICDICFR3_DMAINT11_0 (0x00000100uL) +#define INTC_ICDICFR3_DMAINT11_1 (0x00000200uL) +#define INTC_ICDICFR3_DMAINT12_0 (0x00000400uL) +#define INTC_ICDICFR3_DMAINT12_1 (0x00000800uL) +#define INTC_ICDICFR3_DMAINT13_0 (0x00001000uL) +#define INTC_ICDICFR3_DMAINT13_1 (0x00002000uL) +#define INTC_ICDICFR3_DMAINT14_0 (0x00004000uL) +#define INTC_ICDICFR3_DMAINT14_1 (0x00008000uL) +#define INTC_ICDICFR3_DMAINT15_0 (0x00010000uL) +#define INTC_ICDICFR3_DMAINT15_1 (0x00020000uL) +#define INTC_ICDICFR3_DMAERR_0 (0x00040000uL) +#define INTC_ICDICFR3_DMAERR_1 (0x00080000uL) + +#define INTC_ICDICFR4_USBI0_0 (0x00040000uL) +#define INTC_ICDICFR4_USBI0_1 (0x00080000uL) +#define INTC_ICDICFR4_USBI1_0 (0x00100000uL) +#define INTC_ICDICFR4_USBI1_1 (0x00200000uL) +#define INTC_ICDICFR4_S0_VI_VSYNC0_0 (0x00400000uL) +#define INTC_ICDICFR4_S0_VI_VSYNC0_1 (0x00800000uL) +#define INTC_ICDICFR4_S0_LO_VSYNC0_0 (0x01000000uL) +#define INTC_ICDICFR4_S0_LO_VSYNC0_1 (0x02000000uL) +#define INTC_ICDICFR4_S0_VSYNCERR0_0 (0x04000000uL) +#define INTC_ICDICFR4_S0_VSYNCERR0_1 (0x08000000uL) +#define INTC_ICDICFR4_GR3_VLINE0_0 (0x10000000uL) +#define INTC_ICDICFR4_GR3_VLINE0_1 (0x20000000uL) +#define INTC_ICDICFR4_S0_VFIELD0_0 (0x40000000uL) +#define INTC_ICDICFR4_S0_VFIELD0_1 (0x80000000uL) + +#define INTC_ICDICFR5_IV1_VBUFERR0_0 (0x00000001uL) +#define INTC_ICDICFR5_IV1_VBUFERR0_1 (0x00000002uL) +#define INTC_ICDICFR5_IV3_VBUFERR0_0 (0x00000004uL) +#define INTC_ICDICFR5_IV3_VBUFERR0_1 (0x00000008uL) +#define INTC_ICDICFR5_IV5_VBUFERR0_0 (0x00000010uL) +#define INTC_ICDICFR5_IV5_VBUFERR0_1 (0x00000020uL) +#define INTC_ICDICFR5_IV6_VBUFERR0_0 (0x00000040uL) +#define INTC_ICDICFR5_IV6_VBUFERR0_1 (0x00000080uL) +#define INTC_ICDICFR5_S0_WLINE0_0 (0x00000100uL) +#define INTC_ICDICFR5_S0_WLINE0_1 (0x00000200uL) +#define INTC_ICDICFR5_S1_VI_VSYNC0_0 (0x00000400uL) +#define INTC_ICDICFR5_S1_VI_VSYNC0_1 (0x00000800uL) +#define INTC_ICDICFR5_S1_LO_VSYNC0_0 (0x00001000uL) +#define INTC_ICDICFR5_S1_LO_VSYNC0_1 (0x00002000uL) +#define INTC_ICDICFR5_S1_VSYNCERR0_0 (0x00004000uL) +#define INTC_ICDICFR5_S1_VSYNCERR0_1 (0x00008000uL) +#define INTC_ICDICFR5_S1_VFIELD0_0 (0x00010000uL) +#define INTC_ICDICFR5_S1_VFIELD0_1 (0x00020000uL) +#define INTC_ICDICFR5_IV2_VBUFERR0_0 (0x00040000uL) +#define INTC_ICDICFR5_IV2_VBUFERR0_1 (0x00080000uL) +#define INTC_ICDICFR5_IV4_VBUFERR0_0 (0x00100000uL) +#define INTC_ICDICFR5_IV4_VBUFERR0_1 (0x00200000uL) +#define INTC_ICDICFR5_S1_WLINE0_0 (0x00400000uL) +#define INTC_ICDICFR5_S1_WLINE0_1 (0x00800000uL) +#define INTC_ICDICFR5_OIR_VI_VSYNC0_0 (0x01000000uL) +#define INTC_ICDICFR5_OIR_VI_VSYNC0_1 (0x02000000uL) +#define INTC_ICDICFR5_OIR_LO_VSYNC0_0 (0x04000000uL) +#define INTC_ICDICFR5_OIR_LO_VSYNC0_1 (0x08000000uL) +#define INTC_ICDICFR5_OIR_VSYNCERR0_0 (0x10000000uL) +#define INTC_ICDICFR5_OIR_VSYNCERR0_1 (0x20000000uL) +#define INTC_ICDICFR5_OIR_VFIELD0_0 (0x40000000uL) +#define INTC_ICDICFR5_OIR_VFIELD0_1 (0x80000000uL) + +#define INTC_ICDICFR6_IV7_VBUFERR0_0 (0x00000001uL) +#define INTC_ICDICFR6_IV7_VBUFERR0_1 (0x00000002uL) +#define INTC_ICDICFR6_IV8_VBUFERR0_0 (0x00000004uL) +#define INTC_ICDICFR6_IV8_VBUFERR0_1 (0x00000008uL) +#define INTC_ICDICFR6_S0_VI_VSYNC1_0 (0x00000040uL) +#define INTC_ICDICFR6_S0_VI_VSYNC1_1 (0x00000080uL) +#define INTC_ICDICFR6_S0_LO_VSYNC1_0 (0x00000100uL) +#define INTC_ICDICFR6_S0_LO_VSYNC1_1 (0x00000200uL) +#define INTC_ICDICFR6_S0_VSYNCERR1_0 (0x00000400uL) +#define INTC_ICDICFR6_S0_VSYNCERR1_1 (0x00000800uL) +#define INTC_ICDICFR6_GR3_VLINE1_0 (0x00001000uL) +#define INTC_ICDICFR6_GR3_VLINE1_1 (0x00002000uL) +#define INTC_ICDICFR6_S0_VFIELD1_0 (0x00004000uL) +#define INTC_ICDICFR6_S0_VFIELD1_1 (0x00008000uL) +#define INTC_ICDICFR6_IV1_VBUFERR1_0 (0x00010000uL) +#define INTC_ICDICFR6_IV1_VBUFERR1_1 (0x00020000uL) +#define INTC_ICDICFR6_IV3_VBUFERR1_0 (0x00040000uL) +#define INTC_ICDICFR6_IV3_VBUFERR1_1 (0x00080000uL) +#define INTC_ICDICFR6_IV5_VBUFERR1_0 (0x00100000uL) +#define INTC_ICDICFR6_IV5_VBUFERR1_1 (0x00200000uL) +#define INTC_ICDICFR6_IV6_VBUFERR1_0 (0x00400000uL) +#define INTC_ICDICFR6_IV6_VBUFERR1_1 (0x00800000uL) +#define INTC_ICDICFR6_S0_WLINE1_0 (0x01000000uL) +#define INTC_ICDICFR6_S0_WLINE1_1 (0x02000000uL) +#define INTC_ICDICFR6_S1_VI_VSYNC1_0 (0x04000000uL) +#define INTC_ICDICFR6_S1_VI_VSYNC1_1 (0x08000000uL) +#define INTC_ICDICFR6_S1_LO_VSYNC1_0 (0x10000000uL) +#define INTC_ICDICFR6_S1_LO_VSYNC1_1 (0x20000000uL) +#define INTC_ICDICFR6_S1_VSYNCERR1_0 (0x40000000uL) +#define INTC_ICDICFR6_S1_VSYNCERR1_1 (0x80000000uL) + +#define INTC_ICDICFR7_S1_VFIELD1_0 (0x00000001uL) +#define INTC_ICDICFR7_S1_VFIELD1_1 (0x00000002uL) +#define INTC_ICDICFR7_IV2_VBUFERR1_0 (0x00000004uL) +#define INTC_ICDICFR7_IV2_VBUFERR1_1 (0x00000008uL) +#define INTC_ICDICFR7_IV4_VBUFERR1_0 (0x00000010uL) +#define INTC_ICDICFR7_IV4_VBUFERR1_1 (0x00000020uL) +#define INTC_ICDICFR7_S1_WLINE1_0 (0x00000040uL) +#define INTC_ICDICFR7_S1_WLINE1_1 (0x00000080uL) +#define INTC_ICDICFR7_OIR_VI_VSYNC1_0 (0x00000100uL) +#define INTC_ICDICFR7_OIR_VI_VSYNC1_1 (0x00000200uL) +#define INTC_ICDICFR7_OIR_LO_VSYNC1_0 (0x00000400uL) +#define INTC_ICDICFR7_OIR_LO_VSYNC1_1 (0x00000800uL) +#define INTC_ICDICFR7_OIR_VLINE1_0 (0x00001000uL) +#define INTC_ICDICFR7_OIR_VLINE1_1 (0x00002000uL) +#define INTC_ICDICFR7_OIR_VFIELD1_0 (0x00004000uL) +#define INTC_ICDICFR7_OIR_VFIELD1_1 (0x00008000uL) +#define INTC_ICDICFR7_IV7_VBUFERR1_0 (0x00010000uL) +#define INTC_ICDICFR7_IV7_VBUFERR1_1 (0x00020000uL) +#define INTC_ICDICFR7_IV8_VBUFERR1_0 (0x00040000uL) +#define INTC_ICDICFR7_IV8_VBUFERR1_1 (0x00080000uL) +#define INTC_ICDICFR7_IMRDI_0 (0x00400000uL) +#define INTC_ICDICFR7_IMRDI_1 (0x00800000uL) +#define INTC_ICDICFR7_IMR2I0_0 (0x01000000uL) +#define INTC_ICDICFR7_IMR2I0_1 (0x02000000uL) +#define INTC_ICDICFR7_IMR2I1_0 (0x04000000uL) +#define INTC_ICDICFR7_IMR2I1_1 (0x08000000uL) +#define INTC_ICDICFR7_JEDI_0 (0x10000000uL) +#define INTC_ICDICFR7_JEDI_1 (0x20000000uL) +#define INTC_ICDICFR7_JDTI_0 (0x40000000uL) +#define INTC_ICDICFR7_JDTI_1 (0x80000000uL) + +#define INTC_ICDICFR8_CMP0_0 (0x00000001uL) +#define INTC_ICDICFR8_CMP0_1 (0x00000002uL) +#define INTC_ICDICFR8_CMP1_0 (0x00000004uL) +#define INTC_ICDICFR8_CMP1_1 (0x00000008uL) +#define INTC_ICDICFR8_INT0_0 (0x00000010uL) +#define INTC_ICDICFR8_INT0_1 (0x00000020uL) +#define INTC_ICDICFR8_INT1_0 (0x00000040uL) +#define INTC_ICDICFR8_INT1_1 (0x00000080uL) +#define INTC_ICDICFR8_INT2_0 (0x00000100uL) +#define INTC_ICDICFR8_INT2_1 (0x00000200uL) +#define INTC_ICDICFR8_INT3_0 (0x00000400uL) +#define INTC_ICDICFR8_INT3_1 (0x00000800uL) +#define INTC_ICDICFR8_OSTM0TINT_0 (0x00001000uL) +#define INTC_ICDICFR8_OSTM0TINT_1 (0x00002000uL) +#define INTC_ICDICFR8_OSTM1TINT_0 (0x00004000uL) +#define INTC_ICDICFR8_OSTM1TINT_1 (0x00008000uL) +#define INTC_ICDICFR8_CMI_0 (0x00010000uL) +#define INTC_ICDICFR8_CMI_1 (0x00020000uL) +#define INTC_ICDICFR8_WTOUT_0 (0x00040000uL) +#define INTC_ICDICFR8_WTOUT_1 (0x00080000uL) +#define INTC_ICDICFR8_ITI_0 (0x00100000uL) +#define INTC_ICDICFR8_ITI_1 (0x00200000uL) +#define INTC_ICDICFR8_TGI0A_0 (0x00400000uL) +#define INTC_ICDICFR8_TGI0A_1 (0x00800000uL) +#define INTC_ICDICFR8_TGI0B_0 (0x01000000uL) +#define INTC_ICDICFR8_TGI0B_1 (0x02000000uL) +#define INTC_ICDICFR8_TGI0C_0 (0x04000000uL) +#define INTC_ICDICFR8_TGI0C_1 (0x08000000uL) +#define INTC_ICDICFR8_TGI0D_0 (0x10000000uL) +#define INTC_ICDICFR8_TGI0D_1 (0x20000000uL) +#define INTC_ICDICFR8_TGI0V_0 (0x40000000uL) +#define INTC_ICDICFR8_TGI0V_1 (0x80000000uL) + +#define INTC_ICDICFR9_TGI0E_0 (0x00000001uL) +#define INTC_ICDICFR9_TGI0E_1 (0x00000002uL) +#define INTC_ICDICFR9_TGI0F_0 (0x00000004uL) +#define INTC_ICDICFR9_TGI0F_1 (0x00000008uL) +#define INTC_ICDICFR9_TGI1A_0 (0x00000010uL) +#define INTC_ICDICFR9_TGI1A_1 (0x00000020uL) +#define INTC_ICDICFR9_TGI1B_0 (0x00000040uL) +#define INTC_ICDICFR9_TGI1B_1 (0x00000080uL) +#define INTC_ICDICFR9_TGI1V_0 (0x00000100uL) +#define INTC_ICDICFR9_TGI1V_1 (0x00000200uL) +#define INTC_ICDICFR9_TGI1U_0 (0x00000400uL) +#define INTC_ICDICFR9_TGI1U_1 (0x00000800uL) +#define INTC_ICDICFR9_TGI2A_0 (0x00001000uL) +#define INTC_ICDICFR9_TGI2A_1 (0x00002000uL) +#define INTC_ICDICFR9_TGI2B_0 (0x00004000uL) +#define INTC_ICDICFR9_TGI2B_1 (0x00008000uL) +#define INTC_ICDICFR9_TGI2V_0 (0x00010000uL) +#define INTC_ICDICFR9_TGI2V_1 (0x00020000uL) +#define INTC_ICDICFR9_TGI2U_0 (0x00040000uL) +#define INTC_ICDICFR9_TGI2U_1 (0x00080000uL) +#define INTC_ICDICFR9_TGI3A_0 (0x00100000uL) +#define INTC_ICDICFR9_TGI3A_1 (0x00200000uL) +#define INTC_ICDICFR9_TGI3B_0 (0x00400000uL) +#define INTC_ICDICFR9_TGI3B_1 (0x00800000uL) +#define INTC_ICDICFR9_TGI3C_0 (0x01000000uL) +#define INTC_ICDICFR9_TGI3C_1 (0x02000000uL) +#define INTC_ICDICFR9_TGI3D_0 (0x04000000uL) +#define INTC_ICDICFR9_TGI3D_1 (0x08000000uL) +#define INTC_ICDICFR9_TGI3V_0 (0x10000000uL) +#define INTC_ICDICFR9_TGI3V_1 (0x20000000uL) +#define INTC_ICDICFR9_TGI4A_0 (0x40000000uL) +#define INTC_ICDICFR9_TGI4A_1 (0x80000000uL) + +#define INTC_ICDICFR10_TGI4B_0 (0x00000001uL) +#define INTC_ICDICFR10_TGI4B_1 (0x00000002uL) +#define INTC_ICDICFR10_TGI4C_0 (0x00000004uL) +#define INTC_ICDICFR10_TGI4C_1 (0x00000008uL) +#define INTC_ICDICFR10_TGI4D_0 (0x00000010uL) +#define INTC_ICDICFR10_TGI4D_1 (0x00000020uL) +#define INTC_ICDICFR10_TGI4V_0 (0x00000040uL) +#define INTC_ICDICFR10_TGI4V_1 (0x00000080uL) +#define INTC_ICDICFR10_CMI1_0 (0x00000100uL) +#define INTC_ICDICFR10_CMI1_1 (0x00000200uL) +#define INTC_ICDICFR10_CMI2_0 (0x00000400uL) +#define INTC_ICDICFR10_CMI2_1 (0x00000800uL) +#define INTC_ICDICFR10_SGDEI0_0 (0x00001000uL) +#define INTC_ICDICFR10_SGDEI0_1 (0x00002000uL) +#define INTC_ICDICFR10_SGDEI1_0 (0x00004000uL) +#define INTC_ICDICFR10_SGDEI1_1 (0x00008000uL) +#define INTC_ICDICFR10_SGDEI2_0 (0x00010000uL) +#define INTC_ICDICFR10_SGDEI2_1 (0x00020000uL) +#define INTC_ICDICFR10_SGDEI3_0 (0x00040000uL) +#define INTC_ICDICFR10_SGDEI3_1 (0x00080000uL) +#define INTC_ICDICFR10_ADI_0 (0x00100000uL) +#define INTC_ICDICFR10_ADI_1 (0x00200000uL) +#define INTC_ICDICFR10_LMTI_0 (0x00400000uL) +#define INTC_ICDICFR10_LMTI_1 (0x00800000uL) +#define INTC_ICDICFR10_SSII0_0 (0x01000000uL) +#define INTC_ICDICFR10_SSII0_1 (0x02000000uL) +#define INTC_ICDICFR10_SSIRXI0_0 (0x04000000uL) +#define INTC_ICDICFR10_SSIRXI0_1 (0x08000000uL) +#define INTC_ICDICFR10_SSITXI0_0 (0x10000000uL) +#define INTC_ICDICFR10_SSITXI0_1 (0x20000000uL) +#define INTC_ICDICFR10_SSII1_0 (0x40000000uL) +#define INTC_ICDICFR10_SSII1_1 (0x80000000uL) + +#define INTC_ICDICFR11_SSIRXI1_0 (0x00000001uL) +#define INTC_ICDICFR11_SSIRXI1_1 (0x00000002uL) +#define INTC_ICDICFR11_SSITXI1_0 (0x00000004uL) +#define INTC_ICDICFR11_SSITXI1_1 (0x00000008uL) +#define INTC_ICDICFR11_SSII2_0 (0x00000010uL) +#define INTC_ICDICFR11_SSII2_1 (0x00000020uL) +#define INTC_ICDICFR11_SSIRTI2_0 (0x00000040uL) +#define INTC_ICDICFR11_SSIRTI2_1 (0x00000080uL) +#define INTC_ICDICFR11_SSII3_0 (0x00000100uL) +#define INTC_ICDICFR11_SSII3_1 (0x00000200uL) +#define INTC_ICDICFR11_SSIRXI3_0 (0x00000400uL) +#define INTC_ICDICFR11_SSIRXI3_1 (0x00000800uL) +#define INTC_ICDICFR11_SSITXI3_0 (0x00001000uL) +#define INTC_ICDICFR11_SSITXI3_1 (0x00002000uL) +#define INTC_ICDICFR11_SSII4_0 (0x00004000uL) +#define INTC_ICDICFR11_SSII4_1 (0x00008000uL) +#define INTC_ICDICFR11_SSIRTI4_0 (0x00010000uL) +#define INTC_ICDICFR11_SSIRTI4_1 (0x00020000uL) +#define INTC_ICDICFR11_SSII5_0 (0x00040000uL) +#define INTC_ICDICFR11_SSII5_1 (0x00080000uL) +#define INTC_ICDICFR11_SSIRXI5_0 (0x00100000uL) +#define INTC_ICDICFR11_SSIRXI5_1 (0x00200000uL) +#define INTC_ICDICFR11_SSITXI5_0 (0x00400000uL) +#define INTC_ICDICFR11_SSITXI5_1 (0x00800000uL) +#define INTC_ICDICFR11_SPDIFI_0 (0x01000000uL) +#define INTC_ICDICFR11_SPDIFI_1 (0x02000000uL) +#define INTC_ICDICFR11_INTIICTEI0_0 (0x04000000uL) +#define INTC_ICDICFR11_INTIICTEI0_1 (0x08000000uL) +#define INTC_ICDICFR11_INTIICRI0_0 (0x10000000uL) +#define INTC_ICDICFR11_INTIICRI0_1 (0x20000000uL) +#define INTC_ICDICFR11_INTIICTI0_0 (0x40000000uL) +#define INTC_ICDICFR11_INTIICTI0_1 (0x80000000uL) + +#define INTC_ICDICFR12_INTIICSPI0_0 (0x00000001uL) +#define INTC_ICDICFR12_INTIICSPI0_1 (0x00000002uL) +#define INTC_ICDICFR12_INTIICSTI0_0 (0x00000004uL) +#define INTC_ICDICFR12_INTIICSTI0_1 (0x00000008uL) +#define INTC_ICDICFR12_INTIICNAKI0_0 (0x00000010uL) +#define INTC_ICDICFR12_INTIICNAKI0_1 (0x00000020uL) +#define INTC_ICDICFR12_INTIICALI0_0 (0x00000040uL) +#define INTC_ICDICFR12_INTIICALI0_1 (0x00000080uL) +#define INTC_ICDICFR12_INTIICTMOI0_0 (0x00000100uL) +#define INTC_ICDICFR12_INTIICTMOI0_1 (0x00000200uL) +#define INTC_ICDICFR12_INTIICTEI1_0 (0x00000400uL) +#define INTC_ICDICFR12_INTIICTEI1_1 (0x00000800uL) +#define INTC_ICDICFR12_INTIICRI1_0 (0x00001000uL) +#define INTC_ICDICFR12_INTIICRI1_1 (0x00002000uL) +#define INTC_ICDICFR12_INTIICTI1_0 (0x00004000uL) +#define INTC_ICDICFR12_INTIICTI1_1 (0x00008000uL) +#define INTC_ICDICFR12_INTIICSPI1_0 (0x00010000uL) +#define INTC_ICDICFR12_INTIICSPI1_1 (0x00020000uL) +#define INTC_ICDICFR12_INTIICSTI1_0 (0x00040000uL) +#define INTC_ICDICFR12_INTIICSTI1_1 (0x00080000uL) +#define INTC_ICDICFR12_INTIICNAKI1_0 (0x00100000uL) +#define INTC_ICDICFR12_INTIICNAKI1_1 (0x00200000uL) +#define INTC_ICDICFR12_INTIICALI1_0 (0x00400000uL) +#define INTC_ICDICFR12_INTIICALI1_1 (0x00800000uL) +#define INTC_ICDICFR12_INTIICTMOI1_0 (0x01000000uL) +#define INTC_ICDICFR12_INTIICTMOI1_1 (0x02000000uL) +#define INTC_ICDICFR12_INTIICTEI2_0 (0x04000000uL) +#define INTC_ICDICFR12_INTIICTEI2_1 (0x08000000uL) +#define INTC_ICDICFR12_INTIICRI2_0 (0x10000000uL) +#define INTC_ICDICFR12_INTIICRI2_1 (0x20000000uL) +#define INTC_ICDICFR12_INTIICTI2_0 (0x40000000uL) +#define INTC_ICDICFR12_INTIICTI2_1 (0x80000000uL) + +#define INTC_ICDICFR13_INTIICSPI2_0 (0x00000001uL) +#define INTC_ICDICFR13_INTIICSPI2_1 (0x00000002uL) +#define INTC_ICDICFR13_INTIICSTI2_0 (0x00000004uL) +#define INTC_ICDICFR13_INTIICSTI2_1 (0x00000008uL) +#define INTC_ICDICFR13_INTIICNAKI2_0 (0x00000010uL) +#define INTC_ICDICFR13_INTIICNAKI2_1 (0x00000020uL) +#define INTC_ICDICFR13_INTIICALI2_0 (0x00000040uL) +#define INTC_ICDICFR13_INTIICALI2_1 (0x00000080uL) +#define INTC_ICDICFR13_INTIICTMOI2_0 (0x00000100uL) +#define INTC_ICDICFR13_INTIICTMOI2_1 (0x00000200uL) +#define INTC_ICDICFR13_INTIICTEI3_0 (0x00000400uL) +#define INTC_ICDICFR13_INTIICTEI3_1 (0x00000800uL) +#define INTC_ICDICFR13_INTIICRI3_0 (0x00001000uL) +#define INTC_ICDICFR13_INTIICRI3_1 (0x00002000uL) +#define INTC_ICDICFR13_INTIICTI3_0 (0x00004000uL) +#define INTC_ICDICFR13_INTIICTI3_1 (0x00008000uL) +#define INTC_ICDICFR13_INTIICSPI3_0 (0x00010000uL) +#define INTC_ICDICFR13_INTIICSPI3_1 (0x00020000uL) +#define INTC_ICDICFR13_INTIICSTI3_0 (0x00040000uL) +#define INTC_ICDICFR13_INTIICSTI3_1 (0x00080000uL) +#define INTC_ICDICFR13_INTIICNAKI3_0 (0x00100000uL) +#define INTC_ICDICFR13_INTIICNAKI3_1 (0x00200000uL) +#define INTC_ICDICFR13_INTIICALI3_0 (0x00400000uL) +#define INTC_ICDICFR13_INTIICALI3_1 (0x00800000uL) +#define INTC_ICDICFR13_INTIICTMOI3_0 (0x01000000uL) +#define INTC_ICDICFR13_INTIICTMOI3_1 (0x02000000uL) +#define INTC_ICDICFR13_BRI0_0 (0x04000000uL) +#define INTC_ICDICFR13_BRI0_1 (0x08000000uL) +#define INTC_ICDICFR13_ERI0_0 (0x10000000uL) +#define INTC_ICDICFR13_ERI0_1 (0x20000000uL) +#define INTC_ICDICFR13_RXI0_0 (0x40000000uL) +#define INTC_ICDICFR13_RXI0_1 (0x80000000uL) + +#define INTC_ICDICFR14_TXI0_0 (0x00000001uL) +#define INTC_ICDICFR14_TXI0_1 (0x00000002uL) +#define INTC_ICDICFR14_BRI1_0 (0x00000004uL) +#define INTC_ICDICFR14_BRI1_1 (0x00000008uL) +#define INTC_ICDICFR14_ERI1_0 (0x00000010uL) +#define INTC_ICDICFR14_ERI1_1 (0x00000020uL) +#define INTC_ICDICFR14_RXI1_0 (0x00000040uL) +#define INTC_ICDICFR14_RXI1_1 (0x00000080uL) +#define INTC_ICDICFR14_TXI1_0 (0x00000100uL) +#define INTC_ICDICFR14_TXI1_1 (0x00000200uL) +#define INTC_ICDICFR14_BRI2_0 (0x00000400uL) +#define INTC_ICDICFR14_BRI2_1 (0x00000800uL) +#define INTC_ICDICFR14_ERI2_0 (0x00001000uL) +#define INTC_ICDICFR14_ERI2_1 (0x00002000uL) +#define INTC_ICDICFR14_RXI2_0 (0x00004000uL) +#define INTC_ICDICFR14_RXI2_1 (0x00008000uL) +#define INTC_ICDICFR14_TXI2_0 (0x00010000uL) +#define INTC_ICDICFR14_TXI2_1 (0x00020000uL) +#define INTC_ICDICFR14_BRI3_0 (0x00040000uL) +#define INTC_ICDICFR14_BRI3_1 (0x00080000uL) +#define INTC_ICDICFR14_ERI3_0 (0x00100000uL) +#define INTC_ICDICFR14_ERI3_1 (0x00200000uL) +#define INTC_ICDICFR14_RXI3_0 (0x00400000uL) +#define INTC_ICDICFR14_RXI3_1 (0x00800000uL) +#define INTC_ICDICFR14_TXI3_0 (0x01000000uL) +#define INTC_ICDICFR14_TXI3_1 (0x02000000uL) +#define INTC_ICDICFR14_BRI4_0 (0x04000000uL) +#define INTC_ICDICFR14_BRI4_1 (0x08000000uL) +#define INTC_ICDICFR14_ERI4_0 (0x10000000uL) +#define INTC_ICDICFR14_ERI4_1 (0x20000000uL) +#define INTC_ICDICFR14_RXI4_0 (0x40000000uL) +#define INTC_ICDICFR14_RXI4_1 (0x80000000uL) + +#define INTC_ICDICFR15_TXI4_0 (0x00000001uL) +#define INTC_ICDICFR15_TXI4_1 (0x00000002uL) +#define INTC_ICDICFR15_BRI5_0 (0x00000004uL) +#define INTC_ICDICFR15_BRI5_1 (0x00000008uL) +#define INTC_ICDICFR15_ERI5_0 (0x00000010uL) +#define INTC_ICDICFR15_ERI5_1 (0x00000020uL) +#define INTC_ICDICFR15_RXI5_0 (0x00000040uL) +#define INTC_ICDICFR15_RXI5_1 (0x00000080uL) +#define INTC_ICDICFR15_TXI5_0 (0x00000100uL) +#define INTC_ICDICFR15_TXI5_1 (0x00000200uL) +#define INTC_ICDICFR15_BRI6_0 (0x00000400uL) +#define INTC_ICDICFR15_BRI6_1 (0x00000800uL) +#define INTC_ICDICFR15_ERI6_0 (0x00001000uL) +#define INTC_ICDICFR15_ERI6_1 (0x00002000uL) +#define INTC_ICDICFR15_RXI6_0 (0x00004000uL) +#define INTC_ICDICFR15_RXI6_1 (0x00008000uL) +#define INTC_ICDICFR15_TXI6_0 (0x00010000uL) +#define INTC_ICDICFR15_TXI6_1 (0x00020000uL) +#define INTC_ICDICFR15_BRI7_0 (0x00040000uL) +#define INTC_ICDICFR15_BRI7_1 (0x00080000uL) +#define INTC_ICDICFR15_ERI7_0 (0x00100000uL) +#define INTC_ICDICFR15_ERI7_1 (0x00200000uL) +#define INTC_ICDICFR15_RXI7_0 (0x00400000uL) +#define INTC_ICDICFR15_RXI7_1 (0x00800000uL) +#define INTC_ICDICFR15_TXI7_0 (0x01000000uL) +#define INTC_ICDICFR15_TXI7_1 (0x02000000uL) +#define INTC_ICDICFR15_INTRCANGERR_0 (0x04000000uL) +#define INTC_ICDICFR15_INTRCANGERR_1 (0x08000000uL) +#define INTC_ICDICFR15_INTRCANGRECC_0 (0x10000000uL) +#define INTC_ICDICFR15_INTRCANGRECC_1 (0x20000000uL) +#define INTC_ICDICFR15_INTRCAN0REC_0 (0x40000000uL) +#define INTC_ICDICFR15_INTRCAN0REC_1 (0x80000000uL) + +#define INTC_ICDICFR16_INTRCAN0ERR_0 (0x00000001uL) +#define INTC_ICDICFR16_INTRCAN0ERR_1 (0x00000002uL) +#define INTC_ICDICFR16_INTRCAN0TRX_0 (0x00000004uL) +#define INTC_ICDICFR16_INTRCAN0TRX_1 (0x00000008uL) +#define INTC_ICDICFR16_INTRCAN1REC_0 (0x00000010uL) +#define INTC_ICDICFR16_INTRCAN1REC_1 (0x00000020uL) +#define INTC_ICDICFR16_INTRCAN1ERR_0 (0x00000040uL) +#define INTC_ICDICFR16_INTRCAN1ERR_1 (0x00000080uL) +#define INTC_ICDICFR16_INTRCAN1TRX_0 (0x00000100uL) +#define INTC_ICDICFR16_INTRCAN1TRX_1 (0x00000200uL) +#define INTC_ICDICFR16_INTRCAN2REC_0 (0x00000400uL) +#define INTC_ICDICFR16_INTRCAN2REC_1 (0x00000800uL) +#define INTC_ICDICFR16_INTRCAN2ERR_0 (0x00001000uL) +#define INTC_ICDICFR16_INTRCAN2ERR_1 (0x00002000uL) +#define INTC_ICDICFR16_INTRCAN2TRX_0 (0x00004000uL) +#define INTC_ICDICFR16_INTRCAN2TRX_1 (0x00008000uL) +#define INTC_ICDICFR16_INTRCAN3REC_0 (0x00010000uL) +#define INTC_ICDICFR16_INTRCAN3REC_1 (0x00020000uL) +#define INTC_ICDICFR16_INTRCAN3ERR_0 (0x00040000uL) +#define INTC_ICDICFR16_INTRCAN3ERR_1 (0x00080000uL) +#define INTC_ICDICFR16_INTRCAN3TRX_0 (0x00100000uL) +#define INTC_ICDICFR16_INTRCAN3TRX_1 (0x00200000uL) +#define INTC_ICDICFR16_INTRCAN4REC_0 (0x00400000uL) +#define INTC_ICDICFR16_INTRCAN4REC_1 (0x00800000uL) +#define INTC_ICDICFR16_INTRCAN4ERR_0 (0x01000000uL) +#define INTC_ICDICFR16_INTRCAN4ERR_1 (0x02000000uL) +#define INTC_ICDICFR16_INTRCAN4TRX_0 (0x04000000uL) +#define INTC_ICDICFR16_INTRCAN4TRX_1 (0x08000000uL) +#define INTC_ICDICFR16_SPEI0_0 (0x10000000uL) +#define INTC_ICDICFR16_SPEI0_1 (0x20000000uL) +#define INTC_ICDICFR16_SPRI0_0 (0x40000000uL) +#define INTC_ICDICFR16_SPRI0_1 (0x80000000uL) + +#define INTC_ICDICFR17_SPTI0_0 (0x00000001uL) +#define INTC_ICDICFR17_SPTI0_1 (0x00000002uL) +#define INTC_ICDICFR17_SPEI1_0 (0x00000004uL) +#define INTC_ICDICFR17_SPEI1_1 (0x00000008uL) +#define INTC_ICDICFR17_SPRI1_0 (0x00000010uL) +#define INTC_ICDICFR17_SPRI1_1 (0x00000020uL) +#define INTC_ICDICFR17_SPTI1_0 (0x00000040uL) +#define INTC_ICDICFR17_SPTI1_1 (0x00000080uL) +#define INTC_ICDICFR17_SPEI2_0 (0x00000100uL) +#define INTC_ICDICFR17_SPEI2_1 (0x00000200uL) +#define INTC_ICDICFR17_SPRI2_0 (0x00000400uL) +#define INTC_ICDICFR17_SPRI2_1 (0x00000800uL) +#define INTC_ICDICFR17_SPTI2_0 (0x00001000uL) +#define INTC_ICDICFR17_SPTI2_1 (0x00002000uL) +#define INTC_ICDICFR17_SPEI3_0 (0x00004000uL) +#define INTC_ICDICFR17_SPEI3_1 (0x00008000uL) +#define INTC_ICDICFR17_SPRI3_0 (0x00010000uL) +#define INTC_ICDICFR17_SPRI3_1 (0x00020000uL) +#define INTC_ICDICFR17_SPTI3_0 (0x00040000uL) +#define INTC_ICDICFR17_SPTI3_1 (0x00080000uL) +#define INTC_ICDICFR17_SPEI4_0 (0x00100000uL) +#define INTC_ICDICFR17_SPEI4_1 (0x00200000uL) +#define INTC_ICDICFR17_SPRI4_0 (0x00400000uL) +#define INTC_ICDICFR17_SPRI4_1 (0x00800000uL) +#define INTC_ICDICFR17_SPTI4_0 (0x01000000uL) +#define INTC_ICDICFR17_SPTI4_1 (0x02000000uL) +#define INTC_ICDICFR17_IEBBTD_0 (0x04000000uL) +#define INTC_ICDICFR17_IEBBTD_1 (0x08000000uL) +#define INTC_ICDICFR17_IEBBTERR_0 (0x10000000uL) +#define INTC_ICDICFR17_IEBBTERR_1 (0x20000000uL) +#define INTC_ICDICFR17_IEBBTSTA_0 (0x40000000uL) +#define INTC_ICDICFR17_IEBBTSTA_1 (0x80000000uL) + +#define INTC_ICDICFR18_IEBBTV_0 (0x00000001uL) +#define INTC_ICDICFR18_IEBBTV_1 (0x00000002uL) +#define INTC_ICDICFR18_ISY_0 (0x00000004uL) +#define INTC_ICDICFR18_ISY_1 (0x00000008uL) +#define INTC_ICDICFR18_IERR_0 (0x00000010uL) +#define INTC_ICDICFR18_IERR_1 (0x00000020uL) +#define INTC_ICDICFR18_ITARG_0 (0x00000040uL) +#define INTC_ICDICFR18_ITARG_1 (0x00000080uL) +#define INTC_ICDICFR18_ISEC_0 (0x00000100uL) +#define INTC_ICDICFR18_ISEC_1 (0x00000200uL) +#define INTC_ICDICFR18_IBUF_0 (0x00000400uL) +#define INTC_ICDICFR18_IBUF_1 (0x00000800uL) +#define INTC_ICDICFR18_IREADY_0 (0x00001000uL) +#define INTC_ICDICFR18_IREADY_1 (0x00002000uL) +#define INTC_ICDICFR18_FLSTE_0 (0x00004000uL) +#define INTC_ICDICFR18_FLSTE_1 (0x00008000uL) +#define INTC_ICDICFR18_FLTENDI_0 (0x00010000uL) +#define INTC_ICDICFR18_FLTENDI_1 (0x00020000uL) +#define INTC_ICDICFR18_FLTREQ0I_0 (0x00040000uL) +#define INTC_ICDICFR18_FLTREQ0I_1 (0x00080000uL) +#define INTC_ICDICFR18_FLTREQ1I_0 (0x00100000uL) +#define INTC_ICDICFR18_FLTREQ1I_1 (0x00200000uL) +#define INTC_ICDICFR18_MMC0_0 (0x00400000uL) +#define INTC_ICDICFR18_MMC0_1 (0x00800000uL) +#define INTC_ICDICFR18_MMC1_0 (0x01000000uL) +#define INTC_ICDICFR18_MMC1_1 (0x02000000uL) +#define INTC_ICDICFR18_MMC2_0 (0x04000000uL) +#define INTC_ICDICFR18_MMC2_1 (0x08000000uL) +#define INTC_ICDICFR18_SDHI0_3_0 (0x10000000uL) +#define INTC_ICDICFR18_SDHI0_3_1 (0x20000000uL) +#define INTC_ICDICFR18_SDHI0_0_0 (0x40000000uL) +#define INTC_ICDICFR18_SDHI0_0_1 (0x80000000uL) + +#define INTC_ICDICFR19_SDHI0_1_0 (0x00000001uL) +#define INTC_ICDICFR19_SDHI0_1_1 (0x00000002uL) +#define INTC_ICDICFR19_SDHI1_3_0 (0x00000004uL) +#define INTC_ICDICFR19_SDHI1_3_1 (0x00000008uL) +#define INTC_ICDICFR19_SDHI1_0_0 (0x00000010uL) +#define INTC_ICDICFR19_SDHI1_0_1 (0x00000020uL) +#define INTC_ICDICFR19_SDHI1_1_0 (0x00000040uL) +#define INTC_ICDICFR19_SDHI1_1_1 (0x00000080uL) +#define INTC_ICDICFR19_ARM_0 (0x00000100uL) +#define INTC_ICDICFR19_ARM_1 (0x00000200uL) +#define INTC_ICDICFR19_PRD_0 (0x00000400uL) +#define INTC_ICDICFR19_PRD_1 (0x00000800uL) +#define INTC_ICDICFR19_CUP_0 (0x00001000uL) +#define INTC_ICDICFR19_CUP_1 (0x00002000uL) +#define INTC_ICDICFR19_SCUAI0_0 (0x00004000uL) +#define INTC_ICDICFR19_SCUAI0_1 (0x00008000uL) +#define INTC_ICDICFR19_SCUAI1_0 (0x00010000uL) +#define INTC_ICDICFR19_SCUAI1_1 (0x00020000uL) +#define INTC_ICDICFR19_SCUFDI0_0 (0x00040000uL) +#define INTC_ICDICFR19_SCUFDI0_1 (0x00080000uL) +#define INTC_ICDICFR19_SCUFDI1_0 (0x00100000uL) +#define INTC_ICDICFR19_SCUFDI1_1 (0x00200000uL) +#define INTC_ICDICFR19_SCUFDI2_0 (0x00400000uL) +#define INTC_ICDICFR19_SCUFDI2_1 (0x00800000uL) +#define INTC_ICDICFR19_SCUFDI3_0 (0x01000000uL) +#define INTC_ICDICFR19_SCUFDI3_1 (0x02000000uL) +#define INTC_ICDICFR19_SCUFUI0_0 (0x04000000uL) +#define INTC_ICDICFR19_SCUFUI0_1 (0x08000000uL) +#define INTC_ICDICFR19_SCUFUI1_0 (0x10000000uL) +#define INTC_ICDICFR19_SCUFUI1_1 (0x20000000uL) +#define INTC_ICDICFR19_SCUFUI2_0 (0x40000000uL) +#define INTC_ICDICFR19_SCUFUI2_1 (0x80000000uL) + +#define INTC_ICDICFR20_SCUFUI3_0 (0x00000001uL) +#define INTC_ICDICFR20_SCUFUI3_1 (0x00000002uL) +#define INTC_ICDICFR20_SCUDVI0_0 (0x00000004uL) +#define INTC_ICDICFR20_SCUDVI0_1 (0x00000008uL) +#define INTC_ICDICFR20_SCUDVI1_0 (0x00000010uL) +#define INTC_ICDICFR20_SCUDVI1_1 (0x00000020uL) +#define INTC_ICDICFR20_SCUDVI2_0 (0x00000040uL) +#define INTC_ICDICFR20_SCUDVI2_1 (0x00000080uL) +#define INTC_ICDICFR20_SCUDVI3_0 (0x00000100uL) +#define INTC_ICDICFR20_SCUDVI3_1 (0x00000200uL) +#define INTC_ICDICFR20_MLB_CINT_0 (0x00000400uL) +#define INTC_ICDICFR20_MLB_CINT_1 (0x00000800uL) +#define INTC_ICDICFR20_MLB_SINT_0 (0x00001000uL) +#define INTC_ICDICFR20_MLB_SINT_1 (0x00002000uL) +#define INTC_ICDICFR20_DRC0_0 (0x00004000uL) +#define INTC_ICDICFR20_DRC0_1 (0x00008000uL) +#define INTC_ICDICFR20_DRC1_0 (0x00010000uL) +#define INTC_ICDICFR20_DRC1_1 (0x00020000uL) +#define INTC_ICDICFR20_LINI0_INT_T_0 (0x00400000uL) +#define INTC_ICDICFR20_LINI0_INT_T_1 (0x00800000uL) +#define INTC_ICDICFR20_LINI0_INT_R_0 (0x01000000uL) +#define INTC_ICDICFR20_LINI0_INT_R_1 (0x02000000uL) +#define INTC_ICDICFR20_LINI0_INT_S_0 (0x04000000uL) +#define INTC_ICDICFR20_LINI0_INT_S_1 (0x08000000uL) +#define INTC_ICDICFR20_LINI0_INT_M_0 (0x10000000uL) +#define INTC_ICDICFR20_LINI0_INT_M_1 (0x20000000uL) +#define INTC_ICDICFR20_LINI1_INT_T_0 (0x40000000uL) +#define INTC_ICDICFR20_LINI1_INT_T_1 (0x80000000uL) + +#define INTC_ICDICFR21_LINI1_INT_R_0 (0x00000001uL) +#define INTC_ICDICFR21_LINI1_INT_R_1 (0x00000002uL) +#define INTC_ICDICFR21_LINI1_INT_S_0 (0x00000004uL) +#define INTC_ICDICFR21_LINI1_INT_S_1 (0x00000008uL) +#define INTC_ICDICFR21_LINI1_INT_M_0 (0x00000010uL) +#define INTC_ICDICFR21_LINI1_INT_M_1 (0x00000020uL) +#define INTC_ICDICFR21_ERI0_0 (0x00400000uL) +#define INTC_ICDICFR21_ERI0_1 (0x00800000uL) +#define INTC_ICDICFR21_RXI0_0 (0x01000000uL) +#define INTC_ICDICFR21_RXI0_1 (0x02000000uL) +#define INTC_ICDICFR21_TXI0_0 (0x04000000uL) +#define INTC_ICDICFR21_TXI0_1 (0x08000000uL) +#define INTC_ICDICFR21_TEI0_0 (0x10000000uL) +#define INTC_ICDICFR21_TEI0_1 (0x20000000uL) +#define INTC_ICDICFR21_ERI1_0 (0x40000000uL) +#define INTC_ICDICFR21_ERI1_1 (0x80000000uL) + +#define INTC_ICDICFR22_RXI1_0 (0x00000001uL) +#define INTC_ICDICFR22_RXI1_1 (0x00000002uL) +#define INTC_ICDICFR22_TXI1_0 (0x00000004uL) +#define INTC_ICDICFR22_TXI1_1 (0x00000008uL) +#define INTC_ICDICFR22_TEI1_0 (0x00000010uL) +#define INTC_ICDICFR22_TEI1_1 (0x00000020uL) +#define INTC_ICDICFR22_AVBI_DATA_0 (0x00000040uL) +#define INTC_ICDICFR22_AVBI_DATA_1 (0x00000080uL) +#define INTC_ICDICFR22_AVBI_ERROR_0 (0x00000100uL) +#define INTC_ICDICFR22_AVBI_ERROR_1 (0x00000200uL) +#define INTC_ICDICFR22_AVBI_MANAGE_0 (0x00000400uL) +#define INTC_ICDICFR22_AVBI_MANAGE_1 (0x00000800uL) +#define INTC_ICDICFR22_AVBI_MAC_0 (0x00001000uL) +#define INTC_ICDICFR22_AVBI_MAC_1 (0x00002000uL) +#define INTC_ICDICFR22_ETHERI_0 (0x00004000uL) +#define INTC_ICDICFR22_ETHERI_1 (0x00008000uL) +#define INTC_ICDICFR22_CEUI_0 (0x01000000uL) +#define INTC_ICDICFR22_CEUI_1 (0x02000000uL) + +#define INTC_ICDICFR23_H2XMLB_ERRINT_0 (0x04000000uL) +#define INTC_ICDICFR23_H2XMLB_ERRINT_1 (0x08000000uL) +#define INTC_ICDICFR23_H2XIC1_ERRINT_0 (0x10000000uL) +#define INTC_ICDICFR23_H2XIC1_ERRINT_1 (0x20000000uL) +#define INTC_ICDICFR23_X2HPERI1_ERRINT_0 (0x40000000uL) +#define INTC_ICDICFR23_X2HPERI1_ERRINT_1 (0x80000000uL) + +#define INTC_ICDICFR24_X2HPERI2_ERRINT_0 (0x00000001uL) +#define INTC_ICDICFR24_X2HPERI2_ERRINT_1 (0x00000002uL) +#define INTC_ICDICFR24_X2HPERI34_ERRINT_0 (0x00000004uL) +#define INTC_ICDICFR24_X2HPERI34_ERRINT_1 (0x00000008uL) +#define INTC_ICDICFR24_X2HPERI5_ERRINT_0 (0x00000010uL) +#define INTC_ICDICFR24_X2HPERI5_ERRINT_1 (0x00000020uL) +#define INTC_ICDICFR24_X2HPERI67_ERRINT_0 (0x00000040uL) +#define INTC_ICDICFR24_X2HPERI67_ERRINT_1 (0x00000080uL) +#define INTC_ICDICFR24_X2HDBGR_ERRINT_0 (0x00000100uL) +#define INTC_ICDICFR24_X2HDBGR_ERRINT_1 (0x00000200uL) +#define INTC_ICDICFR24_X2HBSC_ERRINT_0 (0x00000400uL) +#define INTC_ICDICFR24_X2HBSC_ERRINT_1 (0x00000800uL) +#define INTC_ICDICFR24_X2HSPI1_ERRINT_0 (0x00001000uL) +#define INTC_ICDICFR24_X2HSPI1_ERRINT_1 (0x00002000uL) +#define INTC_ICDICFR24_X2HSPI2_ERRINT_0 (0x00004000uL) +#define INTC_ICDICFR24_X2HSPI2_ERRINT_1 (0x00008000uL) +#define INTC_ICDICFR24_PRRI_0 (0x00010000uL) +#define INTC_ICDICFR24_PRRI_1 (0x00020000uL) +#define INTC_ICDICFR24_IFEI0_0 (0x00040000uL) +#define INTC_ICDICFR24_IFEI0_1 (0x00080000uL) +#define INTC_ICDICFR24_OFFI0_0 (0x00100000uL) +#define INTC_ICDICFR24_OFFI0_1 (0x00200000uL) +#define INTC_ICDICFR24_PFVEI0_0 (0x00400000uL) +#define INTC_ICDICFR24_PFVEI0_1 (0x00800000uL) +#define INTC_ICDICFR24_IFEI1_0 (0x01000000uL) +#define INTC_ICDICFR24_IFEI1_1 (0x02000000uL) +#define INTC_ICDICFR24_OFFI1_0 (0x04000000uL) +#define INTC_ICDICFR24_OFFI1_1 (0x08000000uL) +#define INTC_ICDICFR24_PFVEI1_0 (0x10000000uL) +#define INTC_ICDICFR24_PFVEI1_1 (0x20000000uL) + +#define INTC_ICDICFR26_TINT0_0 (0x00000001uL) +#define INTC_ICDICFR26_TINT0_1 (0x00000002uL) +#define INTC_ICDICFR26_TINT1_0 (0x00000004uL) +#define INTC_ICDICFR26_TINT1_1 (0x00000008uL) +#define INTC_ICDICFR26_TINT2_0 (0x00000010uL) +#define INTC_ICDICFR26_TINT2_1 (0x00000020uL) +#define INTC_ICDICFR26_TINT3_0 (0x00000040uL) +#define INTC_ICDICFR26_TINT3_1 (0x00000080uL) +#define INTC_ICDICFR26_TINT4_0 (0x00000100uL) +#define INTC_ICDICFR26_TINT4_1 (0x00000200uL) +#define INTC_ICDICFR26_TINT5_0 (0x00000400uL) +#define INTC_ICDICFR26_TINT5_1 (0x00000800uL) +#define INTC_ICDICFR26_TINT6_0 (0x00001000uL) +#define INTC_ICDICFR26_TINT6_1 (0x00002000uL) +#define INTC_ICDICFR26_TINT7_0 (0x00004000uL) +#define INTC_ICDICFR26_TINT7_1 (0x00008000uL) +#define INTC_ICDICFR26_TINT8_0 (0x00010000uL) +#define INTC_ICDICFR26_TINT8_1 (0x00020000uL) +#define INTC_ICDICFR26_TINT9_0 (0x00040000uL) +#define INTC_ICDICFR26_TINT9_1 (0x00080000uL) +#define INTC_ICDICFR26_TINT10_0 (0x00100000uL) +#define INTC_ICDICFR26_TINT10_1 (0x00200000uL) +#define INTC_ICDICFR26_TINT11_0 (0x00400000uL) +#define INTC_ICDICFR26_TINT11_1 (0x00800000uL) +#define INTC_ICDICFR26_TINT12_0 (0x01000000uL) +#define INTC_ICDICFR26_TINT12_1 (0x02000000uL) +#define INTC_ICDICFR26_TINT13_0 (0x04000000uL) +#define INTC_ICDICFR26_TINT13_1 (0x08000000uL) +#define INTC_ICDICFR26_TINT14_0 (0x10000000uL) +#define INTC_ICDICFR26_TINT14_1 (0x20000000uL) +#define INTC_ICDICFR26_TINT15_0 (0x40000000uL) +#define INTC_ICDICFR26_TINT15_1 (0x80000000uL) + +#define INTC_ICDICFR27_TINT16_0 (0x00000001uL) +#define INTC_ICDICFR27_TINT16_1 (0x00000002uL) +#define INTC_ICDICFR27_TINT17_0 (0x00000004uL) +#define INTC_ICDICFR27_TINT17_1 (0x00000008uL) +#define INTC_ICDICFR27_TINT18_0 (0x00000010uL) +#define INTC_ICDICFR27_TINT18_1 (0x00000020uL) +#define INTC_ICDICFR27_TINT19_0 (0x00000040uL) +#define INTC_ICDICFR27_TINT19_1 (0x00000080uL) +#define INTC_ICDICFR27_TINT20_0 (0x00000100uL) +#define INTC_ICDICFR27_TINT20_1 (0x00000200uL) +#define INTC_ICDICFR27_TINT21_0 (0x00000400uL) +#define INTC_ICDICFR27_TINT21_1 (0x00000800uL) +#define INTC_ICDICFR27_TINT22_0 (0x00001000uL) +#define INTC_ICDICFR27_TINT22_1 (0x00002000uL) +#define INTC_ICDICFR27_TINT23_0 (0x00004000uL) +#define INTC_ICDICFR27_TINT23_1 (0x00008000uL) +#define INTC_ICDICFR27_TINT24_0 (0x00010000uL) +#define INTC_ICDICFR27_TINT24_1 (0x00020000uL) +#define INTC_ICDICFR27_TINT25_0 (0x00040000uL) +#define INTC_ICDICFR27_TINT25_1 (0x00080000uL) +#define INTC_ICDICFR27_TINT26_0 (0x00100000uL) +#define INTC_ICDICFR27_TINT26_1 (0x00200000uL) +#define INTC_ICDICFR27_TINT27_0 (0x00400000uL) +#define INTC_ICDICFR27_TINT27_1 (0x00800000uL) +#define INTC_ICDICFR27_TINT28_0 (0x01000000uL) +#define INTC_ICDICFR27_TINT28_1 (0x02000000uL) +#define INTC_ICDICFR27_TINT29_0 (0x04000000uL) +#define INTC_ICDICFR27_TINT29_1 (0x08000000uL) +#define INTC_ICDICFR27_TINT30_0 (0x10000000uL) +#define INTC_ICDICFR27_TINT30_1 (0x20000000uL) +#define INTC_ICDICFR27_TINT31_0 (0x40000000uL) +#define INTC_ICDICFR27_TINT31_1 (0x80000000uL) + +#define INTC_ICDICFR28_TINT32_0 (0x00000001uL) +#define INTC_ICDICFR28_TINT32_1 (0x00000002uL) +#define INTC_ICDICFR28_TINT33_0 (0x00000004uL) +#define INTC_ICDICFR28_TINT33_1 (0x00000008uL) +#define INTC_ICDICFR28_TINT34_0 (0x00000010uL) +#define INTC_ICDICFR28_TINT34_1 (0x00000020uL) +#define INTC_ICDICFR28_TINT35_0 (0x00000040uL) +#define INTC_ICDICFR28_TINT35_1 (0x00000080uL) +#define INTC_ICDICFR28_TINT36_0 (0x00000100uL) +#define INTC_ICDICFR28_TINT36_1 (0x00000200uL) +#define INTC_ICDICFR28_TINT37_0 (0x00000400uL) +#define INTC_ICDICFR28_TINT37_1 (0x00000800uL) +#define INTC_ICDICFR28_TINT38_0 (0x00001000uL) +#define INTC_ICDICFR28_TINT38_1 (0x00002000uL) +#define INTC_ICDICFR28_TINT39_0 (0x00004000uL) +#define INTC_ICDICFR28_TINT39_1 (0x00008000uL) +#define INTC_ICDICFR28_TINT40_0 (0x00010000uL) +#define INTC_ICDICFR28_TINT40_1 (0x00020000uL) +#define INTC_ICDICFR28_TINT41_0 (0x00040000uL) +#define INTC_ICDICFR28_TINT41_1 (0x00080000uL) +#define INTC_ICDICFR28_TINT42_0 (0x00100000uL) +#define INTC_ICDICFR28_TINT42_1 (0x00200000uL) +#define INTC_ICDICFR28_TINT43_0 (0x00400000uL) +#define INTC_ICDICFR28_TINT43_1 (0x00800000uL) +#define INTC_ICDICFR28_TINT44_0 (0x01000000uL) +#define INTC_ICDICFR28_TINT44_1 (0x02000000uL) +#define INTC_ICDICFR28_TINT45_0 (0x04000000uL) +#define INTC_ICDICFR28_TINT45_1 (0x08000000uL) +#define INTC_ICDICFR28_TINT46_0 (0x10000000uL) +#define INTC_ICDICFR28_TINT46_1 (0x20000000uL) +#define INTC_ICDICFR28_TINT47_0 (0x40000000uL) +#define INTC_ICDICFR28_TINT47_1 (0x80000000uL) + +#define INTC_ICDICFR29_TINT48_0 (0x00000001uL) +#define INTC_ICDICFR29_TINT48_1 (0x00000002uL) +#define INTC_ICDICFR29_TINT49_0 (0x00000004uL) +#define INTC_ICDICFR29_TINT49_1 (0x00000008uL) +#define INTC_ICDICFR29_TINT50_0 (0x00000010uL) +#define INTC_ICDICFR29_TINT50_1 (0x00000020uL) +#define INTC_ICDICFR29_TINT51_0 (0x00000040uL) +#define INTC_ICDICFR29_TINT51_1 (0x00000080uL) +#define INTC_ICDICFR29_TINT52_0 (0x00000100uL) +#define INTC_ICDICFR29_TINT52_1 (0x00000200uL) +#define INTC_ICDICFR29_TINT53_0 (0x00000400uL) +#define INTC_ICDICFR29_TINT53_1 (0x00000800uL) +#define INTC_ICDICFR29_TINT54_0 (0x00001000uL) +#define INTC_ICDICFR29_TINT54_1 (0x00002000uL) +#define INTC_ICDICFR29_TINT55_0 (0x00004000uL) +#define INTC_ICDICFR29_TINT55_1 (0x00008000uL) +#define INTC_ICDICFR29_TINT56_0 (0x00010000uL) +#define INTC_ICDICFR29_TINT56_1 (0x00020000uL) +#define INTC_ICDICFR29_TINT57_0 (0x00040000uL) +#define INTC_ICDICFR29_TINT57_1 (0x00080000uL) +#define INTC_ICDICFR29_TINT58_0 (0x00100000uL) +#define INTC_ICDICFR29_TINT58_1 (0x00200000uL) +#define INTC_ICDICFR29_TINT59_0 (0x00400000uL) +#define INTC_ICDICFR29_TINT59_1 (0x00800000uL) +#define INTC_ICDICFR29_TINT60_0 (0x01000000uL) +#define INTC_ICDICFR29_TINT60_1 (0x02000000uL) +#define INTC_ICDICFR29_TINT61_0 (0x04000000uL) +#define INTC_ICDICFR29_TINT61_1 (0x08000000uL) +#define INTC_ICDICFR29_TINT62_0 (0x10000000uL) +#define INTC_ICDICFR29_TINT62_1 (0x20000000uL) +#define INTC_ICDICFR29_TINT63_0 (0x40000000uL) +#define INTC_ICDICFR29_TINT63_1 (0x80000000uL) + +#define INTC_ICDICFR30_TINT64_0 (0x00000001uL) +#define INTC_ICDICFR30_TINT64_1 (0x00000002uL) +#define INTC_ICDICFR30_TINT65_0 (0x00000004uL) +#define INTC_ICDICFR30_TINT65_1 (0x00000008uL) +#define INTC_ICDICFR30_TINT66_0 (0x00000010uL) +#define INTC_ICDICFR30_TINT66_1 (0x00000020uL) +#define INTC_ICDICFR30_TINT67_0 (0x00000040uL) +#define INTC_ICDICFR30_TINT67_1 (0x00000080uL) +#define INTC_ICDICFR30_TINT68_0 (0x00000100uL) +#define INTC_ICDICFR30_TINT68_1 (0x00000200uL) +#define INTC_ICDICFR30_TINT69_0 (0x00000400uL) +#define INTC_ICDICFR30_TINT69_1 (0x00000800uL) +#define INTC_ICDICFR30_TINT70_0 (0x00001000uL) +#define INTC_ICDICFR30_TINT70_1 (0x00002000uL) +#define INTC_ICDICFR30_TINT71_0 (0x00004000uL) +#define INTC_ICDICFR30_TINT71_1 (0x00008000uL) +#define INTC_ICDICFR30_TINT72_0 (0x00010000uL) +#define INTC_ICDICFR30_TINT72_1 (0x00020000uL) +#define INTC_ICDICFR30_TINT73_0 (0x00040000uL) +#define INTC_ICDICFR30_TINT73_1 (0x00080000uL) +#define INTC_ICDICFR30_TINT74_0 (0x00100000uL) +#define INTC_ICDICFR30_TINT74_1 (0x00200000uL) +#define INTC_ICDICFR30_TINT75_0 (0x00400000uL) +#define INTC_ICDICFR30_TINT75_1 (0x00800000uL) +#define INTC_ICDICFR30_TINT76_0 (0x01000000uL) +#define INTC_ICDICFR30_TINT76_1 (0x02000000uL) +#define INTC_ICDICFR30_TINT77_0 (0x04000000uL) +#define INTC_ICDICFR30_TINT77_1 (0x08000000uL) +#define INTC_ICDICFR30_TINT78_0 (0x10000000uL) +#define INTC_ICDICFR30_TINT78_1 (0x20000000uL) +#define INTC_ICDICFR30_TINT79_0 (0x40000000uL) +#define INTC_ICDICFR30_TINT79_1 (0x80000000uL) + +#define INTC_ICDICFR31_TINT80_0 (0x00000001uL) +#define INTC_ICDICFR31_TINT80_1 (0x00000002uL) +#define INTC_ICDICFR31_TINT81_0 (0x00000004uL) +#define INTC_ICDICFR31_TINT81_1 (0x00000008uL) +#define INTC_ICDICFR31_TINT82_0 (0x00000010uL) +#define INTC_ICDICFR31_TINT82_1 (0x00000020uL) +#define INTC_ICDICFR31_TINT83_0 (0x00000040uL) +#define INTC_ICDICFR31_TINT83_1 (0x00000080uL) +#define INTC_ICDICFR31_TINT84_0 (0x00000100uL) +#define INTC_ICDICFR31_TINT84_1 (0x00000200uL) +#define INTC_ICDICFR31_TINT85_0 (0x00000400uL) +#define INTC_ICDICFR31_TINT85_1 (0x00000800uL) +#define INTC_ICDICFR31_TINT86_0 (0x00001000uL) +#define INTC_ICDICFR31_TINT86_1 (0x00002000uL) +#define INTC_ICDICFR31_TINT87_0 (0x00004000uL) +#define INTC_ICDICFR31_TINT87_1 (0x00008000uL) +#define INTC_ICDICFR31_TINT88_0 (0x00010000uL) +#define INTC_ICDICFR31_TINT88_1 (0x00020000uL) +#define INTC_ICDICFR31_TINT89_0 (0x00040000uL) +#define INTC_ICDICFR31_TINT89_1 (0x00080000uL) +#define INTC_ICDICFR31_TINT90_0 (0x00100000uL) +#define INTC_ICDICFR31_TINT90_1 (0x00200000uL) +#define INTC_ICDICFR31_TINT91_0 (0x00400000uL) +#define INTC_ICDICFR31_TINT91_1 (0x00800000uL) +#define INTC_ICDICFR31_TINT92_0 (0x01000000uL) +#define INTC_ICDICFR31_TINT92_1 (0x02000000uL) +#define INTC_ICDICFR31_TINT93_0 (0x04000000uL) +#define INTC_ICDICFR31_TINT93_1 (0x08000000uL) +#define INTC_ICDICFR31_TINT94_0 (0x10000000uL) +#define INTC_ICDICFR31_TINT94_1 (0x20000000uL) +#define INTC_ICDICFR31_TINT95_0 (0x40000000uL) +#define INTC_ICDICFR31_TINT95_1 (0x80000000uL) + +#define INTC_ICDICFR32_TINT96_0 (0x00000001uL) +#define INTC_ICDICFR32_TINT96_1 (0x00000002uL) +#define INTC_ICDICFR32_TINT97_0 (0x00000004uL) +#define INTC_ICDICFR32_TINT97_1 (0x00000008uL) +#define INTC_ICDICFR32_TINT98_0 (0x00000010uL) +#define INTC_ICDICFR32_TINT98_1 (0x00000020uL) +#define INTC_ICDICFR32_TINT99_0 (0x00000040uL) +#define INTC_ICDICFR32_TINT99_1 (0x00000080uL) +#define INTC_ICDICFR32_TINT100_0 (0x00000100uL) +#define INTC_ICDICFR32_TINT100_1 (0x00000200uL) +#define INTC_ICDICFR32_TINT101_0 (0x00000400uL) +#define INTC_ICDICFR32_TINT101_1 (0x00000800uL) +#define INTC_ICDICFR32_TINT102_0 (0x00001000uL) +#define INTC_ICDICFR32_TINT102_1 (0x00002000uL) +#define INTC_ICDICFR32_TINT103_0 (0x00004000uL) +#define INTC_ICDICFR32_TINT103_1 (0x00008000uL) +#define INTC_ICDICFR32_TINT104_0 (0x00010000uL) +#define INTC_ICDICFR32_TINT104_1 (0x00020000uL) +#define INTC_ICDICFR32_TINT105_0 (0x00040000uL) +#define INTC_ICDICFR32_TINT105_1 (0x00080000uL) +#define INTC_ICDICFR32_TINT106_0 (0x00100000uL) +#define INTC_ICDICFR32_TINT106_1 (0x00200000uL) +#define INTC_ICDICFR32_TINT107_0 (0x00400000uL) +#define INTC_ICDICFR32_TINT107_1 (0x00800000uL) +#define INTC_ICDICFR32_TINT108_0 (0x01000000uL) +#define INTC_ICDICFR32_TINT108_1 (0x02000000uL) +#define INTC_ICDICFR32_TINT109_0 (0x04000000uL) +#define INTC_ICDICFR32_TINT109_1 (0x08000000uL) +#define INTC_ICDICFR32_TINT110_0 (0x10000000uL) +#define INTC_ICDICFR32_TINT110_1 (0x20000000uL) +#define INTC_ICDICFR32_TINT111_0 (0x40000000uL) +#define INTC_ICDICFR32_TINT111_1 (0x80000000uL) + +#define INTC_ICDICFR33_TINT112_0 (0x00000001uL) +#define INTC_ICDICFR33_TINT112_1 (0x00000002uL) +#define INTC_ICDICFR33_TINT113_0 (0x00000004uL) +#define INTC_ICDICFR33_TINT113_1 (0x00000008uL) +#define INTC_ICDICFR33_TINT114_0 (0x00000010uL) +#define INTC_ICDICFR33_TINT114_1 (0x00000020uL) +#define INTC_ICDICFR33_TINT115_0 (0x00000040uL) +#define INTC_ICDICFR33_TINT115_1 (0x00000080uL) +#define INTC_ICDICFR33_TINT116_0 (0x00000100uL) +#define INTC_ICDICFR33_TINT116_1 (0x00000200uL) +#define INTC_ICDICFR33_TINT117_0 (0x00000400uL) +#define INTC_ICDICFR33_TINT117_1 (0x00000800uL) +#define INTC_ICDICFR33_TINT118_0 (0x00001000uL) +#define INTC_ICDICFR33_TINT118_1 (0x00002000uL) +#define INTC_ICDICFR33_TINT119_0 (0x00004000uL) +#define INTC_ICDICFR33_TINT119_1 (0x00008000uL) +#define INTC_ICDICFR33_TINT120_0 (0x00010000uL) +#define INTC_ICDICFR33_TINT120_1 (0x00020000uL) +#define INTC_ICDICFR33_TINT121_0 (0x00040000uL) +#define INTC_ICDICFR33_TINT121_1 (0x00080000uL) +#define INTC_ICDICFR33_TINT122_0 (0x00100000uL) +#define INTC_ICDICFR33_TINT122_1 (0x00200000uL) +#define INTC_ICDICFR33_TINT123_0 (0x00400000uL) +#define INTC_ICDICFR33_TINT123_1 (0x00800000uL) +#define INTC_ICDICFR33_TINT124_0 (0x01000000uL) +#define INTC_ICDICFR33_TINT124_1 (0x02000000uL) +#define INTC_ICDICFR33_TINT125_0 (0x04000000uL) +#define INTC_ICDICFR33_TINT125_1 (0x08000000uL) +#define INTC_ICDICFR33_TINT126_0 (0x10000000uL) +#define INTC_ICDICFR33_TINT126_1 (0x20000000uL) +#define INTC_ICDICFR33_TINT127_0 (0x40000000uL) +#define INTC_ICDICFR33_TINT127_1 (0x80000000uL) + +#define INTC_ICDICFR34_TINT128_0 (0x00000001uL) +#define INTC_ICDICFR34_TINT128_1 (0x00000002uL) +#define INTC_ICDICFR34_TINT129_0 (0x00000004uL) +#define INTC_ICDICFR34_TINT129_1 (0x00000008uL) +#define INTC_ICDICFR34_TINT130_0 (0x00000010uL) +#define INTC_ICDICFR34_TINT130_1 (0x00000020uL) +#define INTC_ICDICFR34_TINT131_0 (0x00000040uL) +#define INTC_ICDICFR34_TINT131_1 (0x00000080uL) +#define INTC_ICDICFR34_TINT132_0 (0x00000100uL) +#define INTC_ICDICFR34_TINT132_1 (0x00000200uL) +#define INTC_ICDICFR34_TINT133_0 (0x00000400uL) +#define INTC_ICDICFR34_TINT133_1 (0x00000800uL) +#define INTC_ICDICFR34_TINT134_0 (0x00001000uL) +#define INTC_ICDICFR34_TINT134_1 (0x00002000uL) +#define INTC_ICDICFR34_TINT135_0 (0x00004000uL) +#define INTC_ICDICFR34_TINT135_1 (0x00008000uL) +#define INTC_ICDICFR34_TINT136_0 (0x00010000uL) +#define INTC_ICDICFR34_TINT136_1 (0x00020000uL) +#define INTC_ICDICFR34_TINT137_0 (0x00040000uL) +#define INTC_ICDICFR34_TINT137_1 (0x00080000uL) +#define INTC_ICDICFR34_TINT138_0 (0x00100000uL) +#define INTC_ICDICFR34_TINT138_1 (0x00200000uL) +#define INTC_ICDICFR34_TINT139_0 (0x00400000uL) +#define INTC_ICDICFR34_TINT139_1 (0x00800000uL) +#define INTC_ICDICFR34_TINT140_0 (0x01000000uL) +#define INTC_ICDICFR34_TINT140_1 (0x02000000uL) +#define INTC_ICDICFR34_TINT141_0 (0x04000000uL) +#define INTC_ICDICFR34_TINT141_1 (0x08000000uL) +#define INTC_ICDICFR34_TINT142_0 (0x10000000uL) +#define INTC_ICDICFR34_TINT142_1 (0x20000000uL) +#define INTC_ICDICFR34_TINT143_0 (0x40000000uL) +#define INTC_ICDICFR34_TINT143_1 (0x80000000uL) + +#define INTC_ICDICFR35_TINT144_0 (0x00000001uL) +#define INTC_ICDICFR35_TINT144_1 (0x00000002uL) +#define INTC_ICDICFR35_TINT145_0 (0x00000004uL) +#define INTC_ICDICFR35_TINT145_1 (0x00000008uL) +#define INTC_ICDICFR35_TINT146_0 (0x00000010uL) +#define INTC_ICDICFR35_TINT146_1 (0x00000020uL) +#define INTC_ICDICFR35_TINT147_0 (0x00000040uL) +#define INTC_ICDICFR35_TINT147_1 (0x00000080uL) +#define INTC_ICDICFR35_TINT148_0 (0x00000100uL) +#define INTC_ICDICFR35_TINT148_1 (0x00000200uL) +#define INTC_ICDICFR35_TINT149_0 (0x00000400uL) +#define INTC_ICDICFR35_TINT149_1 (0x00000800uL) +#define INTC_ICDICFR35_TINT150_0 (0x00001000uL) +#define INTC_ICDICFR35_TINT150_1 (0x00002000uL) +#define INTC_ICDICFR35_TINT151_0 (0x00004000uL) +#define INTC_ICDICFR35_TINT151_1 (0x00008000uL) +#define INTC_ICDICFR35_TINT152_0 (0x00010000uL) +#define INTC_ICDICFR35_TINT152_1 (0x00020000uL) +#define INTC_ICDICFR35_TINT153_0 (0x00040000uL) +#define INTC_ICDICFR35_TINT153_1 (0x00080000uL) +#define INTC_ICDICFR35_TINT154_0 (0x00100000uL) +#define INTC_ICDICFR35_TINT154_1 (0x00200000uL) +#define INTC_ICDICFR35_TINT155_0 (0x00400000uL) +#define INTC_ICDICFR35_TINT155_1 (0x00800000uL) +#define INTC_ICDICFR35_TINT156_0 (0x01000000uL) +#define INTC_ICDICFR35_TINT156_1 (0x02000000uL) +#define INTC_ICDICFR35_TINT157_0 (0x04000000uL) +#define INTC_ICDICFR35_TINT157_1 (0x08000000uL) +#define INTC_ICDICFR35_TINT158_0 (0x10000000uL) +#define INTC_ICDICFR35_TINT158_1 (0x20000000uL) +#define INTC_ICDICFR35_TINT159_0 (0x40000000uL) +#define INTC_ICDICFR35_TINT159_1 (0x80000000uL) + +#define INTC_ICDICFR36_TINT160_0 (0x00000001uL) +#define INTC_ICDICFR36_TINT160_1 (0x00000002uL) +#define INTC_ICDICFR36_TINT161_0 (0x00000004uL) +#define INTC_ICDICFR36_TINT161_1 (0x00000008uL) +#define INTC_ICDICFR36_TINT162_0 (0x00000010uL) +#define INTC_ICDICFR36_TINT162_1 (0x00000020uL) +#define INTC_ICDICFR36_TINT163_0 (0x00000040uL) +#define INTC_ICDICFR36_TINT163_1 (0x00000080uL) +#define INTC_ICDICFR36_TINT164_0 (0x00000100uL) +#define INTC_ICDICFR36_TINT164_1 (0x00000200uL) +#define INTC_ICDICFR36_TINT165_0 (0x00000400uL) +#define INTC_ICDICFR36_TINT165_1 (0x00000800uL) +#define INTC_ICDICFR36_TINT166_0 (0x00001000uL) +#define INTC_ICDICFR36_TINT166_1 (0x00002000uL) +#define INTC_ICDICFR36_TINT167_0 (0x00004000uL) +#define INTC_ICDICFR36_TINT167_1 (0x00008000uL) +#define INTC_ICDICFR36_TINT168_0 (0x00010000uL) +#define INTC_ICDICFR36_TINT168_1 (0x00020000uL) +#define INTC_ICDICFR36_TINT169_0 (0x00040000uL) +#define INTC_ICDICFR36_TINT169_1 (0x00080000uL) +#define INTC_ICDICFR36_TINT170_0 (0x00100000uL) +#define INTC_ICDICFR36_TINT170_1 (0x00200000uL) + +#define INTC_ICDSGIR_SGIINTID (0x0000000FuL) +#define INTC_ICDSGIR_SATT (0x00008000uL) +#define INTC_ICDSGIR_CPUTargetList (0x00FF0000uL) +#define INTC_ICDSGIR_TargetListFilter (0x03000000uL) + +#define INTC_ICCICR_EnableS (0x00000001uL) +#define INTC_ICCICR_EnableNS (0x00000002uL) +#define INTC_ICCICR_AckCtl (0x00000004uL) +#define INTC_ICCICR_FIQEn (0x00000008uL) +#define INTC_ICCICR_SBPR (0x00000010uL) + +#define INTC_ICCPMR_Priority (0x000000FFuL) + +#define INTC_ICCBPR_Binarypoint (0x00000007uL) + +#define INTC_ICCIAR_ACKINTID (0x000003FFuL) +#define INTC_ICCIAR_CPUID (0x00001C00uL) + +#define INTC_ICCEOIR_EOIINTID (0x000003FFuL) +#define INTC_ICCEOIR_CPUID (0x00001C00uL) + +#define INTC_ICCRPR_Priority (0x000000FFuL) + +#define INTC_ICCHPIR_PENDINTID (0x000003FFuL) +#define INTC_ICCHPIR_CPUID (0x00001C00uL) + +#define INTC_ICCABPR_Binarypoint (0x00000007uL) + +#define INTC_ICCIIDR_Implementer (0x00000FFFuL) +#define INTC_ICCIIDR_Revision (0x0000F000uL) +#define INTC_ICCIIDR_Architecture_version (0x000F0000uL) +#define INTC_ICCIIDR_ProductID (0xFFF00000uL) + +#define INTC_ICR0_NMIF (0x0002u) +#define INTC_ICR0_NMIE (0x0100u) +#define INTC_ICR0_NMIL (0x8000u) + +#define INTC_ICR1_IRQ00S (0x0001u) +#define INTC_ICR1_IRQ01S (0x0002u) +#define INTC_ICR1_IRQ10S (0x0004u) +#define INTC_ICR1_IRQ11S (0x0008u) +#define INTC_ICR1_IRQ20S (0x0010u) +#define INTC_ICR1_IRQ21S (0x0020u) +#define INTC_ICR1_IRQ30S (0x0040u) +#define INTC_ICR1_IRQ31S (0x0080u) +#define INTC_ICR1_IRQ40S (0x0100u) +#define INTC_ICR1_IRQ41S (0x0200u) +#define INTC_ICR1_IRQ50S (0x0400u) +#define INTC_ICR1_IRQ51S (0x0800u) +#define INTC_ICR1_IRQ60S (0x1000u) +#define INTC_ICR1_IRQ61S (0x2000u) +#define INTC_ICR1_IRQ70S (0x4000u) +#define INTC_ICR1_IRQ71S (0x8000u) + +#define INTC_IRQRR_IRQ0F (0x0001u) +#define INTC_IRQRR_IRQ1F (0x0002u) +#define INTC_IRQRR_IRQ2F (0x0004u) +#define INTC_IRQRR_IRQ3F (0x0008u) +#define INTC_IRQRR_IRQ4F (0x0010u) +#define INTC_IRQRR_IRQ5F (0x0020u) +#define INTC_IRQRR_IRQ6F (0x0040u) +#define INTC_IRQRR_IRQ7F (0x0080u) + + +/* ==== Shift values for IO registers ==== */ +#define INTC_ICDDCR_Enable_SHIFT (0u) + +#define INTC_ICDICTR_ITLinesNumber_SHIFT (0u) +#define INTC_ICDICTR_CPUNumber_SHIFT (5u) +#define INTC_ICDICTR_SecurityExtn_SHIFT (10u) +#define INTC_ICDICTR_LSPI_SHIFT (11u) + +#define INTC_ICDIIDR_Implementer_SHIFT (0u) +#define INTC_ICDIIDR_Revision_SHIFT (12u) +#define INTC_ICDIIDR_Variant_SHIFT (16u) +#define INTC_ICDIIDR_ProductID_SHIFT (24u) + +#define INTC_ICDISR0_SW0_SHIFT (0u) +#define INTC_ICDISR0_SW1_SHIFT (1u) +#define INTC_ICDISR0_SW2_SHIFT (2u) +#define INTC_ICDISR0_SW3_SHIFT (3u) +#define INTC_ICDISR0_SW4_SHIFT (4u) +#define INTC_ICDISR0_SW5_SHIFT (5u) +#define INTC_ICDISR0_SW6_SHIFT (6u) +#define INTC_ICDISR0_SW7_SHIFT (7u) +#define INTC_ICDISR0_SW8_SHIFT (8u) +#define INTC_ICDISR0_SW9_SHIFT (9u) +#define INTC_ICDISR0_SW10_SHIFT (10u) +#define INTC_ICDISR0_SW11_SHIFT (11u) +#define INTC_ICDISR0_SW12_SHIFT (12u) +#define INTC_ICDISR0_SW13_SHIFT (13u) +#define INTC_ICDISR0_SW14_SHIFT (14u) +#define INTC_ICDISR0_SW15_SHIFT (15u) +#define INTC_ICDISR0_PMUIRQ0_SHIFT (16u) +#define INTC_ICDISR0_COMMRX0_SHIFT (17u) +#define INTC_ICDISR0_COMMTX0_SHIFT (18u) +#define INTC_ICDISR0_CTIIRQ0_SHIFT (19u) + +#define INTC_ICDISR1_IRQ0_SHIFT (0u) +#define INTC_ICDISR1_IRQ1_SHIFT (1u) +#define INTC_ICDISR1_IRQ2_SHIFT (2u) +#define INTC_ICDISR1_IRQ3_SHIFT (3u) +#define INTC_ICDISR1_IRQ4_SHIFT (4u) +#define INTC_ICDISR1_IRQ5_SHIFT (5u) +#define INTC_ICDISR1_IRQ6_SHIFT (6u) +#define INTC_ICDISR1_IRQ7_SHIFT (7u) +#define INTC_ICDISR1_PL310ERR_SHIFT (8u) +#define INTC_ICDISR1_DMAINT0_SHIFT (9u) +#define INTC_ICDISR1_DMAINT1_SHIFT (10u) +#define INTC_ICDISR1_DMAINT2_SHIFT (11u) +#define INTC_ICDISR1_DMAINT3_SHIFT (12u) +#define INTC_ICDISR1_DMAINT4_SHIFT (13u) +#define INTC_ICDISR1_DMAINT5_SHIFT (14u) +#define INTC_ICDISR1_DMAINT6_SHIFT (15u) +#define INTC_ICDISR1_DMAINT7_SHIFT (16u) +#define INTC_ICDISR1_DMAINT8_SHIFT (17u) +#define INTC_ICDISR1_DMAINT9_SHIFT (18u) +#define INTC_ICDISR1_DMAINT10_SHIFT (19u) +#define INTC_ICDISR1_DMAINT11_SHIFT (20u) +#define INTC_ICDISR1_DMAINT12_SHIFT (21u) +#define INTC_ICDISR1_DMAINT13_SHIFT (22u) +#define INTC_ICDISR1_DMAINT14_SHIFT (23u) +#define INTC_ICDISR1_DMAINT15_SHIFT (24u) +#define INTC_ICDISR1_DMAERR_SHIFT (25u) + +#define INTC_ICDISR2_USBI0_SHIFT (9u) +#define INTC_ICDISR2_USBI1_SHIFT (10u) +#define INTC_ICDISR2_S0_VI_VSYNC0_SHIFT (11u) +#define INTC_ICDISR2_S0_LO_VSYNC0_SHIFT (12u) +#define INTC_ICDISR2_S0_VSYNCERR0_SHIFT (13u) +#define INTC_ICDISR2_GR3_VLINE0_SHIFT (14u) +#define INTC_ICDISR2_S0_VFIELD0_SHIFT (15u) +#define INTC_ICDISR2_IV1_VBUFERR0_SHIFT (16u) +#define INTC_ICDISR2_IV3_VBUFERR0_SHIFT (17u) +#define INTC_ICDISR2_IV5_VBUFERR0_SHIFT (18u) +#define INTC_ICDISR2_IV6_VBUFERR0_SHIFT (19u) +#define INTC_ICDISR2_S0_WLINE0_SHIFT (20u) +#define INTC_ICDISR2_S1_VI_VSYNC0_SHIFT (21u) +#define INTC_ICDISR2_S1_LO_VSYNC0_SHIFT (22u) +#define INTC_ICDISR2_S1_VSYNCERR0_SHIFT (23u) +#define INTC_ICDISR2_S1_VFIELD0_SHIFT (24u) +#define INTC_ICDISR2_IV2_VBUFERR0_SHIFT (25u) +#define INTC_ICDISR2_IV4_VBUFERR0_SHIFT (26u) +#define INTC_ICDISR2_S1_WLINE0_SHIFT (27u) +#define INTC_ICDISR2_OIR_VI_VSYNC0_SHIFT (28u) +#define INTC_ICDISR2_OIR_LO_VSYNC0_SHIFT (29u) +#define INTC_ICDISR2_OIR_VSYNCERR0_SHIFT (30u) +#define INTC_ICDISR2_OIR_VFIELD0_SHIFT (31u) + +#define INTC_ICDISR3_IV7_VBUFERR0_SHIFT (0u) +#define INTC_ICDISR3_IV8_VBUFERR0_SHIFT (1u) +#define INTC_ICDISR3_S0_VI_VSYNC1_SHIFT (3u) +#define INTC_ICDISR3_S0_LO_VSYNC1_SHIFT (4u) +#define INTC_ICDISR3_S0_VSYNCERR1_SHIFT (5u) +#define INTC_ICDISR3_GR3_VLINE1_SHIFT (6u) +#define INTC_ICDISR3_S0_VFIELD1_SHIFT (7u) +#define INTC_ICDISR3_IV1_VBUFERR1_SHIFT (8u) +#define INTC_ICDISR3_IV3_VBUFERR1_SHIFT (9u) +#define INTC_ICDISR3_IV5_VBUFERR1_SHIFT (10u) +#define INTC_ICDISR3_IV6_VBUFERR1_SHIFT (11u) +#define INTC_ICDISR3_S0_WLINE1_SHIFT (12u) +#define INTC_ICDISR3_S1_VI_VSYNC1_SHIFT (13u) +#define INTC_ICDISR3_S1_LO_VSYNC1_SHIFT (14u) +#define INTC_ICDISR3_S1_VSYNCERR1_SHIFT (15u) +#define INTC_ICDISR3_S1_VFIELD1_SHIFT (16u) +#define INTC_ICDISR3_IV2_VBUFERR1_SHIFT (17u) +#define INTC_ICDISR3_IV4_VBUFERR1_SHIFT (18u) +#define INTC_ICDISR3_S1_WLINE1_SHIFT (19u) +#define INTC_ICDISR3_OIR_VI_VSYNC1_SHIFT (20u) +#define INTC_ICDISR3_OIR_LO_VSYNC1_SHIFT (21u) +#define INTC_ICDISR3_OIR_VLINE1_SHIFT (22u) +#define INTC_ICDISR3_OIR_VFIELD1_SHIFT (23u) +#define INTC_ICDISR3_IV7_VBUFERR1_SHIFT (24u) +#define INTC_ICDISR3_IV8_VBUFERR1_SHIFT (25u) +#define INTC_ICDISR3_IMRDI_SHIFT (27u) +#define INTC_ICDISR3_IMR2I0_SHIFT (28u) +#define INTC_ICDISR3_IMR2I1_SHIFT (29u) +#define INTC_ICDISR3_JEDI_SHIFT (30u) +#define INTC_ICDISR3_JDTI_SHIFT (31u) + +#define INTC_ICDISR4_CMP0_SHIFT (0u) +#define INTC_ICDISR4_CMP1_SHIFT (1u) +#define INTC_ICDISR4_INT0_SHIFT (2u) +#define INTC_ICDISR4_INT1_SHIFT (3u) +#define INTC_ICDISR4_INT2_SHIFT (4u) +#define INTC_ICDISR4_INT3_SHIFT (5u) +#define INTC_ICDISR4_OSTM0TINT_SHIFT (6u) +#define INTC_ICDISR4_OSTM1TINT_SHIFT (7u) +#define INTC_ICDISR4_CMI_SHIFT (8u) +#define INTC_ICDISR4_WTOUT_SHIFT (9u) +#define INTC_ICDISR4_ITI_SHIFT (10u) +#define INTC_ICDISR4_TGI0A_SHIFT (11u) +#define INTC_ICDISR4_TGI0B_SHIFT (12u) +#define INTC_ICDISR4_TGI0C_SHIFT (13u) +#define INTC_ICDISR4_TGI0D_SHIFT (14u) +#define INTC_ICDISR4_TGI0V_SHIFT (15u) +#define INTC_ICDISR4_TGI0E_SHIFT (16u) +#define INTC_ICDISR4_TGI0F_SHIFT (17u) +#define INTC_ICDISR4_TGI1A_SHIFT (18u) +#define INTC_ICDISR4_TGI1B_SHIFT (19u) +#define INTC_ICDISR4_TGI1V_SHIFT (20u) +#define INTC_ICDISR4_TGI1U_SHIFT (21u) +#define INTC_ICDISR4_TGI2A_SHIFT (22u) +#define INTC_ICDISR4_TGI2B_SHIFT (23u) +#define INTC_ICDISR4_TGI2V_SHIFT (24u) +#define INTC_ICDISR4_TGI2U_SHIFT (25u) +#define INTC_ICDISR4_TGI3A_SHIFT (26u) +#define INTC_ICDISR4_TGI3B_SHIFT (27u) +#define INTC_ICDISR4_TGI3C_SHIFT (28u) +#define INTC_ICDISR4_TGI3D_SHIFT (29u) +#define INTC_ICDISR4_TGI3V_SHIFT (30u) +#define INTC_ICDISR4_TGI4A_SHIFT (31u) + +#define INTC_ICDISR5_TGI4B_SHIFT (0u) +#define INTC_ICDISR5_TGI4C_SHIFT (1u) +#define INTC_ICDISR5_TGI4D_SHIFT (2u) +#define INTC_ICDISR5_TGI4V_SHIFT (3u) +#define INTC_ICDISR5_CMI1_SHIFT (4u) +#define INTC_ICDISR5_CMI2_SHIFT (5u) +#define INTC_ICDISR5_SGDEI0_SHIFT (6u) +#define INTC_ICDISR5_SGDEI1_SHIFT (7u) +#define INTC_ICDISR5_SGDEI2_SHIFT (8u) +#define INTC_ICDISR5_SGDEI3_SHIFT (9u) +#define INTC_ICDISR5_ADI_SHIFT (10u) +#define INTC_ICDISR5_LMTI_SHIFT (11u) +#define INTC_ICDISR5_SSII0_SHIFT (12u) +#define INTC_ICDISR5_SSIRXI0_SHIFT (13u) +#define INTC_ICDISR5_SSITXI0_SHIFT (14u) +#define INTC_ICDISR5_SSII1_SHIFT (15u) +#define INTC_ICDISR5_SSIRXI1_SHIFT (16u) +#define INTC_ICDISR5_SSITXI1_SHIFT (17u) +#define INTC_ICDISR5_SSII2_SHIFT (18u) +#define INTC_ICDISR5_SSIRTI2_SHIFT (19u) +#define INTC_ICDISR5_SSII3_SHIFT (20u) +#define INTC_ICDISR5_SSIRXI3_SHIFT (21u) +#define INTC_ICDISR5_SSITXI3_SHIFT (22u) +#define INTC_ICDISR5_SSII4_SHIFT (23u) +#define INTC_ICDISR5_SSIRTI4_SHIFT (24u) +#define INTC_ICDISR5_SSII5_SHIFT (25u) +#define INTC_ICDISR5_SSIRXI5_SHIFT (26u) +#define INTC_ICDISR5_SSITXI5_SHIFT (27u) +#define INTC_ICDISR5_SPDIFI_SHIFT (28u) +#define INTC_ICDISR5_INTIICTEI0_SHIFT (29u) +#define INTC_ICDISR5_INTIICRI0_SHIFT (30u) +#define INTC_ICDISR5_INTIICTI0_SHIFT (31u) + +#define INTC_ICDISR6_INTIICSPI0_SHIFT (0u) +#define INTC_ICDISR6_INTIICSTI0_SHIFT (1u) +#define INTC_ICDISR6_INTIICNAKI0_SHIFT (2u) +#define INTC_ICDISR6_INTIICALI0_SHIFT (3u) +#define INTC_ICDISR6_INTIICTMOI0_SHIFT (4u) +#define INTC_ICDISR6_INTIICTEI1_SHIFT (5u) +#define INTC_ICDISR6_INTIICRI1_SHIFT (6u) +#define INTC_ICDISR6_INTIICTI1_SHIFT (7u) +#define INTC_ICDISR6_INTIICSPI1_SHIFT (8u) +#define INTC_ICDISR6_INTIICSTI1_SHIFT (9u) +#define INTC_ICDISR6_INTIICNAKI1_SHIFT (10u) +#define INTC_ICDISR6_INTIICALI1_SHIFT (11u) +#define INTC_ICDISR6_INTIICTMOI1_SHIFT (12u) +#define INTC_ICDISR6_INTIICTEI2_SHIFT (13u) +#define INTC_ICDISR6_INTIICRI2_SHIFT (14u) +#define INTC_ICDISR6_INTIICTI2_SHIFT (15u) +#define INTC_ICDISR6_INTIICSPI2_SHIFT (16u) +#define INTC_ICDISR6_INTIICSTI2_SHIFT (17u) +#define INTC_ICDISR6_INTIICNAKI2_SHIFT (18u) +#define INTC_ICDISR6_INTIICALI2_SHIFT (19u) +#define INTC_ICDISR6_INTIICTMOI2_SHIFT (20u) +#define INTC_ICDISR6_INTIICTEI3_SHIFT (21u) +#define INTC_ICDISR6_INTIICRI3_SHIFT (22u) +#define INTC_ICDISR6_INTIICTI3_SHIFT (23u) +#define INTC_ICDISR6_INTIICSPI3_SHIFT (24u) +#define INTC_ICDISR6_INTIICSTI3_SHIFT (25u) +#define INTC_ICDISR6_INTIICNAKI3_SHIFT (26u) +#define INTC_ICDISR6_INTIICALI3_SHIFT (27u) +#define INTC_ICDISR6_INTIICTMOI3_SHIFT (28u) +#define INTC_ICDISR6_BRI0_SHIFT (29u) +#define INTC_ICDISR6_ERI0_SHIFT (30u) +#define INTC_ICDISR6_RXI0_SHIFT (31u) + +#define INTC_ICDISR7_TXI0_SHIFT (0u) +#define INTC_ICDISR7_BRI1_SHIFT (1u) +#define INTC_ICDISR7_ERI1_SHIFT (2u) +#define INTC_ICDISR7_RXI1_SHIFT (3u) +#define INTC_ICDISR7_TXI1_SHIFT (4u) +#define INTC_ICDISR7_BRI2_SHIFT (5u) +#define INTC_ICDISR7_ERI2_SHIFT (6u) +#define INTC_ICDISR7_RXI2_SHIFT (7u) +#define INTC_ICDISR7_TXI2_SHIFT (8u) +#define INTC_ICDISR7_BRI3_SHIFT (9u) +#define INTC_ICDISR7_ERI3_SHIFT (10u) +#define INTC_ICDISR7_RXI3_SHIFT (11u) +#define INTC_ICDISR7_TXI3_SHIFT (12u) +#define INTC_ICDISR7_BRI4_SHIFT (13u) +#define INTC_ICDISR7_ERI4_SHIFT (14u) +#define INTC_ICDISR7_RXI4_SHIFT (15u) +#define INTC_ICDISR7_TXI4_SHIFT (16u) +#define INTC_ICDISR7_BRI5_SHIFT (17u) +#define INTC_ICDISR7_ERI5_SHIFT (18u) +#define INTC_ICDISR7_RXI5_SHIFT (19u) +#define INTC_ICDISR7_TXI5_SHIFT (20u) +#define INTC_ICDISR7_BRI6_SHIFT (21u) +#define INTC_ICDISR7_ERI6_SHIFT (22u) +#define INTC_ICDISR7_RXI6_SHIFT (23u) +#define INTC_ICDISR7_TXI6_SHIFT (24u) +#define INTC_ICDISR7_BRI7_SHIFT (25u) +#define INTC_ICDISR7_ERI7_SHIFT (26u) +#define INTC_ICDISR7_RXI7_SHIFT (27u) +#define INTC_ICDISR7_TXI7_SHIFT (28u) +#define INTC_ICDISR7_INTRCANGERR_SHIFT (29u) +#define INTC_ICDISR7_INTRCANGRECC_SHIFT (30u) +#define INTC_ICDISR7_INTRCAN0REC_SHIFT (31u) + +#define INTC_ICDISR8_INTRCAN0ERR_SHIFT (0u) +#define INTC_ICDISR8_INTRCAN0TRX_SHIFT (1u) +#define INTC_ICDISR8_INTRCAN1REC_SHIFT (2u) +#define INTC_ICDISR8_INTRCAN1ERR_SHIFT (3u) +#define INTC_ICDISR8_INTRCAN1TRX_SHIFT (4u) +#define INTC_ICDISR8_INTRCAN2REC_SHIFT (5u) +#define INTC_ICDISR8_INTRCAN2ERR_SHIFT (6u) +#define INTC_ICDISR8_INTRCAN2TRX_SHIFT (7u) +#define INTC_ICDISR8_INTRCAN3REC_SHIFT (8u) +#define INTC_ICDISR8_INTRCAN3ERR_SHIFT (9u) +#define INTC_ICDISR8_INTRCAN3TRX_SHIFT (10u) +#define INTC_ICDISR8_INTRCAN4REC_SHIFT (11u) +#define INTC_ICDISR8_INTRCAN4ERR_SHIFT (12u) +#define INTC_ICDISR8_INTRCAN4TRX_SHIFT (13u) +#define INTC_ICDISR8_SPEI0_SHIFT (14u) +#define INTC_ICDISR8_SPRI0_SHIFT (15u) +#define INTC_ICDISR8_SPTI0_SHIFT (16u) +#define INTC_ICDISR8_SPEI1_SHIFT (17u) +#define INTC_ICDISR8_SPRI1_SHIFT (18u) +#define INTC_ICDISR8_SPTI1_SHIFT (19u) +#define INTC_ICDISR8_SPEI2_SHIFT (20u) +#define INTC_ICDISR8_SPRI2_SHIFT (21u) +#define INTC_ICDISR8_SPTI2_SHIFT (22u) +#define INTC_ICDISR8_SPEI3_SHIFT (23u) +#define INTC_ICDISR8_SPRI3_SHIFT (24u) +#define INTC_ICDISR8_SPTI3_SHIFT (25u) +#define INTC_ICDISR8_SPEI4_SHIFT (26u) +#define INTC_ICDISR8_SPRI4_SHIFT (27u) +#define INTC_ICDISR8_SPTI4_SHIFT (28u) +#define INTC_ICDISR8_IEBBTD_SHIFT (29u) +#define INTC_ICDISR8_IEBBTERR_SHIFT (30u) +#define INTC_ICDISR8_IEBBTSTA_SHIFT (31u) + +#define INTC_ICDISR9_IEBBTV_SHIFT (0u) +#define INTC_ICDISR9_ISY_SHIFT (1u) +#define INTC_ICDISR9_IERR_SHIFT (2u) +#define INTC_ICDISR9_ITARG_SHIFT (3u) +#define INTC_ICDISR9_ISEC_SHIFT (4u) +#define INTC_ICDISR9_IBUF_SHIFT (5u) +#define INTC_ICDISR9_IREADY_SHIFT (6u) +#define INTC_ICDISR9_FLSTE_SHIFT (7u) +#define INTC_ICDISR9_FLTENDI_SHIFT (8u) +#define INTC_ICDISR9_FLTREQ0I_SHIFT (9u) +#define INTC_ICDISR9_FLTREQ1I_SHIFT (10u) +#define INTC_ICDISR9_MMC0_SHIFT (11u) +#define INTC_ICDISR9_MMC1_SHIFT (12u) +#define INTC_ICDISR9_MMC2_SHIFT (13u) +#define INTC_ICDISR9_SDHI0_3_SHIFT (14u) +#define INTC_ICDISR9_SDHI0_0_SHIFT (15u) +#define INTC_ICDISR9_SDHI0_1_SHIFT (16u) +#define INTC_ICDISR9_SDHI1_3_SHIFT (17u) +#define INTC_ICDISR9_SDHI1_0_SHIFT (18u) +#define INTC_ICDISR9_SDHI1_1_SHIFT (19u) +#define INTC_ICDISR9_ARM_SHIFT (20u) +#define INTC_ICDISR9_PRD_SHIFT (21u) +#define INTC_ICDISR9_CUP_SHIFT (22u) +#define INTC_ICDISR9_SCUAI0_SHIFT (23u) +#define INTC_ICDISR9_SCUAI1_SHIFT (24u) +#define INTC_ICDISR9_SCUFDI0_SHIFT (25u) +#define INTC_ICDISR9_SCUFDI1_SHIFT (26u) +#define INTC_ICDISR9_SCUFDI2_SHIFT (27u) +#define INTC_ICDISR9_SCUFDI3_SHIFT (28u) +#define INTC_ICDISR9_SCUFUI0_SHIFT (29u) +#define INTC_ICDISR9_SCUFUI1_SHIFT (30u) +#define INTC_ICDISR9_SCUFUI2_SHIFT (31u) + +#define INTC_ICDISR10_SCUFUI3_SHIFT (0u) +#define INTC_ICDISR10_SCUDVI0_SHIFT (1u) +#define INTC_ICDISR10_SCUDVI1_SHIFT (2u) +#define INTC_ICDISR10_SCUDVI2_SHIFT (3u) +#define INTC_ICDISR10_SCUDVI3_SHIFT (4u) +#define INTC_ICDISR10_MLB_CINT_SHIFT (5u) +#define INTC_ICDISR10_MLB_SINT_SHIFT (6u) +#define INTC_ICDISR10_DRC0_SHIFT (7u) +#define INTC_ICDISR10_DRC1_SHIFT (8u) +#define INTC_ICDISR10_LINI0_INT_T_SHIFT (11u) +#define INTC_ICDISR10_LINI0_INT_R_SHIFT (12u) +#define INTC_ICDISR10_LINI0_INT_S_SHIFT (13u) +#define INTC_ICDISR10_LINI0_INT_M_SHIFT (14u) +#define INTC_ICDISR10_LINI1_INT_T_SHIFT (15u) +#define INTC_ICDISR10_LINI1_INT_R_SHIFT (16u) +#define INTC_ICDISR10_LINI1_INT_S_SHIFT (17u) +#define INTC_ICDISR10_LINI1_INT_M_SHIFT (18u) +#define INTC_ICDISR10_ERI0_SHIFT (27u) +#define INTC_ICDISR10_RXI0_SHIFT (28u) +#define INTC_ICDISR10_TXI0_SHIFT (29u) +#define INTC_ICDISR10_TEI0_SHIFT (30u) +#define INTC_ICDISR10_ERI1_SHIFT (31u) + +#define INTC_ICDISR11_RXI1_SHIFT (0u) +#define INTC_ICDISR11_TXI1_SHIFT (1u) +#define INTC_ICDISR11_TEI1_SHIFT (2u) +#define INTC_ICDISR11_AVBI_DATA_SHIFT (3u) +#define INTC_ICDISR11_AVBI_ERROR_SHIFT (4u) +#define INTC_ICDISR11_AVBI_MANAGE_SHIFT (5u) +#define INTC_ICDISR11_AVBI_MAC_SHIFT (6u) +#define INTC_ICDISR11_ETHERI_SHIFT (7u) +#define INTC_ICDISR11_CEUI_SHIFT (12u) +#define INTC_ICDISR11_H2XMLB_ERRINT_SHIFT (29u) +#define INTC_ICDISR11_H2XIC1_ERRINT_SHIFT (30u) +#define INTC_ICDISR11_X2HPERI1_ERRINT_SHIFT (31u) + +#define INTC_ICDISR12_X2HPERI2_ERRINT_SHIFT (0u) +#define INTC_ICDISR12_X2HPERI34_ERRINT_SHIFT (1u) +#define INTC_ICDISR12_X2HPERI5_ERRINT_SHIFT (2u) +#define INTC_ICDISR12_X2HPERI67_ERRINT_SHIFT (3u) +#define INTC_ICDISR12_X2HDBGR_ERRINT_SHIFT (4u) +#define INTC_ICDISR12_X2HBSC_ERRINT_SHIFT (5u) +#define INTC_ICDISR12_X2HSPI1_ERRINT_SHIFT (6u) +#define INTC_ICDISR12_X2HSPI2_ERRINT_SHIFT (7u) +#define INTC_ICDISR12_PRRI_SHIFT (8u) +#define INTC_ICDISR12_IFEI0_SHIFT (9u) +#define INTC_ICDISR12_OFFI0_SHIFT (10u) +#define INTC_ICDISR12_PFVEI0_SHIFT (11u) +#define INTC_ICDISR12_IFEI1_SHIFT (12u) +#define INTC_ICDISR12_OFFI1_SHIFT (13u) +#define INTC_ICDISR12_PFVEI1_SHIFT (14u) + +#define INTC_ICDISR13_TINT0_SHIFT (0u) +#define INTC_ICDISR13_TINT1_SHIFT (1u) +#define INTC_ICDISR13_TINT2_SHIFT (2u) +#define INTC_ICDISR13_TINT3_SHIFT (3u) +#define INTC_ICDISR13_TINT4_SHIFT (4u) +#define INTC_ICDISR13_TINT5_SHIFT (5u) +#define INTC_ICDISR13_TINT6_SHIFT (6u) +#define INTC_ICDISR13_TINT7_SHIFT (7u) +#define INTC_ICDISR13_TINT8_SHIFT (8u) +#define INTC_ICDISR13_TINT9_SHIFT (9u) +#define INTC_ICDISR13_TINT10_SHIFT (10u) +#define INTC_ICDISR13_TINT11_SHIFT (11u) +#define INTC_ICDISR13_TINT12_SHIFT (12u) +#define INTC_ICDISR13_TINT13_SHIFT (13u) +#define INTC_ICDISR13_TINT14_SHIFT (14u) +#define INTC_ICDISR13_TINT15_SHIFT (15u) +#define INTC_ICDISR13_TINT16_SHIFT (16u) +#define INTC_ICDISR13_TINT17_SHIFT (17u) +#define INTC_ICDISR13_TINT18_SHIFT (18u) +#define INTC_ICDISR13_TINT19_SHIFT (19u) +#define INTC_ICDISR13_TINT20_SHIFT (20u) +#define INTC_ICDISR13_TINT21_SHIFT (21u) +#define INTC_ICDISR13_TINT22_SHIFT (22u) +#define INTC_ICDISR13_TINT23_SHIFT (23u) +#define INTC_ICDISR13_TINT24_SHIFT (24u) +#define INTC_ICDISR13_TINT25_SHIFT (25u) +#define INTC_ICDISR13_TINT26_SHIFT (26u) +#define INTC_ICDISR13_TINT27_SHIFT (27u) +#define INTC_ICDISR13_TINT28_SHIFT (28u) +#define INTC_ICDISR13_TINT29_SHIFT (29u) +#define INTC_ICDISR13_TINT30_SHIFT (30u) +#define INTC_ICDISR13_TINT31_SHIFT (31u) + +#define INTC_ICDISR14_TINT32_SHIFT (0u) +#define INTC_ICDISR14_TINT33_SHIFT (1u) +#define INTC_ICDISR14_TINT34_SHIFT (2u) +#define INTC_ICDISR14_TINT35_SHIFT (3u) +#define INTC_ICDISR14_TINT36_SHIFT (4u) +#define INTC_ICDISR14_TINT37_SHIFT (5u) +#define INTC_ICDISR14_TINT38_SHIFT (6u) +#define INTC_ICDISR14_TINT39_SHIFT (7u) +#define INTC_ICDISR14_TINT40_SHIFT (8u) +#define INTC_ICDISR14_TINT41_SHIFT (9u) +#define INTC_ICDISR14_TINT42_SHIFT (10u) +#define INTC_ICDISR14_TINT43_SHIFT (11u) +#define INTC_ICDISR14_TINT44_SHIFT (12u) +#define INTC_ICDISR14_TINT45_SHIFT (13u) +#define INTC_ICDISR14_TINT46_SHIFT (14u) +#define INTC_ICDISR14_TINT47_SHIFT (15u) +#define INTC_ICDISR14_TINT48_SHIFT (16u) +#define INTC_ICDISR14_TINT49_SHIFT (17u) +#define INTC_ICDISR14_TINT50_SHIFT (18u) +#define INTC_ICDISR14_TINT51_SHIFT (19u) +#define INTC_ICDISR14_TINT52_SHIFT (20u) +#define INTC_ICDISR14_TINT53_SHIFT (21u) +#define INTC_ICDISR14_TINT54_SHIFT (22u) +#define INTC_ICDISR14_TINT55_SHIFT (23u) +#define INTC_ICDISR14_TINT56_SHIFT (24u) +#define INTC_ICDISR14_TINT57_SHIFT (25u) +#define INTC_ICDISR14_TINT58_SHIFT (26u) +#define INTC_ICDISR14_TINT59_SHIFT (27u) +#define INTC_ICDISR14_TINT60_SHIFT (28u) +#define INTC_ICDISR14_TINT61_SHIFT (29u) +#define INTC_ICDISR14_TINT62_SHIFT (30u) +#define INTC_ICDISR14_TINT63_SHIFT (31u) + +#define INTC_ICDISR15_TINT64_SHIFT (0u) +#define INTC_ICDISR15_TINT65_SHIFT (1u) +#define INTC_ICDISR15_TINT66_SHIFT (2u) +#define INTC_ICDISR15_TINT67_SHIFT (3u) +#define INTC_ICDISR15_TINT68_SHIFT (4u) +#define INTC_ICDISR15_TINT69_SHIFT (5u) +#define INTC_ICDISR15_TINT70_SHIFT (6u) +#define INTC_ICDISR15_TINT71_SHIFT (7u) +#define INTC_ICDISR15_TINT72_SHIFT (8u) +#define INTC_ICDISR15_TINT73_SHIFT (9u) +#define INTC_ICDISR15_TINT74_SHIFT (10u) +#define INTC_ICDISR15_TINT75_SHIFT (11u) +#define INTC_ICDISR15_TINT76_SHIFT (12u) +#define INTC_ICDISR15_TINT77_SHIFT (13u) +#define INTC_ICDISR15_TINT78_SHIFT (14u) +#define INTC_ICDISR15_TINT79_SHIFT (15u) +#define INTC_ICDISR15_TINT80_SHIFT (16u) +#define INTC_ICDISR15_TINT81_SHIFT (17u) +#define INTC_ICDISR15_TINT82_SHIFT (18u) +#define INTC_ICDISR15_TINT83_SHIFT (19u) +#define INTC_ICDISR15_TINT84_SHIFT (20u) +#define INTC_ICDISR15_TINT85_SHIFT (21u) +#define INTC_ICDISR15_TINT86_SHIFT (22u) +#define INTC_ICDISR15_TINT87_SHIFT (23u) +#define INTC_ICDISR15_TINT88_SHIFT (24u) +#define INTC_ICDISR15_TINT89_SHIFT (25u) +#define INTC_ICDISR15_TINT90_SHIFT (26u) +#define INTC_ICDISR15_TINT91_SHIFT (27u) +#define INTC_ICDISR15_TINT92_SHIFT (28u) +#define INTC_ICDISR15_TINT93_SHIFT (29u) +#define INTC_ICDISR15_TINT94_SHIFT (30u) +#define INTC_ICDISR15_TINT95_SHIFT (31u) + +#define INTC_ICDISR16_TINT96_SHIFT (0u) +#define INTC_ICDISR16_TINT97_SHIFT (1u) +#define INTC_ICDISR16_TINT98_SHIFT (2u) +#define INTC_ICDISR16_TINT99_SHIFT (3u) +#define INTC_ICDISR16_TINT100_SHIFT (4u) +#define INTC_ICDISR16_TINT101_SHIFT (5u) +#define INTC_ICDISR16_TINT102_SHIFT (6u) +#define INTC_ICDISR16_TINT103_SHIFT (7u) +#define INTC_ICDISR16_TINT104_SHIFT (8u) +#define INTC_ICDISR16_TINT105_SHIFT (9u) +#define INTC_ICDISR16_TINT106_SHIFT (10u) +#define INTC_ICDISR16_TINT107_SHIFT (11u) +#define INTC_ICDISR16_TINT108_SHIFT (12u) +#define INTC_ICDISR16_TINT109_SHIFT (13u) +#define INTC_ICDISR16_TINT110_SHIFT (14u) +#define INTC_ICDISR16_TINT111_SHIFT (15u) +#define INTC_ICDISR16_TINT112_SHIFT (16u) +#define INTC_ICDISR16_TINT113_SHIFT (17u) +#define INTC_ICDISR16_TINT114_SHIFT (18u) +#define INTC_ICDISR16_TINT115_SHIFT (19u) +#define INTC_ICDISR16_TINT116_SHIFT (20u) +#define INTC_ICDISR16_TINT117_SHIFT (21u) +#define INTC_ICDISR16_TINT118_SHIFT (22u) +#define INTC_ICDISR16_TINT119_SHIFT (23u) +#define INTC_ICDISR16_TINT120_SHIFT (24u) +#define INTC_ICDISR16_TINT121_SHIFT (25u) +#define INTC_ICDISR16_TINT122_SHIFT (26u) +#define INTC_ICDISR16_TINT123_SHIFT (27u) +#define INTC_ICDISR16_TINT124_SHIFT (28u) +#define INTC_ICDISR16_TINT125_SHIFT (29u) +#define INTC_ICDISR16_TINT126_SHIFT (30u) +#define INTC_ICDISR16_TINT127_SHIFT (31u) + +#define INTC_ICDISR17_TINT128_SHIFT (0u) +#define INTC_ICDISR17_TINT129_SHIFT (1u) +#define INTC_ICDISR17_TINT130_SHIFT (2u) +#define INTC_ICDISR17_TINT131_SHIFT (3u) +#define INTC_ICDISR17_TINT132_SHIFT (4u) +#define INTC_ICDISR17_TINT133_SHIFT (5u) +#define INTC_ICDISR17_TINT134_SHIFT (6u) +#define INTC_ICDISR17_TINT135_SHIFT (7u) +#define INTC_ICDISR17_TINT136_SHIFT (8u) +#define INTC_ICDISR17_TINT137_SHIFT (9u) +#define INTC_ICDISR17_TINT138_SHIFT (10u) +#define INTC_ICDISR17_TINT139_SHIFT (11u) +#define INTC_ICDISR17_TINT140_SHIFT (12u) +#define INTC_ICDISR17_TINT141_SHIFT (13u) +#define INTC_ICDISR17_TINT142_SHIFT (14u) +#define INTC_ICDISR17_TINT143_SHIFT (15u) +#define INTC_ICDISR17_TINT144_SHIFT (16u) +#define INTC_ICDISR17_TINT145_SHIFT (17u) +#define INTC_ICDISR17_TINT146_SHIFT (18u) +#define INTC_ICDISR17_TINT147_SHIFT (19u) +#define INTC_ICDISR17_TINT148_SHIFT (20u) +#define INTC_ICDISR17_TINT149_SHIFT (21u) +#define INTC_ICDISR17_TINT150_SHIFT (22u) +#define INTC_ICDISR17_TINT151_SHIFT (23u) +#define INTC_ICDISR17_TINT152_SHIFT (24u) +#define INTC_ICDISR17_TINT153_SHIFT (25u) +#define INTC_ICDISR17_TINT154_SHIFT (26u) +#define INTC_ICDISR17_TINT155_SHIFT (27u) +#define INTC_ICDISR17_TINT156_SHIFT (28u) +#define INTC_ICDISR17_TINT157_SHIFT (29u) +#define INTC_ICDISR17_TINT158_SHIFT (30u) +#define INTC_ICDISR17_TINT159_SHIFT (31u) + +#define INTC_ICDISR18_TINT160_SHIFT (0u) +#define INTC_ICDISR18_TINT161_SHIFT (1u) +#define INTC_ICDISR18_TINT162_SHIFT (2u) +#define INTC_ICDISR18_TINT163_SHIFT (3u) +#define INTC_ICDISR18_TINT164_SHIFT (4u) +#define INTC_ICDISR18_TINT165_SHIFT (5u) +#define INTC_ICDISR18_TINT166_SHIFT (6u) +#define INTC_ICDISR18_TINT167_SHIFT (7u) +#define INTC_ICDISR18_TINT168_SHIFT (8u) +#define INTC_ICDISR18_TINT169_SHIFT (9u) +#define INTC_ICDISR18_TINT170_SHIFT (10u) + +#define INTC_ICDISER0_SW0_SHIFT (0u) +#define INTC_ICDISER0_SW1_SHIFT (1u) +#define INTC_ICDISER0_SW2_SHIFT (2u) +#define INTC_ICDISER0_SW3_SHIFT (3u) +#define INTC_ICDISER0_SW4_SHIFT (4u) +#define INTC_ICDISER0_SW5_SHIFT (5u) +#define INTC_ICDISER0_SW6_SHIFT (6u) +#define INTC_ICDISER0_SW7_SHIFT (7u) +#define INTC_ICDISER0_SW8_SHIFT (8u) +#define INTC_ICDISER0_SW9_SHIFT (9u) +#define INTC_ICDISER0_SW10_SHIFT (10u) +#define INTC_ICDISER0_SW11_SHIFT (11u) +#define INTC_ICDISER0_SW12_SHIFT (12u) +#define INTC_ICDISER0_SW13_SHIFT (13u) +#define INTC_ICDISER0_SW14_SHIFT (14u) +#define INTC_ICDISER0_SW15_SHIFT (15u) +#define INTC_ICDISER0_PMUIRQ0_SHIFT (16u) +#define INTC_ICDISER0_COMMRX0_SHIFT (17u) +#define INTC_ICDISER0_COMMTX0_SHIFT (18u) +#define INTC_ICDISER0_CTIIRQ0_SHIFT (19u) + +#define INTC_ICDISER1_IRQ0_SHIFT (0u) +#define INTC_ICDISER1_IRQ1_SHIFT (1u) +#define INTC_ICDISER1_IRQ2_SHIFT (2u) +#define INTC_ICDISER1_IRQ3_SHIFT (3u) +#define INTC_ICDISER1_IRQ4_SHIFT (4u) +#define INTC_ICDISER1_IRQ5_SHIFT (5u) +#define INTC_ICDISER1_IRQ6_SHIFT (6u) +#define INTC_ICDISER1_IRQ7_SHIFT (7u) +#define INTC_ICDISER1_PL310ERR_SHIFT (8u) +#define INTC_ICDISER1_DMAINT0_SHIFT (9u) +#define INTC_ICDISER1_DMAINT1_SHIFT (10u) +#define INTC_ICDISER1_DMAINT2_SHIFT (11u) +#define INTC_ICDISER1_DMAINT3_SHIFT (12u) +#define INTC_ICDISER1_DMAINT4_SHIFT (13u) +#define INTC_ICDISER1_DMAINT5_SHIFT (14u) +#define INTC_ICDISER1_DMAINT6_SHIFT (15u) +#define INTC_ICDISER1_DMAINT7_SHIFT (16u) +#define INTC_ICDISER1_DMAINT8_SHIFT (17u) +#define INTC_ICDISER1_DMAINT9_SHIFT (18u) +#define INTC_ICDISER1_DMAINT10_SHIFT (19u) +#define INTC_ICDISER1_DMAINT11_SHIFT (20u) +#define INTC_ICDISER1_DMAINT12_SHIFT (21u) +#define INTC_ICDISER1_DMAINT13_SHIFT (22u) +#define INTC_ICDISER1_DMAINT14_SHIFT (23u) +#define INTC_ICDISER1_DMAINT15_SHIFT (24u) +#define INTC_ICDISER1_DMAERR_SHIFT (25u) + +#define INTC_ICDISER2_USBI0_SHIFT (9u) +#define INTC_ICDISER2_USBI1_SHIFT (10u) +#define INTC_ICDISER2_S0_VI_VSYNC0_SHIFT (11u) +#define INTC_ICDISER2_S0_LO_VSYNC0_SHIFT (12u) +#define INTC_ICDISER2_S0_VSYNCERR0_SHIFT (13u) +#define INTC_ICDISER2_GR3_VLINE0_SHIFT (14u) +#define INTC_ICDISER2_S0_VFIELD0_SHIFT (15u) +#define INTC_ICDISER2_IV1_VBUFERR0_SHIFT (16u) +#define INTC_ICDISER2_IV3_VBUFERR0_SHIFT (17u) +#define INTC_ICDISER2_IV5_VBUFERR0_SHIFT (18u) +#define INTC_ICDISER2_IV6_VBUFERR0_SHIFT (19u) +#define INTC_ICDISER2_S0_WLINE0_SHIFT (20u) +#define INTC_ICDISER2_S1_VI_VSYNC0_SHIFT (21u) +#define INTC_ICDISER2_S1_LO_VSYNC0_SHIFT (22u) +#define INTC_ICDISER2_S1_VSYNCERR0_SHIFT (23u) +#define INTC_ICDISER2_S1_VFIELD0_SHIFT (24u) +#define INTC_ICDISER2_IV2_VBUFERR0_SHIFT (25u) +#define INTC_ICDISER2_IV4_VBUFERR0_SHIFT (26u) +#define INTC_ICDISER2_S1_WLINE0_SHIFT (27u) +#define INTC_ICDISER2_OIR_VI_VSYNC0_SHIFT (28u) +#define INTC_ICDISER2_OIR_LO_VSYNC0_SHIFT (29u) +#define INTC_ICDISER2_OIR_VSYNCERR0_SHIFT (30u) +#define INTC_ICDISER2_OIR_VFIELD0_SHIFT (31u) + +#define INTC_ICDISER3_IV7_VBUFERR0_SHIFT (0u) +#define INTC_ICDISER3_IV8_VBUFERR0_SHIFT (1u) +#define INTC_ICDISER3_S0_VI_VSYNC1_SHIFT (3u) +#define INTC_ICDISER3_S0_LO_VSYNC1_SHIFT (4u) +#define INTC_ICDISER3_S0_VSYNCERR1_SHIFT (5u) +#define INTC_ICDISER3_GR3_VLINE1_SHIFT (6u) +#define INTC_ICDISER3_S0_VFIELD1_SHIFT (7u) +#define INTC_ICDISER3_IV1_VBUFERR1_SHIFT (8u) +#define INTC_ICDISER3_IV3_VBUFERR1_SHIFT (9u) +#define INTC_ICDISER3_IV5_VBUFERR1_SHIFT (10u) +#define INTC_ICDISER3_IV6_VBUFERR1_SHIFT (11u) +#define INTC_ICDISER3_S0_WLINE1_SHIFT (12u) +#define INTC_ICDISER3_S1_VI_VSYNC1_SHIFT (13u) +#define INTC_ICDISER3_S1_LO_VSYNC1_SHIFT (14u) +#define INTC_ICDISER3_S1_VSYNCERR1_SHIFT (15u) +#define INTC_ICDISER3_S1_VFIELD1_SHIFT (16u) +#define INTC_ICDISER3_IV2_VBUFERR1_SHIFT (17u) +#define INTC_ICDISER3_IV4_VBUFERR1_SHIFT (18u) +#define INTC_ICDISER3_S1_WLINE1_SHIFT (19u) +#define INTC_ICDISER3_OIR_VI_VSYNC1_SHIFT (20u) +#define INTC_ICDISER3_OIR_LO_VSYNC1_SHIFT (21u) +#define INTC_ICDISER3_OIR_VLINE1_SHIFT (22u) +#define INTC_ICDISER3_OIR_VFIELD1_SHIFT (23u) +#define INTC_ICDISER3_IV7_VBUFERR1_SHIFT (24u) +#define INTC_ICDISER3_IV8_VBUFERR1_SHIFT (25u) +#define INTC_ICDISER3_IMRDI_SHIFT (27u) +#define INTC_ICDISER3_IMR2I0_SHIFT (28u) +#define INTC_ICDISER3_IMR2I1_SHIFT (29u) +#define INTC_ICDISER3_JEDI_SHIFT (30u) +#define INTC_ICDISER3_JDTI_SHIFT (31u) + +#define INTC_ICDISER4_CMP0_SHIFT (0u) +#define INTC_ICDISER4_CMP1_SHIFT (1u) +#define INTC_ICDISER4_INT0_SHIFT (2u) +#define INTC_ICDISER4_INT1_SHIFT (3u) +#define INTC_ICDISER4_INT2_SHIFT (4u) +#define INTC_ICDISER4_INT3_SHIFT (5u) +#define INTC_ICDISER4_OSTM0TINT_SHIFT (6u) +#define INTC_ICDISER4_OSTM1TINT_SHIFT (7u) +#define INTC_ICDISER4_CMI_SHIFT (8u) +#define INTC_ICDISER4_WTOUT_SHIFT (9u) +#define INTC_ICDISER4_ITI_SHIFT (10u) +#define INTC_ICDISER4_TGI0A_SHIFT (11u) +#define INTC_ICDISER4_TGI0B_SHIFT (12u) +#define INTC_ICDISER4_TGI0C_SHIFT (13u) +#define INTC_ICDISER4_TGI0D_SHIFT (14u) +#define INTC_ICDISER4_TGI0V_SHIFT (15u) +#define INTC_ICDISER4_TGI0E_SHIFT (16u) +#define INTC_ICDISER4_TGI0F_SHIFT (17u) +#define INTC_ICDISER4_TGI1A_SHIFT (18u) +#define INTC_ICDISER4_TGI1B_SHIFT (19u) +#define INTC_ICDISER4_TGI1V_SHIFT (20u) +#define INTC_ICDISER4_TGI1U_SHIFT (21u) +#define INTC_ICDISER4_TGI2A_SHIFT (22u) +#define INTC_ICDISER4_TGI2B_SHIFT (23u) +#define INTC_ICDISER4_TGI2V_SHIFT (24u) +#define INTC_ICDISER4_TGI2U_SHIFT (25u) +#define INTC_ICDISER4_TGI3A_SHIFT (26u) +#define INTC_ICDISER4_TGI3B_SHIFT (27u) +#define INTC_ICDISER4_TGI3C_SHIFT (28u) +#define INTC_ICDISER4_TGI3D_SHIFT (29u) +#define INTC_ICDISER4_TGI3V_SHIFT (30u) +#define INTC_ICDISER4_TGI4A_SHIFT (31u) + +#define INTC_ICDISER5_TGI4B_SHIFT (0u) +#define INTC_ICDISER5_TGI4C_SHIFT (1u) +#define INTC_ICDISER5_TGI4D_SHIFT (2u) +#define INTC_ICDISER5_TGI4V_SHIFT (3u) +#define INTC_ICDISER5_CMI1_SHIFT (4u) +#define INTC_ICDISER5_CMI2_SHIFT (5u) +#define INTC_ICDISER5_SGDEI0_SHIFT (6u) +#define INTC_ICDISER5_SGDEI1_SHIFT (7u) +#define INTC_ICDISER5_SGDEI2_SHIFT (8u) +#define INTC_ICDISER5_SGDEI3_SHIFT (9u) +#define INTC_ICDISER5_ADI_SHIFT (10u) +#define INTC_ICDISER5_LMTI_SHIFT (11u) +#define INTC_ICDISER5_SSII0_SHIFT (12u) +#define INTC_ICDISER5_SSIRXI0_SHIFT (13u) +#define INTC_ICDISER5_SSITXI0_SHIFT (14u) +#define INTC_ICDISER5_SSII1_SHIFT (15u) +#define INTC_ICDISER5_SSIRXI1_SHIFT (16u) +#define INTC_ICDISER5_SSITXI1_SHIFT (17u) +#define INTC_ICDISER5_SSII2_SHIFT (18u) +#define INTC_ICDISER5_SSIRTI2_SHIFT (19u) +#define INTC_ICDISER5_SSII3_SHIFT (20u) +#define INTC_ICDISER5_SSIRXI3_SHIFT (21u) +#define INTC_ICDISER5_SSITXI3_SHIFT (22u) +#define INTC_ICDISER5_SSII4_SHIFT (23u) +#define INTC_ICDISER5_SSIRTI4_SHIFT (24u) +#define INTC_ICDISER5_SSII5_SHIFT (25u) +#define INTC_ICDISER5_SSIRXI5_SHIFT (26u) +#define INTC_ICDISER5_SSITXI5_SHIFT (27u) +#define INTC_ICDISER5_SPDIFI_SHIFT (28u) +#define INTC_ICDISER5_INTIICTEI0_SHIFT (29u) +#define INTC_ICDISER5_INTIICRI0_SHIFT (30u) +#define INTC_ICDISER5_INTIICTI0_SHIFT (31u) + +#define INTC_ICDISER6_INTIICSPI0_SHIFT (0u) +#define INTC_ICDISER6_INTIICSTI0_SHIFT (1u) +#define INTC_ICDISER6_INTIICNAKI0_SHIFT (2u) +#define INTC_ICDISER6_INTIICALI0_SHIFT (3u) +#define INTC_ICDISER6_INTIICTMOI0_SHIFT (4u) +#define INTC_ICDISER6_INTIICTEI1_SHIFT (5u) +#define INTC_ICDISER6_INTIICRI1_SHIFT (6u) +#define INTC_ICDISER6_INTIICTI1_SHIFT (7u) +#define INTC_ICDISER6_INTIICSPI1_SHIFT (8u) +#define INTC_ICDISER6_INTIICSTI1_SHIFT (9u) +#define INTC_ICDISER6_INTIICNAKI1_SHIFT (10u) +#define INTC_ICDISER6_INTIICALI1_SHIFT (11u) +#define INTC_ICDISER6_INTIICTMOI1_SHIFT (12u) +#define INTC_ICDISER6_INTIICTEI2_SHIFT (13u) +#define INTC_ICDISER6_INTIICRI2_SHIFT (14u) +#define INTC_ICDISER6_INTIICTI2_SHIFT (15u) +#define INTC_ICDISER6_INTIICSPI2_SHIFT (16u) +#define INTC_ICDISER6_INTIICSTI2_SHIFT (17u) +#define INTC_ICDISER6_INTIICNAKI2_SHIFT (18u) +#define INTC_ICDISER6_INTIICALI2_SHIFT (19u) +#define INTC_ICDISER6_INTIICTMOI2_SHIFT (20u) +#define INTC_ICDISER6_INTIICTEI3_SHIFT (21u) +#define INTC_ICDISER6_INTIICRI3_SHIFT (22u) +#define INTC_ICDISER6_INTIICTI3_SHIFT (23u) +#define INTC_ICDISER6_INTIICSPI3_SHIFT (24u) +#define INTC_ICDISER6_INTIICSTI3_SHIFT (25u) +#define INTC_ICDISER6_INTIICNAKI3_SHIFT (26u) +#define INTC_ICDISER6_INTIICALI3_SHIFT (27u) +#define INTC_ICDISER6_INTIICTMOI3_SHIFT (28u) +#define INTC_ICDISER6_BRI0_SHIFT (29u) +#define INTC_ICDISER6_ERI0_SHIFT (30u) +#define INTC_ICDISER6_RXI0_SHIFT (31u) + +#define INTC_ICDISER7_TXI0_SHIFT (0u) +#define INTC_ICDISER7_BRI1_SHIFT (1u) +#define INTC_ICDISER7_ERI1_SHIFT (2u) +#define INTC_ICDISER7_RXI1_SHIFT (3u) +#define INTC_ICDISER7_TXI1_SHIFT (4u) +#define INTC_ICDISER7_BRI2_SHIFT (5u) +#define INTC_ICDISER7_ERI2_SHIFT (6u) +#define INTC_ICDISER7_RXI2_SHIFT (7u) +#define INTC_ICDISER7_TXI2_SHIFT (8u) +#define INTC_ICDISER7_BRI3_SHIFT (9u) +#define INTC_ICDISER7_ERI3_SHIFT (10u) +#define INTC_ICDISER7_RXI3_SHIFT (11u) +#define INTC_ICDISER7_TXI3_SHIFT (12u) +#define INTC_ICDISER7_BRI4_SHIFT (13u) +#define INTC_ICDISER7_ERI4_SHIFT (14u) +#define INTC_ICDISER7_RXI4_SHIFT (15u) +#define INTC_ICDISER7_TXI4_SHIFT (16u) +#define INTC_ICDISER7_BRI5_SHIFT (17u) +#define INTC_ICDISER7_ERI5_SHIFT (18u) +#define INTC_ICDISER7_RXI5_SHIFT (19u) +#define INTC_ICDISER7_TXI5_SHIFT (20u) +#define INTC_ICDISER7_BRI6_SHIFT (21u) +#define INTC_ICDISER7_ERI6_SHIFT (22u) +#define INTC_ICDISER7_RXI6_SHIFT (23u) +#define INTC_ICDISER7_TXI6_SHIFT (24u) +#define INTC_ICDISER7_BRI7_SHIFT (25u) +#define INTC_ICDISER7_ERI7_SHIFT (26u) +#define INTC_ICDISER7_RXI7_SHIFT (27u) +#define INTC_ICDISER7_TXI7_SHIFT (28u) +#define INTC_ICDISER7_INTRCANGERR_SHIFT (29u) +#define INTC_ICDISER7_INTRCANGRECC_SHIFT (30u) +#define INTC_ICDISER7_INTRCAN0REC_SHIFT (31u) + +#define INTC_ICDISER8_INTRCAN0ERR_SHIFT (0u) +#define INTC_ICDISER8_INTRCAN0TRX_SHIFT (1u) +#define INTC_ICDISER8_INTRCAN1REC_SHIFT (2u) +#define INTC_ICDISER8_INTRCAN1ERR_SHIFT (3u) +#define INTC_ICDISER8_INTRCAN1TRX_SHIFT (4u) +#define INTC_ICDISER8_INTRCAN2REC_SHIFT (5u) +#define INTC_ICDISER8_INTRCAN2ERR_SHIFT (6u) +#define INTC_ICDISER8_INTRCAN2TRX_SHIFT (7u) +#define INTC_ICDISER8_INTRCAN3REC_SHIFT (8u) +#define INTC_ICDISER8_INTRCAN3ERR_SHIFT (9u) +#define INTC_ICDISER8_INTRCAN3TRX_SHIFT (10u) +#define INTC_ICDISER8_INTRCAN4REC_SHIFT (11u) +#define INTC_ICDISER8_INTRCAN4ERR_SHIFT (12u) +#define INTC_ICDISER8_INTRCAN4TRX_SHIFT (13u) +#define INTC_ICDISER8_SPEI0_SHIFT (14u) +#define INTC_ICDISER8_SPRI0_SHIFT (15u) +#define INTC_ICDISER8_SPTI0_SHIFT (16u) +#define INTC_ICDISER8_SPEI1_SHIFT (17u) +#define INTC_ICDISER8_SPRI1_SHIFT (18u) +#define INTC_ICDISER8_SPTI1_SHIFT (19u) +#define INTC_ICDISER8_SPEI2_SHIFT (20u) +#define INTC_ICDISER8_SPRI2_SHIFT (21u) +#define INTC_ICDISER8_SPTI2_SHIFT (22u) +#define INTC_ICDISER8_SPEI3_SHIFT (23u) +#define INTC_ICDISER8_SPRI3_SHIFT (24u) +#define INTC_ICDISER8_SPTI3_SHIFT (25u) +#define INTC_ICDISER8_SPEI4_SHIFT (26u) +#define INTC_ICDISER8_SPRI4_SHIFT (27u) +#define INTC_ICDISER8_SPTI4_SHIFT (28u) +#define INTC_ICDISER8_IEBBTD_SHIFT (29u) +#define INTC_ICDISER8_IEBBTERR_SHIFT (30u) +#define INTC_ICDISER8_IEBBTSTA_SHIFT (31u) + +#define INTC_ICDISER9_IEBBTV_SHIFT (0u) +#define INTC_ICDISER9_ISY_SHIFT (1u) +#define INTC_ICDISER9_IERR_SHIFT (2u) +#define INTC_ICDISER9_ITARG_SHIFT (3u) +#define INTC_ICDISER9_ISEC_SHIFT (4u) +#define INTC_ICDISER9_IBUF_SHIFT (5u) +#define INTC_ICDISER9_IREADY_SHIFT (6u) +#define INTC_ICDISER9_FLSTE_SHIFT (7u) +#define INTC_ICDISER9_FLTENDI_SHIFT (8u) +#define INTC_ICDISER9_FLTREQ0I_SHIFT (9u) +#define INTC_ICDISER9_FLTREQ1I_SHIFT (10u) +#define INTC_ICDISER9_MMC0_SHIFT (11u) +#define INTC_ICDISER9_MMC1_SHIFT (12u) +#define INTC_ICDISER9_MMC2_SHIFT (13u) +#define INTC_ICDISER9_SDHI0_3_SHIFT (14u) +#define INTC_ICDISER9_SDHI0_0_SHIFT (15u) +#define INTC_ICDISER9_SDHI0_1_SHIFT (16u) +#define INTC_ICDISER9_SDHI1_3_SHIFT (17u) +#define INTC_ICDISER9_SDHI1_0_SHIFT (18u) +#define INTC_ICDISER9_SDHI1_1_SHIFT (19u) +#define INTC_ICDISER9_ARM_SHIFT (20u) +#define INTC_ICDISER9_PRD_SHIFT (21u) +#define INTC_ICDISER9_CUP_SHIFT (22u) +#define INTC_ICDISER9_SCUAI0_SHIFT (23u) +#define INTC_ICDISER9_SCUAI1_SHIFT (24u) +#define INTC_ICDISER9_SCUFDI0_SHIFT (25u) +#define INTC_ICDISER9_SCUFDI1_SHIFT (26u) +#define INTC_ICDISER9_SCUFDI2_SHIFT (27u) +#define INTC_ICDISER9_SCUFDI3_SHIFT (28u) +#define INTC_ICDISER9_SCUFUI0_SHIFT (29u) +#define INTC_ICDISER9_SCUFUI1_SHIFT (30u) +#define INTC_ICDISER9_SCUFUI2_SHIFT (31u) + +#define INTC_ICDISER10_SCUFUI3_SHIFT (0u) +#define INTC_ICDISER10_SCUDVI0_SHIFT (1u) +#define INTC_ICDISER10_SCUDVI1_SHIFT (2u) +#define INTC_ICDISER10_SCUDVI2_SHIFT (3u) +#define INTC_ICDISER10_SCUDVI3_SHIFT (4u) +#define INTC_ICDISER10_MLB_CINT_SHIFT (5u) +#define INTC_ICDISER10_MLB_SINT_SHIFT (6u) +#define INTC_ICDISER10_DRC0_SHIFT (7u) +#define INTC_ICDISER10_DRC1_SHIFT (8u) +#define INTC_ICDISER10_LINI0_INT_T_SHIFT (11u) +#define INTC_ICDISER10_LINI0_INT_R_SHIFT (12u) +#define INTC_ICDISER10_LINI0_INT_S_SHIFT (13u) +#define INTC_ICDISER10_LINI0_INT_M_SHIFT (14u) +#define INTC_ICDISER10_LINI1_INT_T_SHIFT (15u) +#define INTC_ICDISER10_LINI1_INT_R_SHIFT (16u) +#define INTC_ICDISER10_LINI1_INT_S_SHIFT (17u) +#define INTC_ICDISER10_LINI1_INT_M_SHIFT (18u) +#define INTC_ICDISER10_ERI0_SHIFT (27u) +#define INTC_ICDISER10_RXI0_SHIFT (28u) +#define INTC_ICDISER10_TXI0_SHIFT (29u) +#define INTC_ICDISER10_TEI0_SHIFT (30u) +#define INTC_ICDISER10_ERI1_SHIFT (31u) + +#define INTC_ICDISER11_RXI1_SHIFT (0u) +#define INTC_ICDISER11_TXI1_SHIFT (1u) +#define INTC_ICDISER11_TEI1_SHIFT (2u) +#define INTC_ICDISER11_AVBI_DATA_SHIFT (3u) +#define INTC_ICDISER11_AVBI_ERROR_SHIFT (4u) +#define INTC_ICDISER11_AVBI_MANAGE_SHIFT (5u) +#define INTC_ICDISER11_AVBI_MAC_SHIFT (6u) +#define INTC_ICDISER11_ETHERI_SHIFT (7u) +#define INTC_ICDISER11_CEUI_SHIFT (12u) +#define INTC_ICDISER11_H2XMLB_ERRINT_SHIFT (29u) +#define INTC_ICDISER11_H2XIC1_ERRINT_SHIFT (30u) +#define INTC_ICDISER11_X2HPERI1_ERRINT_SHIFT (31u) + +#define INTC_ICDISER12_X2HPERI2_ERRINT_SHIFT (0u) +#define INTC_ICDISER12_X2HPERI34_ERRINT_SHIFT (1u) +#define INTC_ICDISER12_X2HPERI5_ERRINT_SHIFT (2u) +#define INTC_ICDISER12_X2HPERI67_ERRINT_SHIFT (3u) +#define INTC_ICDISER12_X2HDBGR_ERRINT_SHIFT (4u) +#define INTC_ICDISER12_X2HBSC_ERRINT_SHIFT (5u) +#define INTC_ICDISER12_X2HSPI1_ERRINT_SHIFT (6u) +#define INTC_ICDISER12_X2HSPI2_ERRINT_SHIFT (7u) +#define INTC_ICDISER12_PRRI_SHIFT (8u) +#define INTC_ICDISER12_IFEI0_SHIFT (9u) +#define INTC_ICDISER12_OFFI0_SHIFT (10u) +#define INTC_ICDISER12_PFVEI0_SHIFT (11u) +#define INTC_ICDISER12_IFEI1_SHIFT (12u) +#define INTC_ICDISER12_OFFI1_SHIFT (13u) +#define INTC_ICDISER12_PFVEI1_SHIFT (14u) + +#define INTC_ICDISER13_TINT0_SHIFT (0u) +#define INTC_ICDISER13_TINT1_SHIFT (1u) +#define INTC_ICDISER13_TINT2_SHIFT (2u) +#define INTC_ICDISER13_TINT3_SHIFT (3u) +#define INTC_ICDISER13_TINT4_SHIFT (4u) +#define INTC_ICDISER13_TINT5_SHIFT (5u) +#define INTC_ICDISER13_TINT6_SHIFT (6u) +#define INTC_ICDISER13_TINT7_SHIFT (7u) +#define INTC_ICDISER13_TINT8_SHIFT (8u) +#define INTC_ICDISER13_TINT9_SHIFT (9u) +#define INTC_ICDISER13_TINT10_SHIFT (10u) +#define INTC_ICDISER13_TINT11_SHIFT (11u) +#define INTC_ICDISER13_TINT12_SHIFT (12u) +#define INTC_ICDISER13_TINT13_SHIFT (13u) +#define INTC_ICDISER13_TINT14_SHIFT (14u) +#define INTC_ICDISER13_TINT15_SHIFT (15u) +#define INTC_ICDISER13_TINT16_SHIFT (16u) +#define INTC_ICDISER13_TINT17_SHIFT (17u) +#define INTC_ICDISER13_TINT18_SHIFT (18u) +#define INTC_ICDISER13_TINT19_SHIFT (19u) +#define INTC_ICDISER13_TINT20_SHIFT (20u) +#define INTC_ICDISER13_TINT21_SHIFT (21u) +#define INTC_ICDISER13_TINT22_SHIFT (22u) +#define INTC_ICDISER13_TINT23_SHIFT (23u) +#define INTC_ICDISER13_TINT24_SHIFT (24u) +#define INTC_ICDISER13_TINT25_SHIFT (25u) +#define INTC_ICDISER13_TINT26_SHIFT (26u) +#define INTC_ICDISER13_TINT27_SHIFT (27u) +#define INTC_ICDISER13_TINT28_SHIFT (28u) +#define INTC_ICDISER13_TINT29_SHIFT (29u) +#define INTC_ICDISER13_TINT30_SHIFT (30u) +#define INTC_ICDISER13_TINT31_SHIFT (31u) + +#define INTC_ICDISER14_TINT32_SHIFT (0u) +#define INTC_ICDISER14_TINT33_SHIFT (1u) +#define INTC_ICDISER14_TINT34_SHIFT (2u) +#define INTC_ICDISER14_TINT35_SHIFT (3u) +#define INTC_ICDISER14_TINT36_SHIFT (4u) +#define INTC_ICDISER14_TINT37_SHIFT (5u) +#define INTC_ICDISER14_TINT38_SHIFT (6u) +#define INTC_ICDISER14_TINT39_SHIFT (7u) +#define INTC_ICDISER14_TINT40_SHIFT (8u) +#define INTC_ICDISER14_TINT41_SHIFT (9u) +#define INTC_ICDISER14_TINT42_SHIFT (10u) +#define INTC_ICDISER14_TINT43_SHIFT (11u) +#define INTC_ICDISER14_TINT44_SHIFT (12u) +#define INTC_ICDISER14_TINT45_SHIFT (13u) +#define INTC_ICDISER14_TINT46_SHIFT (14u) +#define INTC_ICDISER14_TINT47_SHIFT (15u) +#define INTC_ICDISER14_TINT48_SHIFT (16u) +#define INTC_ICDISER14_TINT49_SHIFT (17u) +#define INTC_ICDISER14_TINT50_SHIFT (18u) +#define INTC_ICDISER14_TINT51_SHIFT (19u) +#define INTC_ICDISER14_TINT52_SHIFT (20u) +#define INTC_ICDISER14_TINT53_SHIFT (21u) +#define INTC_ICDISER14_TINT54_SHIFT (22u) +#define INTC_ICDISER14_TINT55_SHIFT (23u) +#define INTC_ICDISER14_TINT56_SHIFT (24u) +#define INTC_ICDISER14_TINT57_SHIFT (25u) +#define INTC_ICDISER14_TINT58_SHIFT (26u) +#define INTC_ICDISER14_TINT59_SHIFT (27u) +#define INTC_ICDISER14_TINT60_SHIFT (28u) +#define INTC_ICDISER14_TINT61_SHIFT (29u) +#define INTC_ICDISER14_TINT62_SHIFT (30u) +#define INTC_ICDISER14_TINT63_SHIFT (31u) + +#define INTC_ICDISER15_TINT64_SHIFT (0u) +#define INTC_ICDISER15_TINT65_SHIFT (1u) +#define INTC_ICDISER15_TINT66_SHIFT (2u) +#define INTC_ICDISER15_TINT67_SHIFT (3u) +#define INTC_ICDISER15_TINT68_SHIFT (4u) +#define INTC_ICDISER15_TINT69_SHIFT (5u) +#define INTC_ICDISER15_TINT70_SHIFT (6u) +#define INTC_ICDISER15_TINT71_SHIFT (7u) +#define INTC_ICDISER15_TINT72_SHIFT (8u) +#define INTC_ICDISER15_TINT73_SHIFT (9u) +#define INTC_ICDISER15_TINT74_SHIFT (10u) +#define INTC_ICDISER15_TINT75_SHIFT (11u) +#define INTC_ICDISER15_TINT76_SHIFT (12u) +#define INTC_ICDISER15_TINT77_SHIFT (13u) +#define INTC_ICDISER15_TINT78_SHIFT (14u) +#define INTC_ICDISER15_TINT79_SHIFT (15u) +#define INTC_ICDISER15_TINT80_SHIFT (16u) +#define INTC_ICDISER15_TINT81_SHIFT (17u) +#define INTC_ICDISER15_TINT82_SHIFT (18u) +#define INTC_ICDISER15_TINT83_SHIFT (19u) +#define INTC_ICDISER15_TINT84_SHIFT (20u) +#define INTC_ICDISER15_TINT85_SHIFT (21u) +#define INTC_ICDISER15_TINT86_SHIFT (22u) +#define INTC_ICDISER15_TINT87_SHIFT (23u) +#define INTC_ICDISER15_TINT88_SHIFT (24u) +#define INTC_ICDISER15_TINT89_SHIFT (25u) +#define INTC_ICDISER15_TINT90_SHIFT (26u) +#define INTC_ICDISER15_TINT91_SHIFT (27u) +#define INTC_ICDISER15_TINT92_SHIFT (28u) +#define INTC_ICDISER15_TINT93_SHIFT (29u) +#define INTC_ICDISER15_TINT94_SHIFT (30u) +#define INTC_ICDISER15_TINT95_SHIFT (31u) + +#define INTC_ICDISER16_TINT96_SHIFT (0u) +#define INTC_ICDISER16_TINT97_SHIFT (1u) +#define INTC_ICDISER16_TINT98_SHIFT (2u) +#define INTC_ICDISER16_TINT99_SHIFT (3u) +#define INTC_ICDISER16_TINT100_SHIFT (4u) +#define INTC_ICDISER16_TINT101_SHIFT (5u) +#define INTC_ICDISER16_TINT102_SHIFT (6u) +#define INTC_ICDISER16_TINT103_SHIFT (7u) +#define INTC_ICDISER16_TINT104_SHIFT (8u) +#define INTC_ICDISER16_TINT105_SHIFT (9u) +#define INTC_ICDISER16_TINT106_SHIFT (10u) +#define INTC_ICDISER16_TINT107_SHIFT (11u) +#define INTC_ICDISER16_TINT108_SHIFT (12u) +#define INTC_ICDISER16_TINT109_SHIFT (13u) +#define INTC_ICDISER16_TINT110_SHIFT (14u) +#define INTC_ICDISER16_TINT111_SHIFT (15u) +#define INTC_ICDISER16_TINT112_SHIFT (16u) +#define INTC_ICDISER16_TINT113_SHIFT (17u) +#define INTC_ICDISER16_TINT114_SHIFT (18u) +#define INTC_ICDISER16_TINT115_SHIFT (19u) +#define INTC_ICDISER16_TINT116_SHIFT (20u) +#define INTC_ICDISER16_TINT117_SHIFT (21u) +#define INTC_ICDISER16_TINT118_SHIFT (22u) +#define INTC_ICDISER16_TINT119_SHIFT (23u) +#define INTC_ICDISER16_TINT120_SHIFT (24u) +#define INTC_ICDISER16_TINT121_SHIFT (25u) +#define INTC_ICDISER16_TINT122_SHIFT (26u) +#define INTC_ICDISER16_TINT123_SHIFT (27u) +#define INTC_ICDISER16_TINT124_SHIFT (28u) +#define INTC_ICDISER16_TINT125_SHIFT (29u) +#define INTC_ICDISER16_TINT126_SHIFT (30u) +#define INTC_ICDISER16_TINT127_SHIFT (31u) + +#define INTC_ICDISER17_TINT128_SHIFT (0u) +#define INTC_ICDISER17_TINT129_SHIFT (1u) +#define INTC_ICDISER17_TINT130_SHIFT (2u) +#define INTC_ICDISER17_TINT131_SHIFT (3u) +#define INTC_ICDISER17_TINT132_SHIFT (4u) +#define INTC_ICDISER17_TINT133_SHIFT (5u) +#define INTC_ICDISER17_TINT134_SHIFT (6u) +#define INTC_ICDISER17_TINT135_SHIFT (7u) +#define INTC_ICDISER17_TINT136_SHIFT (8u) +#define INTC_ICDISER17_TINT137_SHIFT (9u) +#define INTC_ICDISER17_TINT138_SHIFT (10u) +#define INTC_ICDISER17_TINT139_SHIFT (11u) +#define INTC_ICDISER17_TINT140_SHIFT (12u) +#define INTC_ICDISER17_TINT141_SHIFT (13u) +#define INTC_ICDISER17_TINT142_SHIFT (14u) +#define INTC_ICDISER17_TINT143_SHIFT (15u) +#define INTC_ICDISER17_TINT144_SHIFT (16u) +#define INTC_ICDISER17_TINT145_SHIFT (17u) +#define INTC_ICDISER17_TINT146_SHIFT (18u) +#define INTC_ICDISER17_TINT147_SHIFT (19u) +#define INTC_ICDISER17_TINT148_SHIFT (20u) +#define INTC_ICDISER17_TINT149_SHIFT (21u) +#define INTC_ICDISER17_TINT150_SHIFT (22u) +#define INTC_ICDISER17_TINT151_SHIFT (23u) +#define INTC_ICDISER17_TINT152_SHIFT (24u) +#define INTC_ICDISER17_TINT153_SHIFT (25u) +#define INTC_ICDISER17_TINT154_SHIFT (26u) +#define INTC_ICDISER17_TINT155_SHIFT (27u) +#define INTC_ICDISER17_TINT156_SHIFT (28u) +#define INTC_ICDISER17_TINT157_SHIFT (29u) +#define INTC_ICDISER17_TINT158_SHIFT (30u) +#define INTC_ICDISER17_TINT159_SHIFT (31u) + +#define INTC_ICDISER18_TINT160_SHIFT (0u) +#define INTC_ICDISER18_TINT161_SHIFT (1u) +#define INTC_ICDISER18_TINT162_SHIFT (2u) +#define INTC_ICDISER18_TINT163_SHIFT (3u) +#define INTC_ICDISER18_TINT164_SHIFT (4u) +#define INTC_ICDISER18_TINT165_SHIFT (5u) +#define INTC_ICDISER18_TINT166_SHIFT (6u) +#define INTC_ICDISER18_TINT167_SHIFT (7u) +#define INTC_ICDISER18_TINT168_SHIFT (8u) +#define INTC_ICDISER18_TINT169_SHIFT (9u) +#define INTC_ICDISER18_TINT170_SHIFT (10u) + +#define INTC_ICDICER0_SW0_SHIFT (0u) +#define INTC_ICDICER0_SW1_SHIFT (1u) +#define INTC_ICDICER0_SW2_SHIFT (2u) +#define INTC_ICDICER0_SW3_SHIFT (3u) +#define INTC_ICDICER0_SW4_SHIFT (4u) +#define INTC_ICDICER0_SW5_SHIFT (5u) +#define INTC_ICDICER0_SW6_SHIFT (6u) +#define INTC_ICDICER0_SW7_SHIFT (7u) +#define INTC_ICDICER0_SW8_SHIFT (8u) +#define INTC_ICDICER0_SW9_SHIFT (9u) +#define INTC_ICDICER0_SW10_SHIFT (10u) +#define INTC_ICDICER0_SW11_SHIFT (11u) +#define INTC_ICDICER0_SW12_SHIFT (12u) +#define INTC_ICDICER0_SW13_SHIFT (13u) +#define INTC_ICDICER0_SW14_SHIFT (14u) +#define INTC_ICDICER0_SW15_SHIFT (15u) +#define INTC_ICDICER0_PMUIRQ0_SHIFT (16u) +#define INTC_ICDICER0_COMMRX0_SHIFT (17u) +#define INTC_ICDICER0_COMMTX0_SHIFT (18u) +#define INTC_ICDICER0_CTIIRQ0_SHIFT (19u) + +#define INTC_ICDICER1_IRQ0_SHIFT (0u) +#define INTC_ICDICER1_IRQ1_SHIFT (1u) +#define INTC_ICDICER1_IRQ2_SHIFT (2u) +#define INTC_ICDICER1_IRQ3_SHIFT (3u) +#define INTC_ICDICER1_IRQ4_SHIFT (4u) +#define INTC_ICDICER1_IRQ5_SHIFT (5u) +#define INTC_ICDICER1_IRQ6_SHIFT (6u) +#define INTC_ICDICER1_IRQ7_SHIFT (7u) +#define INTC_ICDICER1_PL310ERR_SHIFT (8u) +#define INTC_ICDICER1_DMAINT0_SHIFT (9u) +#define INTC_ICDICER1_DMAINT1_SHIFT (10u) +#define INTC_ICDICER1_DMAINT2_SHIFT (11u) +#define INTC_ICDICER1_DMAINT3_SHIFT (12u) +#define INTC_ICDICER1_DMAINT4_SHIFT (13u) +#define INTC_ICDICER1_DMAINT5_SHIFT (14u) +#define INTC_ICDICER1_DMAINT6_SHIFT (15u) +#define INTC_ICDICER1_DMAINT7_SHIFT (16u) +#define INTC_ICDICER1_DMAINT8_SHIFT (17u) +#define INTC_ICDICER1_DMAINT9_SHIFT (18u) +#define INTC_ICDICER1_DMAINT10_SHIFT (19u) +#define INTC_ICDICER1_DMAINT11_SHIFT (20u) +#define INTC_ICDICER1_DMAINT12_SHIFT (21u) +#define INTC_ICDICER1_DMAINT13_SHIFT (22u) +#define INTC_ICDICER1_DMAINT14_SHIFT (23u) +#define INTC_ICDICER1_DMAINT15_SHIFT (24u) +#define INTC_ICDICER1_DMAERR_SHIFT (25u) + +#define INTC_ICDICER2_USBI0_SHIFT (9u) +#define INTC_ICDICER2_USBI1_SHIFT (10u) +#define INTC_ICDICER2_S0_VI_VSYNC0_SHIFT (11u) +#define INTC_ICDICER2_S0_LO_VSYNC0_SHIFT (12u) +#define INTC_ICDICER2_S0_VSYNCERR0_SHIFT (13u) +#define INTC_ICDICER2_GR3_VLINE0_SHIFT (14u) +#define INTC_ICDICER2_S0_VFIELD0_SHIFT (15u) +#define INTC_ICDICER2_IV1_VBUFERR0_SHIFT (16u) +#define INTC_ICDICER2_IV3_VBUFERR0_SHIFT (17u) +#define INTC_ICDICER2_IV5_VBUFERR0_SHIFT (18u) +#define INTC_ICDICER2_IV6_VBUFERR0_SHIFT (19u) +#define INTC_ICDICER2_S0_WLINE0_SHIFT (20u) +#define INTC_ICDICER2_S1_VI_VSYNC0_SHIFT (21u) +#define INTC_ICDICER2_S1_LO_VSYNC0_SHIFT (22u) +#define INTC_ICDICER2_S1_VSYNCERR0_SHIFT (23u) +#define INTC_ICDICER2_S1_VFIELD0_SHIFT (24u) +#define INTC_ICDICER2_IV2_VBUFERR0_SHIFT (25u) +#define INTC_ICDICER2_IV4_VBUFERR0_SHIFT (26u) +#define INTC_ICDICER2_S1_WLINE0_SHIFT (27u) +#define INTC_ICDICER2_OIR_VI_VSYNC0_SHIFT (28u) +#define INTC_ICDICER2_OIR_LO_VSYNC0_SHIFT (29u) +#define INTC_ICDICER2_OIR_VSYNCERR0_SHIFT (30u) +#define INTC_ICDICER2_OIR_VFIELD0_SHIFT (31u) + +#define INTC_ICDICER3_IV7_VBUFERR0_SHIFT (0u) +#define INTC_ICDICER3_IV8_VBUFERR0_SHIFT (1u) +#define INTC_ICDICER3_S0_VI_VSYNC1_SHIFT (3u) +#define INTC_ICDICER3_S0_LO_VSYNC1_SHIFT (4u) +#define INTC_ICDICER3_S0_VSYNCERR1_SHIFT (5u) +#define INTC_ICDICER3_GR3_VLINE1_SHIFT (6u) +#define INTC_ICDICER3_S0_VFIELD1_SHIFT (7u) +#define INTC_ICDICER3_IV1_VBUFERR1_SHIFT (8u) +#define INTC_ICDICER3_IV3_VBUFERR1_SHIFT (9u) +#define INTC_ICDICER3_IV5_VBUFERR1_SHIFT (10u) +#define INTC_ICDICER3_IV6_VBUFERR1_SHIFT (11u) +#define INTC_ICDICER3_S0_WLINE1_SHIFT (12u) +#define INTC_ICDICER3_S1_VI_VSYNC1_SHIFT (13u) +#define INTC_ICDICER3_S1_LO_VSYNC1_SHIFT (14u) +#define INTC_ICDICER3_S1_VSYNCERR1_SHIFT (15u) +#define INTC_ICDICER3_S1_VFIELD1_SHIFT (16u) +#define INTC_ICDICER3_IV2_VBUFERR1_SHIFT (17u) +#define INTC_ICDICER3_IV4_VBUFERR1_SHIFT (18u) +#define INTC_ICDICER3_S1_WLINE1_SHIFT (19u) +#define INTC_ICDICER3_OIR_VI_VSYNC1_SHIFT (20u) +#define INTC_ICDICER3_OIR_LO_VSYNC1_SHIFT (21u) +#define INTC_ICDICER3_OIR_VLINE1_SHIFT (22u) +#define INTC_ICDICER3_OIR_VFIELD1_SHIFT (23u) +#define INTC_ICDICER3_IV7_VBUFERR1_SHIFT (24u) +#define INTC_ICDICER3_IV8_VBUFERR1_SHIFT (25u) +#define INTC_ICDICER3_IMRDI_SHIFT (27u) +#define INTC_ICDICER3_IMR2I0_SHIFT (28u) +#define INTC_ICDICER3_IMR2I1_SHIFT (29u) +#define INTC_ICDICER3_JEDI_SHIFT (30u) +#define INTC_ICDICER3_JDTI_SHIFT (31u) + +#define INTC_ICDICER4_CMP0_SHIFT (0u) +#define INTC_ICDICER4_CMP1_SHIFT (1u) +#define INTC_ICDICER4_INT0_SHIFT (2u) +#define INTC_ICDICER4_INT1_SHIFT (3u) +#define INTC_ICDICER4_INT2_SHIFT (4u) +#define INTC_ICDICER4_INT3_SHIFT (5u) +#define INTC_ICDICER4_OSTM0TINT_SHIFT (6u) +#define INTC_ICDICER4_OSTM1TINT_SHIFT (7u) +#define INTC_ICDICER4_CMI_SHIFT (8u) +#define INTC_ICDICER4_WTOUT_SHIFT (9u) +#define INTC_ICDICER4_ITI_SHIFT (10u) +#define INTC_ICDICER4_TGI0A_SHIFT (11u) +#define INTC_ICDICER4_TGI0B_SHIFT (12u) +#define INTC_ICDICER4_TGI0C_SHIFT (13u) +#define INTC_ICDICER4_TGI0D_SHIFT (14u) +#define INTC_ICDICER4_TGI0V_SHIFT (15u) +#define INTC_ICDICER4_TGI0E_SHIFT (16u) +#define INTC_ICDICER4_TGI0F_SHIFT (17u) +#define INTC_ICDICER4_TGI1A_SHIFT (18u) +#define INTC_ICDICER4_TGI1B_SHIFT (19u) +#define INTC_ICDICER4_TGI1V_SHIFT (20u) +#define INTC_ICDICER4_TGI1U_SHIFT (21u) +#define INTC_ICDICER4_TGI2A_SHIFT (22u) +#define INTC_ICDICER4_TGI2B_SHIFT (23u) +#define INTC_ICDICER4_TGI2V_SHIFT (24u) +#define INTC_ICDICER4_TGI2U_SHIFT (25u) +#define INTC_ICDICER4_TGI3A_SHIFT (26u) +#define INTC_ICDICER4_TGI3B_SHIFT (27u) +#define INTC_ICDICER4_TGI3C_SHIFT (28u) +#define INTC_ICDICER4_TGI3D_SHIFT (29u) +#define INTC_ICDICER4_TGI3V_SHIFT (30u) +#define INTC_ICDICER4_TGI4A_SHIFT (31u) + +#define INTC_ICDICER5_TGI4B_SHIFT (0u) +#define INTC_ICDICER5_TGI4C_SHIFT (1u) +#define INTC_ICDICER5_TGI4D_SHIFT (2u) +#define INTC_ICDICER5_TGI4V_SHIFT (3u) +#define INTC_ICDICER5_CMI1_SHIFT (4u) +#define INTC_ICDICER5_CMI2_SHIFT (5u) +#define INTC_ICDICER5_SGDEI0_SHIFT (6u) +#define INTC_ICDICER5_SGDEI1_SHIFT (7u) +#define INTC_ICDICER5_SGDEI2_SHIFT (8u) +#define INTC_ICDICER5_SGDEI3_SHIFT (9u) +#define INTC_ICDICER5_ADI_SHIFT (10u) +#define INTC_ICDICER5_LMTI_SHIFT (11u) +#define INTC_ICDICER5_SSII0_SHIFT (12u) +#define INTC_ICDICER5_SSIRXI0_SHIFT (13u) +#define INTC_ICDICER5_SSITXI0_SHIFT (14u) +#define INTC_ICDICER5_SSII1_SHIFT (15u) +#define INTC_ICDICER5_SSIRXI1_SHIFT (16u) +#define INTC_ICDICER5_SSITXI1_SHIFT (17u) +#define INTC_ICDICER5_SSII2_SHIFT (18u) +#define INTC_ICDICER5_SSIRTI2_SHIFT (19u) +#define INTC_ICDICER5_SSII3_SHIFT (20u) +#define INTC_ICDICER5_SSIRXI3_SHIFT (21u) +#define INTC_ICDICER5_SSITXI3_SHIFT (22u) +#define INTC_ICDICER5_SSII4_SHIFT (23u) +#define INTC_ICDICER5_SSIRTI4_SHIFT (24u) +#define INTC_ICDICER5_SSII5_SHIFT (25u) +#define INTC_ICDICER5_SSIRXI5_SHIFT (26u) +#define INTC_ICDICER5_SSITXI5_SHIFT (27u) +#define INTC_ICDICER5_SPDIFI_SHIFT (28u) +#define INTC_ICDICER5_INTIICTEI0_SHIFT (29u) +#define INTC_ICDICER5_INTIICRI0_SHIFT (30u) +#define INTC_ICDICER5_INTIICTI0_SHIFT (31u) + +#define INTC_ICDICER6_INTIICSPI0_SHIFT (0u) +#define INTC_ICDICER6_INTIICSTI0_SHIFT (1u) +#define INTC_ICDICER6_INTIICNAKI0_SHIFT (2u) +#define INTC_ICDICER6_INTIICALI0_SHIFT (3u) +#define INTC_ICDICER6_INTIICTMOI0_SHIFT (4u) +#define INTC_ICDICER6_INTIICTEI1_SHIFT (5u) +#define INTC_ICDICER6_INTIICRI1_SHIFT (6u) +#define INTC_ICDICER6_INTIICTI1_SHIFT (7u) +#define INTC_ICDICER6_INTIICSPI1_SHIFT (8u) +#define INTC_ICDICER6_INTIICSTI1_SHIFT (9u) +#define INTC_ICDICER6_INTIICNAKI1_SHIFT (10u) +#define INTC_ICDICER6_INTIICALI1_SHIFT (11u) +#define INTC_ICDICER6_INTIICTMOI1_SHIFT (12u) +#define INTC_ICDICER6_INTIICTEI2_SHIFT (13u) +#define INTC_ICDICER6_INTIICRI2_SHIFT (14u) +#define INTC_ICDICER6_INTIICTI2_SHIFT (15u) +#define INTC_ICDICER6_INTIICSPI2_SHIFT (16u) +#define INTC_ICDICER6_INTIICSTI2_SHIFT (17u) +#define INTC_ICDICER6_INTIICNAKI2_SHIFT (18u) +#define INTC_ICDICER6_INTIICALI2_SHIFT (19u) +#define INTC_ICDICER6_INTIICTMOI2_SHIFT (20u) +#define INTC_ICDICER6_INTIICTEI3_SHIFT (21u) +#define INTC_ICDICER6_INTIICRI3_SHIFT (22u) +#define INTC_ICDICER6_INTIICTI3_SHIFT (23u) +#define INTC_ICDICER6_INTIICSPI3_SHIFT (24u) +#define INTC_ICDICER6_INTIICSTI3_SHIFT (25u) +#define INTC_ICDICER6_INTIICNAKI3_SHIFT (26u) +#define INTC_ICDICER6_INTIICALI3_SHIFT (27u) +#define INTC_ICDICER6_INTIICTMOI3_SHIFT (28u) +#define INTC_ICDICER6_BRI0_SHIFT (29u) +#define INTC_ICDICER6_ERI0_SHIFT (30u) +#define INTC_ICDICER6_RXI0_SHIFT (31u) + +#define INTC_ICDICER7_TXI0_SHIFT (0u) +#define INTC_ICDICER7_BRI1_SHIFT (1u) +#define INTC_ICDICER7_ERI1_SHIFT (2u) +#define INTC_ICDICER7_RXI1_SHIFT (3u) +#define INTC_ICDICER7_TXI1_SHIFT (4u) +#define INTC_ICDICER7_BRI2_SHIFT (5u) +#define INTC_ICDICER7_ERI2_SHIFT (6u) +#define INTC_ICDICER7_RXI2_SHIFT (7u) +#define INTC_ICDICER7_TXI2_SHIFT (8u) +#define INTC_ICDICER7_BRI3_SHIFT (9u) +#define INTC_ICDICER7_ERI3_SHIFT (10u) +#define INTC_ICDICER7_RXI3_SHIFT (11u) +#define INTC_ICDICER7_TXI3_SHIFT (12u) +#define INTC_ICDICER7_BRI4_SHIFT (13u) +#define INTC_ICDICER7_ERI4_SHIFT (14u) +#define INTC_ICDICER7_RXI4_SHIFT (15u) +#define INTC_ICDICER7_TXI4_SHIFT (16u) +#define INTC_ICDICER7_BRI5_SHIFT (17u) +#define INTC_ICDICER7_ERI5_SHIFT (18u) +#define INTC_ICDICER7_RXI5_SHIFT (19u) +#define INTC_ICDICER7_TXI5_SHIFT (20u) +#define INTC_ICDICER7_BRI6_SHIFT (21u) +#define INTC_ICDICER7_ERI6_SHIFT (22u) +#define INTC_ICDICER7_RXI6_SHIFT (23u) +#define INTC_ICDICER7_TXI6_SHIFT (24u) +#define INTC_ICDICER7_BRI7_SHIFT (25u) +#define INTC_ICDICER7_ERI7_SHIFT (26u) +#define INTC_ICDICER7_RXI7_SHIFT (27u) +#define INTC_ICDICER7_TXI7_SHIFT (28u) +#define INTC_ICDICER7_INTRCANGERR_SHIFT (29u) +#define INTC_ICDICER7_INTRCANGRECC_SHIFT (30u) +#define INTC_ICDICER7_INTRCAN0REC_SHIFT (31u) + +#define INTC_ICDICER8_INTRCAN0ERR_SHIFT (0u) +#define INTC_ICDICER8_INTRCAN0TRX_SHIFT (1u) +#define INTC_ICDICER8_INTRCAN1REC_SHIFT (2u) +#define INTC_ICDICER8_INTRCAN1ERR_SHIFT (3u) +#define INTC_ICDICER8_INTRCAN1TRX_SHIFT (4u) +#define INTC_ICDICER8_INTRCAN2REC_SHIFT (5u) +#define INTC_ICDICER8_INTRCAN2ERR_SHIFT (6u) +#define INTC_ICDICER8_INTRCAN2TRX_SHIFT (7u) +#define INTC_ICDICER8_INTRCAN3REC_SHIFT (8u) +#define INTC_ICDICER8_INTRCAN3ERR_SHIFT (9u) +#define INTC_ICDICER8_INTRCAN3TRX_SHIFT (10u) +#define INTC_ICDICER8_INTRCAN4REC_SHIFT (11u) +#define INTC_ICDICER8_INTRCAN4ERR_SHIFT (12u) +#define INTC_ICDICER8_INTRCAN4TRX_SHIFT (13u) +#define INTC_ICDICER8_SPEI0_SHIFT (14u) +#define INTC_ICDICER8_SPRI0_SHIFT (15u) +#define INTC_ICDICER8_SPTI0_SHIFT (16u) +#define INTC_ICDICER8_SPEI1_SHIFT (17u) +#define INTC_ICDICER8_SPRI1_SHIFT (18u) +#define INTC_ICDICER8_SPTI1_SHIFT (19u) +#define INTC_ICDICER8_SPEI2_SHIFT (20u) +#define INTC_ICDICER8_SPRI2_SHIFT (21u) +#define INTC_ICDICER8_SPTI2_SHIFT (22u) +#define INTC_ICDICER8_SPEI3_SHIFT (23u) +#define INTC_ICDICER8_SPRI3_SHIFT (24u) +#define INTC_ICDICER8_SPTI3_SHIFT (25u) +#define INTC_ICDICER8_SPEI4_SHIFT (26u) +#define INTC_ICDICER8_SPRI4_SHIFT (27u) +#define INTC_ICDICER8_SPTI4_SHIFT (28u) +#define INTC_ICDICER8_IEBBTD_SHIFT (29u) +#define INTC_ICDICER8_IEBBTERR_SHIFT (30u) +#define INTC_ICDICER8_IEBBTSTA_SHIFT (31u) + +#define INTC_ICDICER9_IEBBTV_SHIFT (0u) +#define INTC_ICDICER9_ISY_SHIFT (1u) +#define INTC_ICDICER9_IERR_SHIFT (2u) +#define INTC_ICDICER9_ITARG_SHIFT (3u) +#define INTC_ICDICER9_ISEC_SHIFT (4u) +#define INTC_ICDICER9_IBUF_SHIFT (5u) +#define INTC_ICDICER9_IREADY_SHIFT (6u) +#define INTC_ICDICER9_FLSTE_SHIFT (7u) +#define INTC_ICDICER9_FLTENDI_SHIFT (8u) +#define INTC_ICDICER9_FLTREQ0I_SHIFT (9u) +#define INTC_ICDICER9_FLTREQ1I_SHIFT (10u) +#define INTC_ICDICER9_MMC0_SHIFT (11u) +#define INTC_ICDICER9_MMC1_SHIFT (12u) +#define INTC_ICDICER9_MMC2_SHIFT (13u) +#define INTC_ICDICER9_SDHI0_3_SHIFT (14u) +#define INTC_ICDICER9_SDHI0_0_SHIFT (15u) +#define INTC_ICDICER9_SDHI0_1_SHIFT (16u) +#define INTC_ICDICER9_SDHI1_3_SHIFT (17u) +#define INTC_ICDICER9_SDHI1_0_SHIFT (18u) +#define INTC_ICDICER9_SDHI1_1_SHIFT (19u) +#define INTC_ICDICER9_ARM_SHIFT (20u) +#define INTC_ICDICER9_PRD_SHIFT (21u) +#define INTC_ICDICER9_CUP_SHIFT (22u) +#define INTC_ICDICER9_SCUAI0_SHIFT (23u) +#define INTC_ICDICER9_SCUAI1_SHIFT (24u) +#define INTC_ICDICER9_SCUFDI0_SHIFT (25u) +#define INTC_ICDICER9_SCUFDI1_SHIFT (26u) +#define INTC_ICDICER9_SCUFDI2_SHIFT (27u) +#define INTC_ICDICER9_SCUFDI3_SHIFT (28u) +#define INTC_ICDICER9_SCUFUI0_SHIFT (29u) +#define INTC_ICDICER9_SCUFUI1_SHIFT (30u) +#define INTC_ICDICER9_SCUFUI2_SHIFT (31u) + +#define INTC_ICDICER10_SCUFUI3_SHIFT (0u) +#define INTC_ICDICER10_SCUDVI0_SHIFT (1u) +#define INTC_ICDICER10_SCUDVI1_SHIFT (2u) +#define INTC_ICDICER10_SCUDVI2_SHIFT (3u) +#define INTC_ICDICER10_SCUDVI3_SHIFT (4u) +#define INTC_ICDICER10_MLB_CINT_SHIFT (5u) +#define INTC_ICDICER10_MLB_SINT_SHIFT (6u) +#define INTC_ICDICER10_DRC0_SHIFT (7u) +#define INTC_ICDICER10_DRC1_SHIFT (8u) +#define INTC_ICDICER10_LINI0_INT_T_SHIFT (11u) +#define INTC_ICDICER10_LINI0_INT_R_SHIFT (12u) +#define INTC_ICDICER10_LINI0_INT_S_SHIFT (13u) +#define INTC_ICDICER10_LINI0_INT_M_SHIFT (14u) +#define INTC_ICDICER10_LINI1_INT_T_SHIFT (15u) +#define INTC_ICDICER10_LINI1_INT_R_SHIFT (16u) +#define INTC_ICDICER10_LINI1_INT_S_SHIFT (17u) +#define INTC_ICDICER10_LINI1_INT_M_SHIFT (18u) +#define INTC_ICDICER10_ERI0_SHIFT (27u) +#define INTC_ICDICER10_RXI0_SHIFT (28u) +#define INTC_ICDICER10_TXI0_SHIFT (29u) +#define INTC_ICDICER10_TEI0_SHIFT (30u) +#define INTC_ICDICER10_ERI1_SHIFT (31u) + +#define INTC_ICDICER11_RXI1_SHIFT (0u) +#define INTC_ICDICER11_TXI1_SHIFT (1u) +#define INTC_ICDICER11_TEI1_SHIFT (2u) +#define INTC_ICDICER11_AVBI_DATA_SHIFT (3u) +#define INTC_ICDICER11_AVBI_ERROR_SHIFT (4u) +#define INTC_ICDICER11_AVBI_MANAGE_SHIFT (5u) +#define INTC_ICDICER11_AVBI_MAC_SHIFT (6u) +#define INTC_ICDICER11_ETHERI_SHIFT (7u) +#define INTC_ICDICER11_CEUI_SHIFT (12u) +#define INTC_ICDICER11_H2XMLB_ERRINT_SHIFT (29u) +#define INTC_ICDICER11_H2XIC1_ERRINT_SHIFT (30u) +#define INTC_ICDICER11_X2HPERI1_ERRINT_SHIFT (31u) + +#define INTC_ICDICER12_X2HPERI2_ERRINT_SHIFT (0u) +#define INTC_ICDICER12_X2HPERI34_ERRINT_SHIFT (1u) +#define INTC_ICDICER12_X2HPERI5_ERRINT_SHIFT (2u) +#define INTC_ICDICER12_X2HPERI67_ERRINT_SHIFT (3u) +#define INTC_ICDICER12_X2HDBGR_ERRINT_SHIFT (4u) +#define INTC_ICDICER12_X2HBSC_ERRINT_SHIFT (5u) +#define INTC_ICDICER12_X2HSPI1_ERRINT_SHIFT (6u) +#define INTC_ICDICER12_X2HSPI2_ERRINT_SHIFT (7u) +#define INTC_ICDICER12_PRRI_SHIFT (8u) +#define INTC_ICDICER12_IFEI0_SHIFT (9u) +#define INTC_ICDICER12_OFFI0_SHIFT (10u) +#define INTC_ICDICER12_PFVEI0_SHIFT (11u) +#define INTC_ICDICER12_IFEI1_SHIFT (12u) +#define INTC_ICDICER12_OFFI1_SHIFT (13u) +#define INTC_ICDICER12_PFVEI1_SHIFT (14u) + +#define INTC_ICDICER13_TINT0_SHIFT (0u) +#define INTC_ICDICER13_TINT1_SHIFT (1u) +#define INTC_ICDICER13_TINT2_SHIFT (2u) +#define INTC_ICDICER13_TINT3_SHIFT (3u) +#define INTC_ICDICER13_TINT4_SHIFT (4u) +#define INTC_ICDICER13_TINT5_SHIFT (5u) +#define INTC_ICDICER13_TINT6_SHIFT (6u) +#define INTC_ICDICER13_TINT7_SHIFT (7u) +#define INTC_ICDICER13_TINT8_SHIFT (8u) +#define INTC_ICDICER13_TINT9_SHIFT (9u) +#define INTC_ICDICER13_TINT10_SHIFT (10u) +#define INTC_ICDICER13_TINT11_SHIFT (11u) +#define INTC_ICDICER13_TINT12_SHIFT (12u) +#define INTC_ICDICER13_TINT13_SHIFT (13u) +#define INTC_ICDICER13_TINT14_SHIFT (14u) +#define INTC_ICDICER13_TINT15_SHIFT (15u) +#define INTC_ICDICER13_TINT16_SHIFT (16u) +#define INTC_ICDICER13_TINT17_SHIFT (17u) +#define INTC_ICDICER13_TINT18_SHIFT (18u) +#define INTC_ICDICER13_TINT19_SHIFT (19u) +#define INTC_ICDICER13_TINT20_SHIFT (20u) +#define INTC_ICDICER13_TINT21_SHIFT (21u) +#define INTC_ICDICER13_TINT22_SHIFT (22u) +#define INTC_ICDICER13_TINT23_SHIFT (23u) +#define INTC_ICDICER13_TINT24_SHIFT (24u) +#define INTC_ICDICER13_TINT25_SHIFT (25u) +#define INTC_ICDICER13_TINT26_SHIFT (26u) +#define INTC_ICDICER13_TINT27_SHIFT (27u) +#define INTC_ICDICER13_TINT28_SHIFT (28u) +#define INTC_ICDICER13_TINT29_SHIFT (29u) +#define INTC_ICDICER13_TINT30_SHIFT (30u) +#define INTC_ICDICER13_TINT31_SHIFT (31u) + +#define INTC_ICDICER14_TINT32_SHIFT (0u) +#define INTC_ICDICER14_TINT33_SHIFT (1u) +#define INTC_ICDICER14_TINT34_SHIFT (2u) +#define INTC_ICDICER14_TINT35_SHIFT (3u) +#define INTC_ICDICER14_TINT36_SHIFT (4u) +#define INTC_ICDICER14_TINT37_SHIFT (5u) +#define INTC_ICDICER14_TINT38_SHIFT (6u) +#define INTC_ICDICER14_TINT39_SHIFT (7u) +#define INTC_ICDICER14_TINT40_SHIFT (8u) +#define INTC_ICDICER14_TINT41_SHIFT (9u) +#define INTC_ICDICER14_TINT42_SHIFT (10u) +#define INTC_ICDICER14_TINT43_SHIFT (11u) +#define INTC_ICDICER14_TINT44_SHIFT (12u) +#define INTC_ICDICER14_TINT45_SHIFT (13u) +#define INTC_ICDICER14_TINT46_SHIFT (14u) +#define INTC_ICDICER14_TINT47_SHIFT (15u) +#define INTC_ICDICER14_TINT48_SHIFT (16u) +#define INTC_ICDICER14_TINT49_SHIFT (17u) +#define INTC_ICDICER14_TINT50_SHIFT (18u) +#define INTC_ICDICER14_TINT51_SHIFT (19u) +#define INTC_ICDICER14_TINT52_SHIFT (20u) +#define INTC_ICDICER14_TINT53_SHIFT (21u) +#define INTC_ICDICER14_TINT54_SHIFT (22u) +#define INTC_ICDICER14_TINT55_SHIFT (23u) +#define INTC_ICDICER14_TINT56_SHIFT (24u) +#define INTC_ICDICER14_TINT57_SHIFT (25u) +#define INTC_ICDICER14_TINT58_SHIFT (26u) +#define INTC_ICDICER14_TINT59_SHIFT (27u) +#define INTC_ICDICER14_TINT60_SHIFT (28u) +#define INTC_ICDICER14_TINT61_SHIFT (29u) +#define INTC_ICDICER14_TINT62_SHIFT (30u) +#define INTC_ICDICER14_TINT63_SHIFT (31u) + +#define INTC_ICDICER15_TINT64_SHIFT (0u) +#define INTC_ICDICER15_TINT65_SHIFT (1u) +#define INTC_ICDICER15_TINT66_SHIFT (2u) +#define INTC_ICDICER15_TINT67_SHIFT (3u) +#define INTC_ICDICER15_TINT68_SHIFT (4u) +#define INTC_ICDICER15_TINT69_SHIFT (5u) +#define INTC_ICDICER15_TINT70_SHIFT (6u) +#define INTC_ICDICER15_TINT71_SHIFT (7u) +#define INTC_ICDICER15_TINT72_SHIFT (8u) +#define INTC_ICDICER15_TINT73_SHIFT (9u) +#define INTC_ICDICER15_TINT74_SHIFT (10u) +#define INTC_ICDICER15_TINT75_SHIFT (11u) +#define INTC_ICDICER15_TINT76_SHIFT (12u) +#define INTC_ICDICER15_TINT77_SHIFT (13u) +#define INTC_ICDICER15_TINT78_SHIFT (14u) +#define INTC_ICDICER15_TINT79_SHIFT (15u) +#define INTC_ICDICER15_TINT80_SHIFT (16u) +#define INTC_ICDICER15_TINT81_SHIFT (17u) +#define INTC_ICDICER15_TINT82_SHIFT (18u) +#define INTC_ICDICER15_TINT83_SHIFT (19u) +#define INTC_ICDICER15_TINT84_SHIFT (20u) +#define INTC_ICDICER15_TINT85_SHIFT (21u) +#define INTC_ICDICER15_TINT86_SHIFT (22u) +#define INTC_ICDICER15_TINT87_SHIFT (23u) +#define INTC_ICDICER15_TINT88_SHIFT (24u) +#define INTC_ICDICER15_TINT89_SHIFT (25u) +#define INTC_ICDICER15_TINT90_SHIFT (26u) +#define INTC_ICDICER15_TINT91_SHIFT (27u) +#define INTC_ICDICER15_TINT92_SHIFT (28u) +#define INTC_ICDICER15_TINT93_SHIFT (29u) +#define INTC_ICDICER15_TINT94_SHIFT (30u) +#define INTC_ICDICER15_TINT95_SHIFT (31u) + +#define INTC_ICDICER16_TINT96_SHIFT (0u) +#define INTC_ICDICER16_TINT97_SHIFT (1u) +#define INTC_ICDICER16_TINT98_SHIFT (2u) +#define INTC_ICDICER16_TINT99_SHIFT (3u) +#define INTC_ICDICER16_TINT100_SHIFT (4u) +#define INTC_ICDICER16_TINT101_SHIFT (5u) +#define INTC_ICDICER16_TINT102_SHIFT (6u) +#define INTC_ICDICER16_TINT103_SHIFT (7u) +#define INTC_ICDICER16_TINT104_SHIFT (8u) +#define INTC_ICDICER16_TINT105_SHIFT (9u) +#define INTC_ICDICER16_TINT106_SHIFT (10u) +#define INTC_ICDICER16_TINT107_SHIFT (11u) +#define INTC_ICDICER16_TINT108_SHIFT (12u) +#define INTC_ICDICER16_TINT109_SHIFT (13u) +#define INTC_ICDICER16_TINT110_SHIFT (14u) +#define INTC_ICDICER16_TINT111_SHIFT (15u) +#define INTC_ICDICER16_TINT112_SHIFT (16u) +#define INTC_ICDICER16_TINT113_SHIFT (17u) +#define INTC_ICDICER16_TINT114_SHIFT (18u) +#define INTC_ICDICER16_TINT115_SHIFT (19u) +#define INTC_ICDICER16_TINT116_SHIFT (20u) +#define INTC_ICDICER16_TINT117_SHIFT (21u) +#define INTC_ICDICER16_TINT118_SHIFT (22u) +#define INTC_ICDICER16_TINT119_SHIFT (23u) +#define INTC_ICDICER16_TINT120_SHIFT (24u) +#define INTC_ICDICER16_TINT121_SHIFT (25u) +#define INTC_ICDICER16_TINT122_SHIFT (26u) +#define INTC_ICDICER16_TINT123_SHIFT (27u) +#define INTC_ICDICER16_TINT124_SHIFT (28u) +#define INTC_ICDICER16_TINT125_SHIFT (29u) +#define INTC_ICDICER16_TINT126_SHIFT (30u) +#define INTC_ICDICER16_TINT127_SHIFT (31u) + +#define INTC_ICDICER17_TINT128_SHIFT (0u) +#define INTC_ICDICER17_TINT129_SHIFT (1u) +#define INTC_ICDICER17_TINT130_SHIFT (2u) +#define INTC_ICDICER17_TINT131_SHIFT (3u) +#define INTC_ICDICER17_TINT132_SHIFT (4u) +#define INTC_ICDICER17_TINT133_SHIFT (5u) +#define INTC_ICDICER17_TINT134_SHIFT (6u) +#define INTC_ICDICER17_TINT135_SHIFT (7u) +#define INTC_ICDICER17_TINT136_SHIFT (8u) +#define INTC_ICDICER17_TINT137_SHIFT (9u) +#define INTC_ICDICER17_TINT138_SHIFT (10u) +#define INTC_ICDICER17_TINT139_SHIFT (11u) +#define INTC_ICDICER17_TINT140_SHIFT (12u) +#define INTC_ICDICER17_TINT141_SHIFT (13u) +#define INTC_ICDICER17_TINT142_SHIFT (14u) +#define INTC_ICDICER17_TINT143_SHIFT (15u) +#define INTC_ICDICER17_TINT144_SHIFT (16u) +#define INTC_ICDICER17_TINT145_SHIFT (17u) +#define INTC_ICDICER17_TINT146_SHIFT (18u) +#define INTC_ICDICER17_TINT147_SHIFT (19u) +#define INTC_ICDICER17_TINT148_SHIFT (20u) +#define INTC_ICDICER17_TINT149_SHIFT (21u) +#define INTC_ICDICER17_TINT150_SHIFT (22u) +#define INTC_ICDICER17_TINT151_SHIFT (23u) +#define INTC_ICDICER17_TINT152_SHIFT (24u) +#define INTC_ICDICER17_TINT153_SHIFT (25u) +#define INTC_ICDICER17_TINT154_SHIFT (26u) +#define INTC_ICDICER17_TINT155_SHIFT (27u) +#define INTC_ICDICER17_TINT156_SHIFT (28u) +#define INTC_ICDICER17_TINT157_SHIFT (29u) +#define INTC_ICDICER17_TINT158_SHIFT (30u) +#define INTC_ICDICER17_TINT159_SHIFT (31u) + +#define INTC_ICDICER18_TINT160_SHIFT (0u) +#define INTC_ICDICER18_TINT161_SHIFT (1u) +#define INTC_ICDICER18_TINT162_SHIFT (2u) +#define INTC_ICDICER18_TINT163_SHIFT (3u) +#define INTC_ICDICER18_TINT164_SHIFT (4u) +#define INTC_ICDICER18_TINT165_SHIFT (5u) +#define INTC_ICDICER18_TINT166_SHIFT (6u) +#define INTC_ICDICER18_TINT167_SHIFT (7u) +#define INTC_ICDICER18_TINT168_SHIFT (8u) +#define INTC_ICDICER18_TINT169_SHIFT (9u) +#define INTC_ICDICER18_TINT170_SHIFT (10u) + +#define INTC_ICDISPR0_SW0_SHIFT (0u) +#define INTC_ICDISPR0_SW1_SHIFT (1u) +#define INTC_ICDISPR0_SW2_SHIFT (2u) +#define INTC_ICDISPR0_SW3_SHIFT (3u) +#define INTC_ICDISPR0_SW4_SHIFT (4u) +#define INTC_ICDISPR0_SW5_SHIFT (5u) +#define INTC_ICDISPR0_SW6_SHIFT (6u) +#define INTC_ICDISPR0_SW7_SHIFT (7u) +#define INTC_ICDISPR0_SW8_SHIFT (8u) +#define INTC_ICDISPR0_SW9_SHIFT (9u) +#define INTC_ICDISPR0_SW10_SHIFT (10u) +#define INTC_ICDISPR0_SW11_SHIFT (11u) +#define INTC_ICDISPR0_SW12_SHIFT (12u) +#define INTC_ICDISPR0_SW13_SHIFT (13u) +#define INTC_ICDISPR0_SW14_SHIFT (14u) +#define INTC_ICDISPR0_SW15_SHIFT (15u) +#define INTC_ICDISPR0_PMUIRQ0_SHIFT (16u) +#define INTC_ICDISPR0_COMMRX0_SHIFT (17u) +#define INTC_ICDISPR0_COMMTX0_SHIFT (18u) +#define INTC_ICDISPR0_CTIIRQ0_SHIFT (19u) + +#define INTC_ICDISPR1_IRQ0_SHIFT (0u) +#define INTC_ICDISPR1_IRQ1_SHIFT (1u) +#define INTC_ICDISPR1_IRQ2_SHIFT (2u) +#define INTC_ICDISPR1_IRQ3_SHIFT (3u) +#define INTC_ICDISPR1_IRQ4_SHIFT (4u) +#define INTC_ICDISPR1_IRQ5_SHIFT (5u) +#define INTC_ICDISPR1_IRQ6_SHIFT (6u) +#define INTC_ICDISPR1_IRQ7_SHIFT (7u) +#define INTC_ICDISPR1_PL310ERR_SHIFT (8u) +#define INTC_ICDISPR1_DMAINT0_SHIFT (9u) +#define INTC_ICDISPR1_DMAINT1_SHIFT (10u) +#define INTC_ICDISPR1_DMAINT2_SHIFT (11u) +#define INTC_ICDISPR1_DMAINT3_SHIFT (12u) +#define INTC_ICDISPR1_DMAINT4_SHIFT (13u) +#define INTC_ICDISPR1_DMAINT5_SHIFT (14u) +#define INTC_ICDISPR1_DMAINT6_SHIFT (15u) +#define INTC_ICDISPR1_DMAINT7_SHIFT (16u) +#define INTC_ICDISPR1_DMAINT8_SHIFT (17u) +#define INTC_ICDISPR1_DMAINT9_SHIFT (18u) +#define INTC_ICDISPR1_DMAINT10_SHIFT (19u) +#define INTC_ICDISPR1_DMAINT11_SHIFT (20u) +#define INTC_ICDISPR1_DMAINT12_SHIFT (21u) +#define INTC_ICDISPR1_DMAINT13_SHIFT (22u) +#define INTC_ICDISPR1_DMAINT14_SHIFT (23u) +#define INTC_ICDISPR1_DMAINT15_SHIFT (24u) +#define INTC_ICDISPR1_DMAERR_SHIFT (25u) + +#define INTC_ICDISPR2_USBI0_SHIFT (9u) +#define INTC_ICDISPR2_USBI1_SHIFT (10u) +#define INTC_ICDISPR2_S0_VI_VSYNC0_SHIFT (11u) +#define INTC_ICDISPR2_S0_LO_VSYNC0_SHIFT (12u) +#define INTC_ICDISPR2_S0_VSYNCERR0_SHIFT (13u) +#define INTC_ICDISPR2_GR3_VLINE0_SHIFT (14u) +#define INTC_ICDISPR2_S0_VFIELD0_SHIFT (15u) +#define INTC_ICDISPR2_IV1_VBUFERR0_SHIFT (16u) +#define INTC_ICDISPR2_IV3_VBUFERR0_SHIFT (17u) +#define INTC_ICDISPR2_IV5_VBUFERR0_SHIFT (18u) +#define INTC_ICDISPR2_IV6_VBUFERR0_SHIFT (19u) +#define INTC_ICDISPR2_S0_WLINE0_SHIFT (20u) +#define INTC_ICDISPR2_S1_VI_VSYNC0_SHIFT (21u) +#define INTC_ICDISPR2_S1_LO_VSYNC0_SHIFT (22u) +#define INTC_ICDISPR2_S1_VSYNCERR0_SHIFT (23u) +#define INTC_ICDISPR2_S1_VFIELD0_SHIFT (24u) +#define INTC_ICDISPR2_IV2_VBUFERR0_SHIFT (25u) +#define INTC_ICDISPR2_IV4_VBUFERR0_SHIFT (26u) +#define INTC_ICDISPR2_S1_WLINE0_SHIFT (27u) +#define INTC_ICDISPR2_OIR_VI_VSYNC0_SHIFT (28u) +#define INTC_ICDISPR2_OIR_LO_VSYNC0_SHIFT (29u) +#define INTC_ICDISPR2_OIR_VSYNCERR0_SHIFT (30u) +#define INTC_ICDISPR2_OIR_VFIELD0_SHIFT (31u) + +#define INTC_ICDISPR3_IV7_VBUFERR0_SHIFT (0u) +#define INTC_ICDISPR3_IV8_VBUFERR0_SHIFT (1u) +#define INTC_ICDISPR3_S0_VI_VSYNC1_SHIFT (3u) +#define INTC_ICDISPR3_S0_LO_VSYNC1_SHIFT (4u) +#define INTC_ICDISPR3_S0_VSYNCERR1_SHIFT (5u) +#define INTC_ICDISPR3_GR3_VLINE1_SHIFT (6u) +#define INTC_ICDISPR3_S0_VFIELD1_SHIFT (7u) +#define INTC_ICDISPR3_IV1_VBUFERR1_SHIFT (8u) +#define INTC_ICDISPR3_IV3_VBUFERR1_SHIFT (9u) +#define INTC_ICDISPR3_IV5_VBUFERR1_SHIFT (10u) +#define INTC_ICDISPR3_IV6_VBUFERR1_SHIFT (11u) +#define INTC_ICDISPR3_S0_WLINE1_SHIFT (12u) +#define INTC_ICDISPR3_S1_VI_VSYNC1_SHIFT (13u) +#define INTC_ICDISPR3_S1_LO_VSYNC1_SHIFT (14u) +#define INTC_ICDISPR3_S1_VSYNCERR1_SHIFT (15u) +#define INTC_ICDISPR3_S1_VFIELD1_SHIFT (16u) +#define INTC_ICDISPR3_IV2_VBUFERR1_SHIFT (17u) +#define INTC_ICDISPR3_IV4_VBUFERR1_SHIFT (18u) +#define INTC_ICDISPR3_S1_WLINE1_SHIFT (19u) +#define INTC_ICDISPR3_OIR_VI_VSYNC1_SHIFT (20u) +#define INTC_ICDISPR3_OIR_LO_VSYNC1_SHIFT (21u) +#define INTC_ICDISPR3_OIR_VLINE1_SHIFT (22u) +#define INTC_ICDISPR3_OIR_VFIELD1_SHIFT (23u) +#define INTC_ICDISPR3_IV7_VBUFERR1_SHIFT (24u) +#define INTC_ICDISPR3_IV8_VBUFERR1_SHIFT (25u) +#define INTC_ICDISPR3_IMRDI_SHIFT (27u) +#define INTC_ICDISPR3_IMR2I0_SHIFT (28u) +#define INTC_ICDISPR3_IMR2I1_SHIFT (29u) +#define INTC_ICDISPR3_JEDI_SHIFT (30u) +#define INTC_ICDISPR3_JDTI_SHIFT (31u) + +#define INTC_ICDISPR4_CMP0_SHIFT (0u) +#define INTC_ICDISPR4_CMP1_SHIFT (1u) +#define INTC_ICDISPR4_INT0_SHIFT (2u) +#define INTC_ICDISPR4_INT1_SHIFT (3u) +#define INTC_ICDISPR4_INT2_SHIFT (4u) +#define INTC_ICDISPR4_INT3_SHIFT (5u) +#define INTC_ICDISPR4_OSTM0TINT_SHIFT (6u) +#define INTC_ICDISPR4_OSTM1TINT_SHIFT (7u) +#define INTC_ICDISPR4_CMI_SHIFT (8u) +#define INTC_ICDISPR4_WTOUT_SHIFT (9u) +#define INTC_ICDISPR4_ITI_SHIFT (10u) +#define INTC_ICDISPR4_TGI0A_SHIFT (11u) +#define INTC_ICDISPR4_TGI0B_SHIFT (12u) +#define INTC_ICDISPR4_TGI0C_SHIFT (13u) +#define INTC_ICDISPR4_TGI0D_SHIFT (14u) +#define INTC_ICDISPR4_TGI0V_SHIFT (15u) +#define INTC_ICDISPR4_TGI0E_SHIFT (16u) +#define INTC_ICDISPR4_TGI0F_SHIFT (17u) +#define INTC_ICDISPR4_TGI1A_SHIFT (18u) +#define INTC_ICDISPR4_TGI1B_SHIFT (19u) +#define INTC_ICDISPR4_TGI1V_SHIFT (20u) +#define INTC_ICDISPR4_TGI1U_SHIFT (21u) +#define INTC_ICDISPR4_TGI2A_SHIFT (22u) +#define INTC_ICDISPR4_TGI2B_SHIFT (23u) +#define INTC_ICDISPR4_TGI2V_SHIFT (24u) +#define INTC_ICDISPR4_TGI2U_SHIFT (25u) +#define INTC_ICDISPR4_TGI3A_SHIFT (26u) +#define INTC_ICDISPR4_TGI3B_SHIFT (27u) +#define INTC_ICDISPR4_TGI3C_SHIFT (28u) +#define INTC_ICDISPR4_TGI3D_SHIFT (29u) +#define INTC_ICDISPR4_TGI3V_SHIFT (30u) +#define INTC_ICDISPR4_TGI4A_SHIFT (31u) + +#define INTC_ICDISPR5_TGI4B_SHIFT (0u) +#define INTC_ICDISPR5_TGI4C_SHIFT (1u) +#define INTC_ICDISPR5_TGI4D_SHIFT (2u) +#define INTC_ICDISPR5_TGI4V_SHIFT (3u) +#define INTC_ICDISPR5_CMI1_SHIFT (4u) +#define INTC_ICDISPR5_CMI2_SHIFT (5u) +#define INTC_ICDISPR5_SGDEI0_SHIFT (6u) +#define INTC_ICDISPR5_SGDEI1_SHIFT (7u) +#define INTC_ICDISPR5_SGDEI2_SHIFT (8u) +#define INTC_ICDISPR5_SGDEI3_SHIFT (9u) +#define INTC_ICDISPR5_ADI_SHIFT (10u) +#define INTC_ICDISPR5_LMTI_SHIFT (11u) +#define INTC_ICDISPR5_SSII0_SHIFT (12u) +#define INTC_ICDISPR5_SSIRXI0_SHIFT (13u) +#define INTC_ICDISPR5_SSITXI0_SHIFT (14u) +#define INTC_ICDISPR5_SSII1_SHIFT (15u) +#define INTC_ICDISPR5_SSIRXI1_SHIFT (16u) +#define INTC_ICDISPR5_SSITXI1_SHIFT (17u) +#define INTC_ICDISPR5_SSII2_SHIFT (18u) +#define INTC_ICDISPR5_SSIRTI2_SHIFT (19u) +#define INTC_ICDISPR5_SSII3_SHIFT (20u) +#define INTC_ICDISPR5_SSIRXI3_SHIFT (21u) +#define INTC_ICDISPR5_SSITXI3_SHIFT (22u) +#define INTC_ICDISPR5_SSII4_SHIFT (23u) +#define INTC_ICDISPR5_SSIRTI4_SHIFT (24u) +#define INTC_ICDISPR5_SSII5_SHIFT (25u) +#define INTC_ICDISPR5_SSIRXI5_SHIFT (26u) +#define INTC_ICDISPR5_SSITXI5_SHIFT (27u) +#define INTC_ICDISPR5_SPDIFI_SHIFT (28u) +#define INTC_ICDISPR5_INTIICTEI0_SHIFT (29u) +#define INTC_ICDISPR5_INTIICRI0_SHIFT (30u) +#define INTC_ICDISPR5_INTIICTI0_SHIFT (31u) + +#define INTC_ICDISPR6_INTIICSPI0_SHIFT (0u) +#define INTC_ICDISPR6_INTIICSTI0_SHIFT (1u) +#define INTC_ICDISPR6_INTIICNAKI0_SHIFT (2u) +#define INTC_ICDISPR6_INTIICALI0_SHIFT (3u) +#define INTC_ICDISPR6_INTIICTMOI0_SHIFT (4u) +#define INTC_ICDISPR6_INTIICTEI1_SHIFT (5u) +#define INTC_ICDISPR6_INTIICRI1_SHIFT (6u) +#define INTC_ICDISPR6_INTIICTI1_SHIFT (7u) +#define INTC_ICDISPR6_INTIICSPI1_SHIFT (8u) +#define INTC_ICDISPR6_INTIICSTI1_SHIFT (9u) +#define INTC_ICDISPR6_INTIICNAKI1_SHIFT (10u) +#define INTC_ICDISPR6_INTIICALI1_SHIFT (11u) +#define INTC_ICDISPR6_INTIICTMOI1_SHIFT (12u) +#define INTC_ICDISPR6_INTIICTEI2_SHIFT (13u) +#define INTC_ICDISPR6_INTIICRI2_SHIFT (14u) +#define INTC_ICDISPR6_INTIICTI2_SHIFT (15u) +#define INTC_ICDISPR6_INTIICSPI2_SHIFT (16u) +#define INTC_ICDISPR6_INTIICSTI2_SHIFT (17u) +#define INTC_ICDISPR6_INTIICNAKI2_SHIFT (18u) +#define INTC_ICDISPR6_INTIICALI2_SHIFT (19u) +#define INTC_ICDISPR6_INTIICTMOI2_SHIFT (20u) +#define INTC_ICDISPR6_INTIICTEI3_SHIFT (21u) +#define INTC_ICDISPR6_INTIICRI3_SHIFT (22u) +#define INTC_ICDISPR6_INTIICTI3_SHIFT (23u) +#define INTC_ICDISPR6_INTIICSPI3_SHIFT (24u) +#define INTC_ICDISPR6_INTIICSTI3_SHIFT (25u) +#define INTC_ICDISPR6_INTIICNAKI3_SHIFT (26u) +#define INTC_ICDISPR6_INTIICALI3_SHIFT (27u) +#define INTC_ICDISPR6_INTIICTMOI3_SHIFT (28u) +#define INTC_ICDISPR6_BRI0_SHIFT (29u) +#define INTC_ICDISPR6_ERI0_SHIFT (30u) +#define INTC_ICDISPR6_RXI0_SHIFT (31u) + +#define INTC_ICDISPR7_TXI0_SHIFT (0u) +#define INTC_ICDISPR7_BRI1_SHIFT (1u) +#define INTC_ICDISPR7_ERI1_SHIFT (2u) +#define INTC_ICDISPR7_RXI1_SHIFT (3u) +#define INTC_ICDISPR7_TXI1_SHIFT (4u) +#define INTC_ICDISPR7_BRI2_SHIFT (5u) +#define INTC_ICDISPR7_ERI2_SHIFT (6u) +#define INTC_ICDISPR7_RXI2_SHIFT (7u) +#define INTC_ICDISPR7_TXI2_SHIFT (8u) +#define INTC_ICDISPR7_BRI3_SHIFT (9u) +#define INTC_ICDISPR7_ERI3_SHIFT (10u) +#define INTC_ICDISPR7_RXI3_SHIFT (11u) +#define INTC_ICDISPR7_TXI3_SHIFT (12u) +#define INTC_ICDISPR7_BRI4_SHIFT (13u) +#define INTC_ICDISPR7_ERI4_SHIFT (14u) +#define INTC_ICDISPR7_RXI4_SHIFT (15u) +#define INTC_ICDISPR7_TXI4_SHIFT (16u) +#define INTC_ICDISPR7_BRI5_SHIFT (17u) +#define INTC_ICDISPR7_ERI5_SHIFT (18u) +#define INTC_ICDISPR7_RXI5_SHIFT (19u) +#define INTC_ICDISPR7_TXI5_SHIFT (20u) +#define INTC_ICDISPR7_BRI6_SHIFT (21u) +#define INTC_ICDISPR7_ERI6_SHIFT (22u) +#define INTC_ICDISPR7_RXI6_SHIFT (23u) +#define INTC_ICDISPR7_TXI6_SHIFT (24u) +#define INTC_ICDISPR7_BRI7_SHIFT (25u) +#define INTC_ICDISPR7_ERI7_SHIFT (26u) +#define INTC_ICDISPR7_RXI7_SHIFT (27u) +#define INTC_ICDISPR7_TXI7_SHIFT (28u) +#define INTC_ICDISPR7_INTRCANGERR_SHIFT (29u) +#define INTC_ICDISPR7_INTRCANGRECC_SHIFT (30u) +#define INTC_ICDISPR7_INTRCAN0REC_SHIFT (31u) + +#define INTC_ICDISPR8_INTRCAN0ERR_SHIFT (0u) +#define INTC_ICDISPR8_INTRCAN0TRX_SHIFT (1u) +#define INTC_ICDISPR8_INTRCAN1REC_SHIFT (2u) +#define INTC_ICDISPR8_INTRCAN1ERR_SHIFT (3u) +#define INTC_ICDISPR8_INTRCAN1TRX_SHIFT (4u) +#define INTC_ICDISPR8_INTRCAN2REC_SHIFT (5u) +#define INTC_ICDISPR8_INTRCAN2ERR_SHIFT (6u) +#define INTC_ICDISPR8_INTRCAN2TRX_SHIFT (7u) +#define INTC_ICDISPR8_INTRCAN3REC_SHIFT (8u) +#define INTC_ICDISPR8_INTRCAN3ERR_SHIFT (9u) +#define INTC_ICDISPR8_INTRCAN3TRX_SHIFT (10u) +#define INTC_ICDISPR8_INTRCAN4REC_SHIFT (11u) +#define INTC_ICDISPR8_INTRCAN4ERR_SHIFT (12u) +#define INTC_ICDISPR8_INTRCAN4TRX_SHIFT (13u) +#define INTC_ICDISPR8_SPEI0_SHIFT (14u) +#define INTC_ICDISPR8_SPRI0_SHIFT (15u) +#define INTC_ICDISPR8_SPTI0_SHIFT (16u) +#define INTC_ICDISPR8_SPEI1_SHIFT (17u) +#define INTC_ICDISPR8_SPRI1_SHIFT (18u) +#define INTC_ICDISPR8_SPTI1_SHIFT (19u) +#define INTC_ICDISPR8_SPEI2_SHIFT (20u) +#define INTC_ICDISPR8_SPRI2_SHIFT (21u) +#define INTC_ICDISPR8_SPTI2_SHIFT (22u) +#define INTC_ICDISPR8_SPEI3_SHIFT (23u) +#define INTC_ICDISPR8_SPRI3_SHIFT (24u) +#define INTC_ICDISPR8_SPTI3_SHIFT (25u) +#define INTC_ICDISPR8_SPEI4_SHIFT (26u) +#define INTC_ICDISPR8_SPRI4_SHIFT (27u) +#define INTC_ICDISPR8_SPTI4_SHIFT (28u) +#define INTC_ICDISPR8_IEBBTD_SHIFT (29u) +#define INTC_ICDISPR8_IEBBTERR_SHIFT (30u) +#define INTC_ICDISPR8_IEBBTSTA_SHIFT (31u) + +#define INTC_ICDISPR9_IEBBTV_SHIFT (0u) +#define INTC_ICDISPR9_ISY_SHIFT (1u) +#define INTC_ICDISPR9_IERR_SHIFT (2u) +#define INTC_ICDISPR9_ITARG_SHIFT (3u) +#define INTC_ICDISPR9_ISEC_SHIFT (4u) +#define INTC_ICDISPR9_IBUF_SHIFT (5u) +#define INTC_ICDISPR9_IREADY_SHIFT (6u) +#define INTC_ICDISPR9_FLSTE_SHIFT (7u) +#define INTC_ICDISPR9_FLTENDI_SHIFT (8u) +#define INTC_ICDISPR9_FLTREQ0I_SHIFT (9u) +#define INTC_ICDISPR9_FLTREQ1I_SHIFT (10u) +#define INTC_ICDISPR9_MMC0_SHIFT (11u) +#define INTC_ICDISPR9_MMC1_SHIFT (12u) +#define INTC_ICDISPR9_MMC2_SHIFT (13u) +#define INTC_ICDISPR9_SDHI0_3_SHIFT (14u) +#define INTC_ICDISPR9_SDHI0_0_SHIFT (15u) +#define INTC_ICDISPR9_SDHI0_1_SHIFT (16u) +#define INTC_ICDISPR9_SDHI1_3_SHIFT (17u) +#define INTC_ICDISPR9_SDHI1_0_SHIFT (18u) +#define INTC_ICDISPR9_SDHI1_1_SHIFT (19u) +#define INTC_ICDISPR9_ARM_SHIFT (20u) +#define INTC_ICDISPR9_PRD_SHIFT (21u) +#define INTC_ICDISPR9_CUP_SHIFT (22u) +#define INTC_ICDISPR9_SCUAI0_SHIFT (23u) +#define INTC_ICDISPR9_SCUAI1_SHIFT (24u) +#define INTC_ICDISPR9_SCUFDI0_SHIFT (25u) +#define INTC_ICDISPR9_SCUFDI1_SHIFT (26u) +#define INTC_ICDISPR9_SCUFDI2_SHIFT (27u) +#define INTC_ICDISPR9_SCUFDI3_SHIFT (28u) +#define INTC_ICDISPR9_SCUFUI0_SHIFT (29u) +#define INTC_ICDISPR9_SCUFUI1_SHIFT (30u) +#define INTC_ICDISPR9_SCUFUI2_SHIFT (31u) + +#define INTC_ICDISPR10_SCUFUI3_SHIFT (0u) +#define INTC_ICDISPR10_SCUDVI0_SHIFT (1u) +#define INTC_ICDISPR10_SCUDVI1_SHIFT (2u) +#define INTC_ICDISPR10_SCUDVI2_SHIFT (3u) +#define INTC_ICDISPR10_SCUDVI3_SHIFT (4u) +#define INTC_ICDISPR10_MLB_CINT_SHIFT (5u) +#define INTC_ICDISPR10_MLB_SINT_SHIFT (6u) +#define INTC_ICDISPR10_DRC0_SHIFT (7u) +#define INTC_ICDISPR10_DRC1_SHIFT (8u) +#define INTC_ICDISPR10_LINI0_INT_T_SHIFT (11u) +#define INTC_ICDISPR10_LINI0_INT_R_SHIFT (12u) +#define INTC_ICDISPR10_LINI0_INT_S_SHIFT (13u) +#define INTC_ICDISPR10_LINI0_INT_M_SHIFT (14u) +#define INTC_ICDISPR10_LINI1_INT_T_SHIFT (15u) +#define INTC_ICDISPR10_LINI1_INT_R_SHIFT (16u) +#define INTC_ICDISPR10_LINI1_INT_S_SHIFT (17u) +#define INTC_ICDISPR10_LINI1_INT_M_SHIFT (18u) +#define INTC_ICDISPR10_ERI0_SHIFT (27u) +#define INTC_ICDISPR10_RXI0_SHIFT (28u) +#define INTC_ICDISPR10_TXI0_SHIFT (29u) +#define INTC_ICDISPR10_TEI0_SHIFT (30u) +#define INTC_ICDISPR10_ERI1_SHIFT (31u) + +#define INTC_ICDISPR11_RXI1_SHIFT (0u) +#define INTC_ICDISPR11_TXI1_SHIFT (1u) +#define INTC_ICDISPR11_TEI1_SHIFT (2u) +#define INTC_ICDISPR11_AVBI_DATA_SHIFT (3u) +#define INTC_ICDISPR11_AVBI_ERROR_SHIFT (4u) +#define INTC_ICDISPR11_AVBI_MANAGE_SHIFT (5u) +#define INTC_ICDISPR11_AVBI_MAC_SHIFT (6u) +#define INTC_ICDISPR11_ETHERI_SHIFT (7u) +#define INTC_ICDISPR11_CEUI_SHIFT (12u) +#define INTC_ICDISPR11_H2XMLB_ERRINT_SHIFT (29u) +#define INTC_ICDISPR11_H2XIC1_ERRINT_SHIFT (30u) +#define INTC_ICDISPR11_X2HPERI1_ERRINT_SHIFT (31u) + +#define INTC_ICDISPR12_X2HPERI2_ERRINT_SHIFT (0u) +#define INTC_ICDISPR12_X2HPERI34_ERRINT_SHIFT (1u) +#define INTC_ICDISPR12_X2HPERI5_ERRINT_SHIFT (2u) +#define INTC_ICDISPR12_X2HPERI67_ERRINT_SHIFT (3u) +#define INTC_ICDISPR12_X2HDBGR_ERRINT_SHIFT (4u) +#define INTC_ICDISPR12_X2HBSC_ERRINT_SHIFT (5u) +#define INTC_ICDISPR12_X2HSPI1_ERRINT_SHIFT (6u) +#define INTC_ICDISPR12_X2HSPI2_ERRINT_SHIFT (7u) +#define INTC_ICDISPR12_PRRI_SHIFT (8u) +#define INTC_ICDISPR12_IFEI0_SHIFT (9u) +#define INTC_ICDISPR12_OFFI0_SHIFT (10u) +#define INTC_ICDISPR12_PFVEI0_SHIFT (11u) +#define INTC_ICDISPR12_IFEI1_SHIFT (12u) +#define INTC_ICDISPR12_OFFI1_SHIFT (13u) +#define INTC_ICDISPR12_PFVEI1_SHIFT (14u) + +#define INTC_ICDISPR13_TINT0_SHIFT (0u) +#define INTC_ICDISPR13_TINT1_SHIFT (1u) +#define INTC_ICDISPR13_TINT2_SHIFT (2u) +#define INTC_ICDISPR13_TINT3_SHIFT (3u) +#define INTC_ICDISPR13_TINT4_SHIFT (4u) +#define INTC_ICDISPR13_TINT5_SHIFT (5u) +#define INTC_ICDISPR13_TINT6_SHIFT (6u) +#define INTC_ICDISPR13_TINT7_SHIFT (7u) +#define INTC_ICDISPR13_TINT8_SHIFT (8u) +#define INTC_ICDISPR13_TINT9_SHIFT (9u) +#define INTC_ICDISPR13_TINT10_SHIFT (10u) +#define INTC_ICDISPR13_TINT11_SHIFT (11u) +#define INTC_ICDISPR13_TINT12_SHIFT (12u) +#define INTC_ICDISPR13_TINT13_SHIFT (13u) +#define INTC_ICDISPR13_TINT14_SHIFT (14u) +#define INTC_ICDISPR13_TINT15_SHIFT (15u) +#define INTC_ICDISPR13_TINT16_SHIFT (16u) +#define INTC_ICDISPR13_TINT17_SHIFT (17u) +#define INTC_ICDISPR13_TINT18_SHIFT (18u) +#define INTC_ICDISPR13_TINT19_SHIFT (19u) +#define INTC_ICDISPR13_TINT20_SHIFT (20u) +#define INTC_ICDISPR13_TINT21_SHIFT (21u) +#define INTC_ICDISPR13_TINT22_SHIFT (22u) +#define INTC_ICDISPR13_TINT23_SHIFT (23u) +#define INTC_ICDISPR13_TINT24_SHIFT (24u) +#define INTC_ICDISPR13_TINT25_SHIFT (25u) +#define INTC_ICDISPR13_TINT26_SHIFT (26u) +#define INTC_ICDISPR13_TINT27_SHIFT (27u) +#define INTC_ICDISPR13_TINT28_SHIFT (28u) +#define INTC_ICDISPR13_TINT29_SHIFT (29u) +#define INTC_ICDISPR13_TINT30_SHIFT (30u) +#define INTC_ICDISPR13_TINT31_SHIFT (31u) + +#define INTC_ICDISPR14_TINT32_SHIFT (0u) +#define INTC_ICDISPR14_TINT33_SHIFT (1u) +#define INTC_ICDISPR14_TINT34_SHIFT (2u) +#define INTC_ICDISPR14_TINT35_SHIFT (3u) +#define INTC_ICDISPR14_TINT36_SHIFT (4u) +#define INTC_ICDISPR14_TINT37_SHIFT (5u) +#define INTC_ICDISPR14_TINT38_SHIFT (6u) +#define INTC_ICDISPR14_TINT39_SHIFT (7u) +#define INTC_ICDISPR14_TINT40_SHIFT (8u) +#define INTC_ICDISPR14_TINT41_SHIFT (9u) +#define INTC_ICDISPR14_TINT42_SHIFT (10u) +#define INTC_ICDISPR14_TINT43_SHIFT (11u) +#define INTC_ICDISPR14_TINT44_SHIFT (12u) +#define INTC_ICDISPR14_TINT45_SHIFT (13u) +#define INTC_ICDISPR14_TINT46_SHIFT (14u) +#define INTC_ICDISPR14_TINT47_SHIFT (15u) +#define INTC_ICDISPR14_TINT48_SHIFT (16u) +#define INTC_ICDISPR14_TINT49_SHIFT (17u) +#define INTC_ICDISPR14_TINT50_SHIFT (18u) +#define INTC_ICDISPR14_TINT51_SHIFT (19u) +#define INTC_ICDISPR14_TINT52_SHIFT (20u) +#define INTC_ICDISPR14_TINT53_SHIFT (21u) +#define INTC_ICDISPR14_TINT54_SHIFT (22u) +#define INTC_ICDISPR14_TINT55_SHIFT (23u) +#define INTC_ICDISPR14_TINT56_SHIFT (24u) +#define INTC_ICDISPR14_TINT57_SHIFT (25u) +#define INTC_ICDISPR14_TINT58_SHIFT (26u) +#define INTC_ICDISPR14_TINT59_SHIFT (27u) +#define INTC_ICDISPR14_TINT60_SHIFT (28u) +#define INTC_ICDISPR14_TINT61_SHIFT (29u) +#define INTC_ICDISPR14_TINT62_SHIFT (30u) +#define INTC_ICDISPR14_TINT63_SHIFT (31u) + +#define INTC_ICDISPR15_TINT64_SHIFT (0u) +#define INTC_ICDISPR15_TINT65_SHIFT (1u) +#define INTC_ICDISPR15_TINT66_SHIFT (2u) +#define INTC_ICDISPR15_TINT67_SHIFT (3u) +#define INTC_ICDISPR15_TINT68_SHIFT (4u) +#define INTC_ICDISPR15_TINT69_SHIFT (5u) +#define INTC_ICDISPR15_TINT70_SHIFT (6u) +#define INTC_ICDISPR15_TINT71_SHIFT (7u) +#define INTC_ICDISPR15_TINT72_SHIFT (8u) +#define INTC_ICDISPR15_TINT73_SHIFT (9u) +#define INTC_ICDISPR15_TINT74_SHIFT (10u) +#define INTC_ICDISPR15_TINT75_SHIFT (11u) +#define INTC_ICDISPR15_TINT76_SHIFT (12u) +#define INTC_ICDISPR15_TINT77_SHIFT (13u) +#define INTC_ICDISPR15_TINT78_SHIFT (14u) +#define INTC_ICDISPR15_TINT79_SHIFT (15u) +#define INTC_ICDISPR15_TINT80_SHIFT (16u) +#define INTC_ICDISPR15_TINT81_SHIFT (17u) +#define INTC_ICDISPR15_TINT82_SHIFT (18u) +#define INTC_ICDISPR15_TINT83_SHIFT (19u) +#define INTC_ICDISPR15_TINT84_SHIFT (20u) +#define INTC_ICDISPR15_TINT85_SHIFT (21u) +#define INTC_ICDISPR15_TINT86_SHIFT (22u) +#define INTC_ICDISPR15_TINT87_SHIFT (23u) +#define INTC_ICDISPR15_TINT88_SHIFT (24u) +#define INTC_ICDISPR15_TINT89_SHIFT (25u) +#define INTC_ICDISPR15_TINT90_SHIFT (26u) +#define INTC_ICDISPR15_TINT91_SHIFT (27u) +#define INTC_ICDISPR15_TINT92_SHIFT (28u) +#define INTC_ICDISPR15_TINT93_SHIFT (29u) +#define INTC_ICDISPR15_TINT94_SHIFT (30u) +#define INTC_ICDISPR15_TINT95_SHIFT (31u) + +#define INTC_ICDISPR16_TINT96_SHIFT (0u) +#define INTC_ICDISPR16_TINT97_SHIFT (1u) +#define INTC_ICDISPR16_TINT98_SHIFT (2u) +#define INTC_ICDISPR16_TINT99_SHIFT (3u) +#define INTC_ICDISPR16_TINT100_SHIFT (4u) +#define INTC_ICDISPR16_TINT101_SHIFT (5u) +#define INTC_ICDISPR16_TINT102_SHIFT (6u) +#define INTC_ICDISPR16_TINT103_SHIFT (7u) +#define INTC_ICDISPR16_TINT104_SHIFT (8u) +#define INTC_ICDISPR16_TINT105_SHIFT (9u) +#define INTC_ICDISPR16_TINT106_SHIFT (10u) +#define INTC_ICDISPR16_TINT107_SHIFT (11u) +#define INTC_ICDISPR16_TINT108_SHIFT (12u) +#define INTC_ICDISPR16_TINT109_SHIFT (13u) +#define INTC_ICDISPR16_TINT110_SHIFT (14u) +#define INTC_ICDISPR16_TINT111_SHIFT (15u) +#define INTC_ICDISPR16_TINT112_SHIFT (16u) +#define INTC_ICDISPR16_TINT113_SHIFT (17u) +#define INTC_ICDISPR16_TINT114_SHIFT (18u) +#define INTC_ICDISPR16_TINT115_SHIFT (19u) +#define INTC_ICDISPR16_TINT116_SHIFT (20u) +#define INTC_ICDISPR16_TINT117_SHIFT (21u) +#define INTC_ICDISPR16_TINT118_SHIFT (22u) +#define INTC_ICDISPR16_TINT119_SHIFT (23u) +#define INTC_ICDISPR16_TINT120_SHIFT (24u) +#define INTC_ICDISPR16_TINT121_SHIFT (25u) +#define INTC_ICDISPR16_TINT122_SHIFT (26u) +#define INTC_ICDISPR16_TINT123_SHIFT (27u) +#define INTC_ICDISPR16_TINT124_SHIFT (28u) +#define INTC_ICDISPR16_TINT125_SHIFT (29u) +#define INTC_ICDISPR16_TINT126_SHIFT (30u) +#define INTC_ICDISPR16_TINT127_SHIFT (31u) + +#define INTC_ICDISPR17_TINT128_SHIFT (0u) +#define INTC_ICDISPR17_TINT129_SHIFT (1u) +#define INTC_ICDISPR17_TINT130_SHIFT (2u) +#define INTC_ICDISPR17_TINT131_SHIFT (3u) +#define INTC_ICDISPR17_TINT132_SHIFT (4u) +#define INTC_ICDISPR17_TINT133_SHIFT (5u) +#define INTC_ICDISPR17_TINT134_SHIFT (6u) +#define INTC_ICDISPR17_TINT135_SHIFT (7u) +#define INTC_ICDISPR17_TINT136_SHIFT (8u) +#define INTC_ICDISPR17_TINT137_SHIFT (9u) +#define INTC_ICDISPR17_TINT138_SHIFT (10u) +#define INTC_ICDISPR17_TINT139_SHIFT (11u) +#define INTC_ICDISPR17_TINT140_SHIFT (12u) +#define INTC_ICDISPR17_TINT141_SHIFT (13u) +#define INTC_ICDISPR17_TINT142_SHIFT (14u) +#define INTC_ICDISPR17_TINT143_SHIFT (15u) +#define INTC_ICDISPR17_TINT144_SHIFT (16u) +#define INTC_ICDISPR17_TINT145_SHIFT (17u) +#define INTC_ICDISPR17_TINT146_SHIFT (18u) +#define INTC_ICDISPR17_TINT147_SHIFT (19u) +#define INTC_ICDISPR17_TINT148_SHIFT (20u) +#define INTC_ICDISPR17_TINT149_SHIFT (21u) +#define INTC_ICDISPR17_TINT150_SHIFT (22u) +#define INTC_ICDISPR17_TINT151_SHIFT (23u) +#define INTC_ICDISPR17_TINT152_SHIFT (24u) +#define INTC_ICDISPR17_TINT153_SHIFT (25u) +#define INTC_ICDISPR17_TINT154_SHIFT (26u) +#define INTC_ICDISPR17_TINT155_SHIFT (27u) +#define INTC_ICDISPR17_TINT156_SHIFT (28u) +#define INTC_ICDISPR17_TINT157_SHIFT (29u) +#define INTC_ICDISPR17_TINT158_SHIFT (30u) +#define INTC_ICDISPR17_TINT159_SHIFT (31u) + +#define INTC_ICDISPR18_TINT160_SHIFT (0u) +#define INTC_ICDISPR18_TINT161_SHIFT (1u) +#define INTC_ICDISPR18_TINT162_SHIFT (2u) +#define INTC_ICDISPR18_TINT163_SHIFT (3u) +#define INTC_ICDISPR18_TINT164_SHIFT (4u) +#define INTC_ICDISPR18_TINT165_SHIFT (5u) +#define INTC_ICDISPR18_TINT166_SHIFT (6u) +#define INTC_ICDISPR18_TINT167_SHIFT (7u) +#define INTC_ICDISPR18_TINT168_SHIFT (8u) +#define INTC_ICDISPR18_TINT169_SHIFT (9u) +#define INTC_ICDISPR18_TINT170_SHIFT (10u) + +#define INTC_ICDICPR0_SW0_SHIFT (0u) +#define INTC_ICDICPR0_SW1_SHIFT (1u) +#define INTC_ICDICPR0_SW2_SHIFT (2u) +#define INTC_ICDICPR0_SW3_SHIFT (3u) +#define INTC_ICDICPR0_SW4_SHIFT (4u) +#define INTC_ICDICPR0_SW5_SHIFT (5u) +#define INTC_ICDICPR0_SW6_SHIFT (6u) +#define INTC_ICDICPR0_SW7_SHIFT (7u) +#define INTC_ICDICPR0_SW8_SHIFT (8u) +#define INTC_ICDICPR0_SW9_SHIFT (9u) +#define INTC_ICDICPR0_SW10_SHIFT (10u) +#define INTC_ICDICPR0_SW11_SHIFT (11u) +#define INTC_ICDICPR0_SW12_SHIFT (12u) +#define INTC_ICDICPR0_SW13_SHIFT (13u) +#define INTC_ICDICPR0_SW14_SHIFT (14u) +#define INTC_ICDICPR0_SW15_SHIFT (15u) +#define INTC_ICDICPR0_PMUIRQ0_SHIFT (16u) +#define INTC_ICDICPR0_COMMRX0_SHIFT (17u) +#define INTC_ICDICPR0_COMMTX0_SHIFT (18u) +#define INTC_ICDICPR0_CTIIRQ0_SHIFT (19u) + +#define INTC_ICDICPR1_IRQ0_SHIFT (0u) +#define INTC_ICDICPR1_IRQ1_SHIFT (1u) +#define INTC_ICDICPR1_IRQ2_SHIFT (2u) +#define INTC_ICDICPR1_IRQ3_SHIFT (3u) +#define INTC_ICDICPR1_IRQ4_SHIFT (4u) +#define INTC_ICDICPR1_IRQ5_SHIFT (5u) +#define INTC_ICDICPR1_IRQ6_SHIFT (6u) +#define INTC_ICDICPR1_IRQ7_SHIFT (7u) +#define INTC_ICDICPR1_PL310ERR_SHIFT (8u) +#define INTC_ICDICPR1_DMAINT0_SHIFT (9u) +#define INTC_ICDICPR1_DMAINT1_SHIFT (10u) +#define INTC_ICDICPR1_DMAINT2_SHIFT (11u) +#define INTC_ICDICPR1_DMAINT3_SHIFT (12u) +#define INTC_ICDICPR1_DMAINT4_SHIFT (13u) +#define INTC_ICDICPR1_DMAINT5_SHIFT (14u) +#define INTC_ICDICPR1_DMAINT6_SHIFT (15u) +#define INTC_ICDICPR1_DMAINT7_SHIFT (16u) +#define INTC_ICDICPR1_DMAINT8_SHIFT (17u) +#define INTC_ICDICPR1_DMAINT9_SHIFT (18u) +#define INTC_ICDICPR1_DMAINT10_SHIFT (19u) +#define INTC_ICDICPR1_DMAINT11_SHIFT (20u) +#define INTC_ICDICPR1_DMAINT12_SHIFT (21u) +#define INTC_ICDICPR1_DMAINT13_SHIFT (22u) +#define INTC_ICDICPR1_DMAINT14_SHIFT (23u) +#define INTC_ICDICPR1_DMAINT15_SHIFT (24u) +#define INTC_ICDICPR1_DMAERR_SHIFT (25u) + +#define INTC_ICDICPR2_USBI0_SHIFT (9u) +#define INTC_ICDICPR2_USBI1_SHIFT (10u) +#define INTC_ICDICPR2_S0_VI_VSYNC0_SHIFT (11u) +#define INTC_ICDICPR2_S0_LO_VSYNC0_SHIFT (12u) +#define INTC_ICDICPR2_S0_VSYNCERR0_SHIFT (13u) +#define INTC_ICDICPR2_GR3_VLINE0_SHIFT (14u) +#define INTC_ICDICPR2_S0_VFIELD0_SHIFT (15u) +#define INTC_ICDICPR2_IV1_VBUFERR0_SHIFT (16u) +#define INTC_ICDICPR2_IV3_VBUFERR0_SHIFT (17u) +#define INTC_ICDICPR2_IV5_VBUFERR0_SHIFT (18u) +#define INTC_ICDICPR2_IV6_VBUFERR0_SHIFT (19u) +#define INTC_ICDICPR2_S0_WLINE0_SHIFT (20u) +#define INTC_ICDICPR2_S1_VI_VSYNC0_SHIFT (21u) +#define INTC_ICDICPR2_S1_LO_VSYNC0_SHIFT (22u) +#define INTC_ICDICPR2_S1_VSYNCERR0_SHIFT (23u) +#define INTC_ICDICPR2_S1_VFIELD0_SHIFT (24u) +#define INTC_ICDICPR2_IV2_VBUFERR0_SHIFT (25u) +#define INTC_ICDICPR2_IV4_VBUFERR0_SHIFT (26u) +#define INTC_ICDICPR2_S1_WLINE0_SHIFT (27u) +#define INTC_ICDICPR2_OIR_VI_VSYNC0_SHIFT (28u) +#define INTC_ICDICPR2_OIR_LO_VSYNC0_SHIFT (29u) +#define INTC_ICDICPR2_OIR_VSYNCERR0_SHIFT (30u) +#define INTC_ICDICPR2_OIR_VFIELD0_SHIFT (31u) + +#define INTC_ICDICPR3_IV7_VBUFERR0_SHIFT (0u) +#define INTC_ICDICPR3_IV8_VBUFERR0_SHIFT (1u) +#define INTC_ICDICPR3_S0_VI_VSYNC1_SHIFT (3u) +#define INTC_ICDICPR3_S0_LO_VSYNC1_SHIFT (4u) +#define INTC_ICDICPR3_S0_VSYNCERR1_SHIFT (5u) +#define INTC_ICDICPR3_GR3_VLINE1_SHIFT (6u) +#define INTC_ICDICPR3_S0_VFIELD1_SHIFT (7u) +#define INTC_ICDICPR3_IV1_VBUFERR1_SHIFT (8u) +#define INTC_ICDICPR3_IV3_VBUFERR1_SHIFT (9u) +#define INTC_ICDICPR3_IV5_VBUFERR1_SHIFT (10u) +#define INTC_ICDICPR3_IV6_VBUFERR1_SHIFT (11u) +#define INTC_ICDICPR3_S0_WLINE1_SHIFT (12u) +#define INTC_ICDICPR3_S1_VI_VSYNC1_SHIFT (13u) +#define INTC_ICDICPR3_S1_LO_VSYNC1_SHIFT (14u) +#define INTC_ICDICPR3_S1_VSYNCERR1_SHIFT (15u) +#define INTC_ICDICPR3_S1_VFIELD1_SHIFT (16u) +#define INTC_ICDICPR3_IV2_VBUFERR1_SHIFT (17u) +#define INTC_ICDICPR3_IV4_VBUFERR1_SHIFT (18u) +#define INTC_ICDICPR3_S1_WLINE1_SHIFT (19u) +#define INTC_ICDICPR3_OIR_VI_VSYNC1_SHIFT (20u) +#define INTC_ICDICPR3_OIR_LO_VSYNC1_SHIFT (21u) +#define INTC_ICDICPR3_OIR_VLINE1_SHIFT (22u) +#define INTC_ICDICPR3_OIR_VFIELD1_SHIFT (23u) +#define INTC_ICDICPR3_IV7_VBUFERR1_SHIFT (24u) +#define INTC_ICDICPR3_IV8_VBUFERR1_SHIFT (25u) +#define INTC_ICDICPR3_IMRDI_SHIFT (27u) +#define INTC_ICDICPR3_IMR2I0_SHIFT (28u) +#define INTC_ICDICPR3_IMR2I1_SHIFT (29u) +#define INTC_ICDICPR3_JEDI_SHIFT (30u) +#define INTC_ICDICPR3_JDTI_SHIFT (31u) + +#define INTC_ICDICPR4_CMP0_SHIFT (0u) +#define INTC_ICDICPR4_CMP1_SHIFT (1u) +#define INTC_ICDICPR4_INT0_SHIFT (2u) +#define INTC_ICDICPR4_INT1_SHIFT (3u) +#define INTC_ICDICPR4_INT2_SHIFT (4u) +#define INTC_ICDICPR4_INT3_SHIFT (5u) +#define INTC_ICDICPR4_OSTM0TINT_SHIFT (6u) +#define INTC_ICDICPR4_OSTM1TINT_SHIFT (7u) +#define INTC_ICDICPR4_CMI_SHIFT (8u) +#define INTC_ICDICPR4_WTOUT_SHIFT (9u) +#define INTC_ICDICPR4_ITI_SHIFT (10u) +#define INTC_ICDICPR4_TGI0A_SHIFT (11u) +#define INTC_ICDICPR4_TGI0B_SHIFT (12u) +#define INTC_ICDICPR4_TGI0C_SHIFT (13u) +#define INTC_ICDICPR4_TGI0D_SHIFT (14u) +#define INTC_ICDICPR4_TGI0V_SHIFT (15u) +#define INTC_ICDICPR4_TGI0E_SHIFT (16u) +#define INTC_ICDICPR4_TGI0F_SHIFT (17u) +#define INTC_ICDICPR4_TGI1A_SHIFT (18u) +#define INTC_ICDICPR4_TGI1B_SHIFT (19u) +#define INTC_ICDICPR4_TGI1V_SHIFT (20u) +#define INTC_ICDICPR4_TGI1U_SHIFT (21u) +#define INTC_ICDICPR4_TGI2A_SHIFT (22u) +#define INTC_ICDICPR4_TGI2B_SHIFT (23u) +#define INTC_ICDICPR4_TGI2V_SHIFT (24u) +#define INTC_ICDICPR4_TGI2U_SHIFT (25u) +#define INTC_ICDICPR4_TGI3A_SHIFT (26u) +#define INTC_ICDICPR4_TGI3B_SHIFT (27u) +#define INTC_ICDICPR4_TGI3C_SHIFT (28u) +#define INTC_ICDICPR4_TGI3D_SHIFT (29u) +#define INTC_ICDICPR4_TGI3V_SHIFT (30u) +#define INTC_ICDICPR4_TGI4A_SHIFT (31u) + +#define INTC_ICDICPR5_TGI4B_SHIFT (0u) +#define INTC_ICDICPR5_TGI4C_SHIFT (1u) +#define INTC_ICDICPR5_TGI4D_SHIFT (2u) +#define INTC_ICDICPR5_TGI4V_SHIFT (3u) +#define INTC_ICDICPR5_CMI1_SHIFT (4u) +#define INTC_ICDICPR5_CMI2_SHIFT (5u) +#define INTC_ICDICPR5_SGDEI0_SHIFT (6u) +#define INTC_ICDICPR5_SGDEI1_SHIFT (7u) +#define INTC_ICDICPR5_SGDEI2_SHIFT (8u) +#define INTC_ICDICPR5_SGDEI3_SHIFT (9u) +#define INTC_ICDICPR5_ADI_SHIFT (10u) +#define INTC_ICDICPR5_LMTI_SHIFT (11u) +#define INTC_ICDICPR5_SSII0_SHIFT (12u) +#define INTC_ICDICPR5_SSIRXI0_SHIFT (13u) +#define INTC_ICDICPR5_SSITXI0_SHIFT (14u) +#define INTC_ICDICPR5_SSII1_SHIFT (15u) +#define INTC_ICDICPR5_SSIRXI1_SHIFT (16u) +#define INTC_ICDICPR5_SSITXI1_SHIFT (17u) +#define INTC_ICDICPR5_SSII2_SHIFT (18u) +#define INTC_ICDICPR5_SSIRTI2_SHIFT (19u) +#define INTC_ICDICPR5_SSII3_SHIFT (20u) +#define INTC_ICDICPR5_SSIRXI3_SHIFT (21u) +#define INTC_ICDICPR5_SSITXI3_SHIFT (22u) +#define INTC_ICDICPR5_SSII4_SHIFT (23u) +#define INTC_ICDICPR5_SSIRTI4_SHIFT (24u) +#define INTC_ICDICPR5_SSII5_SHIFT (25u) +#define INTC_ICDICPR5_SSIRXI5_SHIFT (26u) +#define INTC_ICDICPR5_SSITXI5_SHIFT (27u) +#define INTC_ICDICPR5_SPDIFI_SHIFT (28u) +#define INTC_ICDICPR5_INTIICTEI0_SHIFT (29u) +#define INTC_ICDICPR5_INTIICRI0_SHIFT (30u) +#define INTC_ICDICPR5_INTIICTI0_SHIFT (31u) + +#define INTC_ICDICPR6_INTIICSPI0_SHIFT (0u) +#define INTC_ICDICPR6_INTIICSTI0_SHIFT (1u) +#define INTC_ICDICPR6_INTIICNAKI0_SHIFT (2u) +#define INTC_ICDICPR6_INTIICALI0_SHIFT (3u) +#define INTC_ICDICPR6_INTIICTMOI0_SHIFT (4u) +#define INTC_ICDICPR6_INTIICTEI1_SHIFT (5u) +#define INTC_ICDICPR6_INTIICRI1_SHIFT (6u) +#define INTC_ICDICPR6_INTIICTI1_SHIFT (7u) +#define INTC_ICDICPR6_INTIICSPI1_SHIFT (8u) +#define INTC_ICDICPR6_INTIICSTI1_SHIFT (9u) +#define INTC_ICDICPR6_INTIICNAKI1_SHIFT (10u) +#define INTC_ICDICPR6_INTIICALI1_SHIFT (11u) +#define INTC_ICDICPR6_INTIICTMOI1_SHIFT (12u) +#define INTC_ICDICPR6_INTIICTEI2_SHIFT (13u) +#define INTC_ICDICPR6_INTIICRI2_SHIFT (14u) +#define INTC_ICDICPR6_INTIICTI2_SHIFT (15u) +#define INTC_ICDICPR6_INTIICSPI2_SHIFT (16u) +#define INTC_ICDICPR6_INTIICSTI2_SHIFT (17u) +#define INTC_ICDICPR6_INTIICNAKI2_SHIFT (18u) +#define INTC_ICDICPR6_INTIICALI2_SHIFT (19u) +#define INTC_ICDICPR6_INTIICTMOI2_SHIFT (20u) +#define INTC_ICDICPR6_INTIICTEI3_SHIFT (21u) +#define INTC_ICDICPR6_INTIICRI3_SHIFT (22u) +#define INTC_ICDICPR6_INTIICTI3_SHIFT (23u) +#define INTC_ICDICPR6_INTIICSPI3_SHIFT (24u) +#define INTC_ICDICPR6_INTIICSTI3_SHIFT (25u) +#define INTC_ICDICPR6_INTIICNAKI3_SHIFT (26u) +#define INTC_ICDICPR6_INTIICALI3_SHIFT (27u) +#define INTC_ICDICPR6_INTIICTMOI3_SHIFT (28u) +#define INTC_ICDICPR6_BRI0_SHIFT (29u) +#define INTC_ICDICPR6_ERI0_SHIFT (30u) +#define INTC_ICDICPR6_RXI0_SHIFT (31u) + +#define INTC_ICDICPR7_TXI0_SHIFT (0u) +#define INTC_ICDICPR7_BRI1_SHIFT (1u) +#define INTC_ICDICPR7_ERI1_SHIFT (2u) +#define INTC_ICDICPR7_RXI1_SHIFT (3u) +#define INTC_ICDICPR7_TXI1_SHIFT (4u) +#define INTC_ICDICPR7_BRI2_SHIFT (5u) +#define INTC_ICDICPR7_ERI2_SHIFT (6u) +#define INTC_ICDICPR7_RXI2_SHIFT (7u) +#define INTC_ICDICPR7_TXI2_SHIFT (8u) +#define INTC_ICDICPR7_BRI3_SHIFT (9u) +#define INTC_ICDICPR7_ERI3_SHIFT (10u) +#define INTC_ICDICPR7_RXI3_SHIFT (11u) +#define INTC_ICDICPR7_TXI3_SHIFT (12u) +#define INTC_ICDICPR7_BRI4_SHIFT (13u) +#define INTC_ICDICPR7_ERI4_SHIFT (14u) +#define INTC_ICDICPR7_RXI4_SHIFT (15u) +#define INTC_ICDICPR7_TXI4_SHIFT (16u) +#define INTC_ICDICPR7_BRI5_SHIFT (17u) +#define INTC_ICDICPR7_ERI5_SHIFT (18u) +#define INTC_ICDICPR7_RXI5_SHIFT (19u) +#define INTC_ICDICPR7_TXI5_SHIFT (20u) +#define INTC_ICDICPR7_BRI6_SHIFT (21u) +#define INTC_ICDICPR7_ERI6_SHIFT (22u) +#define INTC_ICDICPR7_RXI6_SHIFT (23u) +#define INTC_ICDICPR7_TXI6_SHIFT (24u) +#define INTC_ICDICPR7_BRI7_SHIFT (25u) +#define INTC_ICDICPR7_ERI7_SHIFT (26u) +#define INTC_ICDICPR7_RXI7_SHIFT (27u) +#define INTC_ICDICPR7_TXI7_SHIFT (28u) +#define INTC_ICDICPR7_INTRCANGERR_SHIFT (29u) +#define INTC_ICDICPR7_INTRCANGRECC_SHIFT (30u) +#define INTC_ICDICPR7_INTRCAN0REC_SHIFT (31u) + +#define INTC_ICDICPR8_INTRCAN0ERR_SHIFT (0u) +#define INTC_ICDICPR8_INTRCAN0TRX_SHIFT (1u) +#define INTC_ICDICPR8_INTRCAN1REC_SHIFT (2u) +#define INTC_ICDICPR8_INTRCAN1ERR_SHIFT (3u) +#define INTC_ICDICPR8_INTRCAN1TRX_SHIFT (4u) +#define INTC_ICDICPR8_INTRCAN2REC_SHIFT (5u) +#define INTC_ICDICPR8_INTRCAN2ERR_SHIFT (6u) +#define INTC_ICDICPR8_INTRCAN2TRX_SHIFT (7u) +#define INTC_ICDICPR8_INTRCAN3REC_SHIFT (8u) +#define INTC_ICDICPR8_INTRCAN3ERR_SHIFT (9u) +#define INTC_ICDICPR8_INTRCAN3TRX_SHIFT (10u) +#define INTC_ICDICPR8_INTRCAN4REC_SHIFT (11u) +#define INTC_ICDICPR8_INTRCAN4ERR_SHIFT (12u) +#define INTC_ICDICPR8_INTRCAN4TRX_SHIFT (13u) +#define INTC_ICDICPR8_SPEI0_SHIFT (14u) +#define INTC_ICDICPR8_SPRI0_SHIFT (15u) +#define INTC_ICDICPR8_SPTI0_SHIFT (16u) +#define INTC_ICDICPR8_SPEI1_SHIFT (17u) +#define INTC_ICDICPR8_SPRI1_SHIFT (18u) +#define INTC_ICDICPR8_SPTI1_SHIFT (19u) +#define INTC_ICDICPR8_SPEI2_SHIFT (20u) +#define INTC_ICDICPR8_SPRI2_SHIFT (21u) +#define INTC_ICDICPR8_SPTI2_SHIFT (22u) +#define INTC_ICDICPR8_SPEI3_SHIFT (23u) +#define INTC_ICDICPR8_SPRI3_SHIFT (24u) +#define INTC_ICDICPR8_SPTI3_SHIFT (25u) +#define INTC_ICDICPR8_SPEI4_SHIFT (26u) +#define INTC_ICDICPR8_SPRI4_SHIFT (27u) +#define INTC_ICDICPR8_SPTI4_SHIFT (28u) +#define INTC_ICDICPR8_IEBBTD_SHIFT (29u) +#define INTC_ICDICPR8_IEBBTERR_SHIFT (30u) +#define INTC_ICDICPR8_IEBBTSTA_SHIFT (31u) + +#define INTC_ICDICPR9_IEBBTV_SHIFT (0u) +#define INTC_ICDICPR9_ISY_SHIFT (1u) +#define INTC_ICDICPR9_IERR_SHIFT (2u) +#define INTC_ICDICPR9_ITARG_SHIFT (3u) +#define INTC_ICDICPR9_ISEC_SHIFT (4u) +#define INTC_ICDICPR9_IBUF_SHIFT (5u) +#define INTC_ICDICPR9_IREADY_SHIFT (6u) +#define INTC_ICDICPR9_FLSTE_SHIFT (7u) +#define INTC_ICDICPR9_FLTENDI_SHIFT (8u) +#define INTC_ICDICPR9_FLTREQ0I_SHIFT (9u) +#define INTC_ICDICPR9_FLTREQ1I_SHIFT (10u) +#define INTC_ICDICPR9_MMC0_SHIFT (11u) +#define INTC_ICDICPR9_MMC1_SHIFT (12u) +#define INTC_ICDICPR9_MMC2_SHIFT (13u) +#define INTC_ICDICPR9_SDHI0_3_SHIFT (14u) +#define INTC_ICDICPR9_SDHI0_0_SHIFT (15u) +#define INTC_ICDICPR9_SDHI0_1_SHIFT (16u) +#define INTC_ICDICPR9_SDHI1_3_SHIFT (17u) +#define INTC_ICDICPR9_SDHI1_0_SHIFT (18u) +#define INTC_ICDICPR9_SDHI1_1_SHIFT (19u) +#define INTC_ICDICPR9_ARM_SHIFT (20u) +#define INTC_ICDICPR9_PRD_SHIFT (21u) +#define INTC_ICDICPR9_CUP_SHIFT (22u) +#define INTC_ICDICPR9_SCUAI0_SHIFT (23u) +#define INTC_ICDICPR9_SCUAI1_SHIFT (24u) +#define INTC_ICDICPR9_SCUFDI0_SHIFT (25u) +#define INTC_ICDICPR9_SCUFDI1_SHIFT (26u) +#define INTC_ICDICPR9_SCUFDI2_SHIFT (27u) +#define INTC_ICDICPR9_SCUFDI3_SHIFT (28u) +#define INTC_ICDICPR9_SCUFUI0_SHIFT (29u) +#define INTC_ICDICPR9_SCUFUI1_SHIFT (30u) +#define INTC_ICDICPR9_SCUFUI2_SHIFT (31u) + +#define INTC_ICDICPR10_SCUFUI3_SHIFT (0u) +#define INTC_ICDICPR10_SCUDVI0_SHIFT (1u) +#define INTC_ICDICPR10_SCUDVI1_SHIFT (2u) +#define INTC_ICDICPR10_SCUDVI2_SHIFT (3u) +#define INTC_ICDICPR10_SCUDVI3_SHIFT (4u) +#define INTC_ICDICPR10_MLB_CINT_SHIFT (5u) +#define INTC_ICDICPR10_MLB_SINT_SHIFT (6u) +#define INTC_ICDICPR10_DRC0_SHIFT (7u) +#define INTC_ICDICPR10_DRC1_SHIFT (8u) +#define INTC_ICDICPR10_LINI0_INT_T_SHIFT (11u) +#define INTC_ICDICPR10_LINI0_INT_R_SHIFT (12u) +#define INTC_ICDICPR10_LINI0_INT_S_SHIFT (13u) +#define INTC_ICDICPR10_LINI0_INT_M_SHIFT (14u) +#define INTC_ICDICPR10_LINI1_INT_T_SHIFT (15u) +#define INTC_ICDICPR10_LINI1_INT_R_SHIFT (16u) +#define INTC_ICDICPR10_LINI1_INT_S_SHIFT (17u) +#define INTC_ICDICPR10_LINI1_INT_M_SHIFT (18u) +#define INTC_ICDICPR10_ERI0_SHIFT (27u) +#define INTC_ICDICPR10_RXI0_SHIFT (28u) +#define INTC_ICDICPR10_TXI0_SHIFT (29u) +#define INTC_ICDICPR10_TEI0_SHIFT (30u) +#define INTC_ICDICPR10_ERI1_SHIFT (31u) + +#define INTC_ICDICPR11_RXI1_SHIFT (0u) +#define INTC_ICDICPR11_TXI1_SHIFT (1u) +#define INTC_ICDICPR11_TEI1_SHIFT (2u) +#define INTC_ICDICPR11_AVBI_DATA_SHIFT (3u) +#define INTC_ICDICPR11_AVBI_ERROR_SHIFT (4u) +#define INTC_ICDICPR11_AVBI_MANAGE_SHIFT (5u) +#define INTC_ICDICPR11_AVBI_MAC_SHIFT (6u) +#define INTC_ICDICPR11_ETHERI_SHIFT (7u) +#define INTC_ICDICPR11_CEUI_SHIFT (12u) +#define INTC_ICDICPR11_H2XMLB_ERRINT_SHIFT (29u) +#define INTC_ICDICPR11_H2XIC1_ERRINT_SHIFT (30u) +#define INTC_ICDICPR11_X2HPERI1_ERRINT_SHIFT (31u) + +#define INTC_ICDICPR12_X2HPERI2_ERRINT_SHIFT (0u) +#define INTC_ICDICPR12_X2HPERI34_ERRINT_SHIFT (1u) +#define INTC_ICDICPR12_X2HPERI5_ERRINT_SHIFT (2u) +#define INTC_ICDICPR12_X2HPERI67_ERRINT_SHIFT (3u) +#define INTC_ICDICPR12_X2HDBGR_ERRINT_SHIFT (4u) +#define INTC_ICDICPR12_X2HBSC_ERRINT_SHIFT (5u) +#define INTC_ICDICPR12_X2HSPI1_ERRINT_SHIFT (6u) +#define INTC_ICDICPR12_X2HSPI2_ERRINT_SHIFT (7u) +#define INTC_ICDICPR12_PRRI_SHIFT (8u) +#define INTC_ICDICPR12_IFEI0_SHIFT (9u) +#define INTC_ICDICPR12_OFFI0_SHIFT (10u) +#define INTC_ICDICPR12_PFVEI0_SHIFT (11u) +#define INTC_ICDICPR12_IFEI1_SHIFT (12u) +#define INTC_ICDICPR12_OFFI1_SHIFT (13u) +#define INTC_ICDICPR12_PFVEI1_SHIFT (14u) + +#define INTC_ICDICPR13_TINT0_SHIFT (0u) +#define INTC_ICDICPR13_TINT1_SHIFT (1u) +#define INTC_ICDICPR13_TINT2_SHIFT (2u) +#define INTC_ICDICPR13_TINT3_SHIFT (3u) +#define INTC_ICDICPR13_TINT4_SHIFT (4u) +#define INTC_ICDICPR13_TINT5_SHIFT (5u) +#define INTC_ICDICPR13_TINT6_SHIFT (6u) +#define INTC_ICDICPR13_TINT7_SHIFT (7u) +#define INTC_ICDICPR13_TINT8_SHIFT (8u) +#define INTC_ICDICPR13_TINT9_SHIFT (9u) +#define INTC_ICDICPR13_TINT10_SHIFT (10u) +#define INTC_ICDICPR13_TINT11_SHIFT (11u) +#define INTC_ICDICPR13_TINT12_SHIFT (12u) +#define INTC_ICDICPR13_TINT13_SHIFT (13u) +#define INTC_ICDICPR13_TINT14_SHIFT (14u) +#define INTC_ICDICPR13_TINT15_SHIFT (15u) +#define INTC_ICDICPR13_TINT16_SHIFT (16u) +#define INTC_ICDICPR13_TINT17_SHIFT (17u) +#define INTC_ICDICPR13_TINT18_SHIFT (18u) +#define INTC_ICDICPR13_TINT19_SHIFT (19u) +#define INTC_ICDICPR13_TINT20_SHIFT (20u) +#define INTC_ICDICPR13_TINT21_SHIFT (21u) +#define INTC_ICDICPR13_TINT22_SHIFT (22u) +#define INTC_ICDICPR13_TINT23_SHIFT (23u) +#define INTC_ICDICPR13_TINT24_SHIFT (24u) +#define INTC_ICDICPR13_TINT25_SHIFT (25u) +#define INTC_ICDICPR13_TINT26_SHIFT (26u) +#define INTC_ICDICPR13_TINT27_SHIFT (27u) +#define INTC_ICDICPR13_TINT28_SHIFT (28u) +#define INTC_ICDICPR13_TINT29_SHIFT (29u) +#define INTC_ICDICPR13_TINT30_SHIFT (30u) +#define INTC_ICDICPR13_TINT31_SHIFT (31u) + +#define INTC_ICDICPR14_TINT32_SHIFT (0u) +#define INTC_ICDICPR14_TINT33_SHIFT (1u) +#define INTC_ICDICPR14_TINT34_SHIFT (2u) +#define INTC_ICDICPR14_TINT35_SHIFT (3u) +#define INTC_ICDICPR14_TINT36_SHIFT (4u) +#define INTC_ICDICPR14_TINT37_SHIFT (5u) +#define INTC_ICDICPR14_TINT38_SHIFT (6u) +#define INTC_ICDICPR14_TINT39_SHIFT (7u) +#define INTC_ICDICPR14_TINT40_SHIFT (8u) +#define INTC_ICDICPR14_TINT41_SHIFT (9u) +#define INTC_ICDICPR14_TINT42_SHIFT (10u) +#define INTC_ICDICPR14_TINT43_SHIFT (11u) +#define INTC_ICDICPR14_TINT44_SHIFT (12u) +#define INTC_ICDICPR14_TINT45_SHIFT (13u) +#define INTC_ICDICPR14_TINT46_SHIFT (14u) +#define INTC_ICDICPR14_TINT47_SHIFT (15u) +#define INTC_ICDICPR14_TINT48_SHIFT (16u) +#define INTC_ICDICPR14_TINT49_SHIFT (17u) +#define INTC_ICDICPR14_TINT50_SHIFT (18u) +#define INTC_ICDICPR14_TINT51_SHIFT (19u) +#define INTC_ICDICPR14_TINT52_SHIFT (20u) +#define INTC_ICDICPR14_TINT53_SHIFT (21u) +#define INTC_ICDICPR14_TINT54_SHIFT (22u) +#define INTC_ICDICPR14_TINT55_SHIFT (23u) +#define INTC_ICDICPR14_TINT56_SHIFT (24u) +#define INTC_ICDICPR14_TINT57_SHIFT (25u) +#define INTC_ICDICPR14_TINT58_SHIFT (26u) +#define INTC_ICDICPR14_TINT59_SHIFT (27u) +#define INTC_ICDICPR14_TINT60_SHIFT (28u) +#define INTC_ICDICPR14_TINT61_SHIFT (29u) +#define INTC_ICDICPR14_TINT62_SHIFT (30u) +#define INTC_ICDICPR14_TINT63_SHIFT (31u) + +#define INTC_ICDICPR15_TINT64_SHIFT (0u) +#define INTC_ICDICPR15_TINT65_SHIFT (1u) +#define INTC_ICDICPR15_TINT66_SHIFT (2u) +#define INTC_ICDICPR15_TINT67_SHIFT (3u) +#define INTC_ICDICPR15_TINT68_SHIFT (4u) +#define INTC_ICDICPR15_TINT69_SHIFT (5u) +#define INTC_ICDICPR15_TINT70_SHIFT (6u) +#define INTC_ICDICPR15_TINT71_SHIFT (7u) +#define INTC_ICDICPR15_TINT72_SHIFT (8u) +#define INTC_ICDICPR15_TINT73_SHIFT (9u) +#define INTC_ICDICPR15_TINT74_SHIFT (10u) +#define INTC_ICDICPR15_TINT75_SHIFT (11u) +#define INTC_ICDICPR15_TINT76_SHIFT (12u) +#define INTC_ICDICPR15_TINT77_SHIFT (13u) +#define INTC_ICDICPR15_TINT78_SHIFT (14u) +#define INTC_ICDICPR15_TINT79_SHIFT (15u) +#define INTC_ICDICPR15_TINT80_SHIFT (16u) +#define INTC_ICDICPR15_TINT81_SHIFT (17u) +#define INTC_ICDICPR15_TINT82_SHIFT (18u) +#define INTC_ICDICPR15_TINT83_SHIFT (19u) +#define INTC_ICDICPR15_TINT84_SHIFT (20u) +#define INTC_ICDICPR15_TINT85_SHIFT (21u) +#define INTC_ICDICPR15_TINT86_SHIFT (22u) +#define INTC_ICDICPR15_TINT87_SHIFT (23u) +#define INTC_ICDICPR15_TINT88_SHIFT (24u) +#define INTC_ICDICPR15_TINT89_SHIFT (25u) +#define INTC_ICDICPR15_TINT90_SHIFT (26u) +#define INTC_ICDICPR15_TINT91_SHIFT (27u) +#define INTC_ICDICPR15_TINT92_SHIFT (28u) +#define INTC_ICDICPR15_TINT93_SHIFT (29u) +#define INTC_ICDICPR15_TINT94_SHIFT (30u) +#define INTC_ICDICPR15_TINT95_SHIFT (31u) + +#define INTC_ICDICPR16_TINT96_SHIFT (0u) +#define INTC_ICDICPR16_TINT97_SHIFT (1u) +#define INTC_ICDICPR16_TINT98_SHIFT (2u) +#define INTC_ICDICPR16_TINT99_SHIFT (3u) +#define INTC_ICDICPR16_TINT100_SHIFT (4u) +#define INTC_ICDICPR16_TINT101_SHIFT (5u) +#define INTC_ICDICPR16_TINT102_SHIFT (6u) +#define INTC_ICDICPR16_TINT103_SHIFT (7u) +#define INTC_ICDICPR16_TINT104_SHIFT (8u) +#define INTC_ICDICPR16_TINT105_SHIFT (9u) +#define INTC_ICDICPR16_TINT106_SHIFT (10u) +#define INTC_ICDICPR16_TINT107_SHIFT (11u) +#define INTC_ICDICPR16_TINT108_SHIFT (12u) +#define INTC_ICDICPR16_TINT109_SHIFT (13u) +#define INTC_ICDICPR16_TINT110_SHIFT (14u) +#define INTC_ICDICPR16_TINT111_SHIFT (15u) +#define INTC_ICDICPR16_TINT112_SHIFT (16u) +#define INTC_ICDICPR16_TINT113_SHIFT (17u) +#define INTC_ICDICPR16_TINT114_SHIFT (18u) +#define INTC_ICDICPR16_TINT115_SHIFT (19u) +#define INTC_ICDICPR16_TINT116_SHIFT (20u) +#define INTC_ICDICPR16_TINT117_SHIFT (21u) +#define INTC_ICDICPR16_TINT118_SHIFT (22u) +#define INTC_ICDICPR16_TINT119_SHIFT (23u) +#define INTC_ICDICPR16_TINT120_SHIFT (24u) +#define INTC_ICDICPR16_TINT121_SHIFT (25u) +#define INTC_ICDICPR16_TINT122_SHIFT (26u) +#define INTC_ICDICPR16_TINT123_SHIFT (27u) +#define INTC_ICDICPR16_TINT124_SHIFT (28u) +#define INTC_ICDICPR16_TINT125_SHIFT (29u) +#define INTC_ICDICPR16_TINT126_SHIFT (30u) +#define INTC_ICDICPR16_TINT127_SHIFT (31u) + +#define INTC_ICDICPR17_TINT128_SHIFT (0u) +#define INTC_ICDICPR17_TINT129_SHIFT (1u) +#define INTC_ICDICPR17_TINT130_SHIFT (2u) +#define INTC_ICDICPR17_TINT131_SHIFT (3u) +#define INTC_ICDICPR17_TINT132_SHIFT (4u) +#define INTC_ICDICPR17_TINT133_SHIFT (5u) +#define INTC_ICDICPR17_TINT134_SHIFT (6u) +#define INTC_ICDICPR17_TINT135_SHIFT (7u) +#define INTC_ICDICPR17_TINT136_SHIFT (8u) +#define INTC_ICDICPR17_TINT137_SHIFT (9u) +#define INTC_ICDICPR17_TINT138_SHIFT (10u) +#define INTC_ICDICPR17_TINT139_SHIFT (11u) +#define INTC_ICDICPR17_TINT140_SHIFT (12u) +#define INTC_ICDICPR17_TINT141_SHIFT (13u) +#define INTC_ICDICPR17_TINT142_SHIFT (14u) +#define INTC_ICDICPR17_TINT143_SHIFT (15u) +#define INTC_ICDICPR17_TINT144_SHIFT (16u) +#define INTC_ICDICPR17_TINT145_SHIFT (17u) +#define INTC_ICDICPR17_TINT146_SHIFT (18u) +#define INTC_ICDICPR17_TINT147_SHIFT (19u) +#define INTC_ICDICPR17_TINT148_SHIFT (20u) +#define INTC_ICDICPR17_TINT149_SHIFT (21u) +#define INTC_ICDICPR17_TINT150_SHIFT (22u) +#define INTC_ICDICPR17_TINT151_SHIFT (23u) +#define INTC_ICDICPR17_TINT152_SHIFT (24u) +#define INTC_ICDICPR17_TINT153_SHIFT (25u) +#define INTC_ICDICPR17_TINT154_SHIFT (26u) +#define INTC_ICDICPR17_TINT155_SHIFT (27u) +#define INTC_ICDICPR17_TINT156_SHIFT (28u) +#define INTC_ICDICPR17_TINT157_SHIFT (29u) +#define INTC_ICDICPR17_TINT158_SHIFT (30u) +#define INTC_ICDICPR17_TINT159_SHIFT (31u) + +#define INTC_ICDICPR18_TINT160_SHIFT (0u) +#define INTC_ICDICPR18_TINT161_SHIFT (1u) +#define INTC_ICDICPR18_TINT162_SHIFT (2u) +#define INTC_ICDICPR18_TINT163_SHIFT (3u) +#define INTC_ICDICPR18_TINT164_SHIFT (4u) +#define INTC_ICDICPR18_TINT165_SHIFT (5u) +#define INTC_ICDICPR18_TINT166_SHIFT (6u) +#define INTC_ICDICPR18_TINT167_SHIFT (7u) +#define INTC_ICDICPR18_TINT168_SHIFT (8u) +#define INTC_ICDICPR18_TINT169_SHIFT (9u) +#define INTC_ICDICPR18_TINT170_SHIFT (10u) + +#define INTC_ICDABR0_SW0_SHIFT (0u) +#define INTC_ICDABR0_SW1_SHIFT (1u) +#define INTC_ICDABR0_SW2_SHIFT (2u) +#define INTC_ICDABR0_SW3_SHIFT (3u) +#define INTC_ICDABR0_SW4_SHIFT (4u) +#define INTC_ICDABR0_SW5_SHIFT (5u) +#define INTC_ICDABR0_SW6_SHIFT (6u) +#define INTC_ICDABR0_SW7_SHIFT (7u) +#define INTC_ICDABR0_SW8_SHIFT (8u) +#define INTC_ICDABR0_SW9_SHIFT (9u) +#define INTC_ICDABR0_SW10_SHIFT (10u) +#define INTC_ICDABR0_SW11_SHIFT (11u) +#define INTC_ICDABR0_SW12_SHIFT (12u) +#define INTC_ICDABR0_SW13_SHIFT (13u) +#define INTC_ICDABR0_SW14_SHIFT (14u) +#define INTC_ICDABR0_SW15_SHIFT (15u) +#define INTC_ICDABR0_PMUIRQ0_SHIFT (16u) +#define INTC_ICDABR0_COMMRX0_SHIFT (17u) +#define INTC_ICDABR0_COMMTX0_SHIFT (18u) +#define INTC_ICDABR0_CTIIRQ0_SHIFT (19u) + +#define INTC_ICDABR1_IRQ0_SHIFT (0u) +#define INTC_ICDABR1_IRQ1_SHIFT (1u) +#define INTC_ICDABR1_IRQ2_SHIFT (2u) +#define INTC_ICDABR1_IRQ3_SHIFT (3u) +#define INTC_ICDABR1_IRQ4_SHIFT (4u) +#define INTC_ICDABR1_IRQ5_SHIFT (5u) +#define INTC_ICDABR1_IRQ6_SHIFT (6u) +#define INTC_ICDABR1_IRQ7_SHIFT (7u) +#define INTC_ICDABR1_PL310ERR_SHIFT (8u) +#define INTC_ICDABR1_DMAINT0_SHIFT (9u) +#define INTC_ICDABR1_DMAINT1_SHIFT (10u) +#define INTC_ICDABR1_DMAINT2_SHIFT (11u) +#define INTC_ICDABR1_DMAINT3_SHIFT (12u) +#define INTC_ICDABR1_DMAINT4_SHIFT (13u) +#define INTC_ICDABR1_DMAINT5_SHIFT (14u) +#define INTC_ICDABR1_DMAINT6_SHIFT (15u) +#define INTC_ICDABR1_DMAINT7_SHIFT (16u) +#define INTC_ICDABR1_DMAINT8_SHIFT (17u) +#define INTC_ICDABR1_DMAINT9_SHIFT (18u) +#define INTC_ICDABR1_DMAINT10_SHIFT (19u) +#define INTC_ICDABR1_DMAINT11_SHIFT (20u) +#define INTC_ICDABR1_DMAINT12_SHIFT (21u) +#define INTC_ICDABR1_DMAINT13_SHIFT (22u) +#define INTC_ICDABR1_DMAINT14_SHIFT (23u) +#define INTC_ICDABR1_DMAINT15_SHIFT (24u) +#define INTC_ICDABR1_DMAERR_SHIFT (25u) + +#define INTC_ICDABR2_USBI0_SHIFT (9u) +#define INTC_ICDABR2_USBI1_SHIFT (10u) +#define INTC_ICDABR2_S0_VI_VSYNC0_SHIFT (11u) +#define INTC_ICDABR2_S0_LO_VSYNC0_SHIFT (12u) +#define INTC_ICDABR2_S0_VSYNCERR0_SHIFT (13u) +#define INTC_ICDABR2_GR3_VLINE0_SHIFT (14u) +#define INTC_ICDABR2_S0_VFIELD0_SHIFT (15u) +#define INTC_ICDABR2_IV1_VBUFERR0_SHIFT (16u) +#define INTC_ICDABR2_IV3_VBUFERR0_SHIFT (17u) +#define INTC_ICDABR2_IV5_VBUFERR0_SHIFT (18u) +#define INTC_ICDABR2_IV6_VBUFERR0_SHIFT (19u) +#define INTC_ICDABR2_S0_WLINE0_SHIFT (20u) +#define INTC_ICDABR2_S1_VI_VSYNC0_SHIFT (21u) +#define INTC_ICDABR2_S1_LO_VSYNC0_SHIFT (22u) +#define INTC_ICDABR2_S1_VSYNCERR0_SHIFT (23u) +#define INTC_ICDABR2_S1_VFIELD0_SHIFT (24u) +#define INTC_ICDABR2_IV2_VBUFERR0_SHIFT (25u) +#define INTC_ICDABR2_IV4_VBUFERR0_SHIFT (26u) +#define INTC_ICDABR2_S1_WLINE0_SHIFT (27u) +#define INTC_ICDABR2_OIR_VI_VSYNC0_SHIFT (28u) +#define INTC_ICDABR2_OIR_LO_VSYNC0_SHIFT (29u) +#define INTC_ICDABR2_OIR_VSYNCERR0_SHIFT (30u) +#define INTC_ICDABR2_OIR_VFIELD0_SHIFT (31u) + +#define INTC_ICDABR3_IV7_VBUFERR0_SHIFT (0u) +#define INTC_ICDABR3_IV8_VBUFERR0_SHIFT (1u) +#define INTC_ICDABR3_S0_VI_VSYNC1_SHIFT (3u) +#define INTC_ICDABR3_S0_LO_VSYNC1_SHIFT (4u) +#define INTC_ICDABR3_S0_VSYNCERR1_SHIFT (5u) +#define INTC_ICDABR3_GR3_VLINE1_SHIFT (6u) +#define INTC_ICDABR3_S0_VFIELD1_SHIFT (7u) +#define INTC_ICDABR3_IV1_VBUFERR1_SHIFT (8u) +#define INTC_ICDABR3_IV3_VBUFERR1_SHIFT (9u) +#define INTC_ICDABR3_IV5_VBUFERR1_SHIFT (10u) +#define INTC_ICDABR3_IV6_VBUFERR1_SHIFT (11u) +#define INTC_ICDABR3_S0_WLINE1_SHIFT (12u) +#define INTC_ICDABR3_S1_VI_VSYNC1_SHIFT (13u) +#define INTC_ICDABR3_S1_LO_VSYNC1_SHIFT (14u) +#define INTC_ICDABR3_S1_VSYNCERR1_SHIFT (15u) +#define INTC_ICDABR3_S1_VFIELD1_SHIFT (16u) +#define INTC_ICDABR3_IV2_VBUFERR1_SHIFT (17u) +#define INTC_ICDABR3_IV4_VBUFERR1_SHIFT (18u) +#define INTC_ICDABR3_S1_WLINE1_SHIFT (19u) +#define INTC_ICDABR3_OIR_VI_VSYNC1_SHIFT (20u) +#define INTC_ICDABR3_OIR_LO_VSYNC1_SHIFT (21u) +#define INTC_ICDABR3_OIR_VLINE1_SHIFT (22u) +#define INTC_ICDABR3_OIR_VFIELD1_SHIFT (23u) +#define INTC_ICDABR3_IV7_VBUFERR1_SHIFT (24u) +#define INTC_ICDABR3_IV8_VBUFERR1_SHIFT (25u) +#define INTC_ICDABR3_IMRDI_SHIFT (27u) +#define INTC_ICDABR3_IMR2I0_SHIFT (28u) +#define INTC_ICDABR3_IMR2I1_SHIFT (29u) +#define INTC_ICDABR3_JEDI_SHIFT (30u) +#define INTC_ICDABR3_JDTI_SHIFT (31u) + +#define INTC_ICDABR4_CMP0_SHIFT (0u) +#define INTC_ICDABR4_CMP1_SHIFT (1u) +#define INTC_ICDABR4_INT0_SHIFT (2u) +#define INTC_ICDABR4_INT1_SHIFT (3u) +#define INTC_ICDABR4_INT2_SHIFT (4u) +#define INTC_ICDABR4_INT3_SHIFT (5u) +#define INTC_ICDABR4_OSTM0TINT_SHIFT (6u) +#define INTC_ICDABR4_OSTM1TINT_SHIFT (7u) +#define INTC_ICDABR4_CMI_SHIFT (8u) +#define INTC_ICDABR4_WTOUT_SHIFT (9u) +#define INTC_ICDABR4_ITI_SHIFT (10u) +#define INTC_ICDABR4_TGI0A_SHIFT (11u) +#define INTC_ICDABR4_TGI0B_SHIFT (12u) +#define INTC_ICDABR4_TGI0C_SHIFT (13u) +#define INTC_ICDABR4_TGI0D_SHIFT (14u) +#define INTC_ICDABR4_TGI0V_SHIFT (15u) +#define INTC_ICDABR4_TGI0E_SHIFT (16u) +#define INTC_ICDABR4_TGI0F_SHIFT (17u) +#define INTC_ICDABR4_TGI1A_SHIFT (18u) +#define INTC_ICDABR4_TGI1B_SHIFT (19u) +#define INTC_ICDABR4_TGI1V_SHIFT (20u) +#define INTC_ICDABR4_TGI1U_SHIFT (21u) +#define INTC_ICDABR4_TGI2A_SHIFT (22u) +#define INTC_ICDABR4_TGI2B_SHIFT (23u) +#define INTC_ICDABR4_TGI2V_SHIFT (24u) +#define INTC_ICDABR4_TGI2U_SHIFT (25u) +#define INTC_ICDABR4_TGI3A_SHIFT (26u) +#define INTC_ICDABR4_TGI3B_SHIFT (27u) +#define INTC_ICDABR4_TGI3C_SHIFT (28u) +#define INTC_ICDABR4_TGI3D_SHIFT (29u) +#define INTC_ICDABR4_TGI3V_SHIFT (30u) +#define INTC_ICDABR4_TGI4A_SHIFT (31u) + +#define INTC_ICDABR5_TGI4B_SHIFT (0u) +#define INTC_ICDABR5_TGI4C_SHIFT (1u) +#define INTC_ICDABR5_TGI4D_SHIFT (2u) +#define INTC_ICDABR5_TGI4V_SHIFT (3u) +#define INTC_ICDABR5_CMI1_SHIFT (4u) +#define INTC_ICDABR5_CMI2_SHIFT (5u) +#define INTC_ICDABR5_SGDEI0_SHIFT (6u) +#define INTC_ICDABR5_SGDEI1_SHIFT (7u) +#define INTC_ICDABR5_SGDEI2_SHIFT (8u) +#define INTC_ICDABR5_SGDEI3_SHIFT (9u) +#define INTC_ICDABR5_ADI_SHIFT (10u) +#define INTC_ICDABR5_LMTI_SHIFT (11u) +#define INTC_ICDABR5_SSII0_SHIFT (12u) +#define INTC_ICDABR5_SSIRXI0_SHIFT (13u) +#define INTC_ICDABR5_SSITXI0_SHIFT (14u) +#define INTC_ICDABR5_SSII1_SHIFT (15u) +#define INTC_ICDABR5_SSIRXI1_SHIFT (16u) +#define INTC_ICDABR5_SSITXI1_SHIFT (17u) +#define INTC_ICDABR5_SSII2_SHIFT (18u) +#define INTC_ICDABR5_SSIRTI2_SHIFT (19u) +#define INTC_ICDABR5_SSII3_SHIFT (20u) +#define INTC_ICDABR5_SSIRXI3_SHIFT (21u) +#define INTC_ICDABR5_SSITXI3_SHIFT (22u) +#define INTC_ICDABR5_SSII4_SHIFT (23u) +#define INTC_ICDABR5_SSIRTI4_SHIFT (24u) +#define INTC_ICDABR5_SSII5_SHIFT (25u) +#define INTC_ICDABR5_SSIRXI5_SHIFT (26u) +#define INTC_ICDABR5_SSITXI5_SHIFT (27u) +#define INTC_ICDABR5_SPDIFI_SHIFT (28u) +#define INTC_ICDABR5_INTIICTEI0_SHIFT (29u) +#define INTC_ICDABR5_INTIICRI0_SHIFT (30u) +#define INTC_ICDABR5_INTIICTI0_SHIFT (31u) + +#define INTC_ICDABR6_INTIICSPI0_SHIFT (0u) +#define INTC_ICDABR6_INTIICSTI0_SHIFT (1u) +#define INTC_ICDABR6_INTIICNAKI0_SHIFT (2u) +#define INTC_ICDABR6_INTIICALI0_SHIFT (3u) +#define INTC_ICDABR6_INTIICTMOI0_SHIFT (4u) +#define INTC_ICDABR6_INTIICTEI1_SHIFT (5u) +#define INTC_ICDABR6_INTIICRI1_SHIFT (6u) +#define INTC_ICDABR6_INTIICTI1_SHIFT (7u) +#define INTC_ICDABR6_INTIICSPI1_SHIFT (8u) +#define INTC_ICDABR6_INTIICSTI1_SHIFT (9u) +#define INTC_ICDABR6_INTIICNAKI1_SHIFT (10u) +#define INTC_ICDABR6_INTIICALI1_SHIFT (11u) +#define INTC_ICDABR6_INTIICTMOI1_SHIFT (12u) +#define INTC_ICDABR6_INTIICTEI2_SHIFT (13u) +#define INTC_ICDABR6_INTIICRI2_SHIFT (14u) +#define INTC_ICDABR6_INTIICTI2_SHIFT (15u) +#define INTC_ICDABR6_INTIICSPI2_SHIFT (16u) +#define INTC_ICDABR6_INTIICSTI2_SHIFT (17u) +#define INTC_ICDABR6_INTIICNAKI2_SHIFT (18u) +#define INTC_ICDABR6_INTIICALI2_SHIFT (19u) +#define INTC_ICDABR6_INTIICTMOI2_SHIFT (20u) +#define INTC_ICDABR6_INTIICTEI3_SHIFT (21u) +#define INTC_ICDABR6_INTIICRI3_SHIFT (22u) +#define INTC_ICDABR6_INTIICTI3_SHIFT (23u) +#define INTC_ICDABR6_INTIICSPI3_SHIFT (24u) +#define INTC_ICDABR6_INTIICSTI3_SHIFT (25u) +#define INTC_ICDABR6_INTIICNAKI3_SHIFT (26u) +#define INTC_ICDABR6_INTIICALI3_SHIFT (27u) +#define INTC_ICDABR6_INTIICTMOI3_SHIFT (28u) +#define INTC_ICDABR6_BRI0_SHIFT (29u) +#define INTC_ICDABR6_ERI0_SHIFT (30u) +#define INTC_ICDABR6_RXI0_SHIFT (31u) + +#define INTC_ICDABR7_TXI0_SHIFT (0u) +#define INTC_ICDABR7_BRI1_SHIFT (1u) +#define INTC_ICDABR7_ERI1_SHIFT (2u) +#define INTC_ICDABR7_RXI1_SHIFT (3u) +#define INTC_ICDABR7_TXI1_SHIFT (4u) +#define INTC_ICDABR7_BRI2_SHIFT (5u) +#define INTC_ICDABR7_ERI2_SHIFT (6u) +#define INTC_ICDABR7_RXI2_SHIFT (7u) +#define INTC_ICDABR7_TXI2_SHIFT (8u) +#define INTC_ICDABR7_BRI3_SHIFT (9u) +#define INTC_ICDABR7_ERI3_SHIFT (10u) +#define INTC_ICDABR7_RXI3_SHIFT (11u) +#define INTC_ICDABR7_TXI3_SHIFT (12u) +#define INTC_ICDABR7_BRI4_SHIFT (13u) +#define INTC_ICDABR7_ERI4_SHIFT (14u) +#define INTC_ICDABR7_RXI4_SHIFT (15u) +#define INTC_ICDABR7_TXI4_SHIFT (16u) +#define INTC_ICDABR7_BRI5_SHIFT (17u) +#define INTC_ICDABR7_ERI5_SHIFT (18u) +#define INTC_ICDABR7_RXI5_SHIFT (19u) +#define INTC_ICDABR7_TXI5_SHIFT (20u) +#define INTC_ICDABR7_BRI6_SHIFT (21u) +#define INTC_ICDABR7_ERI6_SHIFT (22u) +#define INTC_ICDABR7_RXI6_SHIFT (23u) +#define INTC_ICDABR7_TXI6_SHIFT (24u) +#define INTC_ICDABR7_BRI7_SHIFT (25u) +#define INTC_ICDABR7_ERI7_SHIFT (26u) +#define INTC_ICDABR7_RXI7_SHIFT (27u) +#define INTC_ICDABR7_TXI7_SHIFT (28u) +#define INTC_ICDABR7_INTRCANGERR_SHIFT (29u) +#define INTC_ICDABR7_INTRCANGRECC_SHIFT (30u) +#define INTC_ICDABR7_INTRCAN0REC_SHIFT (31u) + +#define INTC_ICDABR8_INTRCAN0ERR_SHIFT (0u) +#define INTC_ICDABR8_INTRCAN0TRX_SHIFT (1u) +#define INTC_ICDABR8_INTRCAN1REC_SHIFT (2u) +#define INTC_ICDABR8_INTRCAN1ERR_SHIFT (3u) +#define INTC_ICDABR8_INTRCAN1TRX_SHIFT (4u) +#define INTC_ICDABR8_INTRCAN2REC_SHIFT (5u) +#define INTC_ICDABR8_INTRCAN2ERR_SHIFT (6u) +#define INTC_ICDABR8_INTRCAN2TRX_SHIFT (7u) +#define INTC_ICDABR8_INTRCAN3REC_SHIFT (8u) +#define INTC_ICDABR8_INTRCAN3ERR_SHIFT (9u) +#define INTC_ICDABR8_INTRCAN3TRX_SHIFT (10u) +#define INTC_ICDABR8_INTRCAN4REC_SHIFT (11u) +#define INTC_ICDABR8_INTRCAN4ERR_SHIFT (12u) +#define INTC_ICDABR8_INTRCAN4TRX_SHIFT (13u) +#define INTC_ICDABR8_SPEI0_SHIFT (14u) +#define INTC_ICDABR8_SPRI0_SHIFT (15u) +#define INTC_ICDABR8_SPTI0_SHIFT (16u) +#define INTC_ICDABR8_SPEI1_SHIFT (17u) +#define INTC_ICDABR8_SPRI1_SHIFT (18u) +#define INTC_ICDABR8_SPTI1_SHIFT (19u) +#define INTC_ICDABR8_SPEI2_SHIFT (20u) +#define INTC_ICDABR8_SPRI2_SHIFT (21u) +#define INTC_ICDABR8_SPTI2_SHIFT (22u) +#define INTC_ICDABR8_SPEI3_SHIFT (23u) +#define INTC_ICDABR8_SPRI3_SHIFT (24u) +#define INTC_ICDABR8_SPTI3_SHIFT (25u) +#define INTC_ICDABR8_SPEI4_SHIFT (26u) +#define INTC_ICDABR8_SPRI4_SHIFT (27u) +#define INTC_ICDABR8_SPTI4_SHIFT (28u) +#define INTC_ICDABR8_IEBBTD_SHIFT (29u) +#define INTC_ICDABR8_IEBBTERR_SHIFT (30u) +#define INTC_ICDABR8_IEBBTSTA_SHIFT (31u) + +#define INTC_ICDABR9_IEBBTV_SHIFT (0u) +#define INTC_ICDABR9_ISY_SHIFT (1u) +#define INTC_ICDABR9_IERR_SHIFT (2u) +#define INTC_ICDABR9_ITARG_SHIFT (3u) +#define INTC_ICDABR9_ISEC_SHIFT (4u) +#define INTC_ICDABR9_IBUF_SHIFT (5u) +#define INTC_ICDABR9_IREADY_SHIFT (6u) +#define INTC_ICDABR9_FLSTE_SHIFT (7u) +#define INTC_ICDABR9_FLTENDI_SHIFT (8u) +#define INTC_ICDABR9_FLTREQ0I_SHIFT (9u) +#define INTC_ICDABR9_FLTREQ1I_SHIFT (10u) +#define INTC_ICDABR9_MMC0_SHIFT (11u) +#define INTC_ICDABR9_MMC1_SHIFT (12u) +#define INTC_ICDABR9_MMC2_SHIFT (13u) +#define INTC_ICDABR9_SDHI0_3_SHIFT (14u) +#define INTC_ICDABR9_SDHI0_0_SHIFT (15u) +#define INTC_ICDABR9_SDHI0_1_SHIFT (16u) +#define INTC_ICDABR9_SDHI1_3_SHIFT (17u) +#define INTC_ICDABR9_SDHI1_0_SHIFT (18u) +#define INTC_ICDABR9_SDHI1_1_SHIFT (19u) +#define INTC_ICDABR9_ARM_SHIFT (20u) +#define INTC_ICDABR9_PRD_SHIFT (21u) +#define INTC_ICDABR9_CUP_SHIFT (22u) +#define INTC_ICDABR9_SCUAI0_SHIFT (23u) +#define INTC_ICDABR9_SCUAI1_SHIFT (24u) +#define INTC_ICDABR9_SCUFDI0_SHIFT (25u) +#define INTC_ICDABR9_SCUFDI1_SHIFT (26u) +#define INTC_ICDABR9_SCUFDI2_SHIFT (27u) +#define INTC_ICDABR9_SCUFDI3_SHIFT (28u) +#define INTC_ICDABR9_SCUFUI0_SHIFT (29u) +#define INTC_ICDABR9_SCUFUI1_SHIFT (30u) +#define INTC_ICDABR9_SCUFUI2_SHIFT (31u) + +#define INTC_ICDABR10_SCUFUI3_SHIFT (0u) +#define INTC_ICDABR10_SCUDVI0_SHIFT (1u) +#define INTC_ICDABR10_SCUDVI1_SHIFT (2u) +#define INTC_ICDABR10_SCUDVI2_SHIFT (3u) +#define INTC_ICDABR10_SCUDVI3_SHIFT (4u) +#define INTC_ICDABR10_MLB_CINT_SHIFT (5u) +#define INTC_ICDABR10_MLB_SINT_SHIFT (6u) +#define INTC_ICDABR10_DRC0_SHIFT (7u) +#define INTC_ICDABR10_DRC1_SHIFT (8u) +#define INTC_ICDABR10_LINI0_INT_T_SHIFT (11u) +#define INTC_ICDABR10_LINI0_INT_R_SHIFT (12u) +#define INTC_ICDABR10_LINI0_INT_S_SHIFT (13u) +#define INTC_ICDABR10_LINI0_INT_M_SHIFT (14u) +#define INTC_ICDABR10_LINI1_INT_T_SHIFT (15u) +#define INTC_ICDABR10_LINI1_INT_R_SHIFT (16u) +#define INTC_ICDABR10_LINI1_INT_S_SHIFT (17u) +#define INTC_ICDABR10_LINI1_INT_M_SHIFT (18u) +#define INTC_ICDABR10_ERI0_SHIFT (27u) +#define INTC_ICDABR10_RXI0_SHIFT (28u) +#define INTC_ICDABR10_TXI0_SHIFT (29u) +#define INTC_ICDABR10_TEI0_SHIFT (30u) +#define INTC_ICDABR10_ERI1_SHIFT (31u) + +#define INTC_ICDABR11_RXI1_SHIFT (0u) +#define INTC_ICDABR11_TXI1_SHIFT (1u) +#define INTC_ICDABR11_TEI1_SHIFT (2u) +#define INTC_ICDABR11_AVBI_DATA_SHIFT (3u) +#define INTC_ICDABR11_AVBI_ERROR_SHIFT (4u) +#define INTC_ICDABR11_AVBI_MANAGE_SHIFT (5u) +#define INTC_ICDABR11_AVBI_MAC_SHIFT (6u) +#define INTC_ICDABR11_ETHERI_SHIFT (7u) +#define INTC_ICDABR11_CEUI_SHIFT (12u) +#define INTC_ICDABR11_H2XMLB_ERRINT_SHIFT (29u) +#define INTC_ICDABR11_H2XIC1_ERRINT_SHIFT (30u) +#define INTC_ICDABR11_X2HPERI1_ERRINT_SHIFT (31u) + +#define INTC_ICDABR12_X2HPERI2_ERRINT_SHIFT (0u) +#define INTC_ICDABR12_X2HPERI34_ERRINT_SHIFT (1u) +#define INTC_ICDABR12_X2HPERI5_ERRINT_SHIFT (2u) +#define INTC_ICDABR12_X2HPERI67_ERRINT_SHIFT (3u) +#define INTC_ICDABR12_X2HDBGR_ERRINT_SHIFT (4u) +#define INTC_ICDABR12_X2HBSC_ERRINT_SHIFT (5u) +#define INTC_ICDABR12_X2HSPI1_ERRINT_SHIFT (6u) +#define INTC_ICDABR12_X2HSPI2_ERRINT_SHIFT (7u) +#define INTC_ICDABR12_PRRI_SHIFT (8u) +#define INTC_ICDABR12_IFEI0_SHIFT (9u) +#define INTC_ICDABR12_OFFI0_SHIFT (10u) +#define INTC_ICDABR12_PFVEI0_SHIFT (11u) +#define INTC_ICDABR12_IFEI1_SHIFT (12u) +#define INTC_ICDABR12_OFFI1_SHIFT (13u) +#define INTC_ICDABR12_PFVEI1_SHIFT (14u) + +#define INTC_ICDABR13_TINT0_SHIFT (0u) +#define INTC_ICDABR13_TINT1_SHIFT (1u) +#define INTC_ICDABR13_TINT2_SHIFT (2u) +#define INTC_ICDABR13_TINT3_SHIFT (3u) +#define INTC_ICDABR13_TINT4_SHIFT (4u) +#define INTC_ICDABR13_TINT5_SHIFT (5u) +#define INTC_ICDABR13_TINT6_SHIFT (6u) +#define INTC_ICDABR13_TINT7_SHIFT (7u) +#define INTC_ICDABR13_TINT8_SHIFT (8u) +#define INTC_ICDABR13_TINT9_SHIFT (9u) +#define INTC_ICDABR13_TINT10_SHIFT (10u) +#define INTC_ICDABR13_TINT11_SHIFT (11u) +#define INTC_ICDABR13_TINT12_SHIFT (12u) +#define INTC_ICDABR13_TINT13_SHIFT (13u) +#define INTC_ICDABR13_TINT14_SHIFT (14u) +#define INTC_ICDABR13_TINT15_SHIFT (15u) +#define INTC_ICDABR13_TINT16_SHIFT (16u) +#define INTC_ICDABR13_TINT17_SHIFT (17u) +#define INTC_ICDABR13_TINT18_SHIFT (18u) +#define INTC_ICDABR13_TINT19_SHIFT (19u) +#define INTC_ICDABR13_TINT20_SHIFT (20u) +#define INTC_ICDABR13_TINT21_SHIFT (21u) +#define INTC_ICDABR13_TINT22_SHIFT (22u) +#define INTC_ICDABR13_TINT23_SHIFT (23u) +#define INTC_ICDABR13_TINT24_SHIFT (24u) +#define INTC_ICDABR13_TINT25_SHIFT (25u) +#define INTC_ICDABR13_TINT26_SHIFT (26u) +#define INTC_ICDABR13_TINT27_SHIFT (27u) +#define INTC_ICDABR13_TINT28_SHIFT (28u) +#define INTC_ICDABR13_TINT29_SHIFT (29u) +#define INTC_ICDABR13_TINT30_SHIFT (30u) +#define INTC_ICDABR13_TINT31_SHIFT (31u) + +#define INTC_ICDABR14_TINT32_SHIFT (0u) +#define INTC_ICDABR14_TINT33_SHIFT (1u) +#define INTC_ICDABR14_TINT34_SHIFT (2u) +#define INTC_ICDABR14_TINT35_SHIFT (3u) +#define INTC_ICDABR14_TINT36_SHIFT (4u) +#define INTC_ICDABR14_TINT37_SHIFT (5u) +#define INTC_ICDABR14_TINT38_SHIFT (6u) +#define INTC_ICDABR14_TINT39_SHIFT (7u) +#define INTC_ICDABR14_TINT40_SHIFT (8u) +#define INTC_ICDABR14_TINT41_SHIFT (9u) +#define INTC_ICDABR14_TINT42_SHIFT (10u) +#define INTC_ICDABR14_TINT43_SHIFT (11u) +#define INTC_ICDABR14_TINT44_SHIFT (12u) +#define INTC_ICDABR14_TINT45_SHIFT (13u) +#define INTC_ICDABR14_TINT46_SHIFT (14u) +#define INTC_ICDABR14_TINT47_SHIFT (15u) +#define INTC_ICDABR14_TINT48_SHIFT (16u) +#define INTC_ICDABR14_TINT49_SHIFT (17u) +#define INTC_ICDABR14_TINT50_SHIFT (18u) +#define INTC_ICDABR14_TINT51_SHIFT (19u) +#define INTC_ICDABR14_TINT52_SHIFT (20u) +#define INTC_ICDABR14_TINT53_SHIFT (21u) +#define INTC_ICDABR14_TINT54_SHIFT (22u) +#define INTC_ICDABR14_TINT55_SHIFT (23u) +#define INTC_ICDABR14_TINT56_SHIFT (24u) +#define INTC_ICDABR14_TINT57_SHIFT (25u) +#define INTC_ICDABR14_TINT58_SHIFT (26u) +#define INTC_ICDABR14_TINT59_SHIFT (27u) +#define INTC_ICDABR14_TINT60_SHIFT (28u) +#define INTC_ICDABR14_TINT61_SHIFT (29u) +#define INTC_ICDABR14_TINT62_SHIFT (30u) +#define INTC_ICDABR14_TINT63_SHIFT (31u) + +#define INTC_ICDABR15_TINT64_SHIFT (0u) +#define INTC_ICDABR15_TINT65_SHIFT (1u) +#define INTC_ICDABR15_TINT66_SHIFT (2u) +#define INTC_ICDABR15_TINT67_SHIFT (3u) +#define INTC_ICDABR15_TINT68_SHIFT (4u) +#define INTC_ICDABR15_TINT69_SHIFT (5u) +#define INTC_ICDABR15_TINT70_SHIFT (6u) +#define INTC_ICDABR15_TINT71_SHIFT (7u) +#define INTC_ICDABR15_TINT72_SHIFT (8u) +#define INTC_ICDABR15_TINT73_SHIFT (9u) +#define INTC_ICDABR15_TINT74_SHIFT (10u) +#define INTC_ICDABR15_TINT75_SHIFT (11u) +#define INTC_ICDABR15_TINT76_SHIFT (12u) +#define INTC_ICDABR15_TINT77_SHIFT (13u) +#define INTC_ICDABR15_TINT78_SHIFT (14u) +#define INTC_ICDABR15_TINT79_SHIFT (15u) +#define INTC_ICDABR15_TINT80_SHIFT (16u) +#define INTC_ICDABR15_TINT81_SHIFT (17u) +#define INTC_ICDABR15_TINT82_SHIFT (18u) +#define INTC_ICDABR15_TINT83_SHIFT (19u) +#define INTC_ICDABR15_TINT84_SHIFT (20u) +#define INTC_ICDABR15_TINT85_SHIFT (21u) +#define INTC_ICDABR15_TINT86_SHIFT (22u) +#define INTC_ICDABR15_TINT87_SHIFT (23u) +#define INTC_ICDABR15_TINT88_SHIFT (24u) +#define INTC_ICDABR15_TINT89_SHIFT (25u) +#define INTC_ICDABR15_TINT90_SHIFT (26u) +#define INTC_ICDABR15_TINT91_SHIFT (27u) +#define INTC_ICDABR15_TINT92_SHIFT (28u) +#define INTC_ICDABR15_TINT93_SHIFT (29u) +#define INTC_ICDABR15_TINT94_SHIFT (30u) +#define INTC_ICDABR15_TINT95_SHIFT (31u) + +#define INTC_ICDABR16_TINT96_SHIFT (0u) +#define INTC_ICDABR16_TINT97_SHIFT (1u) +#define INTC_ICDABR16_TINT98_SHIFT (2u) +#define INTC_ICDABR16_TINT99_SHIFT (3u) +#define INTC_ICDABR16_TINT100_SHIFT (4u) +#define INTC_ICDABR16_TINT101_SHIFT (5u) +#define INTC_ICDABR16_TINT102_SHIFT (6u) +#define INTC_ICDABR16_TINT103_SHIFT (7u) +#define INTC_ICDABR16_TINT104_SHIFT (8u) +#define INTC_ICDABR16_TINT105_SHIFT (9u) +#define INTC_ICDABR16_TINT106_SHIFT (10u) +#define INTC_ICDABR16_TINT107_SHIFT (11u) +#define INTC_ICDABR16_TINT108_SHIFT (12u) +#define INTC_ICDABR16_TINT109_SHIFT (13u) +#define INTC_ICDABR16_TINT110_SHIFT (14u) +#define INTC_ICDABR16_TINT111_SHIFT (15u) +#define INTC_ICDABR16_TINT112_SHIFT (16u) +#define INTC_ICDABR16_TINT113_SHIFT (17u) +#define INTC_ICDABR16_TINT114_SHIFT (18u) +#define INTC_ICDABR16_TINT115_SHIFT (19u) +#define INTC_ICDABR16_TINT116_SHIFT (20u) +#define INTC_ICDABR16_TINT117_SHIFT (21u) +#define INTC_ICDABR16_TINT118_SHIFT (22u) +#define INTC_ICDABR16_TINT119_SHIFT (23u) +#define INTC_ICDABR16_TINT120_SHIFT (24u) +#define INTC_ICDABR16_TINT121_SHIFT (25u) +#define INTC_ICDABR16_TINT122_SHIFT (26u) +#define INTC_ICDABR16_TINT123_SHIFT (27u) +#define INTC_ICDABR16_TINT124_SHIFT (28u) +#define INTC_ICDABR16_TINT125_SHIFT (29u) +#define INTC_ICDABR16_TINT126_SHIFT (30u) +#define INTC_ICDABR16_TINT127_SHIFT (31u) + +#define INTC_ICDABR17_TINT128_SHIFT (0u) +#define INTC_ICDABR17_TINT129_SHIFT (1u) +#define INTC_ICDABR17_TINT130_SHIFT (2u) +#define INTC_ICDABR17_TINT131_SHIFT (3u) +#define INTC_ICDABR17_TINT132_SHIFT (4u) +#define INTC_ICDABR17_TINT133_SHIFT (5u) +#define INTC_ICDABR17_TINT134_SHIFT (6u) +#define INTC_ICDABR17_TINT135_SHIFT (7u) +#define INTC_ICDABR17_TINT136_SHIFT (8u) +#define INTC_ICDABR17_TINT137_SHIFT (9u) +#define INTC_ICDABR17_TINT138_SHIFT (10u) +#define INTC_ICDABR17_TINT139_SHIFT (11u) +#define INTC_ICDABR17_TINT140_SHIFT (12u) +#define INTC_ICDABR17_TINT141_SHIFT (13u) +#define INTC_ICDABR17_TINT142_SHIFT (14u) +#define INTC_ICDABR17_TINT143_SHIFT (15u) +#define INTC_ICDABR17_TINT144_SHIFT (16u) +#define INTC_ICDABR17_TINT145_SHIFT (17u) +#define INTC_ICDABR17_TINT146_SHIFT (18u) +#define INTC_ICDABR17_TINT147_SHIFT (19u) +#define INTC_ICDABR17_TINT148_SHIFT (20u) +#define INTC_ICDABR17_TINT149_SHIFT (21u) +#define INTC_ICDABR17_TINT150_SHIFT (22u) +#define INTC_ICDABR17_TINT151_SHIFT (23u) +#define INTC_ICDABR17_TINT152_SHIFT (24u) +#define INTC_ICDABR17_TINT153_SHIFT (25u) +#define INTC_ICDABR17_TINT154_SHIFT (26u) +#define INTC_ICDABR17_TINT155_SHIFT (27u) +#define INTC_ICDABR17_TINT156_SHIFT (28u) +#define INTC_ICDABR17_TINT157_SHIFT (29u) +#define INTC_ICDABR17_TINT158_SHIFT (30u) +#define INTC_ICDABR17_TINT159_SHIFT (31u) + +#define INTC_ICDABR18_TINT160_SHIFT (0u) +#define INTC_ICDABR18_TINT161_SHIFT (1u) +#define INTC_ICDABR18_TINT162_SHIFT (2u) +#define INTC_ICDABR18_TINT163_SHIFT (3u) +#define INTC_ICDABR18_TINT164_SHIFT (4u) +#define INTC_ICDABR18_TINT165_SHIFT (5u) +#define INTC_ICDABR18_TINT166_SHIFT (6u) +#define INTC_ICDABR18_TINT167_SHIFT (7u) +#define INTC_ICDABR18_TINT168_SHIFT (8u) +#define INTC_ICDABR18_TINT169_SHIFT (9u) +#define INTC_ICDABR18_TINT170_SHIFT (10u) + +#define INTC_ICDIPR0_SW0_SHIFT (0u) +#define INTC_ICDIPR0_SW1_SHIFT (8u) +#define INTC_ICDIPR0_SW2_SHIFT (16u) +#define INTC_ICDIPR0_SW3_SHIFT (24u) + +#define INTC_ICDIPR1_SW4_SHIFT (0u) +#define INTC_ICDIPR1_SW5_SHIFT (8u) +#define INTC_ICDIPR1_SW6_SHIFT (16u) +#define INTC_ICDIPR1_SW7_SHIFT (24u) + +#define INTC_ICDIPR2_SW8_SHIFT (0u) +#define INTC_ICDIPR2_SW9_SHIFT (8u) +#define INTC_ICDIPR2_SW10_SHIFT (16u) +#define INTC_ICDIPR2_SW11_SHIFT (24u) + +#define INTC_ICDIPR3_SW12_SHIFT (0u) +#define INTC_ICDIPR3_SW13_SHIFT (8u) +#define INTC_ICDIPR3_SW14_SHIFT (16u) +#define INTC_ICDIPR3_SW15_SHIFT (24u) + +#define INTC_ICDIPR4_PMUIRQ0_SHIFT (0u) +#define INTC_ICDIPR4_COMMRX0_SHIFT (8u) +#define INTC_ICDIPR4_COMMTX0_SHIFT (16u) +#define INTC_ICDIPR4_CTIIRQ0_SHIFT (24u) + +#define INTC_ICDIPR8_IRQ0_SHIFT (0u) +#define INTC_ICDIPR8_IRQ1_SHIFT (8u) +#define INTC_ICDIPR8_IRQ2_SHIFT (16u) +#define INTC_ICDIPR8_IRQ3_SHIFT (24u) + +#define INTC_ICDIPR9_IRQ4_SHIFT (0u) +#define INTC_ICDIPR9_IRQ5_SHIFT (8u) +#define INTC_ICDIPR9_IRQ6_SHIFT (16u) +#define INTC_ICDIPR9_IRQ7_SHIFT (24u) + +#define INTC_ICDIPR10_PL310ERR_SHIFT (0u) +#define INTC_ICDIPR10_DMAINT0_SHIFT (8u) +#define INTC_ICDIPR10_DMAINT1_SHIFT (16u) +#define INTC_ICDIPR10_DMAINT2_SHIFT (24u) + +#define INTC_ICDIPR11_DMAINT3_SHIFT (0u) +#define INTC_ICDIPR11_DMAINT4_SHIFT (8u) +#define INTC_ICDIPR11_DMAINT5_SHIFT (16u) +#define INTC_ICDIPR11_DMAINT6_SHIFT (24u) + +#define INTC_ICDIPR12_DMAINT7_SHIFT (0u) +#define INTC_ICDIPR12_DMAINT8_SHIFT (8u) +#define INTC_ICDIPR12_DMAINT9_SHIFT (16u) +#define INTC_ICDIPR12_DMAINT10_SHIFT (24u) + +#define INTC_ICDIPR13_DMAINT11_SHIFT (0u) +#define INTC_ICDIPR13_DMAINT12_SHIFT (8u) +#define INTC_ICDIPR13_DMAINT13_SHIFT (16u) +#define INTC_ICDIPR13_DMAINT14_SHIFT (24u) + +#define INTC_ICDIPR14_DMAINT15_SHIFT (0u) +#define INTC_ICDIPR14_DMAERR_SHIFT (8u) + +#define INTC_ICDIPR18_USBI0_SHIFT (8u) +#define INTC_ICDIPR18_USBI1_SHIFT (16u) +#define INTC_ICDIPR18_S0_VI_VSYNC0_SHIFT (24u) + +#define INTC_ICDIPR19_S0_LO_VSYNC0_SHIFT (0u) +#define INTC_ICDIPR19_S0_VSYNCERR0_SHIFT (8u) +#define INTC_ICDIPR19_GR3_VLINE0_SHIFT (16u) +#define INTC_ICDIPR19_S0_VFIELD0_SHIFT (24u) + +#define INTC_ICDIPR20_IV1_VBUFERR0_SHIFT (0u) +#define INTC_ICDIPR20_IV3_VBUFERR0_SHIFT (8u) +#define INTC_ICDIPR20_IV5_VBUFERR0_SHIFT (16u) +#define INTC_ICDIPR20_IV6_VBUFERR0_SHIFT (24u) + +#define INTC_ICDIPR21_S0_WLINE0_SHIFT (0u) +#define INTC_ICDIPR21_S1_VI_VSYNC0_SHIFT (8u) +#define INTC_ICDIPR21_S1_LO_VSYNC0_SHIFT (16u) +#define INTC_ICDIPR21_S1_VSYNCERR0_SHIFT (24u) + +#define INTC_ICDIPR22_S1_VFIELD0_SHIFT (0u) +#define INTC_ICDIPR22_IV2_VBUFERR0_SHIFT (8u) +#define INTC_ICDIPR22_IV4_VBUFERR0_SHIFT (16u) +#define INTC_ICDIPR22_S1_WLINE0_SHIFT (24u) + +#define INTC_ICDIPR23_OIR_VI_VSYNC0_SHIFT (0u) +#define INTC_ICDIPR23_OIR_LO_VSYNC0_SHIFT (8u) +#define INTC_ICDIPR23_OIR_VSYNCERR0_SHIFT (16u) +#define INTC_ICDIPR23_OIR_VFIELD0_SHIFT (24u) + +#define INTC_ICDIPR24_IV7_VBUFERR0_SHIFT (0u) +#define INTC_ICDIPR24_IV8_VBUFERR0_SHIFT (8u) +#define INTC_ICDIPR24_S0_VI_VSYNC1_SHIFT (24u) + +#define INTC_ICDIPR25_S0_LO_VSYNC1_SHIFT (0u) +#define INTC_ICDIPR25_S0_VSYNCERR1_SHIFT (8u) +#define INTC_ICDIPR25_GR3_VLINE1_SHIFT (16u) +#define INTC_ICDIPR25_S0_VFIELD1_SHIFT (24u) + +#define INTC_ICDIPR26_IV1_VBUFERR1_SHIFT (0u) +#define INTC_ICDIPR26_IV3_VBUFERR1_SHIFT (8u) +#define INTC_ICDIPR26_IV5_VBUFERR1_SHIFT (16u) +#define INTC_ICDIPR26_IV6_VBUFERR1_SHIFT (24u) + +#define INTC_ICDIPR27_S0_WLINE1_SHIFT (0u) +#define INTC_ICDIPR27_S1_VI_VSYNC1_SHIFT (8u) +#define INTC_ICDIPR27_S1_LO_VSYNC1_SHIFT (16u) +#define INTC_ICDIPR27_S1_VSYNCERR1_SHIFT (24u) + +#define INTC_ICDIPR28_S1_VFIELD1_SHIFT (0u) +#define INTC_ICDIPR28_IV2_VBUFERR1_SHIFT (8u) +#define INTC_ICDIPR28_IV4_VBUFERR1_SHIFT (16u) +#define INTC_ICDIPR28_S1_WLINE1_SHIFT (24u) + +#define INTC_ICDIPR29_OIR_VI_VSYNC1_SHIFT (0u) +#define INTC_ICDIPR29_OIR_LO_VSYNC1_SHIFT (8u) +#define INTC_ICDIPR29_OIR_VLINE1_SHIFT (16u) +#define INTC_ICDIPR29_OIR_VFIELD1_SHIFT (24u) + +#define INTC_ICDIPR30_IV7_VBUFERR1_SHIFT (0u) +#define INTC_ICDIPR30_IV8_VBUFERR1_SHIFT (8u) +#define INTC_ICDIPR30_IMRDI_SHIFT (24u) + +#define INTC_ICDIPR31_IMR2I0_SHIFT (0u) +#define INTC_ICDIPR31_IMR2I1_SHIFT (8u) +#define INTC_ICDIPR31_JEDI_SHIFT (16u) +#define INTC_ICDIPR31_JDTI_SHIFT (24u) + +#define INTC_ICDIPR32_CMP0_SHIFT (0u) +#define INTC_ICDIPR32_CMP1_SHIFT (8u) +#define INTC_ICDIPR32_INT0_SHIFT (16u) +#define INTC_ICDIPR32_INT1_SHIFT (24u) + +#define INTC_ICDIPR33_INT2_SHIFT (0u) +#define INTC_ICDIPR33_INT3_SHIFT (8u) +#define INTC_ICDIPR33_OSTM0TINT_SHIFT (16u) +#define INTC_ICDIPR33_OSTM1TINT_SHIFT (24u) + +#define INTC_ICDIPR34_CMI_SHIFT (0u) +#define INTC_ICDIPR34_WTOUT_SHIFT (8u) +#define INTC_ICDIPR34_ITI_SHIFT (16u) +#define INTC_ICDIPR34_TGI0A_SHIFT (24u) + +#define INTC_ICDIPR35_TGI0B_SHIFT (0u) +#define INTC_ICDIPR35_TGI0C_SHIFT (8u) +#define INTC_ICDIPR35_TGI0D_SHIFT (16u) +#define INTC_ICDIPR35_TGI0V_SHIFT (24u) + +#define INTC_ICDIPR36_TGI0E_SHIFT (0u) +#define INTC_ICDIPR36_TGI0F_SHIFT (8u) +#define INTC_ICDIPR36_TGI1A_SHIFT (16u) +#define INTC_ICDIPR36_TGI1B_SHIFT (24u) + +#define INTC_ICDIPR37_TGI1V_SHIFT (0u) +#define INTC_ICDIPR37_TGI1U_SHIFT (8u) +#define INTC_ICDIPR37_TGI2A_SHIFT (16u) +#define INTC_ICDIPR37_TGI2B_SHIFT (24u) + +#define INTC_ICDIPR38_TGI2V_SHIFT (0u) +#define INTC_ICDIPR38_TGI2U_SHIFT (8u) +#define INTC_ICDIPR38_TGI3A_SHIFT (16u) +#define INTC_ICDIPR38_TGI3B_SHIFT (24u) + +#define INTC_ICDIPR39_TGI3C_SHIFT (0u) +#define INTC_ICDIPR39_TGI3D_SHIFT (8u) +#define INTC_ICDIPR39_TGI3V_SHIFT (16u) +#define INTC_ICDIPR39_TGI4A_SHIFT (24u) + +#define INTC_ICDIPR40_TGI4B_SHIFT (0u) +#define INTC_ICDIPR40_TGI4C_SHIFT (8u) +#define INTC_ICDIPR40_TGI4D_SHIFT (16u) +#define INTC_ICDIPR40_TGI4V_SHIFT (24u) + +#define INTC_ICDIPR41_CMI1_SHIFT (0u) +#define INTC_ICDIPR41_CMI2_SHIFT (8u) +#define INTC_ICDIPR41_SGDEI0_SHIFT (16u) +#define INTC_ICDIPR41_SGDEI1_SHIFT (24u) + +#define INTC_ICDIPR42_SGDEI2_SHIFT (0u) +#define INTC_ICDIPR42_SGDEI3_SHIFT (8u) +#define INTC_ICDIPR42_ADI_SHIFT (16u) +#define INTC_ICDIPR42_LMTI_SHIFT (24u) + +#define INTC_ICDIPR43_SSII0_SHIFT (0u) +#define INTC_ICDIPR43_SSIRXI0_SHIFT (8u) +#define INTC_ICDIPR43_SSITXI0_SHIFT (16u) +#define INTC_ICDIPR43_SSII1_SHIFT (24u) + +#define INTC_ICDIPR44_SSIRXI1_SHIFT (0u) +#define INTC_ICDIPR44_SSITXI1_SHIFT (8u) +#define INTC_ICDIPR44_SSII2_SHIFT (16u) +#define INTC_ICDIPR44_SSIRTI2_SHIFT (24u) + +#define INTC_ICDIPR45_SSII3_SHIFT (0u) +#define INTC_ICDIPR45_SSIRXI3_SHIFT (8u) +#define INTC_ICDIPR45_SSITXI3_SHIFT (16u) +#define INTC_ICDIPR45_SSII4_SHIFT (24u) + +#define INTC_ICDIPR46_SSIRTI4_SHIFT (0u) +#define INTC_ICDIPR46_SSII5_SHIFT (8u) +#define INTC_ICDIPR46_SSIRXI5_SHIFT (16u) +#define INTC_ICDIPR46_SSITXI5_SHIFT (24u) + +#define INTC_ICDIPR47_SPDIFI_SHIFT (0u) +#define INTC_ICDIPR47_INTIICTEI0_SHIFT (8u) +#define INTC_ICDIPR47_INTIICRI0_SHIFT (16u) +#define INTC_ICDIPR47_INTIICTI0_SHIFT (24u) + +#define INTC_ICDIPR48_INTIICSPI0_SHIFT (0u) +#define INTC_ICDIPR48_INTIICSTI0_SHIFT (8u) +#define INTC_ICDIPR48_INTIICNAKI0_SHIFT (16u) +#define INTC_ICDIPR48_INTIICALI0_SHIFT (24u) + +#define INTC_ICDIPR49_INTIICTMOI0_SHIFT (0u) +#define INTC_ICDIPR49_INTIICTEI1_SHIFT (8u) +#define INTC_ICDIPR49_INTIICRI1_SHIFT (16u) +#define INTC_ICDIPR49_INTIICTI1_SHIFT (24u) + +#define INTC_ICDIPR50_INTIICSPI1_SHIFT (0u) +#define INTC_ICDIPR50_INTIICSTI1_SHIFT (8u) +#define INTC_ICDIPR50_INTIICNAKI1_SHIFT (16u) +#define INTC_ICDIPR50_INTIICALI1_SHIFT (24u) + +#define INTC_ICDIPR51_INTIICTMOI1_SHIFT (0u) +#define INTC_ICDIPR51_INTIICTEI2_SHIFT (8u) +#define INTC_ICDIPR51_INTIICRI2_SHIFT (16u) +#define INTC_ICDIPR51_INTIICTI2_SHIFT (24u) + +#define INTC_ICDIPR52_INTIICSPI2_SHIFT (0u) +#define INTC_ICDIPR52_INTIICSTI2_SHIFT (8u) +#define INTC_ICDIPR52_INTIICNAKI2_SHIFT (16u) +#define INTC_ICDIPR52_INTIICALI2_SHIFT (24u) + +#define INTC_ICDIPR53_INTIICTMOI2_SHIFT (0u) +#define INTC_ICDIPR53_INTIICTEI3_SHIFT (8u) +#define INTC_ICDIPR53_INTIICRI3_SHIFT (16u) +#define INTC_ICDIPR53_INTIICTI3_SHIFT (24u) + +#define INTC_ICDIPR54_INTIICSPI3_SHIFT (0u) +#define INTC_ICDIPR54_INTIICSTI3_SHIFT (8u) +#define INTC_ICDIPR54_INTIICNAKI3_SHIFT (16u) +#define INTC_ICDIPR54_INTIICALI3_SHIFT (24u) + +#define INTC_ICDIPR55_INTIICTMOI3_SHIFT (0u) +#define INTC_ICDIPR55_BRI0_SHIFT (8u) +#define INTC_ICDIPR55_ERI0_SHIFT (16u) +#define INTC_ICDIPR55_RXI0_SHIFT (24u) + +#define INTC_ICDIPR56_TXI0_SHIFT (0u) +#define INTC_ICDIPR56_BRI1_SHIFT (8u) +#define INTC_ICDIPR56_ERI1_SHIFT (16u) +#define INTC_ICDIPR56_RXI1_SHIFT (24u) + +#define INTC_ICDIPR57_TXI1_SHIFT (0u) +#define INTC_ICDIPR57_BRI2_SHIFT (8u) +#define INTC_ICDIPR57_ERI2_SHIFT (16u) +#define INTC_ICDIPR57_RXI2_SHIFT (24u) + +#define INTC_ICDIPR58_TXI2_SHIFT (0u) +#define INTC_ICDIPR58_BRI3_SHIFT (8u) +#define INTC_ICDIPR58_ERI3_SHIFT (16u) +#define INTC_ICDIPR58_RXI3_SHIFT (24u) + +#define INTC_ICDIPR59_TXI3_SHIFT (0u) +#define INTC_ICDIPR59_BRI4_SHIFT (8u) +#define INTC_ICDIPR59_ERI4_SHIFT (16u) +#define INTC_ICDIPR59_RXI4_SHIFT (24u) + +#define INTC_ICDIPR60_TXI4_SHIFT (0u) +#define INTC_ICDIPR60_BRI5_SHIFT (8u) +#define INTC_ICDIPR60_ERI5_SHIFT (16u) +#define INTC_ICDIPR60_RXI5_SHIFT (24u) + +#define INTC_ICDIPR61_TXI5_SHIFT (0u) +#define INTC_ICDIPR61_BRI6_SHIFT (8u) +#define INTC_ICDIPR61_ERI6_SHIFT (16u) +#define INTC_ICDIPR61_RXI6_SHIFT (24u) + +#define INTC_ICDIPR62_TXI6_SHIFT (0u) +#define INTC_ICDIPR62_BRI7_SHIFT (8u) +#define INTC_ICDIPR62_ERI7_SHIFT (16u) +#define INTC_ICDIPR62_RXI7_SHIFT (24u) + +#define INTC_ICDIPR63_TXI7_SHIFT (0u) +#define INTC_ICDIPR63_INTRCANGERR_SHIFT (8u) +#define INTC_ICDIPR63_INTRCANGRECC_SHIFT (16u) +#define INTC_ICDIPR63_INTRCAN0REC_SHIFT (24u) + +#define INTC_ICDIPR64_INTRCAN0ERR_SHIFT (0u) +#define INTC_ICDIPR64_INTRCAN0TRX_SHIFT (8u) +#define INTC_ICDIPR64_INTRCAN1REC_SHIFT (16u) +#define INTC_ICDIPR64_INTRCAN1ERR_SHIFT (24u) + +#define INTC_ICDIPR65_INTRCAN1TRX_SHIFT (0u) +#define INTC_ICDIPR65_INTRCAN2REC_SHIFT (8u) +#define INTC_ICDIPR65_INTRCAN2ERR_SHIFT (16u) +#define INTC_ICDIPR65_INTRCAN2TRX_SHIFT (24u) + +#define INTC_ICDIPR66_INTRCAN3REC_SHIFT (0u) +#define INTC_ICDIPR66_INTRCAN3ERR_SHIFT (8u) +#define INTC_ICDIPR66_INTRCAN3TRX_SHIFT (16u) +#define INTC_ICDIPR66_INTRCAN4REC_SHIFT (24u) + +#define INTC_ICDIPR67_INTRCAN4ERR_SHIFT (0u) +#define INTC_ICDIPR67_INTRCAN4TRX_SHIFT (8u) +#define INTC_ICDIPR67_SPEI0_SHIFT (16u) +#define INTC_ICDIPR67_SPRI0_SHIFT (24u) + +#define INTC_ICDIPR68_SPTI0_SHIFT (0u) +#define INTC_ICDIPR68_SPEI1_SHIFT (8u) +#define INTC_ICDIPR68_SPRI1_SHIFT (16u) +#define INTC_ICDIPR68_SPTI1_SHIFT (24u) + +#define INTC_ICDIPR69_SPEI2_SHIFT (0u) +#define INTC_ICDIPR69_SPRI2_SHIFT (8u) +#define INTC_ICDIPR69_SPTI2_SHIFT (16u) +#define INTC_ICDIPR69_SPEI3_SHIFT (24u) + +#define INTC_ICDIPR70_SPRI3_SHIFT (0u) +#define INTC_ICDIPR70_SPTI3_SHIFT (8u) +#define INTC_ICDIPR70_SPEI4_SHIFT (16u) +#define INTC_ICDIPR70_SPRI4_SHIFT (24u) + +#define INTC_ICDIPR71_SPTI4_SHIFT (0u) +#define INTC_ICDIPR71_IEBBTD_SHIFT (8u) +#define INTC_ICDIPR71_IEBBTERR_SHIFT (16u) +#define INTC_ICDIPR71_IEBBTSTA_SHIFT (24u) + +#define INTC_ICDIPR72_IEBBTV_SHIFT (0u) +#define INTC_ICDIPR72_ISY_SHIFT (8u) +#define INTC_ICDIPR72_IERR_SHIFT (16u) +#define INTC_ICDIPR72_ITARG_SHIFT (24u) + +#define INTC_ICDIPR73_ISEC_SHIFT (0u) +#define INTC_ICDIPR73_IBUF_SHIFT (8u) +#define INTC_ICDIPR73_IREADY_SHIFT (16u) +#define INTC_ICDIPR73_FLSTE_SHIFT (24u) + +#define INTC_ICDIPR74_FLTENDI_SHIFT (0u) +#define INTC_ICDIPR74_FLTREQ0I_SHIFT (8u) +#define INTC_ICDIPR74_FLTREQ1I_SHIFT (16u) +#define INTC_ICDIPR74_MMC0_SHIFT (24u) + +#define INTC_ICDIPR75_MMC1_SHIFT (0u) +#define INTC_ICDIPR75_MMC2_SHIFT (8u) +#define INTC_ICDIPR75_SDHI0_3_SHIFT (16u) +#define INTC_ICDIPR75_SDHI0_0_SHIFT (24u) + +#define INTC_ICDIPR76_SDHI0_1_SHIFT (0u) +#define INTC_ICDIPR76_SDHI1_3_SHIFT (8u) +#define INTC_ICDIPR76_SDHI1_0_SHIFT (16u) +#define INTC_ICDIPR76_SDHI1_1_SHIFT (24u) + +#define INTC_ICDIPR77_ARM_SHIFT (0u) +#define INTC_ICDIPR77_PRD_SHIFT (8u) +#define INTC_ICDIPR77_CUP_SHIFT (16u) +#define INTC_ICDIPR77_SCUAI0_SHIFT (24u) + +#define INTC_ICDIPR78_SCUAI1_SHIFT (0u) +#define INTC_ICDIPR78_SCUFDI0_SHIFT (8u) +#define INTC_ICDIPR78_SCUFDI1_SHIFT (16u) +#define INTC_ICDIPR78_SCUFDI2_SHIFT (24u) + +#define INTC_ICDIPR79_SCUFDI3_SHIFT (0u) +#define INTC_ICDIPR79_SCUFUI0_SHIFT (8u) +#define INTC_ICDIPR79_SCUFUI1_SHIFT (16u) +#define INTC_ICDIPR79_SCUFUI2_SHIFT (24u) + +#define INTC_ICDIPR80_SCUFUI3_SHIFT (0u) +#define INTC_ICDIPR80_SCUDVI0_SHIFT (8u) +#define INTC_ICDIPR80_SCUDVI1_SHIFT (16u) +#define INTC_ICDIPR80_SCUDVI2_SHIFT (24u) + +#define INTC_ICDIPR81_SCUDVI3_SHIFT (0u) +#define INTC_ICDIPR81_MLB_CINT_SHIFT (8u) +#define INTC_ICDIPR81_MLB_SINT_SHIFT (16u) +#define INTC_ICDIPR81_DRC0_SHIFT (24u) + +#define INTC_ICDIPR82_DRC1_SHIFT (0u) +#define INTC_ICDIPR82_LINI0_INT_T_SHIFT (24u) + +#define INTC_ICDIPR83_LINI0_INT_R_SHIFT (0u) +#define INTC_ICDIPR83_LINI0_INT_S_SHIFT (8u) +#define INTC_ICDIPR83_LINI0_INT_M_SHIFT (16u) +#define INTC_ICDIPR83_LINI1_INT_T_SHIFT (24u) + +#define INTC_ICDIPR84_LINI1_INT_R_SHIFT (0u) +#define INTC_ICDIPR84_LINI1_INT_S_SHIFT (8u) +#define INTC_ICDIPR84_LINI1_INT_M_SHIFT (16u) + +#define INTC_ICDIPR86_ERI0_SHIFT (24u) + +#define INTC_ICDIPR87_RXI0_SHIFT (0u) +#define INTC_ICDIPR87_TXI0_SHIFT (8u) +#define INTC_ICDIPR87_TEI0_SHIFT (16u) +#define INTC_ICDIPR87_ERI1_SHIFT (24u) + +#define INTC_ICDIPR88_RXI1_SHIFT (0u) +#define INTC_ICDIPR88_TXI1_SHIFT (8u) +#define INTC_ICDIPR88_TEI1_SHIFT (16u) +#define INTC_ICDIPR88_AVBI_DATA_SHIFT (24u) + +#define INTC_ICDIPR89_AVBI_ERROR_SHIFT (0u) +#define INTC_ICDIPR89_AVBI_MANAGE_SHIFT (8u) +#define INTC_ICDIPR89_AVBI_MAC_SHIFT (16u) +#define INTC_ICDIPR89_ETHERI_SHIFT (24u) + +#define INTC_ICDIPR91_CEUI_SHIFT (0u) + +#define INTC_ICDIPR95_H2XMLB_ERRINT_SHIFT (8u) +#define INTC_ICDIPR95_H2XIC1_ERRINT_SHIFT (16u) +#define INTC_ICDIPR95_X2HPERI1_ERRINT_SHIFT (24u) + +#define INTC_ICDIPR96_X2HPERI2_ERRINT_SHIFT (0u) +#define INTC_ICDIPR96_X2HPERI34_ERRINT_SHIFT (8u) +#define INTC_ICDIPR96_X2HPERI5_ERRINT_SHIFT (16u) +#define INTC_ICDIPR96_X2HPERI67_ERRINT_SHIFT (24u) + +#define INTC_ICDIPR97_X2HDBGR_ERRINT_SHIFT (0u) +#define INTC_ICDIPR97_X2HBSC_ERRINT_SHIFT (8u) +#define INTC_ICDIPR97_X2HSPI1_ERRINT_SHIFT (16u) +#define INTC_ICDIPR97_X2HSPI2_ERRINT_SHIFT (24u) + +#define INTC_ICDIPR98_PRRI_SHIFT (0u) +#define INTC_ICDIPR98_IFEI0_SHIFT (8u) +#define INTC_ICDIPR98_OFFI0_SHIFT (16u) +#define INTC_ICDIPR98_PFVEI0_SHIFT (24u) + +#define INTC_ICDIPR99_IFEI1_SHIFT (0u) +#define INTC_ICDIPR99_OFFI1_SHIFT (8u) +#define INTC_ICDIPR99_PFVEI1_SHIFT (16u) + +#define INTC_ICDIPR104_TINT0_SHIFT (0u) +#define INTC_ICDIPR104_TINT1_SHIFT (8u) +#define INTC_ICDIPR104_TINT2_SHIFT (16u) +#define INTC_ICDIPR104_TINT3_SHIFT (24u) + +#define INTC_ICDIPR105_TINT4_SHIFT (0u) +#define INTC_ICDIPR105_TINT5_SHIFT (8u) +#define INTC_ICDIPR105_TINT6_SHIFT (16u) +#define INTC_ICDIPR105_TINT7_SHIFT (24u) + +#define INTC_ICDIPR106_TINT8_SHIFT (0u) +#define INTC_ICDIPR106_TINT9_SHIFT (8u) +#define INTC_ICDIPR106_TINT10_SHIFT (16u) +#define INTC_ICDIPR106_TINT11_SHIFT (24u) + +#define INTC_ICDIPR107_TINT12_SHIFT (0u) +#define INTC_ICDIPR107_TINT13_SHIFT (8u) +#define INTC_ICDIPR107_TINT14_SHIFT (16u) +#define INTC_ICDIPR107_TINT15_SHIFT (24u) + +#define INTC_ICDIPR108_TINT16_SHIFT (0u) +#define INTC_ICDIPR108_TINT17_SHIFT (8u) +#define INTC_ICDIPR108_TINT18_SHIFT (16u) +#define INTC_ICDIPR108_TINT19_SHIFT (24u) + +#define INTC_ICDIPR109_TINT20_SHIFT (0u) +#define INTC_ICDIPR109_TINT21_SHIFT (8u) +#define INTC_ICDIPR109_TINT22_SHIFT (16u) +#define INTC_ICDIPR109_TINT23_SHIFT (24u) + +#define INTC_ICDIPR110_TINT24_SHIFT (0u) +#define INTC_ICDIPR110_TINT25_SHIFT (8u) +#define INTC_ICDIPR110_TINT26_SHIFT (16u) +#define INTC_ICDIPR110_TINT27_SHIFT (24u) + +#define INTC_ICDIPR111_TINT28_SHIFT (0u) +#define INTC_ICDIPR111_TINT29_SHIFT (8u) +#define INTC_ICDIPR111_TINT30_SHIFT (16u) +#define INTC_ICDIPR111_TINT31_SHIFT (24u) + +#define INTC_ICDIPR112_TINT32_SHIFT (0u) +#define INTC_ICDIPR112_TINT33_SHIFT (8u) +#define INTC_ICDIPR112_TINT34_SHIFT (16u) +#define INTC_ICDIPR112_TINT35_SHIFT (24u) + +#define INTC_ICDIPR113_TINT36_SHIFT (0u) +#define INTC_ICDIPR113_TINT37_SHIFT (8u) +#define INTC_ICDIPR113_TINT38_SHIFT (16u) +#define INTC_ICDIPR113_TINT39_SHIFT (24u) + +#define INTC_ICDIPR114_TINT40_SHIFT (0u) +#define INTC_ICDIPR114_TINT41_SHIFT (8u) +#define INTC_ICDIPR114_TINT42_SHIFT (16u) +#define INTC_ICDIPR114_TINT43_SHIFT (24u) + +#define INTC_ICDIPR115_TINT44_SHIFT (0u) +#define INTC_ICDIPR115_TINT45_SHIFT (8u) +#define INTC_ICDIPR115_TINT46_SHIFT (16u) +#define INTC_ICDIPR115_TINT47_SHIFT (24u) + +#define INTC_ICDIPR116_TINT48_SHIFT (0u) +#define INTC_ICDIPR116_TINT49_SHIFT (8u) +#define INTC_ICDIPR116_TINT50_SHIFT (16u) +#define INTC_ICDIPR116_TINT51_SHIFT (24u) + +#define INTC_ICDIPR117_TINT52_SHIFT (0u) +#define INTC_ICDIPR117_TINT53_SHIFT (8u) +#define INTC_ICDIPR117_TINT54_SHIFT (16u) +#define INTC_ICDIPR117_TINT55_SHIFT (24u) + +#define INTC_ICDIPR118_TINT56_SHIFT (0u) +#define INTC_ICDIPR118_TINT57_SHIFT (8u) +#define INTC_ICDIPR118_TINT58_SHIFT (16u) +#define INTC_ICDIPR118_TINT59_SHIFT (24u) + +#define INTC_ICDIPR119_TINT60_SHIFT (0u) +#define INTC_ICDIPR119_TINT61_SHIFT (8u) +#define INTC_ICDIPR119_TINT62_SHIFT (16u) +#define INTC_ICDIPR119_TINT63_SHIFT (24u) + +#define INTC_ICDIPR120_TINT64_SHIFT (0u) +#define INTC_ICDIPR120_TINT65_SHIFT (8u) +#define INTC_ICDIPR120_TINT66_SHIFT (16u) +#define INTC_ICDIPR120_TINT67_SHIFT (24u) + +#define INTC_ICDIPR121_TINT68_SHIFT (0u) +#define INTC_ICDIPR121_TINT69_SHIFT (8u) +#define INTC_ICDIPR121_TINT70_SHIFT (16u) +#define INTC_ICDIPR121_TINT71_SHIFT (24u) + +#define INTC_ICDIPR122_TINT72_SHIFT (0u) +#define INTC_ICDIPR122_TINT73_SHIFT (8u) +#define INTC_ICDIPR122_TINT74_SHIFT (16u) +#define INTC_ICDIPR122_TINT75_SHIFT (24u) + +#define INTC_ICDIPR123_TINT76_SHIFT (0u) +#define INTC_ICDIPR123_TINT77_SHIFT (8u) +#define INTC_ICDIPR123_TINT78_SHIFT (16u) +#define INTC_ICDIPR123_TINT79_SHIFT (24u) + +#define INTC_ICDIPR124_TINT80_SHIFT (0u) +#define INTC_ICDIPR124_TINT81_SHIFT (8u) +#define INTC_ICDIPR124_TINT82_SHIFT (16u) +#define INTC_ICDIPR124_TINT83_SHIFT (24u) + +#define INTC_ICDIPR125_TINT84_SHIFT (0u) +#define INTC_ICDIPR125_TINT85_SHIFT (8u) +#define INTC_ICDIPR125_TINT86_SHIFT (16u) +#define INTC_ICDIPR125_TINT87_SHIFT (24u) + +#define INTC_ICDIPR126_TINT88_SHIFT (0u) +#define INTC_ICDIPR126_TINT89_SHIFT (8u) +#define INTC_ICDIPR126_TINT90_SHIFT (16u) +#define INTC_ICDIPR126_TINT91_SHIFT (24u) + +#define INTC_ICDIPR127_TINT92_SHIFT (0u) +#define INTC_ICDIPR127_TINT93_SHIFT (8u) +#define INTC_ICDIPR127_TINT94_SHIFT (16u) +#define INTC_ICDIPR127_TINT95_SHIFT (24u) + +#define INTC_ICDIPR128_TINT96_SHIFT (0u) +#define INTC_ICDIPR128_TINT97_SHIFT (8u) +#define INTC_ICDIPR128_TINT98_SHIFT (16u) +#define INTC_ICDIPR128_TINT99_SHIFT (24u) + +#define INTC_ICDIPR129_TINT100_SHIFT (0u) +#define INTC_ICDIPR129_TINT101_SHIFT (8u) +#define INTC_ICDIPR129_TINT102_SHIFT (16u) +#define INTC_ICDIPR129_TINT103_SHIFT (24u) + +#define INTC_ICDIPR130_TINT104_SHIFT (0u) +#define INTC_ICDIPR130_TINT105_SHIFT (8u) +#define INTC_ICDIPR130_TINT106_SHIFT (16u) +#define INTC_ICDIPR130_TINT107_SHIFT (24u) + +#define INTC_ICDIPR131_TINT108_SHIFT (0u) +#define INTC_ICDIPR131_TINT109_SHIFT (8u) +#define INTC_ICDIPR131_TINT110_SHIFT (16u) +#define INTC_ICDIPR131_TINT111_SHIFT (24u) + +#define INTC_ICDIPR132_TINT112_SHIFT (0u) +#define INTC_ICDIPR132_TINT113_SHIFT (8u) +#define INTC_ICDIPR132_TINT114_SHIFT (16u) +#define INTC_ICDIPR132_TINT115_SHIFT (24u) + +#define INTC_ICDIPR133_TINT116_SHIFT (0u) +#define INTC_ICDIPR133_TINT117_SHIFT (8u) +#define INTC_ICDIPR133_TINT118_SHIFT (16u) +#define INTC_ICDIPR133_TINT119_SHIFT (24u) + +#define INTC_ICDIPR134_TINT120_SHIFT (0u) +#define INTC_ICDIPR134_TINT121_SHIFT (8u) +#define INTC_ICDIPR134_TINT122_SHIFT (16u) +#define INTC_ICDIPR134_TINT123_SHIFT (24u) + +#define INTC_ICDIPR135_TINT124_SHIFT (0u) +#define INTC_ICDIPR135_TINT125_SHIFT (8u) +#define INTC_ICDIPR135_TINT126_SHIFT (16u) +#define INTC_ICDIPR135_TINT127_SHIFT (24u) + +#define INTC_ICDIPR136_TINT128_SHIFT (0u) +#define INTC_ICDIPR136_TINT129_SHIFT (8u) +#define INTC_ICDIPR136_TINT130_SHIFT (16u) +#define INTC_ICDIPR136_TINT131_SHIFT (24u) + +#define INTC_ICDIPR137_TINT132_SHIFT (0u) +#define INTC_ICDIPR137_TINT133_SHIFT (8u) +#define INTC_ICDIPR137_TINT134_SHIFT (16u) +#define INTC_ICDIPR137_TINT135_SHIFT (24u) + +#define INTC_ICDIPR138_TINT136_SHIFT (0u) +#define INTC_ICDIPR138_TINT137_SHIFT (8u) +#define INTC_ICDIPR138_TINT138_SHIFT (16u) +#define INTC_ICDIPR138_TINT139_SHIFT (24u) + +#define INTC_ICDIPR139_TINT140_SHIFT (0u) +#define INTC_ICDIPR139_TINT141_SHIFT (8u) +#define INTC_ICDIPR139_TINT142_SHIFT (16u) +#define INTC_ICDIPR139_TINT143_SHIFT (24u) + +#define INTC_ICDIPR140_TINT144_SHIFT (0u) +#define INTC_ICDIPR140_TINT145_SHIFT (8u) +#define INTC_ICDIPR140_TINT146_SHIFT (16u) +#define INTC_ICDIPR140_TINT147_SHIFT (24u) + +#define INTC_ICDIPR141_TINT148_SHIFT (0u) +#define INTC_ICDIPR141_TINT149_SHIFT (8u) +#define INTC_ICDIPR141_TINT150_SHIFT (16u) +#define INTC_ICDIPR141_TINT151_SHIFT (24u) + +#define INTC_ICDIPR142_TINT152_SHIFT (0u) +#define INTC_ICDIPR142_TINT153_SHIFT (8u) +#define INTC_ICDIPR142_TINT154_SHIFT (16u) +#define INTC_ICDIPR142_TINT155_SHIFT (24u) + +#define INTC_ICDIPR143_TINT156_SHIFT (0u) +#define INTC_ICDIPR143_TINT157_SHIFT (8u) +#define INTC_ICDIPR143_TINT158_SHIFT (16u) +#define INTC_ICDIPR143_TINT159_SHIFT (24u) + +#define INTC_ICDIPR144_TINT160_SHIFT (0u) +#define INTC_ICDIPR144_TINT161_SHIFT (8u) +#define INTC_ICDIPR144_TINT162_SHIFT (16u) +#define INTC_ICDIPR144_TINT163_SHIFT (24u) + +#define INTC_ICDIPR145_TINT164_SHIFT (0u) +#define INTC_ICDIPR145_TINT165_SHIFT (8u) +#define INTC_ICDIPR145_TINT166_SHIFT (16u) +#define INTC_ICDIPR145_TINT167_SHIFT (24u) + +#define INTC_ICDIPR146_TINT168_SHIFT (0u) +#define INTC_ICDIPR146_TINT169_SHIFT (8u) +#define INTC_ICDIPR146_TINT170_SHIFT (16u) + +#define INTC_ICDIPTR0_SW0_SHIFT (0u) +#define INTC_ICDIPTR0_SW1_SHIFT (8u) +#define INTC_ICDIPTR0_SW2_SHIFT (16u) +#define INTC_ICDIPTR0_SW3_SHIFT (24u) + +#define INTC_ICDIPTR1_SW4_SHIFT (0u) +#define INTC_ICDIPTR1_SW5_SHIFT (8u) +#define INTC_ICDIPTR1_SW6_SHIFT (16u) +#define INTC_ICDIPTR1_SW7_SHIFT (24u) + +#define INTC_ICDIPTR2_SW8_SHIFT (0u) +#define INTC_ICDIPTR2_SW9_SHIFT (8u) +#define INTC_ICDIPTR2_SW10_SHIFT (16u) +#define INTC_ICDIPTR2_SW11_SHIFT (24u) + +#define INTC_ICDIPTR3_SW12_SHIFT (0u) +#define INTC_ICDIPTR3_SW13_SHIFT (8u) +#define INTC_ICDIPTR3_SW14_SHIFT (16u) +#define INTC_ICDIPTR3_SW15_SHIFT (24u) + +#define INTC_ICDIPTR4_PMUIRQ0_SHIFT (0u) +#define INTC_ICDIPTR4_COMMRX0_SHIFT (8u) +#define INTC_ICDIPTR4_COMMTX0_SHIFT (16u) +#define INTC_ICDIPTR4_CTIIRQ0_SHIFT (24u) + +#define INTC_ICDIPTR8_IRQ0_SHIFT (0u) +#define INTC_ICDIPTR8_IRQ1_SHIFT (8u) +#define INTC_ICDIPTR8_IRQ2_SHIFT (16u) +#define INTC_ICDIPTR8_IRQ3_SHIFT (24u) + +#define INTC_ICDIPTR9_IRQ4_SHIFT (0u) +#define INTC_ICDIPTR9_IRQ5_SHIFT (8u) +#define INTC_ICDIPTR9_IRQ6_SHIFT (16u) +#define INTC_ICDIPTR9_IRQ7_SHIFT (24u) + +#define INTC_ICDIPTR10_PL310ERR_SHIFT (0u) +#define INTC_ICDIPTR10_DMAINT0_SHIFT (8u) +#define INTC_ICDIPTR10_DMAINT1_SHIFT (16u) +#define INTC_ICDIPTR10_DMAINT2_SHIFT (24u) + +#define INTC_ICDIPTR11_DMAINT3_SHIFT (0u) +#define INTC_ICDIPTR11_DMAINT4_SHIFT (8u) +#define INTC_ICDIPTR11_DMAINT5_SHIFT (16u) +#define INTC_ICDIPTR11_DMAINT6_SHIFT (24u) + +#define INTC_ICDIPTR12_DMAINT7_SHIFT (0u) +#define INTC_ICDIPTR12_DMAINT8_SHIFT (8u) +#define INTC_ICDIPTR12_DMAINT9_SHIFT (16u) +#define INTC_ICDIPTR12_DMAINT10_SHIFT (24u) + +#define INTC_ICDIPTR13_DMAINT11_SHIFT (0u) +#define INTC_ICDIPTR13_DMAINT12_SHIFT (8u) +#define INTC_ICDIPTR13_DMAINT13_SHIFT (16u) +#define INTC_ICDIPTR13_DMAINT14_SHIFT (24u) + +#define INTC_ICDIPTR14_DMAINT15_SHIFT (0u) +#define INTC_ICDIPTR14_DMAERR_SHIFT (8u) + +#define INTC_ICDIPTR18_USBI0_SHIFT (8u) +#define INTC_ICDIPTR18_USBI1_SHIFT (16u) +#define INTC_ICDIPTR18_S0_VI_VSYNC0_SHIFT (24u) + +#define INTC_ICDIPTR19_S0_LO_VSYNC0_SHIFT (0u) +#define INTC_ICDIPTR19_S0_VSYNCERR0_SHIFT (8u) +#define INTC_ICDIPTR19_GR3_VLINE0_SHIFT (16u) +#define INTC_ICDIPTR19_S0_VFIELD0_SHIFT (24u) + +#define INTC_ICDIPTR20_IV1_VBUFERR0_SHIFT (0u) +#define INTC_ICDIPTR20_IV3_VBUFERR0_SHIFT (8u) +#define INTC_ICDIPTR20_IV5_VBUFERR0_SHIFT (16u) +#define INTC_ICDIPTR20_IV6_VBUFERR0_SHIFT (24u) + +#define INTC_ICDIPTR21_S0_WLINE0_SHIFT (0u) +#define INTC_ICDIPTR21_S1_VI_VSYNC0_SHIFT (8u) +#define INTC_ICDIPTR21_S1_LO_VSYNC0_SHIFT (16u) +#define INTC_ICDIPTR21_S1_VSYNCERR0_SHIFT (24u) + +#define INTC_ICDIPTR22_S1_VFIELD0_SHIFT (0u) +#define INTC_ICDIPTR22_IV2_VBUFERR0_SHIFT (8u) +#define INTC_ICDIPTR22_IV4_VBUFERR0_SHIFT (16u) +#define INTC_ICDIPTR22_S1_WLINE0_SHIFT (24u) + +#define INTC_ICDIPTR23_OIR_VI_VSYNC0_SHIFT (0u) +#define INTC_ICDIPTR23_OIR_LO_VSYNC0_SHIFT (8u) +#define INTC_ICDIPTR23_OIR_VSYNCERR0_SHIFT (16u) +#define INTC_ICDIPTR23_OIR_VFIELD0_SHIFT (24u) + +#define INTC_ICDIPTR24_IV7_VBUFERR0_SHIFT (0u) +#define INTC_ICDIPTR24_IV8_VBUFERR0_SHIFT (8u) +#define INTC_ICDIPTR24_S0_VI_VSYNC1_SHIFT (24u) + +#define INTC_ICDIPTR25_S0_LO_VSYNC1_SHIFT (0u) +#define INTC_ICDIPTR25_S0_VSYNCERR1_SHIFT (8u) +#define INTC_ICDIPTR25_GR3_VLINE1_SHIFT (16u) +#define INTC_ICDIPTR25_S0_VFIELD1_SHIFT (24u) + +#define INTC_ICDIPTR26_IV1_VBUFERR1_SHIFT (0u) +#define INTC_ICDIPTR26_IV3_VBUFERR1_SHIFT (8u) +#define INTC_ICDIPTR26_IV5_VBUFERR1_SHIFT (16u) +#define INTC_ICDIPTR26_IV6_VBUFERR1_SHIFT (24u) + +#define INTC_ICDIPTR27_S0_WLINE1_SHIFT (0u) +#define INTC_ICDIPTR27_S1_VI_VSYNC1_SHIFT (8u) +#define INTC_ICDIPTR27_S1_LO_VSYNC1_SHIFT (16u) +#define INTC_ICDIPTR27_S1_VSYNCERR1_SHIFT (24u) + +#define INTC_ICDIPTR28_S1_VFIELD1_SHIFT (0u) +#define INTC_ICDIPTR28_IV2_VBUFERR1_SHIFT (8u) +#define INTC_ICDIPTR28_IV4_VBUFERR1_SHIFT (16u) +#define INTC_ICDIPTR28_S1_WLINE1_SHIFT (24u) + +#define INTC_ICDIPTR29_OIR_VI_VSYNC1_SHIFT (0u) +#define INTC_ICDIPTR29_OIR_LO_VSYNC1_SHIFT (8u) +#define INTC_ICDIPTR29_OIR_VLINE1_SHIFT (16u) +#define INTC_ICDIPTR29_OIR_VFIELD1_SHIFT (24u) + +#define INTC_ICDIPTR30_IV7_VBUFERR1_SHIFT (0u) +#define INTC_ICDIPTR30_IV8_VBUFERR1_SHIFT (8u) +#define INTC_ICDIPTR30_IMRDI_SHIFT (24u) + +#define INTC_ICDIPTR31_IMR2I0_SHIFT (0u) +#define INTC_ICDIPTR31_IMR2I1_SHIFT (8u) +#define INTC_ICDIPTR31_JEDI_SHIFT (16u) +#define INTC_ICDIPTR31_JDTI_SHIFT (24u) + +#define INTC_ICDIPTR32_CMP0_SHIFT (0u) +#define INTC_ICDIPTR32_CMP1_SHIFT (8u) +#define INTC_ICDIPTR32_INT0_SHIFT (16u) +#define INTC_ICDIPTR32_INT1_SHIFT (24u) + +#define INTC_ICDIPTR33_INT2_SHIFT (0u) +#define INTC_ICDIPTR33_INT3_SHIFT (8u) +#define INTC_ICDIPTR33_OSTM0TINT_SHIFT (16u) +#define INTC_ICDIPTR33_OSTM1TINT_SHIFT (24u) + +#define INTC_ICDIPTR34_CMI_SHIFT (0u) +#define INTC_ICDIPTR34_WTOUT_SHIFT (8u) +#define INTC_ICDIPTR34_ITI_SHIFT (16u) +#define INTC_ICDIPTR34_TGI0A_SHIFT (24u) + +#define INTC_ICDIPTR35_TGI0B_SHIFT (0u) +#define INTC_ICDIPTR35_TGI0C_SHIFT (8u) +#define INTC_ICDIPTR35_TGI0D_SHIFT (16u) +#define INTC_ICDIPTR35_TGI0V_SHIFT (24u) + +#define INTC_ICDIPTR36_TGI0E_SHIFT (0u) +#define INTC_ICDIPTR36_TGI0F_SHIFT (8u) +#define INTC_ICDIPTR36_TGI1A_SHIFT (16u) +#define INTC_ICDIPTR36_TGI1B_SHIFT (24u) + +#define INTC_ICDIPTR37_TGI1V_SHIFT (0u) +#define INTC_ICDIPTR37_TGI1U_SHIFT (8u) +#define INTC_ICDIPTR37_TGI2A_SHIFT (16u) +#define INTC_ICDIPTR37_TGI2B_SHIFT (24u) + +#define INTC_ICDIPTR38_TGI2V_SHIFT (0u) +#define INTC_ICDIPTR38_TGI2U_SHIFT (8u) +#define INTC_ICDIPTR38_TGI3A_SHIFT (16u) +#define INTC_ICDIPTR38_TGI3B_SHIFT (24u) + +#define INTC_ICDIPTR39_TGI3C_SHIFT (0u) +#define INTC_ICDIPTR39_TGI3D_SHIFT (8u) +#define INTC_ICDIPTR39_TGI3V_SHIFT (16u) +#define INTC_ICDIPTR39_TGI4A_SHIFT (24u) + +#define INTC_ICDIPTR40_TGI4B_SHIFT (0u) +#define INTC_ICDIPTR40_TGI4C_SHIFT (8u) +#define INTC_ICDIPTR40_TGI4D_SHIFT (16u) +#define INTC_ICDIPTR40_TGI4V_SHIFT (24u) + +#define INTC_ICDIPTR41_CMI1_SHIFT (0u) +#define INTC_ICDIPTR41_CMI2_SHIFT (8u) +#define INTC_ICDIPTR41_SGDEI0_SHIFT (16u) +#define INTC_ICDIPTR41_SGDEI1_SHIFT (24u) + +#define INTC_ICDIPTR42_SGDEI2_SHIFT (0u) +#define INTC_ICDIPTR42_SGDEI3_SHIFT (8u) +#define INTC_ICDIPTR42_ADI_SHIFT (16u) +#define INTC_ICDIPTR42_LMTI_SHIFT (24u) + +#define INTC_ICDIPTR43_SSII0_SHIFT (0u) +#define INTC_ICDIPTR43_SSIRXI0_SHIFT (8u) +#define INTC_ICDIPTR43_SSITXI0_SHIFT (16u) +#define INTC_ICDIPTR43_SSII1_SHIFT (24u) + +#define INTC_ICDIPTR44_SSIRXI1_SHIFT (0u) +#define INTC_ICDIPTR44_SSITXI1_SHIFT (8u) +#define INTC_ICDIPTR44_SSII2_SHIFT (16u) +#define INTC_ICDIPTR44_SSIRTI2_SHIFT (24u) + +#define INTC_ICDIPTR45_SSII3_SHIFT (0u) +#define INTC_ICDIPTR45_SSIRXI3_SHIFT (8u) +#define INTC_ICDIPTR45_SSITXI3_SHIFT (16u) +#define INTC_ICDIPTR45_SSII4_SHIFT (24u) + +#define INTC_ICDIPTR46_SSIRTI4_SHIFT (0u) +#define INTC_ICDIPTR46_SSII5_SHIFT (8u) +#define INTC_ICDIPTR46_SSIRXI5_SHIFT (16u) +#define INTC_ICDIPTR46_SSITXI5_SHIFT (24u) + +#define INTC_ICDIPTR47_SPDIFI_SHIFT (0u) +#define INTC_ICDIPTR47_INTIICTEI0_SHIFT (8u) +#define INTC_ICDIPTR47_INTIICRI0_SHIFT (16u) +#define INTC_ICDIPTR47_INTIICTI0_SHIFT (24u) + +#define INTC_ICDIPTR48_INTIICSPI0_SHIFT (0u) +#define INTC_ICDIPTR48_INTIICSTI0_SHIFT (8u) +#define INTC_ICDIPTR48_INTIICNAKI0_SHIFT (16u) +#define INTC_ICDIPTR48_INTIICALI0_SHIFT (24u) + +#define INTC_ICDIPTR49_INTIICTMOI0_SHIFT (0u) +#define INTC_ICDIPTR49_INTIICTEI1_SHIFT (8u) +#define INTC_ICDIPTR49_INTIICRI1_SHIFT (16u) +#define INTC_ICDIPTR49_INTIICTI1_SHIFT (24u) + +#define INTC_ICDIPTR50_INTIICSPI1_SHIFT (0u) +#define INTC_ICDIPTR50_INTIICSTI1_SHIFT (8u) +#define INTC_ICDIPTR50_INTIICNAKI1_SHIFT (16u) +#define INTC_ICDIPTR50_INTIICALI1_SHIFT (24u) + +#define INTC_ICDIPTR51_INTIICTMOI1_SHIFT (0u) +#define INTC_ICDIPTR51_INTIICTEI2_SHIFT (8u) +#define INTC_ICDIPTR51_INTIICRI2_SHIFT (16u) +#define INTC_ICDIPTR51_INTIICTI2_SHIFT (24u) + +#define INTC_ICDIPTR52_INTIICSPI2_SHIFT (0u) +#define INTC_ICDIPTR52_INTIICSTI2_SHIFT (8u) +#define INTC_ICDIPTR52_INTIICNAKI2_SHIFT (16u) +#define INTC_ICDIPTR52_INTIICALI2_SHIFT (24u) + +#define INTC_ICDIPTR53_INTIICTMOI2_SHIFT (0u) +#define INTC_ICDIPTR53_INTIICTEI3_SHIFT (8u) +#define INTC_ICDIPTR53_INTIICRI3_SHIFT (16u) +#define INTC_ICDIPTR53_INTIICTI3_SHIFT (24u) + +#define INTC_ICDIPTR54_INTIICSPI3_SHIFT (0u) +#define INTC_ICDIPTR54_INTIICSTI3_SHIFT (8u) +#define INTC_ICDIPTR54_INTIICNAKI3_SHIFT (16u) +#define INTC_ICDIPTR54_INTIICALI3_SHIFT (24u) + +#define INTC_ICDIPTR55_INTIICTMOI3_SHIFT (0u) +#define INTC_ICDIPTR55_BRI0_SHIFT (8u) +#define INTC_ICDIPTR55_ERI0_SHIFT (16u) +#define INTC_ICDIPTR55_RXI0_SHIFT (24u) + +#define INTC_ICDIPTR56_TXI0_SHIFT (0u) +#define INTC_ICDIPTR56_BRI1_SHIFT (8u) +#define INTC_ICDIPTR56_ERI1_SHIFT (16u) +#define INTC_ICDIPTR56_RXI1_SHIFT (24u) + +#define INTC_ICDIPTR57_TXI1_SHIFT (0u) +#define INTC_ICDIPTR57_BRI2_SHIFT (8u) +#define INTC_ICDIPTR57_ERI2_SHIFT (16u) +#define INTC_ICDIPTR57_RXI2_SHIFT (24u) + +#define INTC_ICDIPTR58_TXI2_SHIFT (0u) +#define INTC_ICDIPTR58_BRI3_SHIFT (8u) +#define INTC_ICDIPTR58_ERI3_SHIFT (16u) +#define INTC_ICDIPTR58_RXI3_SHIFT (24u) + +#define INTC_ICDIPTR59_TXI3_SHIFT (0u) +#define INTC_ICDIPTR59_BRI4_SHIFT (8u) +#define INTC_ICDIPTR59_ERI4_SHIFT (16u) +#define INTC_ICDIPTR59_RXI4_SHIFT (24u) + +#define INTC_ICDIPTR60_TXI4_SHIFT (0u) +#define INTC_ICDIPTR60_BRI5_SHIFT (8u) +#define INTC_ICDIPTR60_ERI5_SHIFT (16u) +#define INTC_ICDIPTR60_RXI5_SHIFT (24u) + +#define INTC_ICDIPTR61_TXI5_SHIFT (0u) +#define INTC_ICDIPTR61_BRI6_SHIFT (8u) +#define INTC_ICDIPTR61_ERI6_SHIFT (16u) +#define INTC_ICDIPTR61_RXI6_SHIFT (24u) + +#define INTC_ICDIPTR62_TXI6_SHIFT (0u) +#define INTC_ICDIPTR62_BRI7_SHIFT (8u) +#define INTC_ICDIPTR62_ERI7_SHIFT (16u) +#define INTC_ICDIPTR62_RXI7_SHIFT (24u) + +#define INTC_ICDIPTR63_TXI7_SHIFT (0u) +#define INTC_ICDIPTR63_INTRCANGERR_SHIFT (8u) +#define INTC_ICDIPTR63_INTRCANGRECC_SHIFT (16u) +#define INTC_ICDIPTR63_INTRCAN0REC_SHIFT (24u) + +#define INTC_ICDIPTR64_INTRCAN0ERR_SHIFT (0u) +#define INTC_ICDIPTR64_INTRCAN0TRX_SHIFT (8u) +#define INTC_ICDIPTR64_INTRCAN1REC_SHIFT (16u) +#define INTC_ICDIPTR64_INTRCAN1ERR_SHIFT (24u) + +#define INTC_ICDIPTR65_INTRCAN1TRX_SHIFT (0u) +#define INTC_ICDIPTR65_INTRCAN2REC_SHIFT (8u) +#define INTC_ICDIPTR65_INTRCAN2ERR_SHIFT (16u) +#define INTC_ICDIPTR65_INTRCAN2TRX_SHIFT (24u) + +#define INTC_ICDIPTR66_INTRCAN3REC_SHIFT (0u) +#define INTC_ICDIPTR66_INTRCAN3ERR_SHIFT (8u) +#define INTC_ICDIPTR66_INTRCAN3TRX_SHIFT (16u) +#define INTC_ICDIPTR66_INTRCAN4REC_SHIFT (24u) + +#define INTC_ICDIPTR67_INTRCAN4ERR_SHIFT (0u) +#define INTC_ICDIPTR67_INTRCAN4TRX_SHIFT (8u) +#define INTC_ICDIPTR67_SPEI0_SHIFT (16u) +#define INTC_ICDIPTR67_SPRI0_SHIFT (24u) + +#define INTC_ICDIPTR68_SPTI0_SHIFT (0u) +#define INTC_ICDIPTR68_SPEI1_SHIFT (8u) +#define INTC_ICDIPTR68_SPRI1_SHIFT (16u) +#define INTC_ICDIPTR68_SPTI1_SHIFT (24u) + +#define INTC_ICDIPTR69_SPEI2_SHIFT (0u) +#define INTC_ICDIPTR69_SPRI2_SHIFT (8u) +#define INTC_ICDIPTR69_SPTI2_SHIFT (16u) +#define INTC_ICDIPTR69_SPEI3_SHIFT (24u) + +#define INTC_ICDIPTR70_SPRI3_SHIFT (0u) +#define INTC_ICDIPTR70_SPTI3_SHIFT (8u) +#define INTC_ICDIPTR70_SPEI4_SHIFT (16u) +#define INTC_ICDIPTR70_SPRI4_SHIFT (24u) + +#define INTC_ICDIPTR71_SPTI4_SHIFT (0u) +#define INTC_ICDIPTR71_IEBBTD_SHIFT (8u) +#define INTC_ICDIPTR71_IEBBTERR_SHIFT (16u) +#define INTC_ICDIPTR71_IEBBTSTA_SHIFT (24u) + +#define INTC_ICDIPTR72_IEBBTV_SHIFT (0u) +#define INTC_ICDIPTR72_ISY_SHIFT (8u) +#define INTC_ICDIPTR72_IERR_SHIFT (16u) +#define INTC_ICDIPTR72_ITARG_SHIFT (24u) + +#define INTC_ICDIPTR73_ISEC_SHIFT (0u) +#define INTC_ICDIPTR73_IBUF_SHIFT (8u) +#define INTC_ICDIPTR73_IREADY_SHIFT (16u) +#define INTC_ICDIPTR73_FLSTE_SHIFT (24u) + +#define INTC_ICDIPTR74_FLTENDI_SHIFT (0u) +#define INTC_ICDIPTR74_FLTREQ0I_SHIFT (8u) +#define INTC_ICDIPTR74_FLTREQ1I_SHIFT (16u) +#define INTC_ICDIPTR74_MMC0_SHIFT (24u) + +#define INTC_ICDIPTR75_MMC1_SHIFT (0u) +#define INTC_ICDIPTR75_MMC2_SHIFT (8u) +#define INTC_ICDIPTR75_SDHI0_3_SHIFT (16u) +#define INTC_ICDIPTR75_SDHI0_0_SHIFT (24u) + +#define INTC_ICDIPTR76_SDHI0_1_SHIFT (0u) +#define INTC_ICDIPTR76_SDHI1_3_SHIFT (8u) +#define INTC_ICDIPTR76_SDHI1_0_SHIFT (16u) +#define INTC_ICDIPTR76_SDHI1_1_SHIFT (24u) + +#define INTC_ICDIPTR77_ARM_SHIFT (0u) +#define INTC_ICDIPTR77_PRD_SHIFT (8u) +#define INTC_ICDIPTR77_CUP_SHIFT (16u) +#define INTC_ICDIPTR77_SCUAI0_SHIFT (24u) + +#define INTC_ICDIPTR78_SCUAI1_SHIFT (0u) +#define INTC_ICDIPTR78_SCUFDI0_SHIFT (8u) +#define INTC_ICDIPTR78_SCUFDI1_SHIFT (16u) +#define INTC_ICDIPTR78_SCUFDI2_SHIFT (24u) + +#define INTC_ICDIPTR79_SCUFDI3_SHIFT (0u) +#define INTC_ICDIPTR79_SCUFUI0_SHIFT (8u) +#define INTC_ICDIPTR79_SCUFUI1_SHIFT (16u) +#define INTC_ICDIPTR79_SCUFUI2_SHIFT (24u) + +#define INTC_ICDIPTR80_SCUFUI3_SHIFT (0u) +#define INTC_ICDIPTR80_SCUDVI0_SHIFT (8u) +#define INTC_ICDIPTR80_SCUDVI1_SHIFT (16u) +#define INTC_ICDIPTR80_SCUDVI2_SHIFT (24u) + +#define INTC_ICDIPTR81_SCUDVI3_SHIFT (0u) +#define INTC_ICDIPTR81_MLB_CINT_SHIFT (8u) +#define INTC_ICDIPTR81_MLB_SINT_SHIFT (16u) +#define INTC_ICDIPTR81_DRC0_SHIFT (24u) + +#define INTC_ICDIPTR82_DRC1_SHIFT (0u) +#define INTC_ICDIPTR82_LINI0_INT_T_SHIFT (24u) + +#define INTC_ICDIPTR83_LINI0_INT_R_SHIFT (0u) +#define INTC_ICDIPTR83_LINI0_INT_S_SHIFT (8u) +#define INTC_ICDIPTR83_LINI0_INT_M_SHIFT (16u) +#define INTC_ICDIPTR83_LINI1_INT_T_SHIFT (24u) + +#define INTC_ICDIPTR84_LINI1_INT_R_SHIFT (0u) +#define INTC_ICDIPTR84_LINI1_INT_S_SHIFT (8u) +#define INTC_ICDIPTR84_LINI1_INT_M_SHIFT (16u) + +#define INTC_ICDIPTR86_ERI0_SHIFT (24u) + +#define INTC_ICDIPTR87_RXI0_SHIFT (0u) +#define INTC_ICDIPTR87_TXI0_SHIFT (8u) +#define INTC_ICDIPTR87_TEI0_SHIFT (16u) +#define INTC_ICDIPTR87_ERI1_SHIFT (24u) + +#define INTC_ICDIPTR88_RXI1_SHIFT (0u) +#define INTC_ICDIPTR88_TXI1_SHIFT (8u) +#define INTC_ICDIPTR88_TEI1_SHIFT (16u) +#define INTC_ICDIPTR88_AVBI_DATA_SHIFT (24u) + +#define INTC_ICDIPTR89_AVBI_ERROR_SHIFT (0u) +#define INTC_ICDIPTR89_AVBI_MANAGE_SHIFT (8u) +#define INTC_ICDIPTR89_AVBI_MAC_SHIFT (16u) +#define INTC_ICDIPTR89_ETHERI_SHIFT (24u) + +#define INTC_ICDIPTR91_CEUI_SHIFT (0u) + +#define INTC_ICDIPTR95_H2XMLB_ERRINT_SHIFT (8u) +#define INTC_ICDIPTR95_H2XIC1_ERRINT_SHIFT (16u) +#define INTC_ICDIPTR95_X2HPERI1_ERRINT_SHIFT (24u) + +#define INTC_ICDIPTR96_X2HPERI2_ERRINT_SHIFT (0u) +#define INTC_ICDIPTR96_X2HPERI34_ERRINT_SHIFT (8u) +#define INTC_ICDIPTR96_X2HPERI5_ERRINT_SHIFT (16u) +#define INTC_ICDIPTR96_X2HPERI67_ERRINT_SHIFT (24u) + +#define INTC_ICDIPTR97_X2HDBGR_ERRINT_SHIFT (0u) +#define INTC_ICDIPTR97_X2HBSC_ERRINT_SHIFT (8u) +#define INTC_ICDIPTR97_X2HSPI1_ERRINT_SHIFT (16u) +#define INTC_ICDIPTR97_X2HSPI2_ERRINT_SHIFT (24u) + +#define INTC_ICDIPTR98_PRRI_SHIFT (0u) +#define INTC_ICDIPTR98_IFEI0_SHIFT (8u) +#define INTC_ICDIPTR98_OFFI0_SHIFT (16u) +#define INTC_ICDIPTR98_PFVEI0_SHIFT (24u) + +#define INTC_ICDIPTR99_IFEI1_SHIFT (0u) +#define INTC_ICDIPTR99_OFFI1_SHIFT (8u) +#define INTC_ICDIPTR99_PFVEI1_SHIFT (16u) + +#define INTC_ICDIPTR104_TINT0_SHIFT (0u) +#define INTC_ICDIPTR104_TINT1_SHIFT (8u) +#define INTC_ICDIPTR104_TINT2_SHIFT (16u) +#define INTC_ICDIPTR104_TINT3_SHIFT (24u) + +#define INTC_ICDIPTR105_TINT4_SHIFT (0u) +#define INTC_ICDIPTR105_TINT5_SHIFT (8u) +#define INTC_ICDIPTR105_TINT6_SHIFT (16u) +#define INTC_ICDIPTR105_TINT7_SHIFT (24u) + +#define INTC_ICDIPTR106_TINT8_SHIFT (0u) +#define INTC_ICDIPTR106_TINT9_SHIFT (8u) +#define INTC_ICDIPTR106_TINT10_SHIFT (16u) +#define INTC_ICDIPTR106_TINT11_SHIFT (24u) + +#define INTC_ICDIPTR107_TINT12_SHIFT (0u) +#define INTC_ICDIPTR107_TINT13_SHIFT (8u) +#define INTC_ICDIPTR107_TINT14_SHIFT (16u) +#define INTC_ICDIPTR107_TINT15_SHIFT (24u) + +#define INTC_ICDIPTR108_TINT16_SHIFT (0u) +#define INTC_ICDIPTR108_TINT17_SHIFT (8u) +#define INTC_ICDIPTR108_TINT18_SHIFT (16u) +#define INTC_ICDIPTR108_TINT19_SHIFT (24u) + +#define INTC_ICDIPTR109_TINT20_SHIFT (0u) +#define INTC_ICDIPTR109_TINT21_SHIFT (8u) +#define INTC_ICDIPTR109_TINT22_SHIFT (16u) +#define INTC_ICDIPTR109_TINT23_SHIFT (24u) + +#define INTC_ICDIPTR110_TINT24_SHIFT (0u) +#define INTC_ICDIPTR110_TINT25_SHIFT (8u) +#define INTC_ICDIPTR110_TINT26_SHIFT (16u) +#define INTC_ICDIPTR110_TINT27_SHIFT (24u) + +#define INTC_ICDIPTR111_TINT28_SHIFT (0u) +#define INTC_ICDIPTR111_TINT29_SHIFT (8u) +#define INTC_ICDIPTR111_TINT30_SHIFT (16u) +#define INTC_ICDIPTR111_TINT31_SHIFT (24u) + +#define INTC_ICDIPTR112_TINT32_SHIFT (0u) +#define INTC_ICDIPTR112_TINT33_SHIFT (8u) +#define INTC_ICDIPTR112_TINT34_SHIFT (16u) +#define INTC_ICDIPTR112_TINT35_SHIFT (24u) + +#define INTC_ICDIPTR113_TINT36_SHIFT (0u) +#define INTC_ICDIPTR113_TINT37_SHIFT (8u) +#define INTC_ICDIPTR113_TINT38_SHIFT (16u) +#define INTC_ICDIPTR113_TINT39_SHIFT (24u) + +#define INTC_ICDIPTR114_TINT40_SHIFT (0u) +#define INTC_ICDIPTR114_TINT41_SHIFT (8u) +#define INTC_ICDIPTR114_TINT42_SHIFT (16u) +#define INTC_ICDIPTR114_TINT43_SHIFT (24u) + +#define INTC_ICDIPTR115_TINT44_SHIFT (0u) +#define INTC_ICDIPTR115_TINT45_SHIFT (8u) +#define INTC_ICDIPTR115_TINT46_SHIFT (16u) +#define INTC_ICDIPTR115_TINT47_SHIFT (24u) + +#define INTC_ICDIPTR116_TINT48_SHIFT (0u) +#define INTC_ICDIPTR116_TINT49_SHIFT (8u) +#define INTC_ICDIPTR116_TINT50_SHIFT (16u) +#define INTC_ICDIPTR116_TINT51_SHIFT (24u) + +#define INTC_ICDIPTR117_TINT52_SHIFT (0u) +#define INTC_ICDIPTR117_TINT53_SHIFT (8u) +#define INTC_ICDIPTR117_TINT54_SHIFT (16u) +#define INTC_ICDIPTR117_TINT55_SHIFT (24u) + +#define INTC_ICDIPTR118_TINT56_SHIFT (0u) +#define INTC_ICDIPTR118_TINT57_SHIFT (8u) +#define INTC_ICDIPTR118_TINT58_SHIFT (16u) +#define INTC_ICDIPTR118_TINT59_SHIFT (24u) + +#define INTC_ICDIPTR119_TINT60_SHIFT (0u) +#define INTC_ICDIPTR119_TINT61_SHIFT (8u) +#define INTC_ICDIPTR119_TINT62_SHIFT (16u) +#define INTC_ICDIPTR119_TINT63_SHIFT (24u) + +#define INTC_ICDIPTR120_TINT64_SHIFT (0u) +#define INTC_ICDIPTR120_TINT65_SHIFT (8u) +#define INTC_ICDIPTR120_TINT66_SHIFT (16u) +#define INTC_ICDIPTR120_TINT67_SHIFT (24u) + +#define INTC_ICDIPTR121_TINT68_SHIFT (0u) +#define INTC_ICDIPTR121_TINT69_SHIFT (8u) +#define INTC_ICDIPTR121_TINT70_SHIFT (16u) +#define INTC_ICDIPTR121_TINT71_SHIFT (24u) + +#define INTC_ICDIPTR122_TINT72_SHIFT (0u) +#define INTC_ICDIPTR122_TINT73_SHIFT (8u) +#define INTC_ICDIPTR122_TINT74_SHIFT (16u) +#define INTC_ICDIPTR122_TINT75_SHIFT (24u) + +#define INTC_ICDIPTR123_TINT76_SHIFT (0u) +#define INTC_ICDIPTR123_TINT77_SHIFT (8u) +#define INTC_ICDIPTR123_TINT78_SHIFT (16u) +#define INTC_ICDIPTR123_TINT79_SHIFT (24u) + +#define INTC_ICDIPTR124_TINT80_SHIFT (0u) +#define INTC_ICDIPTR124_TINT81_SHIFT (8u) +#define INTC_ICDIPTR124_TINT82_SHIFT (16u) +#define INTC_ICDIPTR124_TINT83_SHIFT (24u) + +#define INTC_ICDIPTR125_TINT84_SHIFT (0u) +#define INTC_ICDIPTR125_TINT85_SHIFT (8u) +#define INTC_ICDIPTR125_TINT86_SHIFT (16u) +#define INTC_ICDIPTR125_TINT87_SHIFT (24u) + +#define INTC_ICDIPTR126_TINT88_SHIFT (0u) +#define INTC_ICDIPTR126_TINT89_SHIFT (8u) +#define INTC_ICDIPTR126_TINT90_SHIFT (16u) +#define INTC_ICDIPTR126_TINT91_SHIFT (24u) + +#define INTC_ICDIPTR127_TINT92_SHIFT (0u) +#define INTC_ICDIPTR127_TINT93_SHIFT (8u) +#define INTC_ICDIPTR127_TINT94_SHIFT (16u) +#define INTC_ICDIPTR127_TINT95_SHIFT (24u) + +#define INTC_ICDIPTR128_TINT96_SHIFT (0u) +#define INTC_ICDIPTR128_TINT97_SHIFT (8u) +#define INTC_ICDIPTR128_TINT98_SHIFT (16u) +#define INTC_ICDIPTR128_TINT99_SHIFT (24u) + +#define INTC_ICDIPTR129_TINT100_SHIFT (0u) +#define INTC_ICDIPTR129_TINT101_SHIFT (8u) +#define INTC_ICDIPTR129_TINT102_SHIFT (16u) +#define INTC_ICDIPTR129_TINT103_SHIFT (24u) + +#define INTC_ICDIPTR130_TINT104_SHIFT (0u) +#define INTC_ICDIPTR130_TINT105_SHIFT (8u) +#define INTC_ICDIPTR130_TINT106_SHIFT (16u) +#define INTC_ICDIPTR130_TINT107_SHIFT (24u) + +#define INTC_ICDIPTR131_TINT108_SHIFT (0u) +#define INTC_ICDIPTR131_TINT109_SHIFT (8u) +#define INTC_ICDIPTR131_TINT110_SHIFT (16u) +#define INTC_ICDIPTR131_TINT111_SHIFT (24u) + +#define INTC_ICDIPTR132_TINT112_SHIFT (0u) +#define INTC_ICDIPTR132_TINT113_SHIFT (8u) +#define INTC_ICDIPTR132_TINT114_SHIFT (16u) +#define INTC_ICDIPTR132_TINT115_SHIFT (24u) + +#define INTC_ICDIPTR133_TINT116_SHIFT (0u) +#define INTC_ICDIPTR133_TINT117_SHIFT (8u) +#define INTC_ICDIPTR133_TINT118_SHIFT (16u) +#define INTC_ICDIPTR133_TINT119_SHIFT (24u) + +#define INTC_ICDIPTR134_TINT120_SHIFT (0u) +#define INTC_ICDIPTR134_TINT121_SHIFT (8u) +#define INTC_ICDIPTR134_TINT122_SHIFT (16u) +#define INTC_ICDIPTR134_TINT123_SHIFT (24u) + +#define INTC_ICDIPTR135_TINT124_SHIFT (0u) +#define INTC_ICDIPTR135_TINT125_SHIFT (8u) +#define INTC_ICDIPTR135_TINT126_SHIFT (16u) +#define INTC_ICDIPTR135_TINT127_SHIFT (24u) + +#define INTC_ICDIPTR136_TINT128_SHIFT (0u) +#define INTC_ICDIPTR136_TINT129_SHIFT (8u) +#define INTC_ICDIPTR136_TINT130_SHIFT (16u) +#define INTC_ICDIPTR136_TINT131_SHIFT (24u) + +#define INTC_ICDIPTR137_TINT132_SHIFT (0u) +#define INTC_ICDIPTR137_TINT133_SHIFT (8u) +#define INTC_ICDIPTR137_TINT134_SHIFT (16u) +#define INTC_ICDIPTR137_TINT135_SHIFT (24u) + +#define INTC_ICDIPTR138_TINT136_SHIFT (0u) +#define INTC_ICDIPTR138_TINT137_SHIFT (8u) +#define INTC_ICDIPTR138_TINT138_SHIFT (16u) +#define INTC_ICDIPTR138_TINT139_SHIFT (24u) + +#define INTC_ICDIPTR139_TINT140_SHIFT (0u) +#define INTC_ICDIPTR139_TINT141_SHIFT (8u) +#define INTC_ICDIPTR139_TINT142_SHIFT (16u) +#define INTC_ICDIPTR139_TINT143_SHIFT (24u) + +#define INTC_ICDIPTR140_TINT144_SHIFT (0u) +#define INTC_ICDIPTR140_TINT145_SHIFT (8u) +#define INTC_ICDIPTR140_TINT146_SHIFT (16u) +#define INTC_ICDIPTR140_TINT147_SHIFT (24u) + +#define INTC_ICDIPTR141_TINT148_SHIFT (0u) +#define INTC_ICDIPTR141_TINT149_SHIFT (8u) +#define INTC_ICDIPTR141_TINT150_SHIFT (16u) +#define INTC_ICDIPTR141_TINT151_SHIFT (24u) + +#define INTC_ICDIPTR142_TINT152_SHIFT (0u) +#define INTC_ICDIPTR142_TINT153_SHIFT (8u) +#define INTC_ICDIPTR142_TINT154_SHIFT (16u) +#define INTC_ICDIPTR142_TINT155_SHIFT (24u) + +#define INTC_ICDIPTR143_TINT156_SHIFT (0u) +#define INTC_ICDIPTR143_TINT157_SHIFT (8u) +#define INTC_ICDIPTR143_TINT158_SHIFT (16u) +#define INTC_ICDIPTR143_TINT159_SHIFT (24u) + +#define INTC_ICDIPTR144_TINT160_SHIFT (0u) +#define INTC_ICDIPTR144_TINT161_SHIFT (8u) +#define INTC_ICDIPTR144_TINT162_SHIFT (16u) +#define INTC_ICDIPTR144_TINT163_SHIFT (24u) + +#define INTC_ICDIPTR145_TINT164_SHIFT (0u) +#define INTC_ICDIPTR145_TINT165_SHIFT (8u) +#define INTC_ICDIPTR145_TINT166_SHIFT (16u) +#define INTC_ICDIPTR145_TINT167_SHIFT (24u) + +#define INTC_ICDIPTR146_TINT168_SHIFT (0u) +#define INTC_ICDIPTR146_TINT169_SHIFT (8u) +#define INTC_ICDIPTR146_TINT170_SHIFT (16u) + +#define INTC_ICDICFR0_SW0_0_SHIFT (0u) +#define INTC_ICDICFR0_SW0_1_SHIFT (1u) +#define INTC_ICDICFR0_SW1_0_SHIFT (2u) +#define INTC_ICDICFR0_SW1_1_SHIFT (3u) +#define INTC_ICDICFR0_SW2_0_SHIFT (4u) +#define INTC_ICDICFR0_SW2_1_SHIFT (5u) +#define INTC_ICDICFR0_SW3_0_SHIFT (6u) +#define INTC_ICDICFR0_SW3_1_SHIFT (7u) +#define INTC_ICDICFR0_SW4_0_SHIFT (8u) +#define INTC_ICDICFR0_SW4_1_SHIFT (9u) +#define INTC_ICDICFR0_SW5_0_SHIFT (10u) +#define INTC_ICDICFR0_SW5_1_SHIFT (11u) +#define INTC_ICDICFR0_SW6_0_SHIFT (12u) +#define INTC_ICDICFR0_SW6_1_SHIFT (13u) +#define INTC_ICDICFR0_SW7_0_SHIFT (14u) +#define INTC_ICDICFR0_SW7_1_SHIFT (15u) +#define INTC_ICDICFR0_SW8_0_SHIFT (16u) +#define INTC_ICDICFR0_SW8_1_SHIFT (17u) +#define INTC_ICDICFR0_SW9_0_SHIFT (18u) +#define INTC_ICDICFR0_SW9_1_SHIFT (19u) +#define INTC_ICDICFR0_SW10_0_SHIFT (20u) +#define INTC_ICDICFR0_SW10_1_SHIFT (21u) +#define INTC_ICDICFR0_SW11_0_SHIFT (22u) +#define INTC_ICDICFR0_SW11_1_SHIFT (23u) +#define INTC_ICDICFR0_SW12_0_SHIFT (24u) +#define INTC_ICDICFR0_SW12_1_SHIFT (25u) +#define INTC_ICDICFR0_SW13_0_SHIFT (26u) +#define INTC_ICDICFR0_SW13_1_SHIFT (27u) +#define INTC_ICDICFR0_SW14_0_SHIFT (28u) +#define INTC_ICDICFR0_SW14_1_SHIFT (29u) +#define INTC_ICDICFR0_SW15_0_SHIFT (30u) +#define INTC_ICDICFR0_SW15_1_SHIFT (31u) + +#define INTC_ICDICFR1_PMUIRQ0_0_SHIFT (0u) +#define INTC_ICDICFR1_PMUIRQ0_1_SHIFT (1u) +#define INTC_ICDICFR1_COMMRX0_0_SHIFT (2u) +#define INTC_ICDICFR1_COMMRX0_1_SHIFT (3u) +#define INTC_ICDICFR1_COMMTX0_0_SHIFT (4u) +#define INTC_ICDICFR1_COMMTX0_1_SHIFT (5u) +#define INTC_ICDICFR1_CTIIRQ0_0_SHIFT (6u) +#define INTC_ICDICFR1_CTIIRQ0_1_SHIFT (7u) + +#define INTC_ICDICFR2_IRQ0_0_SHIFT (0u) +#define INTC_ICDICFR2_IRQ0_1_SHIFT (1u) +#define INTC_ICDICFR2_IRQ1_0_SHIFT (2u) +#define INTC_ICDICFR2_IRQ1_1_SHIFT (3u) +#define INTC_ICDICFR2_IRQ2_0_SHIFT (4u) +#define INTC_ICDICFR2_IRQ2_1_SHIFT (5u) +#define INTC_ICDICFR2_IRQ3_0_SHIFT (6u) +#define INTC_ICDICFR2_IRQ3_1_SHIFT (7u) +#define INTC_ICDICFR2_IRQ4_0_SHIFT (8u) +#define INTC_ICDICFR2_IRQ4_1_SHIFT (9u) +#define INTC_ICDICFR2_IRQ5_0_SHIFT (10u) +#define INTC_ICDICFR2_IRQ5_1_SHIFT (11u) +#define INTC_ICDICFR2_IRQ6_0_SHIFT (12u) +#define INTC_ICDICFR2_IRQ6_1_SHIFT (13u) +#define INTC_ICDICFR2_IRQ7_0_SHIFT (14u) +#define INTC_ICDICFR2_IRQ7_1_SHIFT (15u) +#define INTC_ICDICFR2_PL310ERR_0_SHIFT (16u) +#define INTC_ICDICFR2_PL310ERR_1_SHIFT (17u) +#define INTC_ICDICFR2_DMAINT0_0_SHIFT (18u) +#define INTC_ICDICFR2_DMAINT0_1_SHIFT (19u) +#define INTC_ICDICFR2_DMAINT1_0_SHIFT (20u) +#define INTC_ICDICFR2_DMAINT1_1_SHIFT (21u) +#define INTC_ICDICFR2_DMAINT2_0_SHIFT (22u) +#define INTC_ICDICFR2_DMAINT2_1_SHIFT (23u) +#define INTC_ICDICFR2_DMAINT3_0_SHIFT (24u) +#define INTC_ICDICFR2_DMAINT3_1_SHIFT (25u) +#define INTC_ICDICFR2_DMAINT4_0_SHIFT (26u) +#define INTC_ICDICFR2_DMAINT4_1_SHIFT (27u) +#define INTC_ICDICFR2_DMAINT5_0_SHIFT (28u) +#define INTC_ICDICFR2_DMAINT5_1_SHIFT (29u) +#define INTC_ICDICFR2_DMAINT6_0_SHIFT (30u) +#define INTC_ICDICFR2_DMAINT6_1_SHIFT (31u) + +#define INTC_ICDICFR3_DMAINT7_0_SHIFT (0u) +#define INTC_ICDICFR3_DMAINT7_1_SHIFT (1u) +#define INTC_ICDICFR3_DMAINT8_0_SHIFT (2u) +#define INTC_ICDICFR3_DMAINT8_1_SHIFT (3u) +#define INTC_ICDICFR3_DMAINT9_0_SHIFT (4u) +#define INTC_ICDICFR3_DMAINT9_1_SHIFT (5u) +#define INTC_ICDICFR3_DMAINT10_0_SHIFT (6u) +#define INTC_ICDICFR3_DMAINT10_1_SHIFT (7u) +#define INTC_ICDICFR3_DMAINT11_0_SHIFT (8u) +#define INTC_ICDICFR3_DMAINT11_1_SHIFT (9u) +#define INTC_ICDICFR3_DMAINT12_0_SHIFT (10u) +#define INTC_ICDICFR3_DMAINT12_1_SHIFT (11u) +#define INTC_ICDICFR3_DMAINT13_0_SHIFT (12u) +#define INTC_ICDICFR3_DMAINT13_1_SHIFT (13u) +#define INTC_ICDICFR3_DMAINT14_0_SHIFT (14u) +#define INTC_ICDICFR3_DMAINT14_1_SHIFT (15u) +#define INTC_ICDICFR3_DMAINT15_0_SHIFT (16u) +#define INTC_ICDICFR3_DMAINT15_1_SHIFT (17u) +#define INTC_ICDICFR3_DMAERR_0_SHIFT (18u) +#define INTC_ICDICFR3_DMAERR_1_SHIFT (19u) + +#define INTC_ICDICFR4_USBI0_0_SHIFT (18u) +#define INTC_ICDICFR4_USBI0_1_SHIFT (19u) +#define INTC_ICDICFR4_USBI1_0_SHIFT (20u) +#define INTC_ICDICFR4_USBI1_1_SHIFT (21u) +#define INTC_ICDICFR4_S0_VI_VSYNC0_0_SHIFT (22u) +#define INTC_ICDICFR4_S0_VI_VSYNC0_1_SHIFT (23u) +#define INTC_ICDICFR4_S0_LO_VSYNC0_0_SHIFT (24u) +#define INTC_ICDICFR4_S0_LO_VSYNC0_1_SHIFT (25u) +#define INTC_ICDICFR4_S0_VSYNCERR0_0_SHIFT (26u) +#define INTC_ICDICFR4_S0_VSYNCERR0_1_SHIFT (27u) +#define INTC_ICDICFR4_GR3_VLINE0_0_SHIFT (28u) +#define INTC_ICDICFR4_GR3_VLINE0_1_SHIFT (29u) +#define INTC_ICDICFR4_S0_VFIELD0_0_SHIFT (30u) +#define INTC_ICDICFR4_S0_VFIELD0_1_SHIFT (31u) + +#define INTC_ICDICFR5_IV1_VBUFERR0_0_SHIFT (0u) +#define INTC_ICDICFR5_IV1_VBUFERR0_1_SHIFT (1u) +#define INTC_ICDICFR5_IV3_VBUFERR0_0_SHIFT (2u) +#define INTC_ICDICFR5_IV3_VBUFERR0_1_SHIFT (3u) +#define INTC_ICDICFR5_IV5_VBUFERR0_0_SHIFT (4u) +#define INTC_ICDICFR5_IV5_VBUFERR0_1_SHIFT (5u) +#define INTC_ICDICFR5_IV6_VBUFERR0_0_SHIFT (6u) +#define INTC_ICDICFR5_IV6_VBUFERR0_1_SHIFT (7u) +#define INTC_ICDICFR5_S0_WLINE0_0_SHIFT (8u) +#define INTC_ICDICFR5_S0_WLINE0_1_SHIFT (9u) +#define INTC_ICDICFR5_S1_VI_VSYNC0_0_SHIFT (10u) +#define INTC_ICDICFR5_S1_VI_VSYNC0_1_SHIFT (11u) +#define INTC_ICDICFR5_S1_LO_VSYNC0_0_SHIFT (12u) +#define INTC_ICDICFR5_S1_LO_VSYNC0_1_SHIFT (13u) +#define INTC_ICDICFR5_S1_VSYNCERR0_0_SHIFT (14u) +#define INTC_ICDICFR5_S1_VSYNCERR0_1_SHIFT (15u) +#define INTC_ICDICFR5_S1_VFIELD0_0_SHIFT (16u) +#define INTC_ICDICFR5_S1_VFIELD0_1_SHIFT (17u) +#define INTC_ICDICFR5_IV2_VBUFERR0_0_SHIFT (18u) +#define INTC_ICDICFR5_IV2_VBUFERR0_1_SHIFT (19u) +#define INTC_ICDICFR5_IV4_VBUFERR0_0_SHIFT (20u) +#define INTC_ICDICFR5_IV4_VBUFERR0_1_SHIFT (21u) +#define INTC_ICDICFR5_S1_WLINE0_0_SHIFT (22u) +#define INTC_ICDICFR5_S1_WLINE0_1_SHIFT (23u) +#define INTC_ICDICFR5_OIR_VI_VSYNC0_0_SHIFT (24u) +#define INTC_ICDICFR5_OIR_VI_VSYNC0_1_SHIFT (25u) +#define INTC_ICDICFR5_OIR_LO_VSYNC0_0_SHIFT (26u) +#define INTC_ICDICFR5_OIR_LO_VSYNC0_1_SHIFT (27u) +#define INTC_ICDICFR5_OIR_VSYNCERR0_0_SHIFT (28u) +#define INTC_ICDICFR5_OIR_VSYNCERR0_1_SHIFT (29u) +#define INTC_ICDICFR5_OIR_VFIELD0_0_SHIFT (30u) +#define INTC_ICDICFR5_OIR_VFIELD0_1_SHIFT (31u) + +#define INTC_ICDICFR6_IV7_VBUFERR0_0_SHIFT (0u) +#define INTC_ICDICFR6_IV7_VBUFERR0_1_SHIFT (1u) +#define INTC_ICDICFR6_IV8_VBUFERR0_0_SHIFT (2u) +#define INTC_ICDICFR6_IV8_VBUFERR0_1_SHIFT (3u) +#define INTC_ICDICFR6_S0_VI_VSYNC1_0_SHIFT (6u) +#define INTC_ICDICFR6_S0_VI_VSYNC1_1_SHIFT (7u) +#define INTC_ICDICFR6_S0_LO_VSYNC1_0_SHIFT (8u) +#define INTC_ICDICFR6_S0_LO_VSYNC1_1_SHIFT (9u) +#define INTC_ICDICFR6_S0_VSYNCERR1_0_SHIFT (10u) +#define INTC_ICDICFR6_S0_VSYNCERR1_1_SHIFT (11u) +#define INTC_ICDICFR6_GR3_VLINE1_0_SHIFT (12u) +#define INTC_ICDICFR6_GR3_VLINE1_1_SHIFT (13u) +#define INTC_ICDICFR6_S0_VFIELD1_0_SHIFT (14u) +#define INTC_ICDICFR6_S0_VFIELD1_1_SHIFT (15u) +#define INTC_ICDICFR6_IV1_VBUFERR1_0_SHIFT (16u) +#define INTC_ICDICFR6_IV1_VBUFERR1_1_SHIFT (17u) +#define INTC_ICDICFR6_IV3_VBUFERR1_0_SHIFT (18u) +#define INTC_ICDICFR6_IV3_VBUFERR1_1_SHIFT (19u) +#define INTC_ICDICFR6_IV5_VBUFERR1_0_SHIFT (20u) +#define INTC_ICDICFR6_IV5_VBUFERR1_1_SHIFT (21u) +#define INTC_ICDICFR6_IV6_VBUFERR1_0_SHIFT (22u) +#define INTC_ICDICFR6_IV6_VBUFERR1_1_SHIFT (23u) +#define INTC_ICDICFR6_S0_WLINE1_0_SHIFT (24u) +#define INTC_ICDICFR6_S0_WLINE1_1_SHIFT (25u) +#define INTC_ICDICFR6_S1_VI_VSYNC1_0_SHIFT (26u) +#define INTC_ICDICFR6_S1_VI_VSYNC1_1_SHIFT (27u) +#define INTC_ICDICFR6_S1_LO_VSYNC1_0_SHIFT (28u) +#define INTC_ICDICFR6_S1_LO_VSYNC1_1_SHIFT (29u) +#define INTC_ICDICFR6_S1_VSYNCERR1_0_SHIFT (30u) +#define INTC_ICDICFR6_S1_VSYNCERR1_1_SHIFT (31u) + +#define INTC_ICDICFR7_S1_VFIELD1_0_SHIFT (0u) +#define INTC_ICDICFR7_S1_VFIELD1_1_SHIFT (1u) +#define INTC_ICDICFR7_IV2_VBUFERR1_0_SHIFT (2u) +#define INTC_ICDICFR7_IV2_VBUFERR1_1_SHIFT (3u) +#define INTC_ICDICFR7_IV4_VBUFERR1_0_SHIFT (4u) +#define INTC_ICDICFR7_IV4_VBUFERR1_1_SHIFT (5u) +#define INTC_ICDICFR7_S1_WLINE1_0_SHIFT (6u) +#define INTC_ICDICFR7_S1_WLINE1_1_SHIFT (7u) +#define INTC_ICDICFR7_OIR_VI_VSYNC1_0_SHIFT (8u) +#define INTC_ICDICFR7_OIR_VI_VSYNC1_1_SHIFT (9u) +#define INTC_ICDICFR7_OIR_LO_VSYNC1_0_SHIFT (10u) +#define INTC_ICDICFR7_OIR_LO_VSYNC1_1_SHIFT (11u) +#define INTC_ICDICFR7_OIR_VLINE1_0_SHIFT (12u) +#define INTC_ICDICFR7_OIR_VLINE1_1_SHIFT (13u) +#define INTC_ICDICFR7_OIR_VFIELD1_0_SHIFT (14u) +#define INTC_ICDICFR7_OIR_VFIELD1_1_SHIFT (15u) +#define INTC_ICDICFR7_IV7_VBUFERR1_0_SHIFT (16u) +#define INTC_ICDICFR7_IV7_VBUFERR1_1_SHIFT (17u) +#define INTC_ICDICFR7_IV8_VBUFERR1_0_SHIFT (18u) +#define INTC_ICDICFR7_IV8_VBUFERR1_1_SHIFT (19u) +#define INTC_ICDICFR7_IMRDI_0_SHIFT (22u) +#define INTC_ICDICFR7_IMRDI_1_SHIFT (23u) +#define INTC_ICDICFR7_IMR2I0_0_SHIFT (24u) +#define INTC_ICDICFR7_IMR2I0_1_SHIFT (25u) +#define INTC_ICDICFR7_IMR2I1_0_SHIFT (26u) +#define INTC_ICDICFR7_IMR2I1_1_SHIFT (27u) +#define INTC_ICDICFR7_JEDI_0_SHIFT (28u) +#define INTC_ICDICFR7_JEDI_1_SHIFT (29u) +#define INTC_ICDICFR7_JDTI_0_SHIFT (30u) +#define INTC_ICDICFR7_JDTI_1_SHIFT (31u) + +#define INTC_ICDICFR8_CMP0_0_SHIFT (0u) +#define INTC_ICDICFR8_CMP0_1_SHIFT (1u) +#define INTC_ICDICFR8_CMP1_0_SHIFT (2u) +#define INTC_ICDICFR8_CMP1_1_SHIFT (3u) +#define INTC_ICDICFR8_INT0_0_SHIFT (4u) +#define INTC_ICDICFR8_INT0_1_SHIFT (5u) +#define INTC_ICDICFR8_INT1_0_SHIFT (6u) +#define INTC_ICDICFR8_INT1_1_SHIFT (7u) +#define INTC_ICDICFR8_INT2_0_SHIFT (8u) +#define INTC_ICDICFR8_INT2_1_SHIFT (9u) +#define INTC_ICDICFR8_INT3_0_SHIFT (10u) +#define INTC_ICDICFR8_INT3_1_SHIFT (11u) +#define INTC_ICDICFR8_OSTM0TINT_0_SHIFT (12u) +#define INTC_ICDICFR8_OSTM0TINT_1_SHIFT (13u) +#define INTC_ICDICFR8_OSTM1TINT_0_SHIFT (14u) +#define INTC_ICDICFR8_OSTM1TINT_1_SHIFT (15u) +#define INTC_ICDICFR8_CMI_0_SHIFT (16u) +#define INTC_ICDICFR8_CMI_1_SHIFT (17u) +#define INTC_ICDICFR8_WTOUT_0_SHIFT (18u) +#define INTC_ICDICFR8_WTOUT_1_SHIFT (19u) +#define INTC_ICDICFR8_ITI_0_SHIFT (20u) +#define INTC_ICDICFR8_ITI_1_SHIFT (21u) +#define INTC_ICDICFR8_TGI0A_0_SHIFT (22u) +#define INTC_ICDICFR8_TGI0A_1_SHIFT (23u) +#define INTC_ICDICFR8_TGI0B_0_SHIFT (24u) +#define INTC_ICDICFR8_TGI0B_1_SHIFT (25u) +#define INTC_ICDICFR8_TGI0C_0_SHIFT (26u) +#define INTC_ICDICFR8_TGI0C_1_SHIFT (27u) +#define INTC_ICDICFR8_TGI0D_0_SHIFT (28u) +#define INTC_ICDICFR8_TGI0D_1_SHIFT (29u) +#define INTC_ICDICFR8_TGI0V_0_SHIFT (30u) +#define INTC_ICDICFR8_TGI0V_1_SHIFT (31u) + +#define INTC_ICDICFR9_TGI0E_0_SHIFT (0u) +#define INTC_ICDICFR9_TGI0E_1_SHIFT (1u) +#define INTC_ICDICFR9_TGI0F_0_SHIFT (2u) +#define INTC_ICDICFR9_TGI0F_1_SHIFT (3u) +#define INTC_ICDICFR9_TGI1A_0_SHIFT (4u) +#define INTC_ICDICFR9_TGI1A_1_SHIFT (5u) +#define INTC_ICDICFR9_TGI1B_0_SHIFT (6u) +#define INTC_ICDICFR9_TGI1B_1_SHIFT (7u) +#define INTC_ICDICFR9_TGI1V_0_SHIFT (8u) +#define INTC_ICDICFR9_TGI1V_1_SHIFT (9u) +#define INTC_ICDICFR9_TGI1U_0_SHIFT (10u) +#define INTC_ICDICFR9_TGI1U_1_SHIFT (11u) +#define INTC_ICDICFR9_TGI2A_0_SHIFT (12u) +#define INTC_ICDICFR9_TGI2A_1_SHIFT (13u) +#define INTC_ICDICFR9_TGI2B_0_SHIFT (14u) +#define INTC_ICDICFR9_TGI2B_1_SHIFT (15u) +#define INTC_ICDICFR9_TGI2V_0_SHIFT (16u) +#define INTC_ICDICFR9_TGI2V_1_SHIFT (17u) +#define INTC_ICDICFR9_TGI2U_0_SHIFT (18u) +#define INTC_ICDICFR9_TGI2U_1_SHIFT (19u) +#define INTC_ICDICFR9_TGI3A_0_SHIFT (20u) +#define INTC_ICDICFR9_TGI3A_1_SHIFT (21u) +#define INTC_ICDICFR9_TGI3B_0_SHIFT (22u) +#define INTC_ICDICFR9_TGI3B_1_SHIFT (23u) +#define INTC_ICDICFR9_TGI3C_0_SHIFT (24u) +#define INTC_ICDICFR9_TGI3C_1_SHIFT (25u) +#define INTC_ICDICFR9_TGI3D_0_SHIFT (26u) +#define INTC_ICDICFR9_TGI3D_1_SHIFT (27u) +#define INTC_ICDICFR9_TGI3V_0_SHIFT (28u) +#define INTC_ICDICFR9_TGI3V_1_SHIFT (29u) +#define INTC_ICDICFR9_TGI4A_0_SHIFT (30u) +#define INTC_ICDICFR9_TGI4A_1_SHIFT (31u) + +#define INTC_ICDICFR10_TGI4B_0_SHIFT (0u) +#define INTC_ICDICFR10_TGI4B_1_SHIFT (1u) +#define INTC_ICDICFR10_TGI4C_0_SHIFT (2u) +#define INTC_ICDICFR10_TGI4C_1_SHIFT (3u) +#define INTC_ICDICFR10_TGI4D_0_SHIFT (4u) +#define INTC_ICDICFR10_TGI4D_1_SHIFT (5u) +#define INTC_ICDICFR10_TGI4V_0_SHIFT (6u) +#define INTC_ICDICFR10_TGI4V_1_SHIFT (7u) +#define INTC_ICDICFR10_CMI1_0_SHIFT (8u) +#define INTC_ICDICFR10_CMI1_1_SHIFT (9u) +#define INTC_ICDICFR10_CMI2_0_SHIFT (10u) +#define INTC_ICDICFR10_CMI2_1_SHIFT (11u) +#define INTC_ICDICFR10_SGDEI0_0_SHIFT (12u) +#define INTC_ICDICFR10_SGDEI0_1_SHIFT (13u) +#define INTC_ICDICFR10_SGDEI1_0_SHIFT (14u) +#define INTC_ICDICFR10_SGDEI1_1_SHIFT (15u) +#define INTC_ICDICFR10_SGDEI2_0_SHIFT (16u) +#define INTC_ICDICFR10_SGDEI2_1_SHIFT (17u) +#define INTC_ICDICFR10_SGDEI3_0_SHIFT (18u) +#define INTC_ICDICFR10_SGDEI3_1_SHIFT (19u) +#define INTC_ICDICFR10_ADI_0_SHIFT (20u) +#define INTC_ICDICFR10_ADI_1_SHIFT (21u) +#define INTC_ICDICFR10_LMTI_0_SHIFT (22u) +#define INTC_ICDICFR10_LMTI_1_SHIFT (23u) +#define INTC_ICDICFR10_SSII0_0_SHIFT (24u) +#define INTC_ICDICFR10_SSII0_1_SHIFT (25u) +#define INTC_ICDICFR10_SSIRXI0_0_SHIFT (26u) +#define INTC_ICDICFR10_SSIRXI0_1_SHIFT (27u) +#define INTC_ICDICFR10_SSITXI0_0_SHIFT (28u) +#define INTC_ICDICFR10_SSITXI0_1_SHIFT (29u) +#define INTC_ICDICFR10_SSII1_0_SHIFT (30u) +#define INTC_ICDICFR10_SSII1_1_SHIFT (31u) + +#define INTC_ICDICFR11_SSIRXI1_0_SHIFT (0u) +#define INTC_ICDICFR11_SSIRXI1_1_SHIFT (1u) +#define INTC_ICDICFR11_SSITXI1_0_SHIFT (2u) +#define INTC_ICDICFR11_SSITXI1_1_SHIFT (3u) +#define INTC_ICDICFR11_SSII2_0_SHIFT (4u) +#define INTC_ICDICFR11_SSII2_1_SHIFT (5u) +#define INTC_ICDICFR11_SSIRTI2_0_SHIFT (6u) +#define INTC_ICDICFR11_SSIRTI2_1_SHIFT (7u) +#define INTC_ICDICFR11_SSII3_0_SHIFT (8u) +#define INTC_ICDICFR11_SSII3_1_SHIFT (9u) +#define INTC_ICDICFR11_SSIRXI3_0_SHIFT (10u) +#define INTC_ICDICFR11_SSIRXI3_1_SHIFT (11u) +#define INTC_ICDICFR11_SSITXI3_0_SHIFT (12u) +#define INTC_ICDICFR11_SSITXI3_1_SHIFT (13u) +#define INTC_ICDICFR11_SSII4_0_SHIFT (14u) +#define INTC_ICDICFR11_SSII4_1_SHIFT (15u) +#define INTC_ICDICFR11_SSIRTI4_0_SHIFT (16u) +#define INTC_ICDICFR11_SSIRTI4_1_SHIFT (17u) +#define INTC_ICDICFR11_SSII5_0_SHIFT (18u) +#define INTC_ICDICFR11_SSII5_1_SHIFT (19u) +#define INTC_ICDICFR11_SSIRXI5_0_SHIFT (20u) +#define INTC_ICDICFR11_SSIRXI5_1_SHIFT (21u) +#define INTC_ICDICFR11_SSITXI5_0_SHIFT (22u) +#define INTC_ICDICFR11_SSITXI5_1_SHIFT (23u) +#define INTC_ICDICFR11_SPDIFI_0_SHIFT (24u) +#define INTC_ICDICFR11_SPDIFI_1_SHIFT (25u) +#define INTC_ICDICFR11_INTIICTEI0_0_SHIFT (26u) +#define INTC_ICDICFR11_INTIICTEI0_1_SHIFT (27u) +#define INTC_ICDICFR11_INTIICRI0_0_SHIFT (28u) +#define INTC_ICDICFR11_INTIICRI0_1_SHIFT (29u) +#define INTC_ICDICFR11_INTIICTI0_0_SHIFT (30u) +#define INTC_ICDICFR11_INTIICTI0_1_SHIFT (31u) + +#define INTC_ICDICFR12_INTIICSPI0_0_SHIFT (0u) +#define INTC_ICDICFR12_INTIICSPI0_1_SHIFT (1u) +#define INTC_ICDICFR12_INTIICSTI0_0_SHIFT (2u) +#define INTC_ICDICFR12_INTIICSTI0_1_SHIFT (3u) +#define INTC_ICDICFR12_INTIICNAKI0_0_SHIFT (4u) +#define INTC_ICDICFR12_INTIICNAKI0_1_SHIFT (5u) +#define INTC_ICDICFR12_INTIICALI0_0_SHIFT (6u) +#define INTC_ICDICFR12_INTIICALI0_1_SHIFT (7u) +#define INTC_ICDICFR12_INTIICTMOI0_0_SHIFT (8u) +#define INTC_ICDICFR12_INTIICTMOI0_1_SHIFT (9u) +#define INTC_ICDICFR12_INTIICTEI1_0_SHIFT (10u) +#define INTC_ICDICFR12_INTIICTEI1_1_SHIFT (11u) +#define INTC_ICDICFR12_INTIICRI1_0_SHIFT (12u) +#define INTC_ICDICFR12_INTIICRI1_1_SHIFT (13u) +#define INTC_ICDICFR12_INTIICTI1_0_SHIFT (14u) +#define INTC_ICDICFR12_INTIICTI1_1_SHIFT (15u) +#define INTC_ICDICFR12_INTIICSPI1_0_SHIFT (16u) +#define INTC_ICDICFR12_INTIICSPI1_1_SHIFT (17u) +#define INTC_ICDICFR12_INTIICSTI1_0_SHIFT (18u) +#define INTC_ICDICFR12_INTIICSTI1_1_SHIFT (19u) +#define INTC_ICDICFR12_INTIICNAKI1_0_SHIFT (20u) +#define INTC_ICDICFR12_INTIICNAKI1_1_SHIFT (21u) +#define INTC_ICDICFR12_INTIICALI1_0_SHIFT (22u) +#define INTC_ICDICFR12_INTIICALI1_1_SHIFT (23u) +#define INTC_ICDICFR12_INTIICTMOI1_0_SHIFT (24u) +#define INTC_ICDICFR12_INTIICTMOI1_1_SHIFT (25u) +#define INTC_ICDICFR12_INTIICTEI2_0_SHIFT (26u) +#define INTC_ICDICFR12_INTIICTEI2_1_SHIFT (27u) +#define INTC_ICDICFR12_INTIICRI2_0_SHIFT (28u) +#define INTC_ICDICFR12_INTIICRI2_1_SHIFT (29u) +#define INTC_ICDICFR12_INTIICTI2_0_SHIFT (30u) +#define INTC_ICDICFR12_INTIICTI2_1_SHIFT (31u) + +#define INTC_ICDICFR13_INTIICSPI2_0_SHIFT (0u) +#define INTC_ICDICFR13_INTIICSPI2_1_SHIFT (1u) +#define INTC_ICDICFR13_INTIICSTI2_0_SHIFT (2u) +#define INTC_ICDICFR13_INTIICSTI2_1_SHIFT (3u) +#define INTC_ICDICFR13_INTIICNAKI2_0_SHIFT (4u) +#define INTC_ICDICFR13_INTIICNAKI2_1_SHIFT (5u) +#define INTC_ICDICFR13_INTIICALI2_0_SHIFT (6u) +#define INTC_ICDICFR13_INTIICALI2_1_SHIFT (7u) +#define INTC_ICDICFR13_INTIICTMOI2_0_SHIFT (8u) +#define INTC_ICDICFR13_INTIICTMOI2_1_SHIFT (9u) +#define INTC_ICDICFR13_INTIICTEI3_0_SHIFT (10u) +#define INTC_ICDICFR13_INTIICTEI3_1_SHIFT (11u) +#define INTC_ICDICFR13_INTIICRI3_0_SHIFT (12u) +#define INTC_ICDICFR13_INTIICRI3_1_SHIFT (13u) +#define INTC_ICDICFR13_INTIICTI3_0_SHIFT (14u) +#define INTC_ICDICFR13_INTIICTI3_1_SHIFT (15u) +#define INTC_ICDICFR13_INTIICSPI3_0_SHIFT (16u) +#define INTC_ICDICFR13_INTIICSPI3_1_SHIFT (17u) +#define INTC_ICDICFR13_INTIICSTI3_0_SHIFT (18u) +#define INTC_ICDICFR13_INTIICSTI3_1_SHIFT (19u) +#define INTC_ICDICFR13_INTIICNAKI3_0_SHIFT (20u) +#define INTC_ICDICFR13_INTIICNAKI3_1_SHIFT (21u) +#define INTC_ICDICFR13_INTIICALI3_0_SHIFT (22u) +#define INTC_ICDICFR13_INTIICALI3_1_SHIFT (23u) +#define INTC_ICDICFR13_INTIICTMOI3_0_SHIFT (24u) +#define INTC_ICDICFR13_INTIICTMOI3_1_SHIFT (25u) +#define INTC_ICDICFR13_BRI0_0_SHIFT (26u) +#define INTC_ICDICFR13_BRI0_1_SHIFT (27u) +#define INTC_ICDICFR13_ERI0_0_SHIFT (28u) +#define INTC_ICDICFR13_ERI0_1_SHIFT (29u) +#define INTC_ICDICFR13_RXI0_0_SHIFT (30u) +#define INTC_ICDICFR13_RXI0_1_SHIFT (31u) + +#define INTC_ICDICFR14_TXI0_0_SHIFT (0u) +#define INTC_ICDICFR14_TXI0_1_SHIFT (1u) +#define INTC_ICDICFR14_BRI1_0_SHIFT (2u) +#define INTC_ICDICFR14_BRI1_1_SHIFT (3u) +#define INTC_ICDICFR14_ERI1_0_SHIFT (4u) +#define INTC_ICDICFR14_ERI1_1_SHIFT (5u) +#define INTC_ICDICFR14_RXI1_0_SHIFT (6u) +#define INTC_ICDICFR14_RXI1_1_SHIFT (7u) +#define INTC_ICDICFR14_TXI1_0_SHIFT (8u) +#define INTC_ICDICFR14_TXI1_1_SHIFT (9u) +#define INTC_ICDICFR14_BRI2_0_SHIFT (10u) +#define INTC_ICDICFR14_BRI2_1_SHIFT (11u) +#define INTC_ICDICFR14_ERI2_0_SHIFT (12u) +#define INTC_ICDICFR14_ERI2_1_SHIFT (13u) +#define INTC_ICDICFR14_RXI2_0_SHIFT (14u) +#define INTC_ICDICFR14_RXI2_1_SHIFT (15u) +#define INTC_ICDICFR14_TXI2_0_SHIFT (16u) +#define INTC_ICDICFR14_TXI2_1_SHIFT (17u) +#define INTC_ICDICFR14_BRI3_0_SHIFT (18u) +#define INTC_ICDICFR14_BRI3_1_SHIFT (19u) +#define INTC_ICDICFR14_ERI3_0_SHIFT (20u) +#define INTC_ICDICFR14_ERI3_1_SHIFT (21u) +#define INTC_ICDICFR14_RXI3_0_SHIFT (22u) +#define INTC_ICDICFR14_RXI3_1_SHIFT (23u) +#define INTC_ICDICFR14_TXI3_0_SHIFT (24u) +#define INTC_ICDICFR14_TXI3_1_SHIFT (25u) +#define INTC_ICDICFR14_BRI4_0_SHIFT (26u) +#define INTC_ICDICFR14_BRI4_1_SHIFT (27u) +#define INTC_ICDICFR14_ERI4_0_SHIFT (28u) +#define INTC_ICDICFR14_ERI4_1_SHIFT (29u) +#define INTC_ICDICFR14_RXI4_0_SHIFT (30u) +#define INTC_ICDICFR14_RXI4_1_SHIFT (31u) + +#define INTC_ICDICFR15_TXI4_0_SHIFT (0u) +#define INTC_ICDICFR15_TXI4_1_SHIFT (1u) +#define INTC_ICDICFR15_BRI5_0_SHIFT (2u) +#define INTC_ICDICFR15_BRI5_1_SHIFT (3u) +#define INTC_ICDICFR15_ERI5_0_SHIFT (4u) +#define INTC_ICDICFR15_ERI5_1_SHIFT (5u) +#define INTC_ICDICFR15_RXI5_0_SHIFT (6u) +#define INTC_ICDICFR15_RXI5_1_SHIFT (7u) +#define INTC_ICDICFR15_TXI5_0_SHIFT (8u) +#define INTC_ICDICFR15_TXI5_1_SHIFT (9u) +#define INTC_ICDICFR15_BRI6_0_SHIFT (10u) +#define INTC_ICDICFR15_BRI6_1_SHIFT (11u) +#define INTC_ICDICFR15_ERI6_0_SHIFT (12u) +#define INTC_ICDICFR15_ERI6_1_SHIFT (13u) +#define INTC_ICDICFR15_RXI6_0_SHIFT (14u) +#define INTC_ICDICFR15_RXI6_1_SHIFT (15u) +#define INTC_ICDICFR15_TXI6_0_SHIFT (16u) +#define INTC_ICDICFR15_TXI6_1_SHIFT (17u) +#define INTC_ICDICFR15_BRI7_0_SHIFT (18u) +#define INTC_ICDICFR15_BRI7_1_SHIFT (19u) +#define INTC_ICDICFR15_ERI7_0_SHIFT (20u) +#define INTC_ICDICFR15_ERI7_1_SHIFT (21u) +#define INTC_ICDICFR15_RXI7_0_SHIFT (22u) +#define INTC_ICDICFR15_RXI7_1_SHIFT (23u) +#define INTC_ICDICFR15_TXI7_0_SHIFT (24u) +#define INTC_ICDICFR15_TXI7_1_SHIFT (25u) +#define INTC_ICDICFR15_INTRCANGERR_0_SHIFT (26u) +#define INTC_ICDICFR15_INTRCANGERR_1_SHIFT (27u) +#define INTC_ICDICFR15_INTRCANGRECC_0_SHIFT (28u) +#define INTC_ICDICFR15_INTRCANGRECC_1_SHIFT (29u) +#define INTC_ICDICFR15_INTRCAN0REC_0_SHIFT (30u) +#define INTC_ICDICFR15_INTRCAN0REC_1_SHIFT (31u) + +#define INTC_ICDICFR16_INTRCAN0ERR_0_SHIFT (0u) +#define INTC_ICDICFR16_INTRCAN0ERR_1_SHIFT (1u) +#define INTC_ICDICFR16_INTRCAN0TRX_0_SHIFT (2u) +#define INTC_ICDICFR16_INTRCAN0TRX_1_SHIFT (3u) +#define INTC_ICDICFR16_INTRCAN1REC_0_SHIFT (4u) +#define INTC_ICDICFR16_INTRCAN1REC_1_SHIFT (5u) +#define INTC_ICDICFR16_INTRCAN1ERR_0_SHIFT (6u) +#define INTC_ICDICFR16_INTRCAN1ERR_1_SHIFT (7u) +#define INTC_ICDICFR16_INTRCAN1TRX_0_SHIFT (8u) +#define INTC_ICDICFR16_INTRCAN1TRX_1_SHIFT (9u) +#define INTC_ICDICFR16_INTRCAN2REC_0_SHIFT (10u) +#define INTC_ICDICFR16_INTRCAN2REC_1_SHIFT (11u) +#define INTC_ICDICFR16_INTRCAN2ERR_0_SHIFT (12u) +#define INTC_ICDICFR16_INTRCAN2ERR_1_SHIFT (13u) +#define INTC_ICDICFR16_INTRCAN2TRX_0_SHIFT (14u) +#define INTC_ICDICFR16_INTRCAN2TRX_1_SHIFT (15u) +#define INTC_ICDICFR16_INTRCAN3REC_0_SHIFT (16u) +#define INTC_ICDICFR16_INTRCAN3REC_1_SHIFT (17u) +#define INTC_ICDICFR16_INTRCAN3ERR_0_SHIFT (18u) +#define INTC_ICDICFR16_INTRCAN3ERR_1_SHIFT (19u) +#define INTC_ICDICFR16_INTRCAN3TRX_0_SHIFT (20u) +#define INTC_ICDICFR16_INTRCAN3TRX_1_SHIFT (21u) +#define INTC_ICDICFR16_INTRCAN4REC_0_SHIFT (22u) +#define INTC_ICDICFR16_INTRCAN4REC_1_SHIFT (23u) +#define INTC_ICDICFR16_INTRCAN4ERR_0_SHIFT (24u) +#define INTC_ICDICFR16_INTRCAN4ERR_1_SHIFT (25u) +#define INTC_ICDICFR16_INTRCAN4TRX_0_SHIFT (26u) +#define INTC_ICDICFR16_INTRCAN4TRX_1_SHIFT (27u) +#define INTC_ICDICFR16_SPEI0_0_SHIFT (28u) +#define INTC_ICDICFR16_SPEI0_1_SHIFT (29u) +#define INTC_ICDICFR16_SPRI0_0_SHIFT (30u) +#define INTC_ICDICFR16_SPRI0_1_SHIFT (31u) + +#define INTC_ICDICFR17_SPTI0_0_SHIFT (0u) +#define INTC_ICDICFR17_SPTI0_1_SHIFT (1u) +#define INTC_ICDICFR17_SPEI1_0_SHIFT (2u) +#define INTC_ICDICFR17_SPEI1_1_SHIFT (3u) +#define INTC_ICDICFR17_SPRI1_0_SHIFT (4u) +#define INTC_ICDICFR17_SPRI1_1_SHIFT (5u) +#define INTC_ICDICFR17_SPTI1_0_SHIFT (6u) +#define INTC_ICDICFR17_SPTI1_1_SHIFT (7u) +#define INTC_ICDICFR17_SPEI2_0_SHIFT (8u) +#define INTC_ICDICFR17_SPEI2_1_SHIFT (9u) +#define INTC_ICDICFR17_SPRI2_0_SHIFT (10u) +#define INTC_ICDICFR17_SPRI2_1_SHIFT (11u) +#define INTC_ICDICFR17_SPTI2_0_SHIFT (12u) +#define INTC_ICDICFR17_SPTI2_1_SHIFT (13u) +#define INTC_ICDICFR17_SPEI3_0_SHIFT (14u) +#define INTC_ICDICFR17_SPEI3_1_SHIFT (15u) +#define INTC_ICDICFR17_SPRI3_0_SHIFT (16u) +#define INTC_ICDICFR17_SPRI3_1_SHIFT (17u) +#define INTC_ICDICFR17_SPTI3_0_SHIFT (18u) +#define INTC_ICDICFR17_SPTI3_1_SHIFT (19u) +#define INTC_ICDICFR17_SPEI4_0_SHIFT (20u) +#define INTC_ICDICFR17_SPEI4_1_SHIFT (21u) +#define INTC_ICDICFR17_SPRI4_0_SHIFT (22u) +#define INTC_ICDICFR17_SPRI4_1_SHIFT (23u) +#define INTC_ICDICFR17_SPTI4_0_SHIFT (24u) +#define INTC_ICDICFR17_SPTI4_1_SHIFT (25u) +#define INTC_ICDICFR17_IEBBTD_0_SHIFT (26u) +#define INTC_ICDICFR17_IEBBTD_1_SHIFT (27u) +#define INTC_ICDICFR17_IEBBTERR_0_SHIFT (28u) +#define INTC_ICDICFR17_IEBBTERR_1_SHIFT (29u) +#define INTC_ICDICFR17_IEBBTSTA_0_SHIFT (30u) +#define INTC_ICDICFR17_IEBBTSTA_1_SHIFT (31u) + +#define INTC_ICDICFR18_IEBBTV_0_SHIFT (0u) +#define INTC_ICDICFR18_IEBBTV_1_SHIFT (1u) +#define INTC_ICDICFR18_ISY_0_SHIFT (2u) +#define INTC_ICDICFR18_ISY_1_SHIFT (3u) +#define INTC_ICDICFR18_IERR_0_SHIFT (4u) +#define INTC_ICDICFR18_IERR_1_SHIFT (5u) +#define INTC_ICDICFR18_ITARG_0_SHIFT (6u) +#define INTC_ICDICFR18_ITARG_1_SHIFT (7u) +#define INTC_ICDICFR18_ISEC_0_SHIFT (8u) +#define INTC_ICDICFR18_ISEC_1_SHIFT (9u) +#define INTC_ICDICFR18_IBUF_0_SHIFT (10u) +#define INTC_ICDICFR18_IBUF_1_SHIFT (11u) +#define INTC_ICDICFR18_IREADY_0_SHIFT (12u) +#define INTC_ICDICFR18_IREADY_1_SHIFT (13u) +#define INTC_ICDICFR18_FLSTE_0_SHIFT (14u) +#define INTC_ICDICFR18_FLSTE_1_SHIFT (15u) +#define INTC_ICDICFR18_FLTENDI_0_SHIFT (16u) +#define INTC_ICDICFR18_FLTENDI_1_SHIFT (17u) +#define INTC_ICDICFR18_FLTREQ0I_0_SHIFT (18u) +#define INTC_ICDICFR18_FLTREQ0I_1_SHIFT (19u) +#define INTC_ICDICFR18_FLTREQ1I_0_SHIFT (20u) +#define INTC_ICDICFR18_FLTREQ1I_1_SHIFT (21u) +#define INTC_ICDICFR18_MMC0_0_SHIFT (22u) +#define INTC_ICDICFR18_MMC0_1_SHIFT (23u) +#define INTC_ICDICFR18_MMC1_0_SHIFT (24u) +#define INTC_ICDICFR18_MMC1_1_SHIFT (25u) +#define INTC_ICDICFR18_MMC2_0_SHIFT (26u) +#define INTC_ICDICFR18_MMC2_1_SHIFT (27u) +#define INTC_ICDICFR18_SDHI0_3_0_SHIFT (28u) +#define INTC_ICDICFR18_SDHI0_3_1_SHIFT (29u) +#define INTC_ICDICFR18_SDHI0_0_0_SHIFT (30u) +#define INTC_ICDICFR18_SDHI0_0_1_SHIFT (31u) + +#define INTC_ICDICFR19_SDHI0_1_0_SHIFT (0u) +#define INTC_ICDICFR19_SDHI0_1_1_SHIFT (1u) +#define INTC_ICDICFR19_SDHI1_3_0_SHIFT (2u) +#define INTC_ICDICFR19_SDHI1_3_1_SHIFT (3u) +#define INTC_ICDICFR19_SDHI1_0_0_SHIFT (4u) +#define INTC_ICDICFR19_SDHI1_0_1_SHIFT (5u) +#define INTC_ICDICFR19_SDHI1_1_0_SHIFT (6u) +#define INTC_ICDICFR19_SDHI1_1_1_SHIFT (7u) +#define INTC_ICDICFR19_ARM_0_SHIFT (8u) +#define INTC_ICDICFR19_ARM_1_SHIFT (9u) +#define INTC_ICDICFR19_PRD_0_SHIFT (10u) +#define INTC_ICDICFR19_PRD_1_SHIFT (11u) +#define INTC_ICDICFR19_CUP_0_SHIFT (12u) +#define INTC_ICDICFR19_CUP_1_SHIFT (13u) +#define INTC_ICDICFR19_SCUAI0_0_SHIFT (14u) +#define INTC_ICDICFR19_SCUAI0_1_SHIFT (15u) +#define INTC_ICDICFR19_SCUAI1_0_SHIFT (16u) +#define INTC_ICDICFR19_SCUAI1_1_SHIFT (17u) +#define INTC_ICDICFR19_SCUFDI0_0_SHIFT (18u) +#define INTC_ICDICFR19_SCUFDI0_1_SHIFT (19u) +#define INTC_ICDICFR19_SCUFDI1_0_SHIFT (20u) +#define INTC_ICDICFR19_SCUFDI1_1_SHIFT (21u) +#define INTC_ICDICFR19_SCUFDI2_0_SHIFT (22u) +#define INTC_ICDICFR19_SCUFDI2_1_SHIFT (23u) +#define INTC_ICDICFR19_SCUFDI3_0_SHIFT (24u) +#define INTC_ICDICFR19_SCUFDI3_1_SHIFT (25u) +#define INTC_ICDICFR19_SCUFUI0_0_SHIFT (26u) +#define INTC_ICDICFR19_SCUFUI0_1_SHIFT (27u) +#define INTC_ICDICFR19_SCUFUI1_0_SHIFT (28u) +#define INTC_ICDICFR19_SCUFUI1_1_SHIFT (29u) +#define INTC_ICDICFR19_SCUFUI2_0_SHIFT (30u) +#define INTC_ICDICFR19_SCUFUI2_1_SHIFT (31u) + +#define INTC_ICDICFR20_SCUFUI3_0_SHIFT (0u) +#define INTC_ICDICFR20_SCUFUI3_1_SHIFT (1u) +#define INTC_ICDICFR20_SCUDVI0_0_SHIFT (2u) +#define INTC_ICDICFR20_SCUDVI0_1_SHIFT (3u) +#define INTC_ICDICFR20_SCUDVI1_0_SHIFT (4u) +#define INTC_ICDICFR20_SCUDVI1_1_SHIFT (5u) +#define INTC_ICDICFR20_SCUDVI2_0_SHIFT (6u) +#define INTC_ICDICFR20_SCUDVI2_1_SHIFT (7u) +#define INTC_ICDICFR20_SCUDVI3_0_SHIFT (8u) +#define INTC_ICDICFR20_SCUDVI3_1_SHIFT (9u) +#define INTC_ICDICFR20_MLB_CINT_0_SHIFT (10u) +#define INTC_ICDICFR20_MLB_CINT_1_SHIFT (11u) +#define INTC_ICDICFR20_MLB_SINT_0_SHIFT (12u) +#define INTC_ICDICFR20_MLB_SINT_1_SHIFT (13u) +#define INTC_ICDICFR20_DRC0_0_SHIFT (14u) +#define INTC_ICDICFR20_DRC0_1_SHIFT (15u) +#define INTC_ICDICFR20_DRC1_0_SHIFT (16u) +#define INTC_ICDICFR20_DRC1_1_SHIFT (17u) +#define INTC_ICDICFR20_LINI0_INT_T_0_SHIFT (22u) +#define INTC_ICDICFR20_LINI0_INT_T_1_SHIFT (23u) +#define INTC_ICDICFR20_LINI0_INT_R_0_SHIFT (24u) +#define INTC_ICDICFR20_LINI0_INT_R_1_SHIFT (25u) +#define INTC_ICDICFR20_LINI0_INT_S_0_SHIFT (26u) +#define INTC_ICDICFR20_LINI0_INT_S_1_SHIFT (27u) +#define INTC_ICDICFR20_LINI0_INT_M_0_SHIFT (28u) +#define INTC_ICDICFR20_LINI0_INT_M_1_SHIFT (29u) +#define INTC_ICDICFR20_LINI1_INT_T_0_SHIFT (30u) +#define INTC_ICDICFR20_LINI1_INT_T_1_SHIFT (31u) + +#define INTC_ICDICFR21_LINI1_INT_R_0_SHIFT (0u) +#define INTC_ICDICFR21_LINI1_INT_R_1_SHIFT (1u) +#define INTC_ICDICFR21_LINI1_INT_S_0_SHIFT (2u) +#define INTC_ICDICFR21_LINI1_INT_S_1_SHIFT (3u) +#define INTC_ICDICFR21_LINI1_INT_M_0_SHIFT (4u) +#define INTC_ICDICFR21_LINI1_INT_M_1_SHIFT (5u) +#define INTC_ICDICFR21_ERI0_0_SHIFT (22u) +#define INTC_ICDICFR21_ERI0_1_SHIFT (23u) +#define INTC_ICDICFR21_RXI0_0_SHIFT (24u) +#define INTC_ICDICFR21_RXI0_1_SHIFT (25u) +#define INTC_ICDICFR21_TXI0_0_SHIFT (26u) +#define INTC_ICDICFR21_TXI0_1_SHIFT (27u) +#define INTC_ICDICFR21_TEI0_0_SHIFT (28u) +#define INTC_ICDICFR21_TEI0_1_SHIFT (29u) +#define INTC_ICDICFR21_ERI1_0_SHIFT (30u) +#define INTC_ICDICFR21_ERI1_1_SHIFT (31u) + +#define INTC_ICDICFR22_RXI1_0_SHIFT (0u) +#define INTC_ICDICFR22_RXI1_1_SHIFT (1u) +#define INTC_ICDICFR22_TXI1_0_SHIFT (2u) +#define INTC_ICDICFR22_TXI1_1_SHIFT (3u) +#define INTC_ICDICFR22_TEI1_0_SHIFT (4u) +#define INTC_ICDICFR22_TEI1_1_SHIFT (5u) +#define INTC_ICDICFR22_AVBI_DATA_0_SHIFT (6u) +#define INTC_ICDICFR22_AVBI_DATA_1_SHIFT (7u) +#define INTC_ICDICFR22_AVBI_ERROR_0_SHIFT (8u) +#define INTC_ICDICFR22_AVBI_ERROR_1_SHIFT (9u) +#define INTC_ICDICFR22_AVBI_MANAGE_0_SHIFT (10u) +#define INTC_ICDICFR22_AVBI_MANAGE_1_SHIFT (11u) +#define INTC_ICDICFR22_AVBI_MAC_0_SHIFT (12u) +#define INTC_ICDICFR22_AVBI_MAC_1_SHIFT (13u) +#define INTC_ICDICFR22_ETHERI_0_SHIFT (14u) +#define INTC_ICDICFR22_ETHERI_1_SHIFT (15u) +#define INTC_ICDICFR22_CEUI_0_SHIFT (24u) +#define INTC_ICDICFR22_CEUI_1_SHIFT (25u) + +#define INTC_ICDICFR23_H2XMLB_ERRINT_0_SHIFT (26u) +#define INTC_ICDICFR23_H2XMLB_ERRINT_1_SHIFT (27u) +#define INTC_ICDICFR23_H2XIC1_ERRINT_0_SHIFT (28u) +#define INTC_ICDICFR23_H2XIC1_ERRINT_1_SHIFT (29u) +#define INTC_ICDICFR23_X2HPERI1_ERRINT_0_SHIFT (30u) +#define INTC_ICDICFR23_X2HPERI1_ERRINT_1_SHIFT (31u) + +#define INTC_ICDICFR24_X2HPERI2_ERRINT_0_SHIFT (0u) +#define INTC_ICDICFR24_X2HPERI2_ERRINT_1_SHIFT (1u) +#define INTC_ICDICFR24_X2HPERI34_ERRINT_0_SHIFT (2u) +#define INTC_ICDICFR24_X2HPERI34_ERRINT_1_SHIFT (3u) +#define INTC_ICDICFR24_X2HPERI5_ERRINT_0_SHIFT (4u) +#define INTC_ICDICFR24_X2HPERI5_ERRINT_1_SHIFT (5u) +#define INTC_ICDICFR24_X2HPERI67_ERRINT_0_SHIFT (6u) +#define INTC_ICDICFR24_X2HPERI67_ERRINT_1_SHIFT (7u) +#define INTC_ICDICFR24_X2HDBGR_ERRINT_0_SHIFT (8u) +#define INTC_ICDICFR24_X2HDBGR_ERRINT_1_SHIFT (9u) +#define INTC_ICDICFR24_X2HBSC_ERRINT_0_SHIFT (10u) +#define INTC_ICDICFR24_X2HBSC_ERRINT_1_SHIFT (11u) +#define INTC_ICDICFR24_X2HSPI1_ERRINT_0_SHIFT (12u) +#define INTC_ICDICFR24_X2HSPI1_ERRINT_1_SHIFT (13u) +#define INTC_ICDICFR24_X2HSPI2_ERRINT_0_SHIFT (14u) +#define INTC_ICDICFR24_X2HSPI2_ERRINT_1_SHIFT (15u) +#define INTC_ICDICFR24_PRRI_0_SHIFT (16u) +#define INTC_ICDICFR24_PRRI_1_SHIFT (17u) +#define INTC_ICDICFR24_IFEI0_0_SHIFT (18u) +#define INTC_ICDICFR24_IFEI0_1_SHIFT (19u) +#define INTC_ICDICFR24_OFFI0_0_SHIFT (20u) +#define INTC_ICDICFR24_OFFI0_1_SHIFT (21u) +#define INTC_ICDICFR24_PFVEI0_0_SHIFT (22u) +#define INTC_ICDICFR24_PFVEI0_1_SHIFT (23u) +#define INTC_ICDICFR24_IFEI1_0_SHIFT (24u) +#define INTC_ICDICFR24_IFEI1_1_SHIFT (25u) +#define INTC_ICDICFR24_OFFI1_0_SHIFT (26u) +#define INTC_ICDICFR24_OFFI1_1_SHIFT (27u) +#define INTC_ICDICFR24_PFVEI1_0_SHIFT (28u) +#define INTC_ICDICFR24_PFVEI1_1_SHIFT (29u) + +#define INTC_ICDICFR26_TINT0_0_SHIFT (0u) +#define INTC_ICDICFR26_TINT0_1_SHIFT (1u) +#define INTC_ICDICFR26_TINT1_0_SHIFT (2u) +#define INTC_ICDICFR26_TINT1_1_SHIFT (3u) +#define INTC_ICDICFR26_TINT2_0_SHIFT (4u) +#define INTC_ICDICFR26_TINT2_1_SHIFT (5u) +#define INTC_ICDICFR26_TINT3_0_SHIFT (6u) +#define INTC_ICDICFR26_TINT3_1_SHIFT (7u) +#define INTC_ICDICFR26_TINT4_0_SHIFT (8u) +#define INTC_ICDICFR26_TINT4_1_SHIFT (9u) +#define INTC_ICDICFR26_TINT5_0_SHIFT (10u) +#define INTC_ICDICFR26_TINT5_1_SHIFT (11u) +#define INTC_ICDICFR26_TINT6_0_SHIFT (12u) +#define INTC_ICDICFR26_TINT6_1_SHIFT (13u) +#define INTC_ICDICFR26_TINT7_0_SHIFT (14u) +#define INTC_ICDICFR26_TINT7_1_SHIFT (15u) +#define INTC_ICDICFR26_TINT8_0_SHIFT (16u) +#define INTC_ICDICFR26_TINT8_1_SHIFT (17u) +#define INTC_ICDICFR26_TINT9_0_SHIFT (18u) +#define INTC_ICDICFR26_TINT9_1_SHIFT (19u) +#define INTC_ICDICFR26_TINT10_0_SHIFT (20u) +#define INTC_ICDICFR26_TINT10_1_SHIFT (21u) +#define INTC_ICDICFR26_TINT11_0_SHIFT (22u) +#define INTC_ICDICFR26_TINT11_1_SHIFT (23u) +#define INTC_ICDICFR26_TINT12_0_SHIFT (24u) +#define INTC_ICDICFR26_TINT12_1_SHIFT (25u) +#define INTC_ICDICFR26_TINT13_0_SHIFT (26u) +#define INTC_ICDICFR26_TINT13_1_SHIFT (27u) +#define INTC_ICDICFR26_TINT14_0_SHIFT (28u) +#define INTC_ICDICFR26_TINT14_1_SHIFT (29u) +#define INTC_ICDICFR26_TINT15_0_SHIFT (30u) +#define INTC_ICDICFR26_TINT15_1_SHIFT (31u) + +#define INTC_ICDICFR27_TINT16_0_SHIFT (0u) +#define INTC_ICDICFR27_TINT16_1_SHIFT (1u) +#define INTC_ICDICFR27_TINT17_0_SHIFT (2u) +#define INTC_ICDICFR27_TINT17_1_SHIFT (3u) +#define INTC_ICDICFR27_TINT18_0_SHIFT (4u) +#define INTC_ICDICFR27_TINT18_1_SHIFT (5u) +#define INTC_ICDICFR27_TINT19_0_SHIFT (6u) +#define INTC_ICDICFR27_TINT19_1_SHIFT (7u) +#define INTC_ICDICFR27_TINT20_0_SHIFT (8u) +#define INTC_ICDICFR27_TINT20_1_SHIFT (9u) +#define INTC_ICDICFR27_TINT21_0_SHIFT (10u) +#define INTC_ICDICFR27_TINT21_1_SHIFT (11u) +#define INTC_ICDICFR27_TINT22_0_SHIFT (12u) +#define INTC_ICDICFR27_TINT22_1_SHIFT (13u) +#define INTC_ICDICFR27_TINT23_0_SHIFT (14u) +#define INTC_ICDICFR27_TINT23_1_SHIFT (15u) +#define INTC_ICDICFR27_TINT24_0_SHIFT (16u) +#define INTC_ICDICFR27_TINT24_1_SHIFT (17u) +#define INTC_ICDICFR27_TINT25_0_SHIFT (18u) +#define INTC_ICDICFR27_TINT25_1_SHIFT (19u) +#define INTC_ICDICFR27_TINT26_0_SHIFT (20u) +#define INTC_ICDICFR27_TINT26_1_SHIFT (21u) +#define INTC_ICDICFR27_TINT27_0_SHIFT (22u) +#define INTC_ICDICFR27_TINT27_1_SHIFT (23u) +#define INTC_ICDICFR27_TINT28_0_SHIFT (24u) +#define INTC_ICDICFR27_TINT28_1_SHIFT (25u) +#define INTC_ICDICFR27_TINT29_0_SHIFT (26u) +#define INTC_ICDICFR27_TINT29_1_SHIFT (27u) +#define INTC_ICDICFR27_TINT30_0_SHIFT (28u) +#define INTC_ICDICFR27_TINT30_1_SHIFT (29u) +#define INTC_ICDICFR27_TINT31_0_SHIFT (30u) +#define INTC_ICDICFR27_TINT31_1_SHIFT (31u) + +#define INTC_ICDICFR28_TINT32_0_SHIFT (0u) +#define INTC_ICDICFR28_TINT32_1_SHIFT (1u) +#define INTC_ICDICFR28_TINT33_0_SHIFT (2u) +#define INTC_ICDICFR28_TINT33_1_SHIFT (3u) +#define INTC_ICDICFR28_TINT34_0_SHIFT (4u) +#define INTC_ICDICFR28_TINT34_1_SHIFT (5u) +#define INTC_ICDICFR28_TINT35_0_SHIFT (6u) +#define INTC_ICDICFR28_TINT35_1_SHIFT (7u) +#define INTC_ICDICFR28_TINT36_0_SHIFT (8u) +#define INTC_ICDICFR28_TINT36_1_SHIFT (9u) +#define INTC_ICDICFR28_TINT37_0_SHIFT (10u) +#define INTC_ICDICFR28_TINT37_1_SHIFT (11u) +#define INTC_ICDICFR28_TINT38_0_SHIFT (12u) +#define INTC_ICDICFR28_TINT38_1_SHIFT (13u) +#define INTC_ICDICFR28_TINT39_0_SHIFT (14u) +#define INTC_ICDICFR28_TINT39_1_SHIFT (15u) +#define INTC_ICDICFR28_TINT40_0_SHIFT (16u) +#define INTC_ICDICFR28_TINT40_1_SHIFT (17u) +#define INTC_ICDICFR28_TINT41_0_SHIFT (18u) +#define INTC_ICDICFR28_TINT41_1_SHIFT (19u) +#define INTC_ICDICFR28_TINT42_0_SHIFT (20u) +#define INTC_ICDICFR28_TINT42_1_SHIFT (21u) +#define INTC_ICDICFR28_TINT43_0_SHIFT (22u) +#define INTC_ICDICFR28_TINT43_1_SHIFT (23u) +#define INTC_ICDICFR28_TINT44_0_SHIFT (24u) +#define INTC_ICDICFR28_TINT44_1_SHIFT (25u) +#define INTC_ICDICFR28_TINT45_0_SHIFT (26u) +#define INTC_ICDICFR28_TINT45_1_SHIFT (27u) +#define INTC_ICDICFR28_TINT46_0_SHIFT (28u) +#define INTC_ICDICFR28_TINT46_1_SHIFT (29u) +#define INTC_ICDICFR28_TINT47_0_SHIFT (30u) +#define INTC_ICDICFR28_TINT47_1_SHIFT (31u) + +#define INTC_ICDICFR29_TINT48_0_SHIFT (0u) +#define INTC_ICDICFR29_TINT48_1_SHIFT (1u) +#define INTC_ICDICFR29_TINT49_0_SHIFT (2u) +#define INTC_ICDICFR29_TINT49_1_SHIFT (3u) +#define INTC_ICDICFR29_TINT50_0_SHIFT (4u) +#define INTC_ICDICFR29_TINT50_1_SHIFT (5u) +#define INTC_ICDICFR29_TINT51_0_SHIFT (6u) +#define INTC_ICDICFR29_TINT51_1_SHIFT (7u) +#define INTC_ICDICFR29_TINT52_0_SHIFT (8u) +#define INTC_ICDICFR29_TINT52_1_SHIFT (9u) +#define INTC_ICDICFR29_TINT53_0_SHIFT (10u) +#define INTC_ICDICFR29_TINT53_1_SHIFT (11u) +#define INTC_ICDICFR29_TINT54_0_SHIFT (12u) +#define INTC_ICDICFR29_TINT54_1_SHIFT (13u) +#define INTC_ICDICFR29_TINT55_0_SHIFT (14u) +#define INTC_ICDICFR29_TINT55_1_SHIFT (15u) +#define INTC_ICDICFR29_TINT56_0_SHIFT (16u) +#define INTC_ICDICFR29_TINT56_1_SHIFT (17u) +#define INTC_ICDICFR29_TINT57_0_SHIFT (18u) +#define INTC_ICDICFR29_TINT57_1_SHIFT (19u) +#define INTC_ICDICFR29_TINT58_0_SHIFT (20u) +#define INTC_ICDICFR29_TINT58_1_SHIFT (21u) +#define INTC_ICDICFR29_TINT59_0_SHIFT (22u) +#define INTC_ICDICFR29_TINT59_1_SHIFT (23u) +#define INTC_ICDICFR29_TINT60_0_SHIFT (24u) +#define INTC_ICDICFR29_TINT60_1_SHIFT (25u) +#define INTC_ICDICFR29_TINT61_0_SHIFT (26u) +#define INTC_ICDICFR29_TINT61_1_SHIFT (27u) +#define INTC_ICDICFR29_TINT62_0_SHIFT (28u) +#define INTC_ICDICFR29_TINT62_1_SHIFT (29u) +#define INTC_ICDICFR29_TINT63_0_SHIFT (30u) +#define INTC_ICDICFR29_TINT63_1_SHIFT (31u) + +#define INTC_ICDICFR30_TINT64_0_SHIFT (0u) +#define INTC_ICDICFR30_TINT64_1_SHIFT (1u) +#define INTC_ICDICFR30_TINT65_0_SHIFT (2u) +#define INTC_ICDICFR30_TINT65_1_SHIFT (3u) +#define INTC_ICDICFR30_TINT66_0_SHIFT (4u) +#define INTC_ICDICFR30_TINT66_1_SHIFT (5u) +#define INTC_ICDICFR30_TINT67_0_SHIFT (6u) +#define INTC_ICDICFR30_TINT67_1_SHIFT (7u) +#define INTC_ICDICFR30_TINT68_0_SHIFT (8u) +#define INTC_ICDICFR30_TINT68_1_SHIFT (9u) +#define INTC_ICDICFR30_TINT69_0_SHIFT (10u) +#define INTC_ICDICFR30_TINT69_1_SHIFT (11u) +#define INTC_ICDICFR30_TINT70_0_SHIFT (12u) +#define INTC_ICDICFR30_TINT70_1_SHIFT (13u) +#define INTC_ICDICFR30_TINT71_0_SHIFT (14u) +#define INTC_ICDICFR30_TINT71_1_SHIFT (15u) +#define INTC_ICDICFR30_TINT72_0_SHIFT (16u) +#define INTC_ICDICFR30_TINT72_1_SHIFT (17u) +#define INTC_ICDICFR30_TINT73_0_SHIFT (18u) +#define INTC_ICDICFR30_TINT73_1_SHIFT (19u) +#define INTC_ICDICFR30_TINT74_0_SHIFT (20u) +#define INTC_ICDICFR30_TINT74_1_SHIFT (21u) +#define INTC_ICDICFR30_TINT75_0_SHIFT (22u) +#define INTC_ICDICFR30_TINT75_1_SHIFT (23u) +#define INTC_ICDICFR30_TINT76_0_SHIFT (24u) +#define INTC_ICDICFR30_TINT76_1_SHIFT (25u) +#define INTC_ICDICFR30_TINT77_0_SHIFT (26u) +#define INTC_ICDICFR30_TINT77_1_SHIFT (27u) +#define INTC_ICDICFR30_TINT78_0_SHIFT (28u) +#define INTC_ICDICFR30_TINT78_1_SHIFT (29u) +#define INTC_ICDICFR30_TINT79_0_SHIFT (30u) +#define INTC_ICDICFR30_TINT79_1_SHIFT (31u) + +#define INTC_ICDICFR31_TINT80_0_SHIFT (0u) +#define INTC_ICDICFR31_TINT80_1_SHIFT (1u) +#define INTC_ICDICFR31_TINT81_0_SHIFT (2u) +#define INTC_ICDICFR31_TINT81_1_SHIFT (3u) +#define INTC_ICDICFR31_TINT82_0_SHIFT (4u) +#define INTC_ICDICFR31_TINT82_1_SHIFT (5u) +#define INTC_ICDICFR31_TINT83_0_SHIFT (6u) +#define INTC_ICDICFR31_TINT83_1_SHIFT (7u) +#define INTC_ICDICFR31_TINT84_0_SHIFT (8u) +#define INTC_ICDICFR31_TINT84_1_SHIFT (9u) +#define INTC_ICDICFR31_TINT85_0_SHIFT (10u) +#define INTC_ICDICFR31_TINT85_1_SHIFT (11u) +#define INTC_ICDICFR31_TINT86_0_SHIFT (12u) +#define INTC_ICDICFR31_TINT86_1_SHIFT (13u) +#define INTC_ICDICFR31_TINT87_0_SHIFT (14u) +#define INTC_ICDICFR31_TINT87_1_SHIFT (15u) +#define INTC_ICDICFR31_TINT88_0_SHIFT (16u) +#define INTC_ICDICFR31_TINT88_1_SHIFT (17u) +#define INTC_ICDICFR31_TINT89_0_SHIFT (18u) +#define INTC_ICDICFR31_TINT89_1_SHIFT (19u) +#define INTC_ICDICFR31_TINT90_0_SHIFT (20u) +#define INTC_ICDICFR31_TINT90_1_SHIFT (21u) +#define INTC_ICDICFR31_TINT91_0_SHIFT (22u) +#define INTC_ICDICFR31_TINT91_1_SHIFT (23u) +#define INTC_ICDICFR31_TINT92_0_SHIFT (24u) +#define INTC_ICDICFR31_TINT92_1_SHIFT (25u) +#define INTC_ICDICFR31_TINT93_0_SHIFT (26u) +#define INTC_ICDICFR31_TINT93_1_SHIFT (27u) +#define INTC_ICDICFR31_TINT94_0_SHIFT (28u) +#define INTC_ICDICFR31_TINT94_1_SHIFT (29u) +#define INTC_ICDICFR31_TINT95_0_SHIFT (30u) +#define INTC_ICDICFR31_TINT95_1_SHIFT (31u) + +#define INTC_ICDICFR32_TINT96_0_SHIFT (0u) +#define INTC_ICDICFR32_TINT96_1_SHIFT (1u) +#define INTC_ICDICFR32_TINT97_0_SHIFT (2u) +#define INTC_ICDICFR32_TINT97_1_SHIFT (3u) +#define INTC_ICDICFR32_TINT98_0_SHIFT (4u) +#define INTC_ICDICFR32_TINT98_1_SHIFT (5u) +#define INTC_ICDICFR32_TINT99_0_SHIFT (6u) +#define INTC_ICDICFR32_TINT99_1_SHIFT (7u) +#define INTC_ICDICFR32_TINT100_0_SHIFT (8u) +#define INTC_ICDICFR32_TINT100_1_SHIFT (9u) +#define INTC_ICDICFR32_TINT101_0_SHIFT (10u) +#define INTC_ICDICFR32_TINT101_1_SHIFT (11u) +#define INTC_ICDICFR32_TINT102_0_SHIFT (12u) +#define INTC_ICDICFR32_TINT102_1_SHIFT (13u) +#define INTC_ICDICFR32_TINT103_0_SHIFT (14u) +#define INTC_ICDICFR32_TINT103_1_SHIFT (15u) +#define INTC_ICDICFR32_TINT104_0_SHIFT (16u) +#define INTC_ICDICFR32_TINT104_1_SHIFT (17u) +#define INTC_ICDICFR32_TINT105_0_SHIFT (18u) +#define INTC_ICDICFR32_TINT105_1_SHIFT (19u) +#define INTC_ICDICFR32_TINT106_0_SHIFT (20u) +#define INTC_ICDICFR32_TINT106_1_SHIFT (21u) +#define INTC_ICDICFR32_TINT107_0_SHIFT (22u) +#define INTC_ICDICFR32_TINT107_1_SHIFT (23u) +#define INTC_ICDICFR32_TINT108_0_SHIFT (24u) +#define INTC_ICDICFR32_TINT108_1_SHIFT (25u) +#define INTC_ICDICFR32_TINT109_0_SHIFT (26u) +#define INTC_ICDICFR32_TINT109_1_SHIFT (27u) +#define INTC_ICDICFR32_TINT110_0_SHIFT (28u) +#define INTC_ICDICFR32_TINT110_1_SHIFT (29u) +#define INTC_ICDICFR32_TINT111_0_SHIFT (30u) +#define INTC_ICDICFR32_TINT111_1_SHIFT (31u) + +#define INTC_ICDICFR33_TINT112_0_SHIFT (0u) +#define INTC_ICDICFR33_TINT112_1_SHIFT (1u) +#define INTC_ICDICFR33_TINT113_0_SHIFT (2u) +#define INTC_ICDICFR33_TINT113_1_SHIFT (3u) +#define INTC_ICDICFR33_TINT114_0_SHIFT (4u) +#define INTC_ICDICFR33_TINT114_1_SHIFT (5u) +#define INTC_ICDICFR33_TINT115_0_SHIFT (6u) +#define INTC_ICDICFR33_TINT115_1_SHIFT (7u) +#define INTC_ICDICFR33_TINT116_0_SHIFT (8u) +#define INTC_ICDICFR33_TINT116_1_SHIFT (9u) +#define INTC_ICDICFR33_TINT117_0_SHIFT (10u) +#define INTC_ICDICFR33_TINT117_1_SHIFT (11u) +#define INTC_ICDICFR33_TINT118_0_SHIFT (12u) +#define INTC_ICDICFR33_TINT118_1_SHIFT (13u) +#define INTC_ICDICFR33_TINT119_0_SHIFT (14u) +#define INTC_ICDICFR33_TINT119_1_SHIFT (15u) +#define INTC_ICDICFR33_TINT120_0_SHIFT (16u) +#define INTC_ICDICFR33_TINT120_1_SHIFT (17u) +#define INTC_ICDICFR33_TINT121_0_SHIFT (18u) +#define INTC_ICDICFR33_TINT121_1_SHIFT (19u) +#define INTC_ICDICFR33_TINT122_0_SHIFT (20u) +#define INTC_ICDICFR33_TINT122_1_SHIFT (21u) +#define INTC_ICDICFR33_TINT123_0_SHIFT (22u) +#define INTC_ICDICFR33_TINT123_1_SHIFT (23u) +#define INTC_ICDICFR33_TINT124_0_SHIFT (24u) +#define INTC_ICDICFR33_TINT124_1_SHIFT (25u) +#define INTC_ICDICFR33_TINT125_0_SHIFT (26u) +#define INTC_ICDICFR33_TINT125_1_SHIFT (27u) +#define INTC_ICDICFR33_TINT126_0_SHIFT (28u) +#define INTC_ICDICFR33_TINT126_1_SHIFT (29u) +#define INTC_ICDICFR33_TINT127_0_SHIFT (30u) +#define INTC_ICDICFR33_TINT127_1_SHIFT (31u) + +#define INTC_ICDICFR34_TINT128_0_SHIFT (0u) +#define INTC_ICDICFR34_TINT128_1_SHIFT (1u) +#define INTC_ICDICFR34_TINT129_0_SHIFT (2u) +#define INTC_ICDICFR34_TINT129_1_SHIFT (3u) +#define INTC_ICDICFR34_TINT130_0_SHIFT (4u) +#define INTC_ICDICFR34_TINT130_1_SHIFT (5u) +#define INTC_ICDICFR34_TINT131_0_SHIFT (6u) +#define INTC_ICDICFR34_TINT131_1_SHIFT (7u) +#define INTC_ICDICFR34_TINT132_0_SHIFT (8u) +#define INTC_ICDICFR34_TINT132_1_SHIFT (9u) +#define INTC_ICDICFR34_TINT133_0_SHIFT (10u) +#define INTC_ICDICFR34_TINT133_1_SHIFT (11u) +#define INTC_ICDICFR34_TINT134_0_SHIFT (12u) +#define INTC_ICDICFR34_TINT134_1_SHIFT (13u) +#define INTC_ICDICFR34_TINT135_0_SHIFT (14u) +#define INTC_ICDICFR34_TINT135_1_SHIFT (15u) +#define INTC_ICDICFR34_TINT136_0_SHIFT (16u) +#define INTC_ICDICFR34_TINT136_1_SHIFT (17u) +#define INTC_ICDICFR34_TINT137_0_SHIFT (18u) +#define INTC_ICDICFR34_TINT137_1_SHIFT (19u) +#define INTC_ICDICFR34_TINT138_0_SHIFT (20u) +#define INTC_ICDICFR34_TINT138_1_SHIFT (21u) +#define INTC_ICDICFR34_TINT139_0_SHIFT (22u) +#define INTC_ICDICFR34_TINT139_1_SHIFT (23u) +#define INTC_ICDICFR34_TINT140_0_SHIFT (24u) +#define INTC_ICDICFR34_TINT140_1_SHIFT (25u) +#define INTC_ICDICFR34_TINT141_0_SHIFT (26u) +#define INTC_ICDICFR34_TINT141_1_SHIFT (27u) +#define INTC_ICDICFR34_TINT142_0_SHIFT (28u) +#define INTC_ICDICFR34_TINT142_1_SHIFT (29u) +#define INTC_ICDICFR34_TINT143_0_SHIFT (30u) +#define INTC_ICDICFR34_TINT143_1_SHIFT (31u) + +#define INTC_ICDICFR35_TINT144_0_SHIFT (0u) +#define INTC_ICDICFR35_TINT144_1_SHIFT (1u) +#define INTC_ICDICFR35_TINT145_0_SHIFT (2u) +#define INTC_ICDICFR35_TINT145_1_SHIFT (3u) +#define INTC_ICDICFR35_TINT146_0_SHIFT (4u) +#define INTC_ICDICFR35_TINT146_1_SHIFT (5u) +#define INTC_ICDICFR35_TINT147_0_SHIFT (6u) +#define INTC_ICDICFR35_TINT147_1_SHIFT (7u) +#define INTC_ICDICFR35_TINT148_0_SHIFT (8u) +#define INTC_ICDICFR35_TINT148_1_SHIFT (9u) +#define INTC_ICDICFR35_TINT149_0_SHIFT (10u) +#define INTC_ICDICFR35_TINT149_1_SHIFT (11u) +#define INTC_ICDICFR35_TINT150_0_SHIFT (12u) +#define INTC_ICDICFR35_TINT150_1_SHIFT (13u) +#define INTC_ICDICFR35_TINT151_0_SHIFT (14u) +#define INTC_ICDICFR35_TINT151_1_SHIFT (15u) +#define INTC_ICDICFR35_TINT152_0_SHIFT (16u) +#define INTC_ICDICFR35_TINT152_1_SHIFT (17u) +#define INTC_ICDICFR35_TINT153_0_SHIFT (18u) +#define INTC_ICDICFR35_TINT153_1_SHIFT (19u) +#define INTC_ICDICFR35_TINT154_0_SHIFT (20u) +#define INTC_ICDICFR35_TINT154_1_SHIFT (21u) +#define INTC_ICDICFR35_TINT155_0_SHIFT (22u) +#define INTC_ICDICFR35_TINT155_1_SHIFT (23u) +#define INTC_ICDICFR35_TINT156_0_SHIFT (24u) +#define INTC_ICDICFR35_TINT156_1_SHIFT (25u) +#define INTC_ICDICFR35_TINT157_0_SHIFT (26u) +#define INTC_ICDICFR35_TINT157_1_SHIFT (27u) +#define INTC_ICDICFR35_TINT158_0_SHIFT (28u) +#define INTC_ICDICFR35_TINT158_1_SHIFT (29u) +#define INTC_ICDICFR35_TINT159_0_SHIFT (30u) +#define INTC_ICDICFR35_TINT159_1_SHIFT (31u) + +#define INTC_ICDICFR36_TINT160_0_SHIFT (0u) +#define INTC_ICDICFR36_TINT160_1_SHIFT (1u) +#define INTC_ICDICFR36_TINT161_0_SHIFT (2u) +#define INTC_ICDICFR36_TINT161_1_SHIFT (3u) +#define INTC_ICDICFR36_TINT162_0_SHIFT (4u) +#define INTC_ICDICFR36_TINT162_1_SHIFT (5u) +#define INTC_ICDICFR36_TINT163_0_SHIFT (6u) +#define INTC_ICDICFR36_TINT163_1_SHIFT (7u) +#define INTC_ICDICFR36_TINT164_0_SHIFT (8u) +#define INTC_ICDICFR36_TINT164_1_SHIFT (9u) +#define INTC_ICDICFR36_TINT165_0_SHIFT (10u) +#define INTC_ICDICFR36_TINT165_1_SHIFT (11u) +#define INTC_ICDICFR36_TINT166_0_SHIFT (12u) +#define INTC_ICDICFR36_TINT166_1_SHIFT (13u) +#define INTC_ICDICFR36_TINT167_0_SHIFT (14u) +#define INTC_ICDICFR36_TINT167_1_SHIFT (15u) +#define INTC_ICDICFR36_TINT168_0_SHIFT (16u) +#define INTC_ICDICFR36_TINT168_1_SHIFT (17u) +#define INTC_ICDICFR36_TINT169_0_SHIFT (18u) +#define INTC_ICDICFR36_TINT169_1_SHIFT (19u) +#define INTC_ICDICFR36_TINT170_0_SHIFT (20u) +#define INTC_ICDICFR36_TINT170_1_SHIFT (21u) + +#define INTC_ICDSGIR_SGIINTID_SHIFT (0u) +#define INTC_ICDSGIR_SATT_SHIFT (15u) +#define INTC_ICDSGIR_CPUTargetList_SHIFT (16u) +#define INTC_ICDSGIR_TargetListFilter_SHIFT (24u) + +#define INTC_ICCICR_EnableS_SHIFT (0u) +#define INTC_ICCICR_EnableNS_SHIFT (1u) +#define INTC_ICCICR_AckCtl_SHIFT (2u) +#define INTC_ICCICR_FIQEn_SHIFT (3u) +#define INTC_ICCICR_SBPR_SHIFT (4u) + +#define INTC_ICCPMR_Priority_SHIFT (0u) + +#define INTC_ICCBPR_Binarypoint_SHIFT (0u) + +#define INTC_ICCIAR_ACKINTID_SHIFT (0u) +#define INTC_ICCIAR_CPUID_SHIFT (10u) + +#define INTC_ICCEOIR_EOIINTID_SHIFT (0u) +#define INTC_ICCEOIR_CPUID_SHIFT (10u) + +#define INTC_ICCRPR_Priority_SHIFT (0u) + +#define INTC_ICCHPIR_PENDINTID_SHIFT (0u) +#define INTC_ICCHPIR_CPUID_SHIFT (10u) + +#define INTC_ICCABPR_Binarypoint_SHIFT (0u) + +#define INTC_ICCIIDR_Implementer_SHIFT (0u) +#define INTC_ICCIIDR_Revision_SHIFT (12u) +#define INTC_ICCIIDR_Architecture_version_SHIFT (16u) +#define INTC_ICCIIDR_ProductID_SHIFT (20u) + +#define INTC_ICR0_NMIF_SHIFT (1u) +#define INTC_ICR0_NMIE_SHIFT (8u) +#define INTC_ICR0_NMIL_SHIFT (15u) + +#define INTC_ICR1_IRQ00S_SHIFT (0u) +#define INTC_ICR1_IRQ01S_SHIFT (1u) +#define INTC_ICR1_IRQ10S_SHIFT (2u) +#define INTC_ICR1_IRQ11S_SHIFT (3u) +#define INTC_ICR1_IRQ20S_SHIFT (4u) +#define INTC_ICR1_IRQ21S_SHIFT (5u) +#define INTC_ICR1_IRQ30S_SHIFT (6u) +#define INTC_ICR1_IRQ31S_SHIFT (7u) +#define INTC_ICR1_IRQ40S_SHIFT (8u) +#define INTC_ICR1_IRQ41S_SHIFT (9u) +#define INTC_ICR1_IRQ50S_SHIFT (10u) +#define INTC_ICR1_IRQ51S_SHIFT (11u) +#define INTC_ICR1_IRQ60S_SHIFT (12u) +#define INTC_ICR1_IRQ61S_SHIFT (13u) +#define INTC_ICR1_IRQ70S_SHIFT (14u) +#define INTC_ICR1_IRQ71S_SHIFT (15u) + +#define INTC_IRQRR_IRQ0F_SHIFT (0u) +#define INTC_IRQRR_IRQ1F_SHIFT (1u) +#define INTC_IRQRR_IRQ2F_SHIFT (2u) +#define INTC_IRQRR_IRQ3F_SHIFT (3u) +#define INTC_IRQRR_IRQ4F_SHIFT (4u) +#define INTC_IRQRR_IRQ5F_SHIFT (5u) +#define INTC_IRQRR_IRQ6F_SHIFT (6u) +#define INTC_IRQRR_IRQ7F_SHIFT (7u) + + +#endif /* INTC_IOBITMASK_H */ + +/* End of File */ diff --git a/targets/TARGET_RENESAS/TARGET_RZ_A1XX/TARGET_GR_LYCHEE/device/inc/iobitmasks/mtu2_iobitmask.h b/targets/TARGET_RENESAS/TARGET_RZ_A1XX/TARGET_GR_LYCHEE/device/inc/iobitmasks/mtu2_iobitmask.h new file mode 100644 index 0000000..eea9277 --- /dev/null +++ b/targets/TARGET_RENESAS/TARGET_RZ_A1XX/TARGET_GR_LYCHEE/device/inc/iobitmasks/mtu2_iobitmask.h @@ -0,0 +1,462 @@ +/******************************************************************************* +* DISCLAIMER +* This software is supplied by Renesas Electronics Corporation and is only +* intended for use with Renesas products. No other uses are authorized. This +* software is owned by Renesas Electronics Corporation and is protected under +* all applicable laws, including copyright laws. +* THIS SOFTWARE IS PROVIDED "AS IS" AND RENESAS MAKES NO WARRANTIES REGARDING +* THIS SOFTWARE, WHETHER EXPRESS, IMPLIED OR STATUTORY, INCLUDING BUT NOT +* LIMITED TO WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE +* AND NON-INFRINGEMENT. ALL SUCH WARRANTIES ARE EXPRESSLY DISCLAIMED. +* TO THE MAXIMUM EXTENT PERMITTED NOT PROHIBITED BY LAW, NEITHER RENESAS +* ELECTRONICS CORPORATION NOR ANY OF ITS AFFILIATED COMPANIES SHALL BE LIABLE +* FOR ANY DIRECT, INDIRECT, SPECIAL, INCIDENTAL OR CONSEQUENTIAL DAMAGES FOR +* ANY REASON RELATED TO THIS SOFTWARE, EVEN IF RENESAS OR ITS AFFILIATES HAVE +* BEEN ADVISED OF THE POSSIBILITY OF SUCH DAMAGES. +* Renesas reserves the right, without notice, to make changes to this software +* and to discontinue the availability of this software. By using this software, +* you agree to the additional terms and conditions found by accessing the +* following link: +* http://www.renesas.com/disclaimer +* Copyright (C) 2012 - 2014 Renesas Electronics Corporation. All rights reserved. +*******************************************************************************/ +/******************************************************************************* +* File Name : mtu2_iobitmask.h +* $Rev: 1138 $ +* $Date:: 2014-08-08 11:03:56 +0900#$ +* Description : MTU2 register define header +*******************************************************************************/ +#ifndef MTU2_IOBITMASK_H +#define MTU2_IOBITMASK_H + + +/* ==== Mask values for IO registers ==== */ +#define MTU2_TCR_n_TPSC (0x07u) +#define MTU2_TCR_n_CKEG (0x18u) +#define MTU2_TCR_n_CCLR (0xE0u) + +#define MTU2_TMDR_n_MD (0x0Fu) + +#define MTU2_TIOR_2_IOA (0x0Fu) +#define MTU2_TIOR_2_IOB (0xF0u) + +#define MTU2_TIER_n_TGIEA (0x01u) +#define MTU2_TIER_n_TGIEB (0x02u) +#define MTU2_TIER_n_TCIEV (0x10u) +#define MTU2_TIER_2_TCIEU (0x20u) +#define MTU2_TIER_n_TTGE (0x80u) + +#define MTU2_TSR_n_TGFA (0x01u) +#define MTU2_TSR_n_TGFB (0x02u) +#define MTU2_TSR_n_TCFV (0x10u) +#define MTU2_TSR_2_TCFU (0x20u) +#define MTU2_TSR_2_TCFD (0x80u) + +#define MTU2_TCNT_n_D (0xFFFFu) + +#define MTU2_TGRA_n_D (0xFFFFu) + +#define MTU2_TGRB_n_D (0xFFFFu) + +#define MTU2_TMDR_3_BFA (0x10u) +#define MTU2_TMDR_3_BFB (0x20u) + +#define MTU2_TMDR_4_BFA (0x10u) +#define MTU2_TMDR_4_BFB (0x20u) + +#define MTU2_TIORH_3_IOA (0x0Fu) +#define MTU2_TIORH_3_IOB (0xF0u) + +#define MTU2_TIORL_3_IOC (0x0Fu) +#define MTU2_TIORL_3_IOD (0xF0u) + +#define MTU2_TIORH_4_IOA (0x0Fu) +#define MTU2_TIORH_4_IOB (0xF0u) + +#define MTU2_TIORL_4_IOC (0x0Fu) +#define MTU2_TIORL_4_IOD (0xF0u) + +#define MTU2_TIER_3_TGIEC (0x04u) +#define MTU2_TIER_3_TGIED (0x08u) + +#define MTU2_TIER_4_TGIEC (0x04u) +#define MTU2_TIER_4_TGIED (0x08u) +#define MTU2_TIER_4_TTGE2 (0x40u) + +#define MTU2_TOER_OE3B (0x01u) +#define MTU2_TOER_OE4A (0x02u) +#define MTU2_TOER_OE4B (0x04u) +#define MTU2_TOER_OE3D (0x08u) +#define MTU2_TOER_OE4C (0x10u) +#define MTU2_TOER_OE4D (0x20u) + +#define MTU2_TGCR_UF (0x01u) +#define MTU2_TGCR_VF (0x02u) +#define MTU2_TGCR_WF (0x04u) +#define MTU2_TGCR_FB (0x08u) +#define MTU2_TGCR_P (0x10u) +#define MTU2_TGCR_N (0x20u) +#define MTU2_TGCR_BDC (0x40u) + +#define MTU2_TOCR1_OLSP (0x01u) +#define MTU2_TOCR1_OLSN (0x02u) +#define MTU2_TOCR1_TOCS (0x04u) +#define MTU2_TOCR1_TOCL (0x08u) +#define MTU2_TOCR1_PSYE (0x40u) + +#define MTU2_TOCR2_OLS1P (0x01u) +#define MTU2_TOCR2_OLS1N (0x02u) +#define MTU2_TOCR2_OLS2P (0x04u) +#define MTU2_TOCR2_OLS2N (0x08u) +#define MTU2_TOCR2_OLS3P (0x10u) +#define MTU2_TOCR2_OLS3N (0x20u) +#define MTU2_TOCR2_BF (0xC0u) + +#define MTU2_TCDR_D (0xFFFFu) + +#define MTU2_TDDR_D (0xFFFFu) + +#define MTU2_TCNTS_D (0xFFFFu) + +#define MTU2_TCBR_D (0xFFFFu) + +#define MTU2_TGRC_3_D (0xFFFFu) + +#define MTU2_TGRD_3_D (0xFFFFu) + +#define MTU2_TGRC_4_D (0xFFFFu) + +#define MTU2_TGRD_4_D (0xFFFFu) + +#define MTU2_TSR_3_TGFC (0x04u) +#define MTU2_TSR_3_TGFD (0x08u) +#define MTU2_TSR_3_TCFD (0x80u) + +#define MTU2_TSR_4_TGFC (0x04u) +#define MTU2_TSR_4_TGFD (0x08u) +#define MTU2_TSR_4_TCFD (0x80u) + +#define MTU2_TITCR_4VCOR (0x07u) +#define MTU2_TITCR_T4VEN (0x08u) +#define MTU2_TITCR_3ACOR (0x70u) +#define MTU2_TITCR_T3AEN (0x80u) + +#define MTU2_TITCNT_4VCNT (0x07u) +#define MTU2_TITCNT_3ACNT (0x70u) + +#define MTU2_TBTER_BTE (0x03u) + +#define MTU2_TDER_TDER (0x01u) + +#define MTU2_TOLBR_OLS1P (0x01u) +#define MTU2_TOLBR_OLS1N (0x02u) +#define MTU2_TOLBR_OLS2P (0x04u) +#define MTU2_TOLBR_OLS2N (0x08u) +#define MTU2_TOLBR_OLS3P (0x10u) +#define MTU2_TOLBR_OLS3N (0x20u) + +#define MTU2_TBTM_3_TTSA (0x01u) +#define MTU2_TBTM_3_TTSB (0x02u) + +#define MTU2_TBTM_4_TTSA (0x01u) +#define MTU2_TBTM_4_TTSB (0x02u) + +#define MTU2_TADCR_ITB4VE (0x0001u) +#define MTU2_TADCR_ITB3AE (0x0002u) +#define MTU2_TADCR_ITA4VE (0x0004u) +#define MTU2_TADCR_ITA3AE (0x0008u) +#define MTU2_TADCR_DT4BE (0x0010u) +#define MTU2_TADCR_UT4BE (0x0020u) +#define MTU2_TADCR_DT4AE (0x0040u) +#define MTU2_TADCR_UT4AE (0x0080u) +#define MTU2_TADCR_BF (0xC000u) + +#define MTU2_TADCORA_4_D (0xFFFFu) + +#define MTU2_TADCORB_4_D (0xFFFFu) + +#define MTU2_TADCOBRA_4_D (0xFFFFu) + +#define MTU2_TADCOBRB_4_D (0xFFFFu) + +#define MTU2_TWCR_WRE (0x01u) +#define MTU2_TWCR_CCE (0x80u) + +#define MTU2_TSTR_CST0 (0x01u) +#define MTU2_TSTR_CST1 (0x02u) +#define MTU2_TSTR_CST2 (0x04u) +#define MTU2_TSTR_CST3 (0x40u) +#define MTU2_TSTR_CST4 (0x80u) + +#define MTU2_TSYR_SYNC0 (0x01u) +#define MTU2_TSYR_SYNC1 (0x02u) +#define MTU2_TSYR_SYNC2 (0x04u) +#define MTU2_TSYR_SYNC3 (0x40u) +#define MTU2_TSYR_SYNC4 (0x80u) + +#define MTU2_TRWER_RWE (0x01u) + +#define MTU2_TMDR_0_BFA (0x10u) +#define MTU2_TMDR_0_BFB (0x20u) +#define MTU2_TMDR_0_BFE (0x40u) + +#define MTU2_TIORH_0_IOA (0x0Fu) +#define MTU2_TIORH_0_IOB (0xF0u) + +#define MTU2_TIORL_0_IOC (0x0Fu) +#define MTU2_TIORL_0_IOD (0xF0u) + +#define MTU2_TIER_0_TGIEC (0x04u) +#define MTU2_TIER_0_TGIED (0x08u) + +#define MTU2_TSR_0_TGFC (0x04u) +#define MTU2_TSR_0_TGFD (0x08u) + +#define MTU2_TGRC_0_D (0xFFFFu) + +#define MTU2_TGRD_0_D (0xFFFFu) + +#define MTU2_TGRE_0_D (0xFFFFu) + +#define MTU2_TGRF_0_D (0xFFFFu) + +#define MTU2_TIER2_0_TGIEE (0x01u) +#define MTU2_TIER2_0_TGIEF (0x02u) + +#define MTU2_TSR2_0_TGFE (0x01u) +#define MTU2_TSR2_0_TGFF (0x02u) + +#define MTU2_TBTM_0_TTSA (0x01u) +#define MTU2_TBTM_0_TTSB (0x02u) +#define MTU2_TBTM_0_TTSE (0x04u) + +#define MTU2_TIOR_1_IOA (0x0Fu) +#define MTU2_TIOR_1_IOB (0xF0u) + +#define MTU2_TIER_1_TCIEU (0x20u) + +#define MTU2_TSR_1_TCFU (0x20u) +#define MTU2_TSR_1_TCFD (0x80u) + +#define MTU2_TICCR_I1AE (0x01u) +#define MTU2_TICCR_I1BE (0x02u) +#define MTU2_TICCR_I2AE (0x04u) +#define MTU2_TICCR_I2BE (0x08u) + + +/* ==== Shift values for IO registers ==== */ +#define MTU2_TCR_n_TPSC_SHIFT (0u) +#define MTU2_TCR_n_CKEG_SHIFT (3u) +#define MTU2_TCR_n_CCLR_SHIFT (5u) + +#define MTU2_TMDR_n_MD_SHIFT (0u) + +#define MTU2_TIOR_2_IOA_SHIFT (0u) +#define MTU2_TIOR_2_IOB_SHIFT (4u) + +#define MTU2_TIER_n_TGIEA_SHIFT (0u) +#define MTU2_TIER_n_TGIEB_SHIFT (1u) +#define MTU2_TIER_n_TCIEV_SHIFT (4u) +#define MTU2_TIER_2_TCIEU_SHIFT (5u) +#define MTU2_TIER_n_TTGE_SHIFT (7u) + +#define MTU2_TSR_n_TGFA_SHIFT (0u) +#define MTU2_TSR_n_TGFB_SHIFT (1u) +#define MTU2_TSR_n_TCFV_SHIFT (4u) +#define MTU2_TSR_2_TCFU_SHIFT (5u) +#define MTU2_TSR_2_TCFD_SHIFT (7u) + +#define MTU2_TCNT_n_D_SHIFT (0u) + +#define MTU2_TGRA_n_D_SHIFT (0u) + +#define MTU2_TGRB_n_D_SHIFT (0u) + +#define MTU2_TMDR_3_BFA_SHIFT (4u) +#define MTU2_TMDR_3_BFB_SHIFT (5u) + +#define MTU2_TMDR_4_BFA_SHIFT (4u) +#define MTU2_TMDR_4_BFB_SHIFT (5u) + +#define MTU2_TIORH_3_IOA_SHIFT (0u) +#define MTU2_TIORH_3_IOB_SHIFT (4u) + +#define MTU2_TIORL_3_IOC_SHIFT (0u) +#define MTU2_TIORL_3_IOD_SHIFT (4u) + +#define MTU2_TIORH_4_IOA_SHIFT (0u) +#define MTU2_TIORH_4_IOB_SHIFT (4u) + +#define MTU2_TIORL_4_IOC_SHIFT (0u) +#define MTU2_TIORL_4_IOD_SHIFT (4u) + +#define MTU2_TIER_3_TGIEC_SHIFT (2u) +#define MTU2_TIER_3_TGIED_SHIFT (3u) + +#define MTU2_TIER_4_TGIEC_SHIFT (2u) +#define MTU2_TIER_4_TGIED_SHIFT (3u) +#define MTU2_TIER_4_TTGE2_SHIFT (6u) + +#define MTU2_TOER_OE3B_SHIFT (0u) +#define MTU2_TOER_OE4A_SHIFT (1u) +#define MTU2_TOER_OE4B_SHIFT (2u) +#define MTU2_TOER_OE3D_SHIFT (3u) +#define MTU2_TOER_OE4C_SHIFT (4u) +#define MTU2_TOER_OE4D_SHIFT (5u) + +#define MTU2_TGCR_UF_SHIFT (0u) +#define MTU2_TGCR_VF_SHIFT (1u) +#define MTU2_TGCR_WF_SHIFT (2u) +#define MTU2_TGCR_FB_SHIFT (3u) +#define MTU2_TGCR_P_SHIFT (4u) +#define MTU2_TGCR_N_SHIFT (5u) +#define MTU2_TGCR_BDC_SHIFT (6u) + +#define MTU2_TOCR1_OLSP_SHIFT (0u) +#define MTU2_TOCR1_OLSN_SHIFT (1u) +#define MTU2_TOCR1_TOCS_SHIFT (2u) +#define MTU2_TOCR1_TOCL_SHIFT (3u) +#define MTU2_TOCR1_PSYE_SHIFT (6u) + +#define MTU2_TOCR2_OLS1P_SHIFT (0u) +#define MTU2_TOCR2_OLS1N_SHIFT (1u) +#define MTU2_TOCR2_OLS2P_SHIFT (2u) +#define MTU2_TOCR2_OLS2N_SHIFT (3u) +#define MTU2_TOCR2_OLS3P_SHIFT (4u) +#define MTU2_TOCR2_OLS3N_SHIFT (5u) +#define MTU2_TOCR2_BF_SHIFT (6u) + +#define MTU2_TCDR_D_SHIFT (0u) + +#define MTU2_TDDR_D_SHIFT (0u) + +#define MTU2_TCNTS_D_SHIFT (0u) + +#define MTU2_TCBR_D_SHIFT (0u) + +#define MTU2_TGRC_3_D_SHIFT (0u) + +#define MTU2_TGRD_3_D_SHIFT (0u) + +#define MTU2_TGRC_4_D_SHIFT (0u) + +#define MTU2_TGRD_4_D_SHIFT (0u) + +#define MTU2_TSR_3_TGFC_SHIFT (2u) +#define MTU2_TSR_3_TGFD_SHIFT (3u) +#define MTU2_TSR_3_TCFD_SHIFT (7u) + +#define MTU2_TSR_4_TGFC_SHIFT (2u) +#define MTU2_TSR_4_TGFD_SHIFT (3u) +#define MTU2_TSR_4_TCFD_SHIFT (7u) + +#define MTU2_TITCR_4VCOR_SHIFT (0u) +#define MTU2_TITCR_T4VEN_SHIFT (3u) +#define MTU2_TITCR_3ACOR_SHIFT (4u) +#define MTU2_TITCR_T3AEN_SHIFT (7u) + +#define MTU2_TITCNT_4VCNT_SHIFT (0u) +#define MTU2_TITCNT_3ACNT_SHIFT (4u) + +#define MTU2_TBTER_BTE_SHIFT (0u) + +#define MTU2_TDER_TDER_SHIFT (0u) + +#define MTU2_TOLBR_OLS1P_SHIFT (0u) +#define MTU2_TOLBR_OLS1N_SHIFT (1u) +#define MTU2_TOLBR_OLS2P_SHIFT (2u) +#define MTU2_TOLBR_OLS2N_SHIFT (3u) +#define MTU2_TOLBR_OLS3P_SHIFT (4u) +#define MTU2_TOLBR_OLS3N_SHIFT (5u) + +#define MTU2_TBTM_3_TTSA_SHIFT (0u) +#define MTU2_TBTM_3_TTSB_SHIFT (1u) + +#define MTU2_TBTM_4_TTSA_SHIFT (0u) +#define MTU2_TBTM_4_TTSB_SHIFT (1u) + +#define MTU2_TADCR_ITB4VE_SHIFT (0u) +#define MTU2_TADCR_ITB3AE_SHIFT (1u) +#define MTU2_TADCR_ITA4VE_SHIFT (2u) +#define MTU2_TADCR_ITA3AE_SHIFT (3u) +#define MTU2_TADCR_DT4BE_SHIFT (4u) +#define MTU2_TADCR_UT4BE_SHIFT (5u) +#define MTU2_TADCR_DT4AE_SHIFT (6u) +#define MTU2_TADCR_UT4AE_SHIFT (7u) +#define MTU2_TADCR_BF_SHIFT (14u) + +#define MTU2_TADCORA_4_D_SHIFT (0u) + +#define MTU2_TADCORB_4_D_SHIFT (0u) + +#define MTU2_TADCOBRA_4_D_SHIFT (0u) + +#define MTU2_TADCOBRB_4_D_SHIFT (0u) + +#define MTU2_TWCR_WRE_SHIFT (0u) +#define MTU2_TWCR_CCE_SHIFT (7u) + +#define MTU2_TSTR_CST0_SHIFT (0u) +#define MTU2_TSTR_CST1_SHIFT (1u) +#define MTU2_TSTR_CST2_SHIFT (2u) +#define MTU2_TSTR_CST3_SHIFT (6u) +#define MTU2_TSTR_CST4_SHIFT (7u) + +#define MTU2_TSYR_SYNC0_SHIFT (0u) +#define MTU2_TSYR_SYNC1_SHIFT (1u) +#define MTU2_TSYR_SYNC2_SHIFT (2u) +#define MTU2_TSYR_SYNC3_SHIFT (6u) +#define MTU2_TSYR_SYNC4_SHIFT (7u) + +#define MTU2_TRWER_RWE_SHIFT (0u) + +#define MTU2_TMDR_0_BFA_SHIFT (4u) +#define MTU2_TMDR_0_BFB_SHIFT (5u) +#define MTU2_TMDR_0_BFE_SHIFT (6u) + +#define MTU2_TIORH_0_IOA_SHIFT (0u) +#define MTU2_TIORH_0_IOB_SHIFT (4u) + +#define MTU2_TIORL_0_IOC_SHIFT (0u) +#define MTU2_TIORL_0_IOD_SHIFT (4u) + +#define MTU2_TIER_0_TGIEC_SHIFT (2u) +#define MTU2_TIER_0_TGIED_SHIFT (3u) + +#define MTU2_TSR_0_TGFC_SHIFT (2u) +#define MTU2_TSR_0_TGFD_SHIFT (3u) + +#define MTU2_TGRC_0_D_SHIFT (0u) + +#define MTU2_TGRD_0_D_SHIFT (0u) + +#define MTU2_TGRE_0_D_SHIFT (0u) + +#define MTU2_TGRF_0_D_SHIFT (0u) + +#define MTU2_TIER2_0_TGIEE_SHIFT (0u) +#define MTU2_TIER2_0_TGIEF_SHIFT (1u) + +#define MTU2_TSR2_0_TGFE_SHIFT (0u) +#define MTU2_TSR2_0_TGFF_SHIFT (1u) + +#define MTU2_TBTM_0_TTSA_SHIFT (0u) +#define MTU2_TBTM_0_TTSB_SHIFT (1u) +#define MTU2_TBTM_0_TTSE_SHIFT (2u) + +#define MTU2_TIOR_1_IOA_SHIFT (0u) +#define MTU2_TIOR_1_IOB_SHIFT (4u) + +#define MTU2_TIER_1_TCIEU_SHIFT (5u) + +#define MTU2_TSR_1_TCFU_SHIFT (5u) +#define MTU2_TSR_1_TCFD_SHIFT (7u) + +#define MTU2_TICCR_I1AE_SHIFT (0u) +#define MTU2_TICCR_I1BE_SHIFT (1u) +#define MTU2_TICCR_I2AE_SHIFT (2u) +#define MTU2_TICCR_I2BE_SHIFT (3u) + + +#endif /* MTU2_IOBITMASK_H */ +/* End of File */ diff --git a/targets/TARGET_RENESAS/TARGET_RZ_A1XX/TARGET_GR_LYCHEE/device/inc/iobitmasks/ostm_iobitmask.h b/targets/TARGET_RENESAS/TARGET_RZ_A1XX/TARGET_GR_LYCHEE/device/inc/iobitmasks/ostm_iobitmask.h new file mode 100644 index 0000000..418bca7 --- /dev/null +++ b/targets/TARGET_RENESAS/TARGET_RZ_A1XX/TARGET_GR_LYCHEE/device/inc/iobitmasks/ostm_iobitmask.h @@ -0,0 +1,123 @@ +/******************************************************************************* +* DISCLAIMER +* This software is supplied by Renesas Electronics Corporation and is only +* intended for use with Renesas products. No other uses are authorized. This +* software is owned by Renesas Electronics Corporation and is protected under +* all applicable laws, including copyright laws. +* THIS SOFTWARE IS PROVIDED "AS IS" AND RENESAS MAKES NO WARRANTIES REGARDING +* THIS SOFTWARE, WHETHER EXPRESS, IMPLIED OR STATUTORY, INCLUDING BUT NOT +* LIMITED TO WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE +* AND NON-INFRINGEMENT. ALL SUCH WARRANTIES ARE EXPRESSLY DISCLAIMED. +* TO THE MAXIMUM EXTENT PERMITTED NOT PROHIBITED BY LAW, NEITHER RENESAS +* ELECTRONICS CORPORATION NOR ANY OF ITS AFFILIATED COMPANIES SHALL BE LIABLE +* FOR ANY DIRECT, INDIRECT, SPECIAL, INCIDENTAL OR CONSEQUENTIAL DAMAGES FOR +* ANY REASON RELATED TO THIS SOFTWARE, EVEN IF RENESAS OR ITS AFFILIATES HAVE +* BEEN ADVISED OF THE POSSIBILITY OF SUCH DAMAGES. +* Renesas reserves the right, without notice, to make changes to this software +* and to discontinue the availability of this software. By using this software, +* you agree to the additional terms and conditions found by accessing the +* following link: +* http://www.renesas.com/disclaimer +* Copyright (C) 2012 - 2014 Renesas Electronics Corporation. All rights reserved. +*******************************************************************************/ +/******************************************************************************* +* File Name : ostm_iobitmask.h +* $Rev: 1115 $ +* $Date:: 2014-07-09 15:35:02 +0900#$ +* Description : OSTM register define header +*******************************************************************************/ +#ifndef OSTM_IOBITMASK_H +#define OSTM_IOBITMASK_H + + +/* ==== Mask values for IO registers ==== */ +/* ---- OSTM0 ---- */ +#define OSTM0_OSTMnCMP_OSTMnCMP (0xFFFFFFFFuL) + +#define OSTM0_OSTMnCNT_OSTMnCNT (0xFFFFFFFFuL) + +#define OSTM0_OSTMnTE_OSTMnTE (0x01u) + +#define OSTM0_OSTMnTS_OSTMnTS (0x01u) + +#define OSTM0_OSTMnTT_OSTMnTT (0x01u) + +#define OSTM0_OSTMnCTL_MD0 (0x00000001uL) +#define OSTM0_OSTMnCTL_MD1 (0x00000002uL) + +/* ---- OSTM1 ---- */ +#define OSTM1_OSTMnCMP_OSTMnCMP (0xFFFFFFFFuL) + +#define OSTM1_OSTMnCNT_OSTMnCNT (0xFFFFFFFFuL) + +#define OSTM1_OSTMnTE_OSTMnTE (0x01u) + +#define OSTM1_OSTMnTS_OSTMnTS (0x01u) + +#define OSTM1_OSTMnTT_OSTMnTT (0x01u) + +#define OSTM1_OSTMnCTL_MD0 (0x00000001uL) +#define OSTM1_OSTMnCTL_MD1 (0x00000002uL) + +/* ---- OSTMn ---- */ +#define OSTMn_OSTMnCMP_OSTMnCMP (0xFFFFFFFFuL) + +#define OSTMn_OSTMnCNT_OSTMnCNT (0xFFFFFFFFuL) + +#define OSTMn_OSTMnTE_OSTMnTE (0x01u) + +#define OSTMn_OSTMnTS_OSTMnTS (0x01u) + +#define OSTMn_OSTMnTT_OSTMnTT (0x01u) + +#define OSTMn_OSTMnCTL_MD0 (0x00000001uL) +#define OSTMn_OSTMnCTL_MD1 (0x00000002uL) + + +/* ==== Shift values for IO registers ==== */ +/* ---- OSTM0 ---- */ +#define OSTM0_OSTMnCMP_OSTMnCMP_SHIFT (0u) + +#define OSTM0_OSTMnCNT_OSTMnCNT_SHIFT (0u) + +#define OSTM0_OSTMnTE_OSTMnTE_SHIFT (0u) + +#define OSTM0_OSTMnTS_OSTMnTS_SHIFT (0u) + +#define OSTM0_OSTMnTT_OSTMnTT_SHIFT (0u) + +#define OSTM0_OSTMnCTL_MD0_SHIFT (0u) +#define OSTM0_OSTMnCTL_MD1_SHIFT (1u) + +/* ---- OSTM1 ---- */ +#define OSTM1_OSTMnCMP_OSTMnCMP_SHIFT (0u) + +#define OSTM1_OSTMnCNT_OSTMnCNT_SHIFT (0u) + +#define OSTM1_OSTMnTE_OSTMnTE_SHIFT (0u) + +#define OSTM1_OSTMnTS_OSTMnTS_SHIFT (0u) + +#define OSTM1_OSTMnTT_OSTMnTT_SHIFT (0u) + +#define OSTM1_OSTMnCTL_MD0_SHIFT (0u) +#define OSTM1_OSTMnCTL_MD1_SHIFT (1u) + +/* ---- OSTMn ---- */ +#define OSTMn_OSTMnCMP_OSTMnCMP_SHIFT (0u) + +#define OSTMn_OSTMnCNT_OSTMnCNT_SHIFT (0u) + +#define OSTMn_OSTMnTE_OSTMnTE_SHIFT (0u) + +#define OSTMn_OSTMnTS_OSTMnTS_SHIFT (0u) + +#define OSTMn_OSTMnTT_OSTMnTT_SHIFT (0u) + +#define OSTMn_OSTMnCTL_MD0_SHIFT (0u) +#define OSTMn_OSTMnCTL_MD1_SHIFT (1u) + + +#endif /* OSTM_IOBITMASK_H */ + +/* End of File */ diff --git a/targets/TARGET_RENESAS/TARGET_RZ_A1XX/TARGET_GR_LYCHEE/device/inc/iobitmasks/riic_iobitmask.h b/targets/TARGET_RENESAS/TARGET_RZ_A1XX/TARGET_GR_LYCHEE/device/inc/iobitmasks/riic_iobitmask.h new file mode 100644 index 0000000..8a2a871 --- /dev/null +++ b/targets/TARGET_RENESAS/TARGET_RZ_A1XX/TARGET_GR_LYCHEE/device/inc/iobitmasks/riic_iobitmask.h @@ -0,0 +1,231 @@ +/******************************************************************************* +* DISCLAIMER +* This software is supplied by Renesas Electronics Corporation and is only +* intended for use with Renesas products. No other uses are authorized. This +* software is owned by Renesas Electronics Corporation and is protected under +* all applicable laws, including copyright laws. +* THIS SOFTWARE IS PROVIDED "AS IS" AND RENESAS MAKES NO WARRANTIES REGARDING +* THIS SOFTWARE, WHETHER EXPRESS, IMPLIED OR STATUTORY, INCLUDING BUT NOT +* LIMITED TO WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE +* AND NON-INFRINGEMENT. ALL SUCH WARRANTIES ARE EXPRESSLY DISCLAIMED. +* TO THE MAXIMUM EXTENT PERMITTED NOT PROHIBITED BY LAW, NEITHER RENESAS +* ELECTRONICS CORPORATION NOR ANY OF ITS AFFILIATED COMPANIES SHALL BE LIABLE +* FOR ANY DIRECT, INDIRECT, SPECIAL, INCIDENTAL OR CONSEQUENTIAL DAMAGES FOR +* ANY REASON RELATED TO THIS SOFTWARE, EVEN IF RENESAS OR ITS AFFILIATES HAVE +* BEEN ADVISED OF THE POSSIBILITY OF SUCH DAMAGES. +* Renesas reserves the right, without notice, to make changes to this software +* and to discontinue the availability of this software. By using this software, +* you agree to the additional terms and conditions found by accessing the +* following link: +* http://www.renesas.com/disclaimer +* Copyright (C) 2012 - 2014 Renesas Electronics Corporation. All rights reserved. +*******************************************************************************/ +/******************************************************************************* +* File Name : riic_iobitmask.h +* $Rev: 1114 $ +* $Date:: 2014-07-09 14:56:39 +0900#$ +* Description : RIIC register define header +*******************************************************************************/ +#ifndef RIIC_IOBITMASK_H +#define RIIC_IOBITMASK_H + + +/* ==== Mask values for IO registers ==== */ +#define RIICn_RIICnCR1_SDAI (0x01u) +#define RIICn_RIICnCR1_SCLI (0x02u) +#define RIICn_RIICnCR1_SDAO (0x04u) +#define RIICn_RIICnCR1_SCLO (0x08u) +#define RIICn_RIICnCR1_SOWP (0x10u) +#define RIICn_RIICnCR1_CLO (0x20u) +#define RIICn_RIICnCR1_IICRST (0x40u) +#define RIICn_RIICnCR1_ICE (0x80u) + +#define RIICn_RIICnCR2_ST (0x02u) +#define RIICn_RIICnCR2_RS (0x04u) +#define RIICn_RIICnCR2_SP (0x08u) +#define RIICn_RIICnCR2_TRS (0x20u) +#define RIICn_RIICnCR2_MST (0x40u) +#define RIICn_RIICnCR2_BBSY (0x80u) + +#define RIICn_RIICnMR1_BC (0x07u) +#define RIICn_RIICnMR1_BCWP (0x08u) +#define RIICn_RIICnMR1_CKS (0x70u) +#define RIICn_RIICnMR1_MTWP (0x80u) + +#define RIICn_RIICnMR2_TMOS (0x01u) +#define RIICn_RIICnMR2_TMOL (0x02u) +#define RIICn_RIICnMR2_TMOH (0x04u) +#define RIICn_RIICnMR2_SDDL (0x70u) +#define RIICn_RIICnMR2_DLCS (0x80u) + +#define RIICn_RIICnMR3_NF (0x03u) +#define RIICn_RIICnMR3_ACKBR (0x04u) +#define RIICn_RIICnMR3_ACKBT (0x08u) +#define RIICn_RIICnMR3_ACKWP (0x10u) +#define RIICn_RIICnMR3_RDRFS (0x20u) +#define RIICn_RIICnMR3_WAIT (0x40u) +#define RIICn_RIICnMR3_SMBS (0x80u) + +#define RIICn_RIICnFER_TMOE (0x01u) +#define RIICn_RIICnFER_MALE (0x02u) +#define RIICn_RIICnFER_NALE (0x04u) +#define RIICn_RIICnFER_SALE (0x08u) +#define RIICn_RIICnFER_NACKE (0x10u) +#define RIICn_RIICnFER_NFE (0x20u) +#define RIICn_RIICnFER_SCLE (0x40u) +#define RIICn_RIICnFER_FMPE (0x80u) + +#define RIICn_RIICnSER_SAR0E (0x01u) +#define RIICn_RIICnSER_SAR1E (0x02u) +#define RIICn_RIICnSER_SAR2E (0x04u) +#define RIICn_RIICnSER_GCAE (0x08u) +#define RIICn_RIICnSER_DIDE (0x20u) +#define RIICn_RIICnSER_HOAE (0x80u) + +#define RIICn_RIICnIER_TMOIE (0x01u) +#define RIICn_RIICnIER_ALIE (0x02u) +#define RIICn_RIICnIER_STIE (0x04u) +#define RIICn_RIICnIER_SPIE (0x08u) +#define RIICn_RIICnIER_NAKIE (0x10u) +#define RIICn_RIICnIER_RIE (0x20u) +#define RIICn_RIICnIER_TEIE (0x40u) +#define RIICn_RIICnIER_TIE (0x80u) + +#define RIICn_RIICnSR1_AAS0 (0x01u) +#define RIICn_RIICnSR1_AAS1 (0x02u) +#define RIICn_RIICnSR1_AAS2 (0x04u) +#define RIICn_RIICnSR1_GCA (0x08u) +#define RIICn_RIICnSR1_DID (0x20u) +#define RIICn_RIICnSR1_HOA (0x80u) + +#define RIICn_RIICnSR2_TMOF (0x01u) +#define RIICn_RIICnSR2_AL (0x02u) +#define RIICn_RIICnSR2_START (0x04u) +#define RIICn_RIICnSR2_STOP (0x08u) +#define RIICn_RIICnSR2_NACKF (0x10u) +#define RIICn_RIICnSR2_RDRF (0x20u) +#define RIICn_RIICnSR2_TEND (0x40u) +#define RIICn_RIICnSR2_TDRE (0x80u) + +#define RIICn_RIICnSAR0_SVA0 (0x0001u) +#define RIICn_RIICnSAR0_SVA (0x03FEu) +#define RIICn_RIICnSAR0_FSy (0x8000u) + +#define RIICn_RIICnSAR1_SVA0 (0x0001u) +#define RIICn_RIICnSAR1_SVA (0x03FEu) +#define RIICn_RIICnSAR1_FSy (0x8000u) + +#define RIICn_RIICnSAR2_SVA0 (0x0001u) +#define RIICn_RIICnSAR2_SVA (0x03FEu) +#define RIICn_RIICnSAR2_FSy (0x8000u) + +#define RIICn_RIICnBRL_BRL (0x1Fu) + +#define RIICn_RIICnBRH_BRH (0x1Fu) + +#define RIICn_RIICnDRT_DRT (0xFFu) + +#define RIICn_RIICnDRR_DRR (0xFFu) + + +/* ==== Shift values for IO registers ==== */ +#define RIICn_RIICnCR1_SDAI_SHIFT (0u) +#define RIICn_RIICnCR1_SCLI_SHIFT (1u) +#define RIICn_RIICnCR1_SDAO_SHIFT (2u) +#define RIICn_RIICnCR1_SCLO_SHIFT (3u) +#define RIICn_RIICnCR1_SOWP_SHIFT (4u) +#define RIICn_RIICnCR1_CLO_SHIFT (5u) +#define RIICn_RIICnCR1_IICRST_SHIFT (6u) +#define RIICn_RIICnCR1_ICE_SHIFT (7u) + +#define RIICn_RIICnCR2_ST_SHIFT (1u) +#define RIICn_RIICnCR2_RS_SHIFT (2u) +#define RIICn_RIICnCR2_SP_SHIFT (3u) +#define RIICn_RIICnCR2_TRS_SHIFT (5u) +#define RIICn_RIICnCR2_MST_SHIFT (6u) +#define RIICn_RIICnCR2_BBSY_SHIFT (7u) + +#define RIICn_RIICnMR1_BC_SHIFT (0u) +#define RIICn_RIICnMR1_BCWP_SHIFT (3u) +#define RIICn_RIICnMR1_CKS_SHIFT (4u) +#define RIICn_RIICnMR1_MTWP_SHIFT (7u) + +#define RIICn_RIICnMR2_TMOS_SHIFT (0u) +#define RIICn_RIICnMR2_TMOL_SHIFT (1u) +#define RIICn_RIICnMR2_TMOH_SHIFT (2u) +#define RIICn_RIICnMR2_SDDL_SHIFT (4u) +#define RIICn_RIICnMR2_DLCS_SHIFT (7u) + +#define RIICn_RIICnMR3_NF_SHIFT (0u) +#define RIICn_RIICnMR3_ACKBR_SHIFT (2u) +#define RIICn_RIICnMR3_ACKBT_SHIFT (3u) +#define RIICn_RIICnMR3_ACKWP_SHIFT (4u) +#define RIICn_RIICnMR3_RDRFS_SHIFT (5u) +#define RIICn_RIICnMR3_WAIT_SHIFT (6u) +#define RIICn_RIICnMR3_SMBS_SHIFT (7u) + +#define RIICn_RIICnFER_TMOE_SHIFT (0u) +#define RIICn_RIICnFER_MALE_SHIFT (1u) +#define RIICn_RIICnFER_NALE_SHIFT (2u) +#define RIICn_RIICnFER_SALE_SHIFT (3u) +#define RIICn_RIICnFER_NACKE_SHIFT (4u) +#define RIICn_RIICnFER_NFE_SHIFT (5u) +#define RIICn_RIICnFER_SCLE_SHIFT (6u) +#define RIICn_RIICnFER_FMPE_SHIFT (7u) + +#define RIICn_RIICnSER_SAR0E_SHIFT (0u) +#define RIICn_RIICnSER_SAR1E_SHIFT (1u) +#define RIICn_RIICnSER_SAR2E_SHIFT (2u) +#define RIICn_RIICnSER_GCAE_SHIFT (3u) +#define RIICn_RIICnSER_DIDE_SHIFT (5u) +#define RIICn_RIICnSER_HOAE_SHIFT (7u) + +#define RIICn_RIICnIER_TMOIE_SHIFT (0u) +#define RIICn_RIICnIER_ALIE_SHIFT (1u) +#define RIICn_RIICnIER_STIE_SHIFT (2u) +#define RIICn_RIICnIER_SPIE_SHIFT (3u) +#define RIICn_RIICnIER_NAKIE_SHIFT (4u) +#define RIICn_RIICnIER_RIE_SHIFT (5u) +#define RIICn_RIICnIER_TEIE_SHIFT (6u) +#define RIICn_RIICnIER_TIE_SHIFT (7u) + +#define RIICn_RIICnSR1_AAS0_SHIFT (0u) +#define RIICn_RIICnSR1_AAS1_SHIFT (1u) +#define RIICn_RIICnSR1_AAS2_SHIFT (2u) +#define RIICn_RIICnSR1_GCA_SHIFT (3u) +#define RIICn_RIICnSR1_DID_SHIFT (5u) +#define RIICn_RIICnSR1_HOA_SHIFT (7u) + +#define RIICn_RIICnSR2_TMOF_SHIFT (0u) +#define RIICn_RIICnSR2_AL_SHIFT (1u) +#define RIICn_RIICnSR2_START_SHIFT (2u) +#define RIICn_RIICnSR2_STOP_SHIFT (3u) +#define RIICn_RIICnSR2_NACKF_SHIFT (4u) +#define RIICn_RIICnSR2_RDRF_SHIFT (5u) +#define RIICn_RIICnSR2_TEND_SHIFT (6u) +#define RIICn_RIICnSR2_TDRE_SHIFT (7u) + +#define RIICn_RIICnSAR0_SVA0_SHIFT (0u) +#define RIICn_RIICnSAR0_SVA_SHIFT (1u) +#define RIICn_RIICnSAR0_FSy_SHIFT (15u) + +#define RIICn_RIICnSAR1_SVA0_SHIFT (0u) +#define RIICn_RIICnSAR1_SVA_SHIFT (1u) +#define RIICn_RIICnSAR1_FSy_SHIFT (15u) + +#define RIICn_RIICnSAR2_SVA0_SHIFT (0u) +#define RIICn_RIICnSAR2_SVA_SHIFT (1u) +#define RIICn_RIICnSAR2_FSy_SHIFT (15u) + +#define RIICn_RIICnBRL_BRL_SHIFT (0u) + +#define RIICn_RIICnBRH_BRH_SHIFT (0u) + +#define RIICn_RIICnDRT_DRT_SHIFT (0u) + +#define RIICn_RIICnDRR_DRR_SHIFT (0u) + + +#endif /* RIIC_IOBITMASK_H */ + +/* End of File */ diff --git a/targets/TARGET_RENESAS/TARGET_RZ_A1XX/TARGET_GR_LYCHEE/device/inc/iobitmasks/rspi_iobitmask.h b/targets/TARGET_RENESAS/TARGET_RZ_A1XX/TARGET_GR_LYCHEE/device/inc/iobitmasks/rspi_iobitmask.h new file mode 100644 index 0000000..ca1ba2e --- /dev/null +++ b/targets/TARGET_RENESAS/TARGET_RZ_A1XX/TARGET_GR_LYCHEE/device/inc/iobitmasks/rspi_iobitmask.h @@ -0,0 +1,215 @@ +/******************************************************************************* +* DISCLAIMER +* This software is supplied by Renesas Electronics Corporation and is only +* intended for use with Renesas products. No other uses are authorized. This +* software is owned by Renesas Electronics Corporation and is protected under +* all applicable laws, including copyright laws. +* THIS SOFTWARE IS PROVIDED "AS IS" AND RENESAS MAKES NO WARRANTIES REGARDING +* THIS SOFTWARE, WHETHER EXPRESS, IMPLIED OR STATUTORY, INCLUDING BUT NOT +* LIMITED TO WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE +* AND NON-INFRINGEMENT. ALL SUCH WARRANTIES ARE EXPRESSLY DISCLAIMED. +* TO THE MAXIMUM EXTENT PERMITTED NOT PROHIBITED BY LAW, NEITHER RENESAS +* ELECTRONICS CORPORATION NOR ANY OF ITS AFFILIATED COMPANIES SHALL BE LIABLE +* FOR ANY DIRECT, INDIRECT, SPECIAL, INCIDENTAL OR CONSEQUENTIAL DAMAGES FOR +* ANY REASON RELATED TO THIS SOFTWARE, EVEN IF RENESAS OR ITS AFFILIATES HAVE +* BEEN ADVISED OF THE POSSIBILITY OF SUCH DAMAGES. +* Renesas reserves the right, without notice, to make changes to this software +* and to discontinue the availability of this software. By using this software, +* you agree to the additional terms and conditions found by accessing the +* following link: +* http://www.renesas.com/disclaimer +* Copyright (C) 2012 - 2014 Renesas Electronics Corporation. All rights reserved. +*******************************************************************************/ +/******************************************************************************* +* File Name : rspi_iobitmask.h +* $Rev: 1114 $ +* $Date:: 2014-07-09 14:56:39 +0900#$ +* Description : Renesas Serial Peripheral Interface register define header +*******************************************************************************/ +#ifndef RSPI_IOBITMASK_H +#define RSPI_IOBITMASK_H + + +/* ==== Mask values for IO registers ==== */ +#define RSPIn_SPCR_MODFEN (0x04u) +#define RSPIn_SPCR_MSTR (0x08u) +#define RSPIn_SPCR_SPEIE (0x10u) +#define RSPIn_SPCR_SPTIE (0x20u) +#define RSPIn_SPCR_SPE (0x40u) +#define RSPIn_SPCR_SPRIE (0x80u) + +#define RSPIn_SSLP_SSL0P (0x01u) + +#define RSPIn_SPPCR_SPLP (0x01u) +#define RSPIn_SPPCR_MOIFV (0x10u) +#define RSPIn_SPPCR_MOIFE (0x20u) + +#define RSPIn_SPSR_OVRF (0x01u) +#define RSPIn_SPSR_MODF (0x04u) +#define RSPIn_SPSR_SPTEF (0x20u) +#define RSPIn_SPSR_TEND (0x40u) +#define RSPIn_SPSR_SPRF (0x80u) + +#define RSPIn_SPDR_UINT32 (0xFFFFFFFFuL) + +#define RSPIn_SPDR_UINT16 (0xFFFFu) + +#define RSPIn_SPDR_UINT8 (0xFFu) + +#define RSPIn_SPSCR_SPSLN (0x03u) + +#define RSPIn_SPSSR_SPCP (0x03u) + +#define RSPIn_SPBR_SPR (0xFFu) + +#define RSPIn_SPDCR_SPLW (0x60u) +#define RSPIn_SPDCR_TXDMY (0x80u) + +#define RSPIn_SPCKD_SCKDL (0x07u) + +#define RSPIn_SSLND_SLNDL (0x07u) + +#define RSPIn_SPND_SPNDL (0x07u) + +#define RSPIn_SPCMD0_CPHA (0x0001u) +#define RSPIn_SPCMD0_CPOL (0x0002u) +#define RSPIn_SPCMD0_BRDV (0x000Cu) +#define RSPIn_SPCMD0_SSLKP (0x0080u) +#define RSPIn_SPCMD0_SPB (0x0F00u) +#define RSPIn_SPCMD0_LSBF (0x1000u) +#define RSPIn_SPCMD0_SPNDEN (0x2000u) +#define RSPIn_SPCMD0_SLNDEN (0x4000u) +#define RSPIn_SPCMD0_SCKDEN (0x8000u) + +#define RSPIn_SPCMD1_CPHA (0x0001u) +#define RSPIn_SPCMD1_CPOL (0x0002u) +#define RSPIn_SPCMD1_BRDV (0x000Cu) +#define RSPIn_SPCMD1_SSLKP (0x0080u) +#define RSPIn_SPCMD1_SPB (0x0F00u) +#define RSPIn_SPCMD1_LSBF (0x1000u) +#define RSPIn_SPCMD1_SPNDEN (0x2000u) +#define RSPIn_SPCMD1_SLNDEN (0x4000u) +#define RSPIn_SPCMD1_SCKDEN (0x8000u) + +#define RSPIn_SPCMD2_CPHA (0x0001u) +#define RSPIn_SPCMD2_CPOL (0x0002u) +#define RSPIn_SPCMD2_BRDV (0x000Cu) +#define RSPIn_SPCMD2_SSLKP (0x0080u) +#define RSPIn_SPCMD2_SPB (0x0F00u) +#define RSPIn_SPCMD2_LSBF (0x1000u) +#define RSPIn_SPCMD2_SPNDEN (0x2000u) +#define RSPIn_SPCMD2_SLNDEN (0x4000u) +#define RSPIn_SPCMD2_SCKDEN (0x8000u) + +#define RSPIn_SPCMD3_CPHA (0x0001u) +#define RSPIn_SPCMD3_CPOL (0x0002u) +#define RSPIn_SPCMD3_BRDV (0x000Cu) +#define RSPIn_SPCMD3_SSLKP (0x0080u) +#define RSPIn_SPCMD3_SPB (0x0F00u) +#define RSPIn_SPCMD3_LSBF (0x1000u) +#define RSPIn_SPCMD3_SPNDEN (0x2000u) +#define RSPIn_SPCMD3_SLNDEN (0x4000u) +#define RSPIn_SPCMD3_SCKDEN (0x8000u) + +#define RSPIn_SPBFCR_RXTRG (0x07u) +#define RSPIn_SPBFCR_TXTRG (0x30u) +#define RSPIn_SPBFCR_RXRST (0x40u) +#define RSPIn_SPBFCR_TXRST (0x80u) + +#define RSPIn_SPBFDR_R (0x003Fu) +#define RSPIn_SPBFDR_T (0x0F00u) + + +/* ==== Shift values for IO registers ==== */ +#define RSPIn_SPCR_MODFEN_SHIFT (2u) +#define RSPIn_SPCR_MSTR_SHIFT (3u) +#define RSPIn_SPCR_SPEIE_SHIFT (4u) +#define RSPIn_SPCR_SPTIE_SHIFT (5u) +#define RSPIn_SPCR_SPE_SHIFT (6u) +#define RSPIn_SPCR_SPRIE_SHIFT (7u) + +#define RSPIn_SSLP_SSL0P_SHIFT (0u) + +#define RSPIn_SPPCR_SPLP_SHIFT (0u) +#define RSPIn_SPPCR_MOIFV_SHIFT (4u) +#define RSPIn_SPPCR_MOIFE_SHIFT (5u) + +#define RSPIn_SPSR_OVRF_SHIFT (0u) +#define RSPIn_SPSR_MODF_SHIFT (2u) +#define RSPIn_SPSR_SPTEF_SHIFT (5u) +#define RSPIn_SPSR_TEND_SHIFT (6u) +#define RSPIn_SPSR_SPRF_SHIFT (7u) + +#define RSPIn_SPDR_UINT32_SHIFT (0u) + +#define RSPIn_SPDR_UINT16_SHIFT (0u) + +#define RSPIn_SPDR_UINT8_SHIFT (0u) + +#define RSPIn_SPSCR_SPSLN_SHIFT (0u) + +#define RSPIn_SPSSR_SPCP_SHIFT (0u) + +#define RSPIn_SPBR_SPR_SHIFT (0u) + +#define RSPIn_SPDCR_SPLW_SHIFT (5u) +#define RSPIn_SPDCR_TXDMY_SHIFT (7u) + +#define RSPIn_SPCKD_SCKDL_SHIFT (0u) + +#define RSPIn_SSLND_SLNDL_SHIFT (0u) + +#define RSPIn_SPND_SPNDL_SHIFT (0u) + +#define RSPIn_SPCMD0_CPHA_SHIFT (0u) +#define RSPIn_SPCMD0_CPOL_SHIFT (1u) +#define RSPIn_SPCMD0_BRDV_SHIFT (2u) +#define RSPIn_SPCMD0_SSLKP_SHIFT (7u) +#define RSPIn_SPCMD0_SPB_SHIFT (8u) +#define RSPIn_SPCMD0_LSBF_SHIFT (12u) +#define RSPIn_SPCMD0_SPNDEN_SHIFT (13u) +#define RSPIn_SPCMD0_SLNDEN_SHIFT (14u) +#define RSPIn_SPCMD0_SCKDEN_SHIFT (15u) + +#define RSPIn_SPCMD1_CPHA_SHIFT (0u) +#define RSPIn_SPCMD1_CPOL_SHIFT (1u) +#define RSPIn_SPCMD1_BRDV_SHIFT (2u) +#define RSPIn_SPCMD1_SSLKP_SHIFT (7u) +#define RSPIn_SPCMD1_SPB_SHIFT (8u) +#define RSPIn_SPCMD1_LSBF_SHIFT (12u) +#define RSPIn_SPCMD1_SPNDEN_SHIFT (13u) +#define RSPIn_SPCMD1_SLNDEN_SHIFT (14u) +#define RSPIn_SPCMD1_SCKDEN_SHIFT (15u) + +#define RSPIn_SPCMD2_CPHA_SHIFT (0u) +#define RSPIn_SPCMD2_CPOL_SHIFT (1u) +#define RSPIn_SPCMD2_BRDV_SHIFT (2u) +#define RSPIn_SPCMD2_SSLKP_SHIFT (7u) +#define RSPIn_SPCMD2_SPB_SHIFT (8u) +#define RSPIn_SPCMD2_LSBF_SHIFT (12u) +#define RSPIn_SPCMD2_SPNDEN_SHIFT (13u) +#define RSPIn_SPCMD2_SLNDEN_SHIFT (14u) +#define RSPIn_SPCMD2_SCKDEN_SHIFT (15u) + +#define RSPIn_SPCMD3_CPHA_SHIFT (0u) +#define RSPIn_SPCMD3_CPOL_SHIFT (1u) +#define RSPIn_SPCMD3_BRDV_SHIFT (2u) +#define RSPIn_SPCMD3_SSLKP_SHIFT (7u) +#define RSPIn_SPCMD3_SPB_SHIFT (8u) +#define RSPIn_SPCMD3_LSBF_SHIFT (12u) +#define RSPIn_SPCMD3_SPNDEN_SHIFT (13u) +#define RSPIn_SPCMD3_SLNDEN_SHIFT (14u) +#define RSPIn_SPCMD3_SCKDEN_SHIFT (15u) + +#define RSPIn_SPBFCR_RXTRG_SHIFT (0u) +#define RSPIn_SPBFCR_TXTRG_SHIFT (4u) +#define RSPIn_SPBFCR_RXRST_SHIFT (6u) +#define RSPIn_SPBFCR_TXRST_SHIFT (7u) + +#define RSPIn_SPBFDR_R_SHIFT (0u) +#define RSPIn_SPBFDR_T_SHIFT (8u) + + +#endif /* RSPI_IOBITMASK_H */ + +/* End of File */ diff --git a/targets/TARGET_RENESAS/TARGET_RZ_A1XX/TARGET_GR_LYCHEE/device/inc/iobitmasks/scif_iobitmask.h b/targets/TARGET_RENESAS/TARGET_RZ_A1XX/TARGET_GR_LYCHEE/device/inc/iobitmasks/scif_iobitmask.h new file mode 100644 index 0000000..a545d6b --- /dev/null +++ b/targets/TARGET_RENESAS/TARGET_RZ_A1XX/TARGET_GR_LYCHEE/device/inc/iobitmasks/scif_iobitmask.h @@ -0,0 +1,1065 @@ +/******************************************************************************* +* DISCLAIMER +* This software is supplied by Renesas Electronics Corporation and is only +* intended for use with Renesas products. No other uses are authorized. This +* software is owned by Renesas Electronics Corporation and is protected under +* all applicable laws, including copyright laws. +* THIS SOFTWARE IS PROVIDED "AS IS" AND RENESAS MAKES NO WARRANTIES REGARDING +* THIS SOFTWARE, WHETHER EXPRESS, IMPLIED OR STATUTORY, INCLUDING BUT NOT +* LIMITED TO WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE +* AND NON-INFRINGEMENT. ALL SUCH WARRANTIES ARE EXPRESSLY DISCLAIMED. +* TO THE MAXIMUM EXTENT PERMITTED NOT PROHIBITED BY LAW, NEITHER RENESAS +* ELECTRONICS CORPORATION NOR ANY OF ITS AFFILIATED COMPANIES SHALL BE LIABLE +* FOR ANY DIRECT, INDIRECT, SPECIAL, INCIDENTAL OR CONSEQUENTIAL DAMAGES FOR +* ANY REASON RELATED TO THIS SOFTWARE, EVEN IF RENESAS OR ITS AFFILIATES HAVE +* BEEN ADVISED OF THE POSSIBILITY OF SUCH DAMAGES. +* Renesas reserves the right, without notice, to make changes to this software +* and to discontinue the availability of this software. By using this software, +* you agree to the additional terms and conditions found by accessing the +* following link: +* http://www.renesas.com/disclaimer +* Copyright (C) 2012 - 2014 Renesas Electronics Corporation. All rights reserved. +*******************************************************************************/ +/******************************************************************************* +* File Name : scif_iobitmask.h +* $Rev: 1115 $ +* $Date:: 2014-07-09 15:35:02 +0900#$ +* Description : SCIF register define header +*******************************************************************************/ +#ifndef SCIF_IOBITMASK_H +#define SCIF_IOBITMASK_H + + +/* ==== Mask values for IO registers ==== */ +/* ---- SCIF0 ---- */ +#define SCIF0_SCSMR_CKS (0x0003u) +#define SCIF0_SCSMR_STOP (0x0008u) +#define SCIF0_SCSMR_OE (0x0010u) +#define SCIF0_SCSMR_PE (0x0020u) +#define SCIF0_SCSMR_CHR (0x0040u) +#define SCIF0_SCSMR_CA (0x0080u) + +#define SCIF0_SCBRR_D (0xFFu) + +#define SCIF0_SCSCR_CKE (0x0003u) +#define SCIF0_SCSCR_REIE (0x0008u) +#define SCIF0_SCSCR_RE (0x0010u) +#define SCIF0_SCSCR_TE (0x0020u) +#define SCIF0_SCSCR_RIE (0x0040u) +#define SCIF0_SCSCR_TIE (0x0080u) + +#define SCIF0_SCFTDR_D (0xFFu) + +#define SCIF0_SCFSR_DR (0x0001u) +#define SCIF0_SCFSR_RDF (0x0002u) +#define SCIF0_SCFSR_PER (0x0004u) +#define SCIF0_SCFSR_FER (0x0008u) +#define SCIF0_SCFSR_BRK (0x0010u) +#define SCIF0_SCFSR_TDFE (0x0020u) +#define SCIF0_SCFSR_TEND (0x0040u) +#define SCIF0_SCFSR_ER (0x0080u) +#define SCIF0_SCFSR_FERN (0x0F00u) +#define SCIF0_SCFSR_PERN (0xF000u) + +#define SCIF0_SCFRDR_D (0xFFu) + +#define SCIF0_SCFCR_LOOP (0x0001u) +#define SCIF0_SCFCR_RFRST (0x0002u) +#define SCIF0_SCFCR_TFRST (0x0004u) +#define SCIF0_SCFCR_MCE (0x0008u) +#define SCIF0_SCFCR_TTRG (0x0030u) +#define SCIF0_SCFCR_RTRG (0x00C0u) +#define SCIF0_SCFCR_RSTRG (0x0700u) + +#define SCIF0_SCFDR_R (0x001Fu) +#define SCIF0_SCFDR_T (0x1F00u) + +#define SCIF0_SCSPTR_SPB2DT (0x0001u) +#define SCIF0_SCSPTR_SPB2IO (0x0002u) +#define SCIF0_SCSPTR_SCKDT (0x0004u) +#define SCIF0_SCSPTR_SCKIO (0x0008u) +#define SCIF0_SCSPTR_CTSDT (0x0010u) +#define SCIF0_SCSPTR_CTSIO (0x0020u) +#define SCIF0_SCSPTR_RTSDT (0x0040u) +#define SCIF0_SCSPTR_RTSIO (0x0080u) + +#define SCIF0_SCLSR_ORER (0x0001u) + +#define SCIF0_SCEMR_ABCS (0x0001u) +#define SCIF0_SCEMR_BGDM (0x0080u) + +/* ---- SCIF1 ---- */ +#define SCIF1_SCSMR_CKS (0x0003u) +#define SCIF1_SCSMR_STOP (0x0008u) +#define SCIF1_SCSMR_OE (0x0010u) +#define SCIF1_SCSMR_PE (0x0020u) +#define SCIF1_SCSMR_CHR (0x0040u) +#define SCIF1_SCSMR_CA (0x0080u) + +#define SCIF1_SCBRR_D (0xFFu) + +#define SCIF1_SCSCR_CKE (0x0003u) +#define SCIF1_SCSCR_REIE (0x0008u) +#define SCIF1_SCSCR_RE (0x0010u) +#define SCIF1_SCSCR_TE (0x0020u) +#define SCIF1_SCSCR_RIE (0x0040u) +#define SCIF1_SCSCR_TIE (0x0080u) + +#define SCIF1_SCFTDR_D (0xFFu) + +#define SCIF1_SCFSR_DR (0x0001u) +#define SCIF1_SCFSR_RDF (0x0002u) +#define SCIF1_SCFSR_PER (0x0004u) +#define SCIF1_SCFSR_FER (0x0008u) +#define SCIF1_SCFSR_BRK (0x0010u) +#define SCIF1_SCFSR_TDFE (0x0020u) +#define SCIF1_SCFSR_TEND (0x0040u) +#define SCIF1_SCFSR_ER (0x0080u) +#define SCIF1_SCFSR_FERN (0x0F00u) +#define SCIF1_SCFSR_PERN (0xF000u) + +#define SCIF1_SCFRDR_D (0xFFu) + +#define SCIF1_SCFCR_LOOP (0x0001u) +#define SCIF1_SCFCR_RFRST (0x0002u) +#define SCIF1_SCFCR_TFRST (0x0004u) +#define SCIF1_SCFCR_MCE (0x0008u) +#define SCIF1_SCFCR_TTRG (0x0030u) +#define SCIF1_SCFCR_RTRG (0x00C0u) +#define SCIF1_SCFCR_RSTRG (0x0700u) + +#define SCIF1_SCFDR_R (0x001Fu) +#define SCIF1_SCFDR_T (0x1F00u) + +#define SCIF1_SCSPTR_SPB2DT (0x0001u) +#define SCIF1_SCSPTR_SPB2IO (0x0002u) +#define SCIF1_SCSPTR_SCKDT (0x0004u) +#define SCIF1_SCSPTR_SCKIO (0x0008u) +#define SCIF1_SCSPTR_CTSDT (0x0010u) +#define SCIF1_SCSPTR_CTSIO (0x0020u) +#define SCIF1_SCSPTR_RTSDT (0x0040u) +#define SCIF1_SCSPTR_RTSIO (0x0080u) + +#define SCIF1_SCLSR_ORER (0x0001u) + +#define SCIF1_SCEMR_ABCS (0x0001u) +#define SCIF1_SCEMR_BGDM (0x0080u) + +/* ---- SCIF2 ---- */ +#define SCIF2_SCSMR_CKS (0x0003u) +#define SCIF2_SCSMR_STOP (0x0008u) +#define SCIF2_SCSMR_OE (0x0010u) +#define SCIF2_SCSMR_PE (0x0020u) +#define SCIF2_SCSMR_CHR (0x0040u) +#define SCIF2_SCSMR_CA (0x0080u) + +#define SCIF2_SCBRR_D (0xFFu) + +#define SCIF2_SCSCR_CKE (0x0003u) +#define SCIF2_SCSCR_REIE (0x0008u) +#define SCIF2_SCSCR_RE (0x0010u) +#define SCIF2_SCSCR_TE (0x0020u) +#define SCIF2_SCSCR_RIE (0x0040u) +#define SCIF2_SCSCR_TIE (0x0080u) + +#define SCIF2_SCFTDR_D (0xFFu) + +#define SCIF2_SCFSR_DR (0x0001u) +#define SCIF2_SCFSR_RDF (0x0002u) +#define SCIF2_SCFSR_PER (0x0004u) +#define SCIF2_SCFSR_FER (0x0008u) +#define SCIF2_SCFSR_BRK (0x0010u) +#define SCIF2_SCFSR_TDFE (0x0020u) +#define SCIF2_SCFSR_TEND (0x0040u) +#define SCIF2_SCFSR_ER (0x0080u) +#define SCIF2_SCFSR_FERN (0x0F00u) +#define SCIF2_SCFSR_PERN (0xF000u) + +#define SCIF2_SCFRDR_D (0xFFu) + +#define SCIF2_SCFCR_LOOP (0x0001u) +#define SCIF2_SCFCR_RFRST (0x0002u) +#define SCIF2_SCFCR_TFRST (0x0004u) +#define SCIF2_SCFCR_MCE (0x0008u) +#define SCIF2_SCFCR_TTRG (0x0030u) +#define SCIF2_SCFCR_RTRG (0x00C0u) +#define SCIF2_SCFCR_RSTRG (0x0700u) + +#define SCIF2_SCFDR_R (0x001Fu) +#define SCIF2_SCFDR_T (0x1F00u) + +#define SCIF2_SCSPTR_SPB2DT (0x0001u) +#define SCIF2_SCSPTR_SPB2IO (0x0002u) +#define SCIF2_SCSPTR_SCKDT (0x0004u) +#define SCIF2_SCSPTR_SCKIO (0x0008u) +#define SCIF2_SCSPTR_CTSDT (0x0010u) +#define SCIF2_SCSPTR_CTSIO (0x0020u) +#define SCIF2_SCSPTR_RTSDT (0x0040u) +#define SCIF2_SCSPTR_RTSIO (0x0080u) + +#define SCIF2_SCLSR_ORER (0x0001u) + +#define SCIF2_SCEMR_ABCS (0x0001u) +#define SCIF2_SCEMR_BGDM (0x0080u) + +/* ---- SCIF3 ---- */ +#define SCIF3_SCSMR_CKS (0x0003u) +#define SCIF3_SCSMR_STOP (0x0008u) +#define SCIF3_SCSMR_OE (0x0010u) +#define SCIF3_SCSMR_PE (0x0020u) +#define SCIF3_SCSMR_CHR (0x0040u) +#define SCIF3_SCSMR_CA (0x0080u) + +#define SCIF3_SCBRR_D (0xFFu) + +#define SCIF3_SCSCR_CKE (0x0003u) +#define SCIF3_SCSCR_REIE (0x0008u) +#define SCIF3_SCSCR_RE (0x0010u) +#define SCIF3_SCSCR_TE (0x0020u) +#define SCIF3_SCSCR_RIE (0x0040u) +#define SCIF3_SCSCR_TIE (0x0080u) + +#define SCIF3_SCFTDR_D (0xFFu) + +#define SCIF3_SCFSR_DR (0x0001u) +#define SCIF3_SCFSR_RDF (0x0002u) +#define SCIF3_SCFSR_PER (0x0004u) +#define SCIF3_SCFSR_FER (0x0008u) +#define SCIF3_SCFSR_BRK (0x0010u) +#define SCIF3_SCFSR_TDFE (0x0020u) +#define SCIF3_SCFSR_TEND (0x0040u) +#define SCIF3_SCFSR_ER (0x0080u) +#define SCIF3_SCFSR_FERN (0x0F00u) +#define SCIF3_SCFSR_PERN (0xF000u) + +#define SCIF3_SCFRDR_D (0xFFu) + +#define SCIF3_SCFCR_LOOP (0x0001u) +#define SCIF3_SCFCR_RFRST (0x0002u) +#define SCIF3_SCFCR_TFRST (0x0004u) +#define SCIF3_SCFCR_MCE (0x0008u) +#define SCIF3_SCFCR_TTRG (0x0030u) +#define SCIF3_SCFCR_RTRG (0x00C0u) +#define SCIF3_SCFCR_RSTRG (0x0700u) + +#define SCIF3_SCFDR_R (0x001Fu) +#define SCIF3_SCFDR_T (0x1F00u) + +#define SCIF3_SCSPTR_SPB2DT (0x0001u) +#define SCIF3_SCSPTR_SPB2IO (0x0002u) +#define SCIF3_SCSPTR_SCKDT (0x0004u) +#define SCIF3_SCSPTR_SCKIO (0x0008u) +#define SCIF3_SCSPTR_CTSDT (0x0010u) +#define SCIF3_SCSPTR_CTSIO (0x0020u) +#define SCIF3_SCSPTR_RTSDT (0x0040u) +#define SCIF3_SCSPTR_RTSIO (0x0080u) + +#define SCIF3_SCLSR_ORER (0x0001u) + +#define SCIF3_SCEMR_ABCS (0x0001u) +#define SCIF3_SCEMR_BGDM (0x0080u) + +/* ---- SCIF4 ---- */ +#define SCIF4_SCSMR_CKS (0x0003u) +#define SCIF4_SCSMR_STOP (0x0008u) +#define SCIF4_SCSMR_OE (0x0010u) +#define SCIF4_SCSMR_PE (0x0020u) +#define SCIF4_SCSMR_CHR (0x0040u) +#define SCIF4_SCSMR_CA (0x0080u) + +#define SCIF4_SCBRR_D (0xFFu) + +#define SCIF4_SCSCR_CKE (0x0003u) +#define SCIF4_SCSCR_REIE (0x0008u) +#define SCIF4_SCSCR_RE (0x0010u) +#define SCIF4_SCSCR_TE (0x0020u) +#define SCIF4_SCSCR_RIE (0x0040u) +#define SCIF4_SCSCR_TIE (0x0080u) + +#define SCIF4_SCFTDR_D (0xFFu) + +#define SCIF4_SCFSR_DR (0x0001u) +#define SCIF4_SCFSR_RDF (0x0002u) +#define SCIF4_SCFSR_PER (0x0004u) +#define SCIF4_SCFSR_FER (0x0008u) +#define SCIF4_SCFSR_BRK (0x0010u) +#define SCIF4_SCFSR_TDFE (0x0020u) +#define SCIF4_SCFSR_TEND (0x0040u) +#define SCIF4_SCFSR_ER (0x0080u) +#define SCIF4_SCFSR_FERN (0x0F00u) +#define SCIF4_SCFSR_PERN (0xF000u) + +#define SCIF4_SCFRDR_D (0xFFu) + +#define SCIF4_SCFCR_LOOP (0x0001u) +#define SCIF4_SCFCR_RFRST (0x0002u) +#define SCIF4_SCFCR_TFRST (0x0004u) +#define SCIF4_SCFCR_MCE (0x0008u) +#define SCIF4_SCFCR_TTRG (0x0030u) +#define SCIF4_SCFCR_RTRG (0x00C0u) +#define SCIF4_SCFCR_RSTRG (0x0700u) + +#define SCIF4_SCFDR_R (0x001Fu) +#define SCIF4_SCFDR_T (0x1F00u) + +#define SCIF4_SCSPTR_SPB2DT (0x0001u) +#define SCIF4_SCSPTR_SPB2IO (0x0002u) +#define SCIF4_SCSPTR_SCKDT (0x0004u) +#define SCIF4_SCSPTR_SCKIO (0x0008u) +#define SCIF4_SCSPTR_CTSDT (0x0010u) +#define SCIF4_SCSPTR_CTSIO (0x0020u) +#define SCIF4_SCSPTR_RTSDT (0x0040u) +#define SCIF4_SCSPTR_RTSIO (0x0080u) + +#define SCIF4_SCLSR_ORER (0x0001u) + +#define SCIF4_SCEMR_ABCS (0x0001u) +#define SCIF4_SCEMR_BGDM (0x0080u) + +/* ---- SCIF5 ---- */ +#define SCIF5_SCSMR_CKS (0x0003u) +#define SCIF5_SCSMR_STOP (0x0008u) +#define SCIF5_SCSMR_OE (0x0010u) +#define SCIF5_SCSMR_PE (0x0020u) +#define SCIF5_SCSMR_CHR (0x0040u) +#define SCIF5_SCSMR_CA (0x0080u) + +#define SCIF5_SCBRR_D (0xFFu) + +#define SCIF5_SCSCR_CKE (0x0003u) +#define SCIF5_SCSCR_REIE (0x0008u) +#define SCIF5_SCSCR_RE (0x0010u) +#define SCIF5_SCSCR_TE (0x0020u) +#define SCIF5_SCSCR_RIE (0x0040u) +#define SCIF5_SCSCR_TIE (0x0080u) + +#define SCIF5_SCFTDR_D (0xFFu) + +#define SCIF5_SCFSR_DR (0x0001u) +#define SCIF5_SCFSR_RDF (0x0002u) +#define SCIF5_SCFSR_PER (0x0004u) +#define SCIF5_SCFSR_FER (0x0008u) +#define SCIF5_SCFSR_BRK (0x0010u) +#define SCIF5_SCFSR_TDFE (0x0020u) +#define SCIF5_SCFSR_TEND (0x0040u) +#define SCIF5_SCFSR_ER (0x0080u) +#define SCIF5_SCFSR_FERN (0x0F00u) +#define SCIF5_SCFSR_PERN (0xF000u) + +#define SCIF5_SCFRDR_D (0xFFu) + +#define SCIF5_SCFCR_LOOP (0x0001u) +#define SCIF5_SCFCR_RFRST (0x0002u) +#define SCIF5_SCFCR_TFRST (0x0004u) +#define SCIF5_SCFCR_MCE (0x0008u) +#define SCIF5_SCFCR_TTRG (0x0030u) +#define SCIF5_SCFCR_RTRG (0x00C0u) +#define SCIF5_SCFCR_RSTRG (0x0700u) + +#define SCIF5_SCFDR_R (0x001Fu) +#define SCIF5_SCFDR_T (0x1F00u) + +#define SCIF5_SCSPTR_SPB2DT (0x0001u) +#define SCIF5_SCSPTR_SPB2IO (0x0002u) +#define SCIF5_SCSPTR_SCKDT (0x0004u) +#define SCIF5_SCSPTR_SCKIO (0x0008u) +#define SCIF5_SCSPTR_CTSDT (0x0010u) +#define SCIF5_SCSPTR_CTSIO (0x0020u) +#define SCIF5_SCSPTR_RTSDT (0x0040u) +#define SCIF5_SCSPTR_RTSIO (0x0080u) + +#define SCIF5_SCLSR_ORER (0x0001u) + +#define SCIF5_SCEMR_ABCS (0x0001u) +#define SCIF5_SCEMR_BGDM (0x0080u) + +/* ---- SCIF6 ---- */ +#define SCIF6_SCSMR_CKS (0x0003u) +#define SCIF6_SCSMR_STOP (0x0008u) +#define SCIF6_SCSMR_OE (0x0010u) +#define SCIF6_SCSMR_PE (0x0020u) +#define SCIF6_SCSMR_CHR (0x0040u) +#define SCIF6_SCSMR_CA (0x0080u) + +#define SCIF6_SCBRR_D (0xFFu) + +#define SCIF6_SCSCR_CKE (0x0003u) +#define SCIF6_SCSCR_REIE (0x0008u) +#define SCIF6_SCSCR_RE (0x0010u) +#define SCIF6_SCSCR_TE (0x0020u) +#define SCIF6_SCSCR_RIE (0x0040u) +#define SCIF6_SCSCR_TIE (0x0080u) + +#define SCIF6_SCFTDR_D (0xFFu) + +#define SCIF6_SCFSR_DR (0x0001u) +#define SCIF6_SCFSR_RDF (0x0002u) +#define SCIF6_SCFSR_PER (0x0004u) +#define SCIF6_SCFSR_FER (0x0008u) +#define SCIF6_SCFSR_BRK (0x0010u) +#define SCIF6_SCFSR_TDFE (0x0020u) +#define SCIF6_SCFSR_TEND (0x0040u) +#define SCIF6_SCFSR_ER (0x0080u) +#define SCIF6_SCFSR_FERN (0x0F00u) +#define SCIF6_SCFSR_PERN (0xF000u) + +#define SCIF6_SCFRDR_D (0xFFu) + +#define SCIF6_SCFCR_LOOP (0x0001u) +#define SCIF6_SCFCR_RFRST (0x0002u) +#define SCIF6_SCFCR_TFRST (0x0004u) +#define SCIF6_SCFCR_MCE (0x0008u) +#define SCIF6_SCFCR_TTRG (0x0030u) +#define SCIF6_SCFCR_RTRG (0x00C0u) +#define SCIF6_SCFCR_RSTRG (0x0700u) + +#define SCIF6_SCFDR_R (0x001Fu) +#define SCIF6_SCFDR_T (0x1F00u) + +#define SCIF6_SCSPTR_SPB2DT (0x0001u) +#define SCIF6_SCSPTR_SPB2IO (0x0002u) +#define SCIF6_SCSPTR_SCKDT (0x0004u) +#define SCIF6_SCSPTR_SCKIO (0x0008u) +#define SCIF6_SCSPTR_CTSDT (0x0010u) +#define SCIF6_SCSPTR_CTSIO (0x0020u) +#define SCIF6_SCSPTR_RTSDT (0x0040u) +#define SCIF6_SCSPTR_RTSIO (0x0080u) + +#define SCIF6_SCLSR_ORER (0x0001u) + +#define SCIF6_SCEMR_ABCS (0x0001u) +#define SCIF6_SCEMR_BGDM (0x0080u) + +/* ---- SCIF7 ---- */ +#define SCIF7_SCSMR_CKS (0x0003u) +#define SCIF7_SCSMR_STOP (0x0008u) +#define SCIF7_SCSMR_OE (0x0010u) +#define SCIF7_SCSMR_PE (0x0020u) +#define SCIF7_SCSMR_CHR (0x0040u) +#define SCIF7_SCSMR_CA (0x0080u) + +#define SCIF7_SCBRR_D (0xFFu) + +#define SCIF7_SCSCR_CKE (0x0003u) +#define SCIF7_SCSCR_REIE (0x0008u) +#define SCIF7_SCSCR_RE (0x0010u) +#define SCIF7_SCSCR_TE (0x0020u) +#define SCIF7_SCSCR_RIE (0x0040u) +#define SCIF7_SCSCR_TIE (0x0080u) + +#define SCIF7_SCFTDR_D (0xFFu) + +#define SCIF7_SCFSR_DR (0x0001u) +#define SCIF7_SCFSR_RDF (0x0002u) +#define SCIF7_SCFSR_PER (0x0004u) +#define SCIF7_SCFSR_FER (0x0008u) +#define SCIF7_SCFSR_BRK (0x0010u) +#define SCIF7_SCFSR_TDFE (0x0020u) +#define SCIF7_SCFSR_TEND (0x0040u) +#define SCIF7_SCFSR_ER (0x0080u) +#define SCIF7_SCFSR_FERN (0x0F00u) +#define SCIF7_SCFSR_PERN (0xF000u) + +#define SCIF7_SCFRDR_D (0xFFu) + +#define SCIF7_SCFCR_LOOP (0x0001u) +#define SCIF7_SCFCR_RFRST (0x0002u) +#define SCIF7_SCFCR_TFRST (0x0004u) +#define SCIF7_SCFCR_MCE (0x0008u) +#define SCIF7_SCFCR_TTRG (0x0030u) +#define SCIF7_SCFCR_RTRG (0x00C0u) +#define SCIF7_SCFCR_RSTRG (0x0700u) + +#define SCIF7_SCFDR_R (0x001Fu) +#define SCIF7_SCFDR_T (0x1F00u) + +#define SCIF7_SCSPTR_SPB2DT (0x0001u) +#define SCIF7_SCSPTR_SPB2IO (0x0002u) +#define SCIF7_SCSPTR_SCKDT (0x0004u) +#define SCIF7_SCSPTR_SCKIO (0x0008u) +#define SCIF7_SCSPTR_CTSDT (0x0010u) +#define SCIF7_SCSPTR_CTSIO (0x0020u) +#define SCIF7_SCSPTR_RTSDT (0x0040u) +#define SCIF7_SCSPTR_RTSIO (0x0080u) + +#define SCIF7_SCLSR_ORER (0x0001u) + +#define SCIF7_SCEMR_ABCS (0x0001u) +#define SCIF7_SCEMR_BGDM (0x0080u) + +/* ---- SCIFn ---- */ +#define SCIFn_SCSMR_CKS (0x0003u) +#define SCIFn_SCSMR_STOP (0x0008u) +#define SCIFn_SCSMR_OE (0x0010u) +#define SCIFn_SCSMR_PE (0x0020u) +#define SCIFn_SCSMR_CHR (0x0040u) +#define SCIFn_SCSMR_CA (0x0080u) + +#define SCIFn_SCBRR_D (0xFFu) + +#define SCIFn_SCSCR_CKE (0x0003u) +#define SCIFn_SCSCR_REIE (0x0008u) +#define SCIFn_SCSCR_RE (0x0010u) +#define SCIFn_SCSCR_TE (0x0020u) +#define SCIFn_SCSCR_RIE (0x0040u) +#define SCIFn_SCSCR_TIE (0x0080u) + +#define SCIFn_SCFTDR_D (0xFFu) + +#define SCIFn_SCFSR_DR (0x0001u) +#define SCIFn_SCFSR_RDF (0x0002u) +#define SCIFn_SCFSR_PER (0x0004u) +#define SCIFn_SCFSR_FER (0x0008u) +#define SCIFn_SCFSR_BRK (0x0010u) +#define SCIFn_SCFSR_TDFE (0x0020u) +#define SCIFn_SCFSR_TEND (0x0040u) +#define SCIFn_SCFSR_ER (0x0080u) +#define SCIFn_SCFSR_FERN (0x0F00u) +#define SCIFn_SCFSR_PERN (0xF000u) + +#define SCIFn_SCFRDR_D (0xFFu) + +#define SCIFn_SCFCR_LOOP (0x0001u) +#define SCIFn_SCFCR_RFRST (0x0002u) +#define SCIFn_SCFCR_TFRST (0x0004u) +#define SCIFn_SCFCR_MCE (0x0008u) +#define SCIFn_SCFCR_TTRG (0x0030u) +#define SCIFn_SCFCR_RTRG (0x00C0u) +#define SCIFn_SCFCR_RSTRG (0x0700u) + +#define SCIFn_SCFDR_R (0x001Fu) +#define SCIFn_SCFDR_T (0x1F00u) + +#define SCIFn_SCSPTR_SPB2DT (0x0001u) +#define SCIFn_SCSPTR_SPB2IO (0x0002u) +#define SCIFn_SCSPTR_SCKDT (0x0004u) +#define SCIFn_SCSPTR_SCKIO (0x0008u) +#define SCIFn_SCSPTR_CTSDT (0x0010u) +#define SCIFn_SCSPTR_CTSIO (0x0020u) +#define SCIFn_SCSPTR_RTSDT (0x0040u) +#define SCIFn_SCSPTR_RTSIO (0x0080u) + +#define SCIFn_SCLSR_ORER (0x0001u) + +#define SCIFn_SCEMR_ABCS (0x0001u) +#define SCIFn_SCEMR_BGDM (0x0080u) + + +/* ==== Shift values for IO registers ==== */ +/* ---- SCIF0 ---- */ +#define SCIF0_SCSMR_CKS_SHIFT (0u) +#define SCIF0_SCSMR_STOP_SHIFT (3u) +#define SCIF0_SCSMR_OE_SHIFT (4u) +#define SCIF0_SCSMR_PE_SHIFT (5u) +#define SCIF0_SCSMR_CHR_SHIFT (6u) +#define SCIF0_SCSMR_CA_SHIFT (7u) + +#define SCIF0_SCBRR_D_SHIFT (0u) + +#define SCIF0_SCSCR_CKE_SHIFT (0u) +#define SCIF0_SCSCR_REIE_SHIFT (3u) +#define SCIF0_SCSCR_RE_SHIFT (4u) +#define SCIF0_SCSCR_TE_SHIFT (5u) +#define SCIF0_SCSCR_RIE_SHIFT (6u) +#define SCIF0_SCSCR_TIE_SHIFT (7u) + +#define SCIF0_SCFTDR_D_SHIFT (0u) + +#define SCIF0_SCFSR_DR_SHIFT (0u) +#define SCIF0_SCFSR_RDF_SHIFT (1u) +#define SCIF0_SCFSR_PER_SHIFT (2u) +#define SCIF0_SCFSR_FER_SHIFT (3u) +#define SCIF0_SCFSR_BRK_SHIFT (4u) +#define SCIF0_SCFSR_TDFE_SHIFT (5u) +#define SCIF0_SCFSR_TEND_SHIFT (6u) +#define SCIF0_SCFSR_ER_SHIFT (7u) +#define SCIF0_SCFSR_FERN_SHIFT (8u) +#define SCIF0_SCFSR_PERN_SHIFT (12u) + +#define SCIF0_SCFRDR_D_SHIFT (0u) + +#define SCIF0_SCFCR_LOOP_SHIFT (0u) +#define SCIF0_SCFCR_RFRST_SHIFT (1u) +#define SCIF0_SCFCR_TFRST_SHIFT (2u) +#define SCIF0_SCFCR_MCE_SHIFT (3u) +#define SCIF0_SCFCR_TTRG_SHIFT (4u) +#define SCIF0_SCFCR_RTRG_SHIFT (6u) +#define SCIF0_SCFCR_RSTRG_SHIFT (8u) + +#define SCIF0_SCFDR_R_SHIFT (0u) +#define SCIF0_SCFDR_T_SHIFT (8u) + +#define SCIF0_SCSPTR_SPB2DT_SHIFT (0u) +#define SCIF0_SCSPTR_SPB2IO_SHIFT (1u) +#define SCIF0_SCSPTR_SCKDT_SHIFT (2u) +#define SCIF0_SCSPTR_SCKIO_SHIFT (3u) +#define SCIF0_SCSPTR_CTSDT_SHIFT (4u) +#define SCIF0_SCSPTR_CTSIO_SHIFT (5u) +#define SCIF0_SCSPTR_RTSDT_SHIFT (6u) +#define SCIF0_SCSPTR_RTSIO_SHIFT (7u) + +#define SCIF0_SCLSR_ORER_SHIFT (0u) + +#define SCIF0_SCEMR_ABCS_SHIFT (0u) +#define SCIF0_SCEMR_BGDM_SHIFT (7u) + +/* ---- SCIF1 ---- */ +#define SCIF1_SCSMR_CKS_SHIFT (0u) +#define SCIF1_SCSMR_STOP_SHIFT (3u) +#define SCIF1_SCSMR_OE_SHIFT (4u) +#define SCIF1_SCSMR_PE_SHIFT (5u) +#define SCIF1_SCSMR_CHR_SHIFT (6u) +#define SCIF1_SCSMR_CA_SHIFT (7u) + +#define SCIF1_SCBRR_D_SHIFT (0u) + +#define SCIF1_SCSCR_CKE_SHIFT (0u) +#define SCIF1_SCSCR_REIE_SHIFT (3u) +#define SCIF1_SCSCR_RE_SHIFT (4u) +#define SCIF1_SCSCR_TE_SHIFT (5u) +#define SCIF1_SCSCR_RIE_SHIFT (6u) +#define SCIF1_SCSCR_TIE_SHIFT (7u) + +#define SCIF1_SCFTDR_D_SHIFT (0u) + +#define SCIF1_SCFSR_DR_SHIFT (0u) +#define SCIF1_SCFSR_RDF_SHIFT (1u) +#define SCIF1_SCFSR_PER_SHIFT (2u) +#define SCIF1_SCFSR_FER_SHIFT (3u) +#define SCIF1_SCFSR_BRK_SHIFT (4u) +#define SCIF1_SCFSR_TDFE_SHIFT (5u) +#define SCIF1_SCFSR_TEND_SHIFT (6u) +#define SCIF1_SCFSR_ER_SHIFT (7u) +#define SCIF1_SCFSR_FERN_SHIFT (8u) +#define SCIF1_SCFSR_PERN_SHIFT (12u) + +#define SCIF1_SCFRDR_D_SHIFT (0u) + +#define SCIF1_SCFCR_LOOP_SHIFT (0u) +#define SCIF1_SCFCR_RFRST_SHIFT (1u) +#define SCIF1_SCFCR_TFRST_SHIFT (2u) +#define SCIF1_SCFCR_MCE_SHIFT (3u) +#define SCIF1_SCFCR_TTRG_SHIFT (4u) +#define SCIF1_SCFCR_RTRG_SHIFT (6u) +#define SCIF1_SCFCR_RSTRG_SHIFT (8u) + +#define SCIF1_SCFDR_R_SHIFT (0u) +#define SCIF1_SCFDR_T_SHIFT (8u) + +#define SCIF1_SCSPTR_SPB2DT_SHIFT (0u) +#define SCIF1_SCSPTR_SPB2IO_SHIFT (1u) +#define SCIF1_SCSPTR_SCKDT_SHIFT (2u) +#define SCIF1_SCSPTR_SCKIO_SHIFT (3u) +#define SCIF1_SCSPTR_CTSDT_SHIFT (4u) +#define SCIF1_SCSPTR_CTSIO_SHIFT (5u) +#define SCIF1_SCSPTR_RTSDT_SHIFT (6u) +#define SCIF1_SCSPTR_RTSIO_SHIFT (7u) + +#define SCIF1_SCLSR_ORER_SHIFT (0u) + +#define SCIF1_SCEMR_ABCS_SHIFT (0u) +#define SCIF1_SCEMR_BGDM_SHIFT (7u) + +/* ---- SCIF2 ---- */ +#define SCIF2_SCSMR_CKS_SHIFT (0u) +#define SCIF2_SCSMR_STOP_SHIFT (3u) +#define SCIF2_SCSMR_OE_SHIFT (4u) +#define SCIF2_SCSMR_PE_SHIFT (5u) +#define SCIF2_SCSMR_CHR_SHIFT (6u) +#define SCIF2_SCSMR_CA_SHIFT (7u) + +#define SCIF2_SCBRR_D_SHIFT (0u) + +#define SCIF2_SCSCR_CKE_SHIFT (0u) +#define SCIF2_SCSCR_REIE_SHIFT (3u) +#define SCIF2_SCSCR_RE_SHIFT (4u) +#define SCIF2_SCSCR_TE_SHIFT (5u) +#define SCIF2_SCSCR_RIE_SHIFT (6u) +#define SCIF2_SCSCR_TIE_SHIFT (7u) + +#define SCIF2_SCFTDR_D_SHIFT (0u) + +#define SCIF2_SCFSR_DR_SHIFT (0u) +#define SCIF2_SCFSR_RDF_SHIFT (1u) +#define SCIF2_SCFSR_PER_SHIFT (2u) +#define SCIF2_SCFSR_FER_SHIFT (3u) +#define SCIF2_SCFSR_BRK_SHIFT (4u) +#define SCIF2_SCFSR_TDFE_SHIFT (5u) +#define SCIF2_SCFSR_TEND_SHIFT (6u) +#define SCIF2_SCFSR_ER_SHIFT (7u) +#define SCIF2_SCFSR_FERN_SHIFT (8u) +#define SCIF2_SCFSR_PERN_SHIFT (12u) + +#define SCIF2_SCFRDR_D_SHIFT (0u) + +#define SCIF2_SCFCR_LOOP_SHIFT (0u) +#define SCIF2_SCFCR_RFRST_SHIFT (1u) +#define SCIF2_SCFCR_TFRST_SHIFT (2u) +#define SCIF2_SCFCR_MCE_SHIFT (3u) +#define SCIF2_SCFCR_TTRG_SHIFT (4u) +#define SCIF2_SCFCR_RTRG_SHIFT (6u) +#define SCIF2_SCFCR_RSTRG_SHIFT (8u) + +#define SCIF2_SCFDR_R_SHIFT (0u) +#define SCIF2_SCFDR_T_SHIFT (8u) + +#define SCIF2_SCSPTR_SPB2DT_SHIFT (0u) +#define SCIF2_SCSPTR_SPB2IO_SHIFT (1u) +#define SCIF2_SCSPTR_SCKDT_SHIFT (2u) +#define SCIF2_SCSPTR_SCKIO_SHIFT (3u) +#define SCIF2_SCSPTR_CTSDT_SHIFT (4u) +#define SCIF2_SCSPTR_CTSIO_SHIFT (5u) +#define SCIF2_SCSPTR_RTSDT_SHIFT (6u) +#define SCIF2_SCSPTR_RTSIO_SHIFT (7u) + +#define SCIF2_SCLSR_ORER_SHIFT (0u) + +#define SCIF2_SCEMR_ABCS_SHIFT (0u) +#define SCIF2_SCEMR_BGDM_SHIFT (7u) + +/* ---- SCIF3 ---- */ +#define SCIF3_SCSMR_CKS_SHIFT (0u) +#define SCIF3_SCSMR_STOP_SHIFT (3u) +#define SCIF3_SCSMR_OE_SHIFT (4u) +#define SCIF3_SCSMR_PE_SHIFT (5u) +#define SCIF3_SCSMR_CHR_SHIFT (6u) +#define SCIF3_SCSMR_CA_SHIFT (7u) + +#define SCIF3_SCBRR_D_SHIFT (0u) + +#define SCIF3_SCSCR_CKE_SHIFT (0u) +#define SCIF3_SCSCR_REIE_SHIFT (3u) +#define SCIF3_SCSCR_RE_SHIFT (4u) +#define SCIF3_SCSCR_TE_SHIFT (5u) +#define SCIF3_SCSCR_RIE_SHIFT (6u) +#define SCIF3_SCSCR_TIE_SHIFT (7u) + +#define SCIF3_SCFTDR_D_SHIFT (0u) + +#define SCIF3_SCFSR_DR_SHIFT (0u) +#define SCIF3_SCFSR_RDF_SHIFT (1u) +#define SCIF3_SCFSR_PER_SHIFT (2u) +#define SCIF3_SCFSR_FER_SHIFT (3u) +#define SCIF3_SCFSR_BRK_SHIFT (4u) +#define SCIF3_SCFSR_TDFE_SHIFT (5u) +#define SCIF3_SCFSR_TEND_SHIFT (6u) +#define SCIF3_SCFSR_ER_SHIFT (7u) +#define SCIF3_SCFSR_FERN_SHIFT (8u) +#define SCIF3_SCFSR_PERN_SHIFT (12u) + +#define SCIF3_SCFRDR_D_SHIFT (0u) + +#define SCIF3_SCFCR_LOOP_SHIFT (0u) +#define SCIF3_SCFCR_RFRST_SHIFT (1u) +#define SCIF3_SCFCR_TFRST_SHIFT (2u) +#define SCIF3_SCFCR_MCE_SHIFT (3u) +#define SCIF3_SCFCR_TTRG_SHIFT (4u) +#define SCIF3_SCFCR_RTRG_SHIFT (6u) +#define SCIF3_SCFCR_RSTRG_SHIFT (8u) + +#define SCIF3_SCFDR_R_SHIFT (0u) +#define SCIF3_SCFDR_T_SHIFT (8u) + +#define SCIF3_SCSPTR_SPB2DT_SHIFT (0u) +#define SCIF3_SCSPTR_SPB2IO_SHIFT (1u) +#define SCIF3_SCSPTR_SCKDT_SHIFT (2u) +#define SCIF3_SCSPTR_SCKIO_SHIFT (3u) +#define SCIF3_SCSPTR_CTSDT_SHIFT (4u) +#define SCIF3_SCSPTR_CTSIO_SHIFT (5u) +#define SCIF3_SCSPTR_RTSDT_SHIFT (6u) +#define SCIF3_SCSPTR_RTSIO_SHIFT (7u) + +#define SCIF3_SCLSR_ORER_SHIFT (0u) + +#define SCIF3_SCEMR_ABCS_SHIFT (0u) +#define SCIF3_SCEMR_BGDM_SHIFT (7u) + +/* ---- SCIF4 ---- */ +#define SCIF4_SCSMR_CKS_SHIFT (0u) +#define SCIF4_SCSMR_STOP_SHIFT (3u) +#define SCIF4_SCSMR_OE_SHIFT (4u) +#define SCIF4_SCSMR_PE_SHIFT (5u) +#define SCIF4_SCSMR_CHR_SHIFT (6u) +#define SCIF4_SCSMR_CA_SHIFT (7u) + +#define SCIF4_SCBRR_D_SHIFT (0u) + +#define SCIF4_SCSCR_CKE_SHIFT (0u) +#define SCIF4_SCSCR_REIE_SHIFT (3u) +#define SCIF4_SCSCR_RE_SHIFT (4u) +#define SCIF4_SCSCR_TE_SHIFT (5u) +#define SCIF4_SCSCR_RIE_SHIFT (6u) +#define SCIF4_SCSCR_TIE_SHIFT (7u) + +#define SCIF4_SCFTDR_D_SHIFT (0u) + +#define SCIF4_SCFSR_DR_SHIFT (0u) +#define SCIF4_SCFSR_RDF_SHIFT (1u) +#define SCIF4_SCFSR_PER_SHIFT (2u) +#define SCIF4_SCFSR_FER_SHIFT (3u) +#define SCIF4_SCFSR_BRK_SHIFT (4u) +#define SCIF4_SCFSR_TDFE_SHIFT (5u) +#define SCIF4_SCFSR_TEND_SHIFT (6u) +#define SCIF4_SCFSR_ER_SHIFT (7u) +#define SCIF4_SCFSR_FERN_SHIFT (8u) +#define SCIF4_SCFSR_PERN_SHIFT (12u) + +#define SCIF4_SCFRDR_D_SHIFT (0u) + +#define SCIF4_SCFCR_LOOP_SHIFT (0u) +#define SCIF4_SCFCR_RFRST_SHIFT (1u) +#define SCIF4_SCFCR_TFRST_SHIFT (2u) +#define SCIF4_SCFCR_MCE_SHIFT (3u) +#define SCIF4_SCFCR_TTRG_SHIFT (4u) +#define SCIF4_SCFCR_RTRG_SHIFT (6u) +#define SCIF4_SCFCR_RSTRG_SHIFT (8u) + +#define SCIF4_SCFDR_R_SHIFT (0u) +#define SCIF4_SCFDR_T_SHIFT (8u) + +#define SCIF4_SCSPTR_SPB2DT_SHIFT (0u) +#define SCIF4_SCSPTR_SPB2IO_SHIFT (1u) +#define SCIF4_SCSPTR_SCKDT_SHIFT (2u) +#define SCIF4_SCSPTR_SCKIO_SHIFT (3u) +#define SCIF4_SCSPTR_CTSDT_SHIFT (4u) +#define SCIF4_SCSPTR_CTSIO_SHIFT (5u) +#define SCIF4_SCSPTR_RTSDT_SHIFT (6u) +#define SCIF4_SCSPTR_RTSIO_SHIFT (7u) + +#define SCIF4_SCLSR_ORER_SHIFT (0u) + +#define SCIF4_SCEMR_ABCS_SHIFT (0u) +#define SCIF4_SCEMR_BGDM_SHIFT (7u) + +/* ---- SCIF5 ---- */ +#define SCIF5_SCSMR_CKS_SHIFT (0u) +#define SCIF5_SCSMR_STOP_SHIFT (3u) +#define SCIF5_SCSMR_OE_SHIFT (4u) +#define SCIF5_SCSMR_PE_SHIFT (5u) +#define SCIF5_SCSMR_CHR_SHIFT (6u) +#define SCIF5_SCSMR_CA_SHIFT (7u) + +#define SCIF5_SCBRR_D_SHIFT (0u) + +#define SCIF5_SCSCR_CKE_SHIFT (0u) +#define SCIF5_SCSCR_REIE_SHIFT (3u) +#define SCIF5_SCSCR_RE_SHIFT (4u) +#define SCIF5_SCSCR_TE_SHIFT (5u) +#define SCIF5_SCSCR_RIE_SHIFT (6u) +#define SCIF5_SCSCR_TIE_SHIFT (7u) + +#define SCIF5_SCFTDR_D_SHIFT (0u) + +#define SCIF5_SCFSR_DR_SHIFT (0u) +#define SCIF5_SCFSR_RDF_SHIFT (1u) +#define SCIF5_SCFSR_PER_SHIFT (2u) +#define SCIF5_SCFSR_FER_SHIFT (3u) +#define SCIF5_SCFSR_BRK_SHIFT (4u) +#define SCIF5_SCFSR_TDFE_SHIFT (5u) +#define SCIF5_SCFSR_TEND_SHIFT (6u) +#define SCIF5_SCFSR_ER_SHIFT (7u) +#define SCIF5_SCFSR_FERN_SHIFT (8u) +#define SCIF5_SCFSR_PERN_SHIFT (12u) + +#define SCIF5_SCFRDR_D_SHIFT (0u) + +#define SCIF5_SCFCR_LOOP_SHIFT (0u) +#define SCIF5_SCFCR_RFRST_SHIFT (1u) +#define SCIF5_SCFCR_TFRST_SHIFT (2u) +#define SCIF5_SCFCR_MCE_SHIFT (3u) +#define SCIF5_SCFCR_TTRG_SHIFT (4u) +#define SCIF5_SCFCR_RTRG_SHIFT (6u) +#define SCIF5_SCFCR_RSTRG_SHIFT (8u) + +#define SCIF5_SCFDR_R_SHIFT (0u) +#define SCIF5_SCFDR_T_SHIFT (8u) + +#define SCIF5_SCSPTR_SPB2DT_SHIFT (0u) +#define SCIF5_SCSPTR_SPB2IO_SHIFT (1u) +#define SCIF5_SCSPTR_SCKDT_SHIFT (2u) +#define SCIF5_SCSPTR_SCKIO_SHIFT (3u) +#define SCIF5_SCSPTR_CTSDT_SHIFT (4u) +#define SCIF5_SCSPTR_CTSIO_SHIFT (5u) +#define SCIF5_SCSPTR_RTSDT_SHIFT (6u) +#define SCIF5_SCSPTR_RTSIO_SHIFT (7u) + +#define SCIF5_SCLSR_ORER_SHIFT (0u) + +#define SCIF5_SCEMR_ABCS_SHIFT (0u) +#define SCIF5_SCEMR_BGDM_SHIFT (7u) + +/* ---- SCIF6 ---- */ +#define SCIF6_SCSMR_CKS_SHIFT (0u) +#define SCIF6_SCSMR_STOP_SHIFT (3u) +#define SCIF6_SCSMR_OE_SHIFT (4u) +#define SCIF6_SCSMR_PE_SHIFT (5u) +#define SCIF6_SCSMR_CHR_SHIFT (6u) +#define SCIF6_SCSMR_CA_SHIFT (7u) + +#define SCIF6_SCBRR_D_SHIFT (0u) + +#define SCIF6_SCSCR_CKE_SHIFT (0u) +#define SCIF6_SCSCR_REIE_SHIFT (3u) +#define SCIF6_SCSCR_RE_SHIFT (4u) +#define SCIF6_SCSCR_TE_SHIFT (5u) +#define SCIF6_SCSCR_RIE_SHIFT (6u) +#define SCIF6_SCSCR_TIE_SHIFT (7u) + +#define SCIF6_SCFTDR_D_SHIFT (0u) + +#define SCIF6_SCFSR_DR_SHIFT (0u) +#define SCIF6_SCFSR_RDF_SHIFT (1u) +#define SCIF6_SCFSR_PER_SHIFT (2u) +#define SCIF6_SCFSR_FER_SHIFT (3u) +#define SCIF6_SCFSR_BRK_SHIFT (4u) +#define SCIF6_SCFSR_TDFE_SHIFT (5u) +#define SCIF6_SCFSR_TEND_SHIFT (6u) +#define SCIF6_SCFSR_ER_SHIFT (7u) +#define SCIF6_SCFSR_FERN_SHIFT (8u) +#define SCIF6_SCFSR_PERN_SHIFT (12u) + +#define SCIF6_SCFRDR_D_SHIFT (0u) + +#define SCIF6_SCFCR_LOOP_SHIFT (0u) +#define SCIF6_SCFCR_RFRST_SHIFT (1u) +#define SCIF6_SCFCR_TFRST_SHIFT (2u) +#define SCIF6_SCFCR_MCE_SHIFT (3u) +#define SCIF6_SCFCR_TTRG_SHIFT (4u) +#define SCIF6_SCFCR_RTRG_SHIFT (6u) +#define SCIF6_SCFCR_RSTRG_SHIFT (8u) + +#define SCIF6_SCFDR_R_SHIFT (0u) +#define SCIF6_SCFDR_T_SHIFT (8u) + +#define SCIF6_SCSPTR_SPB2DT_SHIFT (0u) +#define SCIF6_SCSPTR_SPB2IO_SHIFT (1u) +#define SCIF6_SCSPTR_SCKDT_SHIFT (2u) +#define SCIF6_SCSPTR_SCKIO_SHIFT (3u) +#define SCIF6_SCSPTR_CTSDT_SHIFT (4u) +#define SCIF6_SCSPTR_CTSIO_SHIFT (5u) +#define SCIF6_SCSPTR_RTSDT_SHIFT (6u) +#define SCIF6_SCSPTR_RTSIO_SHIFT (7u) + +#define SCIF6_SCLSR_ORER_SHIFT (0u) + +#define SCIF6_SCEMR_ABCS_SHIFT (0u) +#define SCIF6_SCEMR_BGDM_SHIFT (7u) + +/* ---- SCIF7 ---- */ +#define SCIF7_SCSMR_CKS_SHIFT (0u) +#define SCIF7_SCSMR_STOP_SHIFT (3u) +#define SCIF7_SCSMR_OE_SHIFT (4u) +#define SCIF7_SCSMR_PE_SHIFT (5u) +#define SCIF7_SCSMR_CHR_SHIFT (6u) +#define SCIF7_SCSMR_CA_SHIFT (7u) + +#define SCIF7_SCBRR_D_SHIFT (0u) + +#define SCIF7_SCSCR_CKE_SHIFT (0u) +#define SCIF7_SCSCR_REIE_SHIFT (3u) +#define SCIF7_SCSCR_RE_SHIFT (4u) +#define SCIF7_SCSCR_TE_SHIFT (5u) +#define SCIF7_SCSCR_RIE_SHIFT (6u) +#define SCIF7_SCSCR_TIE_SHIFT (7u) + +#define SCIF7_SCFTDR_D_SHIFT (0u) + +#define SCIF7_SCFSR_DR_SHIFT (0u) +#define SCIF7_SCFSR_RDF_SHIFT (1u) +#define SCIF7_SCFSR_PER_SHIFT (2u) +#define SCIF7_SCFSR_FER_SHIFT (3u) +#define SCIF7_SCFSR_BRK_SHIFT (4u) +#define SCIF7_SCFSR_TDFE_SHIFT (5u) +#define SCIF7_SCFSR_TEND_SHIFT (6u) +#define SCIF7_SCFSR_ER_SHIFT (7u) +#define SCIF7_SCFSR_FERN_SHIFT (8u) +#define SCIF7_SCFSR_PERN_SHIFT (12u) + +#define SCIF7_SCFRDR_D_SHIFT (0u) + +#define SCIF7_SCFCR_LOOP_SHIFT (0u) +#define SCIF7_SCFCR_RFRST_SHIFT (1u) +#define SCIF7_SCFCR_TFRST_SHIFT (2u) +#define SCIF7_SCFCR_MCE_SHIFT (3u) +#define SCIF7_SCFCR_TTRG_SHIFT (4u) +#define SCIF7_SCFCR_RTRG_SHIFT (6u) +#define SCIF7_SCFCR_RSTRG_SHIFT (8u) + +#define SCIF7_SCFDR_R_SHIFT (0u) +#define SCIF7_SCFDR_T_SHIFT (8u) + +#define SCIF7_SCSPTR_SPB2DT_SHIFT (0u) +#define SCIF7_SCSPTR_SPB2IO_SHIFT (1u) +#define SCIF7_SCSPTR_SCKDT_SHIFT (2u) +#define SCIF7_SCSPTR_SCKIO_SHIFT (3u) +#define SCIF7_SCSPTR_CTSDT_SHIFT (4u) +#define SCIF7_SCSPTR_CTSIO_SHIFT (5u) +#define SCIF7_SCSPTR_RTSDT_SHIFT (6u) +#define SCIF7_SCSPTR_RTSIO_SHIFT (7u) + +#define SCIF7_SCLSR_ORER_SHIFT (0u) + +#define SCIF7_SCEMR_ABCS_SHIFT (0u) +#define SCIF7_SCEMR_BGDM_SHIFT (7u) + +/* ---- SCIFn ---- */ +#define SCIFn_SCSMR_CKS_SHIFT (0u) +#define SCIFn_SCSMR_STOP_SHIFT (3u) +#define SCIFn_SCSMR_OE_SHIFT (4u) +#define SCIFn_SCSMR_PE_SHIFT (5u) +#define SCIFn_SCSMR_CHR_SHIFT (6u) +#define SCIFn_SCSMR_CA_SHIFT (7u) + +#define SCIFn_SCBRR_D_SHIFT (0u) + +#define SCIFn_SCSCR_CKE_SHIFT (0u) +#define SCIFn_SCSCR_REIE_SHIFT (3u) +#define SCIFn_SCSCR_RE_SHIFT (4u) +#define SCIFn_SCSCR_TE_SHIFT (5u) +#define SCIFn_SCSCR_RIE_SHIFT (6u) +#define SCIFn_SCSCR_TIE_SHIFT (7u) + +#define SCIFn_SCFTDR_D_SHIFT (0u) + +#define SCIFn_SCFSR_DR_SHIFT (0u) +#define SCIFn_SCFSR_RDF_SHIFT (1u) +#define SCIFn_SCFSR_PER_SHIFT (2u) +#define SCIFn_SCFSR_FER_SHIFT (3u) +#define SCIFn_SCFSR_BRK_SHIFT (4u) +#define SCIFn_SCFSR_TDFE_SHIFT (5u) +#define SCIFn_SCFSR_TEND_SHIFT (6u) +#define SCIFn_SCFSR_ER_SHIFT (7u) +#define SCIFn_SCFSR_FERN_SHIFT (8u) +#define SCIFn_SCFSR_PERN_SHIFT (12u) + +#define SCIFn_SCFRDR_D_SHIFT (0u) + +#define SCIFn_SCFCR_LOOP_SHIFT (0u) +#define SCIFn_SCFCR_RFRST_SHIFT (1u) +#define SCIFn_SCFCR_TFRST_SHIFT (2u) +#define SCIFn_SCFCR_MCE_SHIFT (3u) +#define SCIFn_SCFCR_TTRG_SHIFT (4u) +#define SCIFn_SCFCR_RTRG_SHIFT (6u) +#define SCIFn_SCFCR_RSTRG_SHIFT (8u) + +#define SCIFn_SCFDR_R_SHIFT (0u) +#define SCIFn_SCFDR_T_SHIFT (8u) + +#define SCIFn_SCSPTR_SPB2DT_SHIFT (0u) +#define SCIFn_SCSPTR_SPB2IO_SHIFT (1u) +#define SCIFn_SCSPTR_SCKDT_SHIFT (2u) +#define SCIFn_SCSPTR_SCKIO_SHIFT (3u) +#define SCIFn_SCSPTR_CTSDT_SHIFT (4u) +#define SCIFn_SCSPTR_CTSIO_SHIFT (5u) +#define SCIFn_SCSPTR_RTSDT_SHIFT (6u) +#define SCIFn_SCSPTR_RTSIO_SHIFT (7u) + +#define SCIFn_SCLSR_ORER_SHIFT (0u) + +#define SCIFn_SCEMR_ABCS_SHIFT (0u) +#define SCIFn_SCEMR_BGDM_SHIFT (7u) + + +#endif /* SCIF_IOBITMASK_H */ + +/* End of File */ diff --git a/targets/TARGET_RENESAS/TARGET_RZ_A1XX/TARGET_GR_LYCHEE/device/inc/iobitmasks/usb_iobitmask.h b/targets/TARGET_RENESAS/TARGET_RZ_A1XX/TARGET_GR_LYCHEE/device/inc/iobitmasks/usb_iobitmask.h new file mode 100644 index 0000000..cd671e6 --- /dev/null +++ b/targets/TARGET_RENESAS/TARGET_RZ_A1XX/TARGET_GR_LYCHEE/device/inc/iobitmasks/usb_iobitmask.h @@ -0,0 +1,731 @@ +/******************************************************************************* +* DISCLAIMER +* This software is supplied by Renesas Electronics Corporation and is only +* intended for use with Renesas products. No other uses are authorized. This +* software is owned by Renesas Electronics Corporation and is protected under +* all applicable laws, including copyright laws. +* THIS SOFTWARE IS PROVIDED "AS IS" AND RENESAS MAKES NO WARRANTIES REGARDING +* THIS SOFTWARE, WHETHER EXPRESS, IMPLIED OR STATUTORY, INCLUDING BUT NOT +* LIMITED TO WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE +* AND NON-INFRINGEMENT. ALL SUCH WARRANTIES ARE EXPRESSLY DISCLAIMED. +* TO THE MAXIMUM EXTENT PERMITTED NOT PROHIBITED BY LAW, NEITHER RENESAS +* ELECTRONICS CORPORATION NOR ANY OF ITS AFFILIATED COMPANIES SHALL BE LIABLE +* FOR ANY DIRECT, INDIRECT, SPECIAL, INCIDENTAL OR CONSEQUENTIAL DAMAGES FOR +* ANY REASON RELATED TO THIS SOFTWARE, EVEN IF RENESAS OR ITS AFFILIATES HAVE +* BEEN ADVISED OF THE POSSIBILITY OF SUCH DAMAGES. +* Renesas reserves the right, without notice, to make changes to this software +* and to discontinue the availability of this software. By using this software, +* you agree to the additional terms and conditions found by accessing the +* following link: +* http://www.renesas.com/disclaimer +* Copyright (C) 2012 - 2014 Renesas Electronics Corporation. All rights reserved. +*******************************************************************************/ +/******************************************************************************* +* File Name : usb_iobitmask.h +* $Rev: 1116 $ +* $Date:: 2014-07-09 16:29:19 +0900#$ +* Description : USB register define header +*******************************************************************************/ +#ifndef USB_IOBITMASK_H +#define USB_IOBITMASK_H + +/*==============================================*/ +/* SYSCFG */ +/*==============================================*/ +#define USB_SYSCFG_USBE (0x0001u) +#define USB_SYSCFG_UPLLE (0x0002u) +#define USB_SYSCFG_UCKSEL (0x0004u) +/* #define USB_SYSCFG_RESERVED1 (0x0008u) */ +#define USB_SYSCFG_DPRPU (0x0010u) +#define USB_SYSCFG_DRPD (0x0020u) +#define USB_SYSCFG_DCFM (0x0040u) +#define USB_SYSCFG_HSE (0x0080u) +/* #define USB_SYSCFG_RESERVED2 (0xFF00u) */ + +#define USB_SYSCFG_USBE_SHIFT (0) +#define USB_SYSCFG_UPLLE_SHIFT (1) +#define USB_SYSCFG_UCKSEL_SHIFT (2) +/* #define USB_SYSCFG_RESERVED1_SHIFT (3) */ +#define USB_SYSCFG_DPRPU_SHIFT (4) +#define USB_SYSCFG_DRPD_SHIFT (5) +#define USB_SYSCFG_DCFM_SHIFT (6) +#define USB_SYSCFG_HSE_SHIFT (7) +/* #define USB_SYSCFG_RESERVED2_SHIFT (8) */ + +/*==============================================*/ +/* BUSWAIT */ +/*==============================================*/ +#define USB_BUSWAIT_BWAIT (0x003Fu) + +#define USB_BUSWAIT_BWAIT_SHIFT (0) + +/*==============================================*/ +/* SYSSTS0 */ +/*==============================================*/ +#define USB_SYSSTS0_LNST (0x0003u) +#define USB_SYSSTS0_SOFEA (0x0020u) +#define USB_SYSSTS0_HTACT (0x0040u) + +#define USB_SYSSTS0_LNST_SHIFT (0) +#define USB_SYSSTS0_SOFEA_SHIFT (5) +#define USB_SYSSTS0_HTACT_SHIFT (6) + +/*==============================================*/ +/* DVSTCTR0 */ +/*==============================================*/ +#define USB_DVSTCTR0_RHST (0x0007u) +/* #define USB_DVSTCTR0_RESERVED (0x0008u) */ +#define USB_DVSTCTR0_UACT (0x0010u) +#define USB_DVSTCTR0_RESUME (0x0020u) +#define USB_DVSTCTR0_USBRST (0x0040u) +#define USB_DVSTCTR0_RWUPE (0x0080u) +#define USB_DVSTCTR0_WKUP (0x0100u) + +#define USB_DVSTCTR0_RHST_SHIFT (0) +/* #define USB_DVSTCTR0_RESERVED_SHIFT (3) */ +#define USB_DVSTCTR0_UACT_SHIFT (4) +#define USB_DVSTCTR0_RESUME_SHIFT (5) +#define USB_DVSTCTR0_USBRST_SHIFT (6) +#define USB_DVSTCTR0_RWUPE_SHIFT (7) +#define USB_DVSTCTR0_WKUP_SHIFT (8) + +/*==============================================*/ +/* TESTMODE */ +/*==============================================*/ +#define USB_TESTMODE_UTST (0x000Fu) +/* #define USB_TESTMODE_RESERVED (0xFFF0u) */ + +#define USB_TESTMODE_UTST_SHIFT (0) +/* #define USB_TESTMODE_RESERVED_SHIFT (4) */ + +/*==============================================*/ +/* DnFBCFG */ +/*==============================================*/ +/* #define USB_DnFBCFG_RESERVED1 (0x000Fu) */ +#define USB_DnFBCFG_TENDE (0x0010u) +/* #define USB_DnFBCFG_RESERVED2 (0x0FE0u) */ +#define USB_DnFBCFG_DFACC (0x3000u) +/* #define USB_DnFBCFG_RESERVED3 (0xC000u) */ + +/* #define USB_DnFBCFG_RESERVED1_SHIFT (0) */ +#define USB_DnFBCFG_TENDE_SHIFT (4) +/* #define USB_DnFBCFG_RESERVED2_SHIFT (5) */ +#define USB_DnFBCFG_DFACC_SHIFT (12) +/* #define USB_DnFBCFG_RESERVED3_SHIFT (14) */ + +/*==============================================*/ +/* CFIFO */ +/*==============================================*/ +#define USB_CFIFO_FIFOPORT (0xFFFFFFFFuL) + +#define USB_CFIFO_FIFOPORT_SHIFT (0) + +/*==============================================*/ +/* DnFIFO */ +/*==============================================*/ +#define USB_DnFIFO_FIFOPORT (0xFFFFFFFFuL) + +#define USB_DnFIFO_FIFOPORT_SHIFT (0) + +/*==============================================*/ +/* CFIFOSEL */ +/*==============================================*/ +#define USB_CFIFOSEL_CURPIPE (0x000Fu) +/* #define USB_CFIFOSEL_RESERVED1 (0x0010u) */ +#define USB_CFIFOSEL_ISEL_ (0x0020u) +/* #define USB_CFIFOSEL_RESERVED2 (0x00C0u) */ +#define USB_CFIFOSEL_BIGEND (0x0100u) +/* #define USB_CFIFOSEL_RESERVED3 (0x0200u) */ +#define USB_CFIFOSEL_MBW (0x0C00u) +/* #define USB_CFIFOSEL_RESERVED4 (0x3000u) */ +#define USB_CFIFOSEL_REW (0x4000u) +#define USB_CFIFOSEL_RCNT (0x8000u) + +#define USB_CFIFOSEL_CURPIPE_SHIFT (0) +/* #define USB_CFIFOSEL_RESERVED1_SHIFT (4) */ +#define USB_CFIFOSEL_ISEL_SHIFT_ (5) +/* #define USB_CFIFOSEL_RESERVED2_SHIFT (6) */ +#define USB_CFIFOSEL_BIGEND_SHIFT (8) +/* #define USB_CFIFOSEL_RESERVED3_SHIFT (9) */ +#define USB_CFIFOSEL_MBW_SHIFT (10) +/* #define USB_CFIFOSEL_RESERVED4_SHIFT (12) */ +#define USB_CFIFOSEL_REW_SHIFT (14) +#define USB_CFIFOSEL_RCNT_SHIFT (15) + +/*==============================================*/ +/* DnFIFOSEL */ +/*==============================================*/ +#define USB_DnFIFOSEL_CURPIPE (0x000Fu) +/* #define USB_DnFIFOSEL_RESERVED1 (0x00F0u) */ +#define USB_DnFIFOSEL_BIGEND (0x0100u) +/* #define USB_DnFIFOSEL_RESERVED2 (0x0200u) */ +#define USB_DnFIFOSEL_MBW (0x0C00u) +#define USB_DnFIFOSEL_DREQE (0x1000u) +#define USB_DnFIFOSEL_DCLRM (0x2000u) +#define USB_DnFIFOSEL_REW (0x4000u) +#define USB_DnFIFOSEL_RCNT (0x8000u) + +#define USB_DnFIFOSEL_CURPIPE_SHIFT (0) +/* #define USB_DnFIFOSEL_RESERVED1_SHIFT (4) */ +#define USB_DnFIFOSEL_BIGEND_SHIFT (8) +/* #define USB_DnFIFOSEL_RESERVED2_SHIFT (9) */ +#define USB_DnFIFOSEL_MBW_SHIFT (10) +#define USB_DnFIFOSEL_DREQE_SHIFT (12) +#define USB_DnFIFOSEL_DCLRM_SHIFT (13) +#define USB_DnFIFOSEL_REW_SHIFT (14) +#define USB_DnFIFOSEL_RCNT_SHIFT (15) + +/*==============================================*/ +/* CFIFOCTR */ +/*==============================================*/ +#define USB_CFIFOCTR_DTLN (0x0FFFu) +/* #define USB_CFIFOCTR_RESERVED (0x1000u) */ +#define USB_CFIFOCTR_FRDY (0x2000u) +#define USB_CFIFOCTR_BCLR (0x4000u) +#define USB_CFIFOCTR_BVAL (0x8000u) + +#define USB_CFIFOCTR_DTLN_SHIFT (0) +/* #define USB_CFIFOCTR_RESERVED_SHIFT (12) */ +#define USB_CFIFOCTR_FRDY_SHIFT (13) +#define USB_CFIFOCTR_BCLR_SHIFT (14) +#define USB_CFIFOCTR_BVAL_SHIFT (15) + +/*==============================================*/ +/* DnFIFOCTR */ +/*==============================================*/ +#define USB_DnFIFOCTR_DTLN (0x0FFFu) +/* #define USB_DnFIFOCTR_RESERVED (0x1000u) */ +#define USB_DnFIFOCTR_FRDY (0x2000u) +#define USB_DnFIFOCTR_BCLR (0x4000u) +#define USB_DnFIFOCTR_BVAL (0x8000u) + +#define USB_DnFIFOCTR_DTLN_SHIFT (0) +/* #define USB_DnFIFOCTR_RESERVED_SHIFT (12) */ +#define USB_DnFIFOCTR_FRDY_SHIFT (13) +#define USB_DnFIFOCTR_BCLR_SHIFT (14) +#define USB_DnFIFOCTR_BVAL_SHIFT (15) + +/*==============================================*/ +/* INTENB0 */ +/*==============================================*/ +/* #define USB_INTENB0_RESERVED (0x00FFu) */ +#define USB_INTENB0_BRDYE (0x0100u) +#define USB_INTENB0_NRDYE (0x0200u) +#define USB_INTENB0_BEMPE (0x0400u) +#define USB_INTENB0_CTRE (0x0800u) +#define USB_INTENB0_DVSE (0x1000u) +#define USB_INTENB0_SOFE (0x2000u) +#define USB_INTENB0_RSME (0x4000u) +#define USB_INTENB0_VBSE (0x8000u) + +/* #define USB_INTENB0_RESERVED_SHIFT (0) */ +#define USB_INTENB0_BRDYE_SHIFT (8) +#define USB_INTENB0_NRDYE_SHIFT (9) +#define USB_INTENB0_BEMPE_SHIFT (10) +#define USB_INTENB0_CTRE_SHIFT (11) +#define USB_INTENB0_DVSE_SHIFT (12) +#define USB_INTENB0_SOFE_SHIFT (13) +#define USB_INTENB0_RSME_SHIFT (14) +#define USB_INTENB0_VBSE_SHIFT (15) + +/*==============================================*/ +/* INTENB1 */ +/*==============================================*/ +/* #define USB_INTENB1_RESERVED1 (0x000Fu) */ +#define USB_INTENB1_SACKE (0x0010u) +#define USB_INTENB1_SIGNE (0x0020u) +#define USB_INTENB1_EOFERRE (0x0040u) +/* #define USB_INTENB1_RESERVED2 (0x0780u) */ +#define USB_INTENB1_ATTCHE (0x0800u) +#define USB_INTENB1_DTCHE (0x1000u) +/* #define USB_INTENB1_RESERVED3 (0x2000u) */ +#define USB_INTENB1_BCHGE (0x4000u) +/* #define USB_INTENB1_RESERVED4 (0x8000u) */ + +/* #define USB_INTENB1_RESERVED1_SHIFT (0) */ +#define USB_INTENB1_SACKE_SHIFT (4) +#define USB_INTENB1_SIGNE_SHIFT (5) +#define USB_INTENB1_EOFERRE_SHIFT (6) +/* #define USB_INTENB1_RESERVED2_SHIFT (7) */ +#define USB_INTENB1_ATTCHE_SHIFT (11) +#define USB_INTENB1_DTCHE_SHIFT (12) +/* #define USB_INTENB1_RESERVED3_SHIFT (13) */ +#define USB_INTENB1_BCHGE_SHIFT (14) +/* #define USB_INTENB1_RESERVED4_SHIFT (15) */ + +/*==============================================*/ +/* BRDYENB */ +/*==============================================*/ +#define USB_BRDYENB (0xFFFFu) + +#define USB_BRDYENB_SHIFT (0) + +/*==============================================*/ +/* NRDYENB */ +/*==============================================*/ +#define USB_NRDYENB (0xFFFFu) + +#define USB_NRDYENB_SHIFT (0) + +/*==============================================*/ +/* BEMPENB */ +/*==============================================*/ +#define USB_BEMPENB (0xFFFFu) + +#define USB_BEMPENB_SHIFT (0) + +/*==============================================*/ +/* SOFCFG */ +/*==============================================*/ +/* #define USB_SOFCFG_RESERVED1 (0x003Fu) */ +#define USB_SOFCFG_BRDYM (0x0040u) +/* #define USB_SOFCFG_RESERVED2 (0x0080u) */ +#define USB_SOFCFG_TRNENSEL (0x0100u) +/* #define USB_SOFCFG_RESERVED3 (0xFE00u) */ + +/* #define USB_SOFCFG_RESERVED1_SHIFT (0) */ +#define USB_SOFCFG_BRDYM_SHIFT (6) +/* #define USB_SOFCFG_RESERVED2_SHIFT (7) */ +#define USB_SOFCFG_TRNENSEL_SHIFT (8) +/* #define USB_SOFCFG_RESERVED3_SHIFT (9) */ + +/*==============================================*/ +/* INTSTS0 */ +/*==============================================*/ +#define USB_INTSTS0_CTSQ (0x0007u) +#define USB_INTSTS0_VALID (0x0008u) +#define USB_INTSTS0_DVSQ (0x0070u) +#define USB_INTSTS0_VBSTS (0x0080u) +#define USB_INTSTS0_BRDY (0x0100u) +#define USB_INTSTS0_NRDY (0x0200u) +#define USB_INTSTS0_BEMP (0x0400u) +#define USB_INTSTS0_CTRT (0x0800u) +#define USB_INTSTS0_DVST (0x1000u) +#define USB_INTSTS0_SOFR (0x2000u) +#define USB_INTSTS0_RESM (0x4000u) +#define USB_INTSTS0_VBINT (0x8000u) + +#define USB_INTSTS0_CTSQ_SHIFT (0) +#define USB_INTSTS0_VALID_SHIFT (3) +#define USB_INTSTS0_DVSQ_SHIFT (4) +#define USB_INTSTS0_VBSTS_SHIFT (7) +#define USB_INTSTS0_BRDY_SHIFT (8) +#define USB_INTSTS0_NRDY_SHIFT (9) +#define USB_INTSTS0_BEMP_SHIFT (10) +#define USB_INTSTS0_CTRT_SHIFT (11) +#define USB_INTSTS0_DVST_SHIFT (12) +#define USB_INTSTS0_SOFR_SHIFT (13) +#define USB_INTSTS0_RESM_SHIFT (14) +#define USB_INTSTS0_VBINT_SHIFT (15) + +/*==============================================*/ +/* INTSTS1 */ +/*==============================================*/ +/* #define USB_INTSTS1_RESERVED1 (0x000Fu) */ +#define USB_INTSTS1_SACK (0x0010u) +#define USB_INTSTS1_SIGN (0x0020u) +#define USB_INTSTS1_EOFERR (0x0040u) +/* #define USB_INTSTS1_RESERVED2 (0x0780u) */ +#define USB_INTSTS1_ATTCH (0x0800u) +#define USB_INTSTS1_DTCH (0x1000u) +/* #define USB_INTSTS1_RESERVED3 (0x2000u) */ +#define USB_INTSTS1_BCHG (0x4000u) +/* #define USB_INTSTS1_RESERVED4 (0x8000u) */ + +/* #define USB_INTSTS1_RESERVED1_SHIFT (0) */ +#define USB_INTSTS1_SACK_SHIFT (4) +#define USB_INTSTS1_SIGN_SHIFT (5) +#define USB_INTSTS1_EOFERR_SHIFT (6) +/* #define USB_INTSTS1_RESERVED2_SHIFT (7) */ +#define USB_INTSTS1_ATTCH_SHIFT (11) +#define USB_INTSTS1_DTCH_SHIFT (12) +/* #define USB_INTSTS1_RESERVED3_SHIFT (13) */ +#define USB_INTSTS1_BCHG_SHIFT (14) +/* #define USB_INTSTS1_RESERVED4_SHIFT (15) */ + +/*==============================================*/ +/* BRDYSTS */ +/*==============================================*/ +#define USB_BRDYSTS (0xFFFFu) + +#define USB_BRDYSTS_SHIFT (0) + +/*==============================================*/ +/* NRDYSTS */ +/*==============================================*/ +#define USB_NRDYSTS (0xFFFFu) + +#define USB_NRDYSTS_SHIFT (0) + +/*==============================================*/ +/* BEMPSTS */ +/*==============================================*/ +#define USB_BEMPSTS (0xFFFFu) + +#define USB_BEMPSTS_SHIFT (0) + +/*==============================================*/ +/* FRMNUM */ +/*==============================================*/ +#define USB_FRMNUM_FRNM (0x07FFu) +/* #define USB_FRMNUM_RESERVED (0x3800u) */ +#define USB_FRMNUM_CRCE (0x4000u) +#define USB_FRMNUM_OVRN (0x8000u) + +#define USB_FRMNUM_FRNM_SHIFT (0) +/* #define USB_FRMNUM_RESERVED_SHIFT (11) */ +#define USB_FRMNUM_CRCE_SHIFT (14) +#define USB_FRMNUM_OVRN_SHIFT (15) + +/*==============================================*/ +/* UFRMNUM */ +/*==============================================*/ +#define USB_UFRMNUM_UFRNM (0x0007u) +/* #define USB_UFRMNUM_RESERVED (0xFFF8u) */ + +#define USB_UFRMNUM_UFRNM_SHIFT (0) +/* #define USB_UFRMNUM_RESERVED_SHIFT (3) */ + +/*==============================================*/ +/* USBADDR */ +/*==============================================*/ +#define USB_USBADDR_USBADDR (0x007Fu) +/* #define USB_USBADDR_RESERVED (0xFF80u) */ + +#define USB_USBADDR_USBADDR_SHIFT (0) +/* #define USB_USBADDR_RESERVED_SHIFT (7) */ + +/*==============================================*/ +/* USBREQ */ +/*==============================================*/ +#define USB_USBREQ_BMREQUESTTYPE (0x00FFu) +#define USB_USBREQ_BREQUEST (0xFF00u) + +#define USB_USBREQ_BMREQUESTTYPE_SHIFT (0) +#define USB_USBREQ_BREQUEST_SHIFT (8) + +/*==============================================*/ +/* USBVAL */ +/*==============================================*/ +#define USB_USBVAL (0xFFFFu) + +#define USB_USBVAL_SHIFT (0) + +/*==============================================*/ +/* USBINDX */ +/*==============================================*/ +#define USB_USBINDX (0xFFFFu) + +#define USB_USBINDX_SHIFT (0) + +/*==============================================*/ +/* USBLENG */ +/*==============================================*/ +#define USB_USBLENG (0xFFFFu) + +#define USB_USBLENG_SHIFT (0) + +/*==============================================*/ +/* DCPCFG */ +/*==============================================*/ +/* #define USB_DCPCFG_RESERVED1 (0x000Fu) */ +#define USB_DCPCFG_DIR (0x0010u) +/* #define USB_DCPCFG_RESERVED2 (0x0060u) */ +#define USB_DCPCFG_SHTNAK (0x0080u) +#define USB_DCPCFG_CNTMD (0x0100u) +/* #define USB_DCPCFG_RESERVED3 (0xFE00u) */ + +/* #define USB_DCPCFG_RESERVED1_SHIFT (0) */ +#define USB_DCPCFG_DIR_SHIFT (4) +/* #define USB_DCPCFG_RESERVED2_SHIFT (5) */ +#define USB_DCPCFG_SHTNK_SHIFT (7) +#define USB_DCPCFG_CNTMD_SHIFT (8) +/* #define USB_DCPCFG_RESERVED3 (9) */ + +/*==============================================*/ +/* DCPMAXP */ +/*==============================================*/ +#define USB_DCPMAXP_MXPS (0x007Fu) +/* #define USB_DCPMAXP_RESERVED (0x0F80u) */ +#define USB_DCPMAXP_DEVSEL (0xF000u) + +#define USB_DCPMAXP_MXPS_SHIFT (0) +/* #define USB_DCPMAXP_RESERVED_SHIFT (7) */ +#define USB_DCPMAXP_DEVSEL_SHIFT (12) + +/*==============================================*/ +/* DCPCTR */ +/*==============================================*/ +#define USB_DCPCTR_PID (0x0003u) +#define USB_DCPCTR_CCPL (0x0004u) +/* #define USB_DCPCTR_RESERVED1 (0x0008u) */ +#define USB_DCPCTR_PINGE (0x0010u) +#define USB_DCPCTR_PBUSY (0x0020u) +#define USB_DCPCTR_SQMON (0x0040u) +#define USB_DCPCTR_SQSET (0x0080u) +#define USB_DCPCTR_SQCLR (0x0100u) +/* #define USB_DCPCTR_RESERVED2 (0x0600u) */ +#define USB_DCPCTR_SUREQCLR (0x0800u) +#define USB_DCPCTR_CSSTS (0x1000u) +#define USB_DCPCTR_CSCLR (0x2000u) +#define USB_DCPCTR_SUREQ (0x4000u) +#define USB_DCPCTR_BSTS (0x8000u) + +#define USB_DCPCTR_PID_SHIFT (0) +#define USB_DCPCTR_CCPL_SHIFT (2) +/* #define USB_DCPCTR_RESERVED1_SHIFT (3) */ +#define USB_DCPCTR_PINGE_SHIFT (4) +#define USB_DCPCTR_PBUSY_SHIFT (5) +#define USB_DCPCTR_SQMON_SHIFT (6) +#define USB_DCPCTR_SQSET_SHIFT (7) +#define USB_DCPCTR_SQCLR_SHIFT (8) +/* #define USB_DCPCTR_RESERVED2_SHIFT (9) */ +#define USB_DCPCTR_SUREQCLR_SHIFT (11) +#define USB_DCPCTR_CSSTS_SHIFT (12) +#define USB_DCPCTR_CSCLR_SHIFT (13) +#define USB_DCPCTR_SUREQ_SHIFT (14) +#define USB_DCPCTR_BSTS_SHIFT (15) + +/*==============================================*/ +/* PIPESEL */ +/*==============================================*/ +#define USB_PIPESEL_PIPESEL (0x000Fu) +/* #define USB_PIPESEL_RESERVED (0xFFF0u) */ + +#define USB_PIPESEL_PIPESEL_SHIFT (0) +/* #define USB_PIPESEL_RESERVED_SHIFT (4) */ + +/*==============================================*/ +/* PIPECFG */ +/*==============================================*/ +#define USB_PIPECFG_EPNUM (0x000Fu) +#define USB_PIPECFG_DIR (0x0010u) +/* #define USB_PIPECFG_RESERVED1 (0x0060u) */ +#define USB_PIPECFG_SHTNAK (0x0080u) +#define USB_PIPECFG_CNTMD (0x0100u) +#define USB_PIPECFG_DBLB (0x0200u) +#define USB_PIPECFG_BFRE (0x0400u) +/* #define USB_PIPECFG_RESERVED2 (0x3800u) */ +#define USB_PIPECFG_TYPE (0xC000u) + +#define USB_PIPECFG_EPNUM_SHIFT (0) +#define USB_PIPECFG_DIR_SHIFT (4) +/* #define USB_PIPECFG_RESERVED1_SHIFT (5) */ +#define USB_PIPECFG_SHTNAK_SHIFT (7) +#define USB_PIPECFG_CNTMD_SHIFT (8) +#define USB_PIPECFG_DBLB_SHIFT (9) +#define USB_PIPECFG_BFRE_SHIFT (10) +/* #define USB_PIPECFG_RESERVED2_SHIFT (11) */ +#define USB_PIPECFG_TYPE_SHIFT (14) + +/*==============================================*/ +/* PIPEBUF */ +/*==============================================*/ +#define USB_PIPEBUF_BUFNMB (0x00FFu) +/* #define USB_PIPEBUF_RESERVED1 (0x0300u) */ +#define USB_PIPEBUF_BUFSIZE (0x7C00u) +/* #define USB_PIPEBUF_RESERVED2 (0x8000u) */ + +#define USB_PIPEBUF_BUFNMB_SHIFT (0) +/* #define USB_PIPEBUF_RESERVED1_SHIFT (8) */ +#define USB_PIPEBUF_BUFSIZE_SHIFT (10) +/* #define USB_PIPEBUF_RESERVED2_SHIFT (15) */ + +/*==============================================*/ +/* PIPEMAXP */ +/*==============================================*/ +#define USB_PIPEMAXP_MXPS (0x07FFu) +/* #define USB_PIPEMAXP_RESERVED (0x0800u) */ +#define USB_PIPEMAXP_DEVSEL (0xF000u) + +#define USB_PIPEMAXP_MXPS_SHIFT (0) +/* #define USB_PIPEMAXP_RESERVED_SHIFT (11) */ +#define USB_PIPEMAXP_DEVSEL_SHIFT (12) + +/*==============================================*/ +/* PIPEPERI */ +/*==============================================*/ +#define USB_PIPEPERI_IITV (0x0007u) +/* #define USB_PIPEPERI_RESERVED1 (0x0FF8u) */ +#define USB_PIPEPERI_IFIS (0x1000u) +/* #define USB_PIPEPERI_RESERVED2 (0xE000u) */ + +#define USB_PIPEPERI_IITV_SHIFT (0) +/* #define USB_PIPEPERI_RESERVED1_SHIFT (3) */ +#define USB_PIPEPERI_IFIS_SHIFT (12) +/* #define USB_PIPEPERI_RESERVED2_SHIFT (13) */ + +/*==============================================*/ +/* PIPEnCTR_1_5 */ +/*==============================================*/ +#define USB_PIPEnCTR_1_5_PID (0x0003u) +/* #define USB_PIPEnCTR_1_5_RESERVED1 (0x001Cu) */ +#define USB_PIPEnCTR_1_5_PBUSY (0x0020u) +#define USB_PIPEnCTR_1_5_SQMON (0x0040u) +#define USB_PIPEnCTR_1_5_SQSET (0x0080u) +#define USB_PIPEnCTR_1_5_SQCLR (0x0100u) +#define USB_PIPEnCTR_1_5_ACLRM (0x0200u) +#define USB_PIPEnCTR_1_5_ATREPM (0x0400u) +/* #define USB_PIPEnCTR_1_5_RESERVED2 (0x0800u) */ +#define USB_PIPEnCTR_1_5_CSSTS (0x1000u) +#define USB_PIPEnCTR_1_5_CSCLR (0x2000u) +#define USB_PIPEnCTR_1_5_INBUFM (0x4000u) +#define USB_PIPEnCTR_1_5_BSTS (0x8000u) + +#define USB_PIPEnCTR_1_5_PID_SHIFT (0) +/* #define USB_PIPEnCTR_1_5_RESERVED1_SHIFT (2) */ +#define USB_PIPEnCTR_1_5_PBUSY_SHIFT (5) +#define USB_PIPEnCTR_1_5_SQMON_SHIFT (6) +#define USB_PIPEnCTR_1_5_SQSET_SHIFT (7) +#define USB_PIPEnCTR_1_5_SQCLR_SHIFT (8) +#define USB_PIPEnCTR_1_5_ACLRM_SHIFT (9) +#define USB_PIPEnCTR_1_5_ATREPM_SHIFT (10) +/* #define USB_PIPEnCTR_1_5_RESERVED2_SHIFT (11) */ +#define USB_PIPEnCTR_1_5_CSSTS_SHIFT (12) +#define USB_PIPEnCTR_1_5_CSCLR_SHIFT (13) +#define USB_PIPEnCTR_1_5_INBUFM_SHIFT (14) +#define USB_PIPEnCTR_1_5_BSTS_SHIFT (15) + +/*==============================================*/ +/* PIPEnCTR_6_8 */ +/*==============================================*/ +#define USB_PIPEnCTR_6_8_PID (0x0003u) +/* #define USB_PIPEnCTR_6_8_RESERVED1 (0x001Cu) */ +#define USB_PIPEnCTR_6_8_PBUSY (0x0020u) +#define USB_PIPEnCTR_6_8_SQMON (0x0040u) +#define USB_PIPEnCTR_6_8_SQSET (0x0080u) +#define USB_PIPEnCTR_6_8_SQCLR (0x0100u) +#define USB_PIPEnCTR_6_8_ACLRM (0x0200u) +/* #define USB_PIPEnCTR_6_8_RESERVED2 (0x0C00u) */ +#define USB_PIPEnCTR_6_8_CSSTS (0x1000u) +#define USB_PIPEnCTR_6_8_CSCLR (0x2000u) +/* #define USB_PIPEnCTR_6_8_RESERVED3 (0x4000u) */ +#define USB_PIPEnCTR_6_8_BSTS (0x8000u) + +#define USB_PIPEnCTR_6_8_PID_SHIFT (0) +/* #define USB_PIPEnCTR_6_8_RESERVED1_SHIFT (2) */ +#define USB_PIPEnCTR_6_8_PBUSY_SHIFT (5) +#define USB_PIPEnCTR_6_8_SQMON_SHIFT (6) +#define USB_PIPEnCTR_6_8_SQSET_SHIFT (7) +#define USB_PIPEnCTR_6_8_SQCLR_SHIFT (8) +#define USB_PIPEnCTR_6_8_ACLRM_SHIFT (9) +/* #define USB_PIPEnCTR_6_8_RESERVED2_SHIFT (10) */ +#define USB_PIPEnCTR_6_8_CSSTS_SHIFT (12) +#define USB_PIPEnCTR_6_8_CSCLR_SHIFT (13) +/* #define USB_PIPEnCTR_6_8_RESERVED3_SHIFT (14) */ +#define USB_PIPEnCTR_6_8_BSTS_SHIFT (15) + +/*==============================================*/ +/* PIPEnCTR_9 */ +/*==============================================*/ +#define USB_PIPEnCTR_9_PID (0x0003u) +/* #define USB_PIPEnCTR_9_RESERVED1 (0x001Cu) */ +#define USB_PIPEnCTR_9_PBUSY (0x0020u) +#define USB_PIPEnCTR_9_SQMON (0x0040u) +#define USB_PIPEnCTR_9_SQSET (0x0080u) +#define USB_PIPEnCTR_9_SQCLR (0x0100u) +#define USB_PIPEnCTR_9_ACLRM (0x0200u) +#define USB_PIPEnCTR_9_ATREPM (0x0400u) +/* #define USB_PIPEnCTR_9_RESERVED2 (0x0800u) */ +#define USB_PIPEnCTR_9_CSSTS (0x1000u) +#define USB_PIPEnCTR_9_CSCLR (0x2000u) +#define USB_PIPEnCTR_9_INBUFM (0x4000u) +#define USB_PIPEnCTR_9_BSTS (0x8000u) + +#define USB_PIPEnCTR_9_PID_SHIFT (0) +/* #define USB_PIPEnCTR_9_RESERVED1_SHIFT (2) */ +#define USB_PIPEnCTR_9_PBUSY_SHIFT (5) +#define USB_PIPEnCTR_9_SQMON_SHIFT (6) +#define USB_PIPEnCTR_9_SQSET_SHIFT (7) +#define USB_PIPEnCTR_9_SQCLR_SHIFT (8) +#define USB_PIPEnCTR_9_ACLRM_SHIFT (9) +#define USB_PIPEnCTR_9_ATREPM_SHIFT (10) +/* #define USB_PIPEnCTR_9_RESERVED2_SHIFT (11) */ +#define USB_PIPEnCTR_9_CSSTS_SHIFT (12) +#define USB_PIPEnCTR_9_CSCLR_SHIFT (13) +#define USB_PIPEnCTR_9_INBUFM_SHIFT (14) +#define USB_PIPEnCTR_9_BSTS_SHIFT (15) + +/*==============================================*/ +/* PIPEnCTR_A_F */ +/*==============================================*/ +#define USB_PIPEnCTR_A_F_PID (0x0003u) +/* #define USB_PIPEnCTR_A_F_RESERVED1 (0x001Cu) */ +#define USB_PIPEnCTR_A_F_PBUSY (0x0020u) +#define USB_PIPEnCTR_A_F_SQMON (0x0040u) +#define USB_PIPEnCTR_A_F_SQSET (0x0080u) +#define USB_PIPEnCTR_A_F_SQCLR (0x0100u) +#define USB_PIPEnCTR_A_F_ACLRM (0x0200u) +#define USB_PIPEnCTR_A_F_ATREPM (0x0400u) +/* #define USB_PIPEnCTR_A_F_RESERVED2 (0x3800u) */ +#define USB_PIPEnCTR_A_F_INBUFM (0x4000u) +#define USB_PIPEnCTR_A_F_BSTS (0x8000u) + +#define USB_PIPEnCTR_A_F_PID_SHIFT (0) +/* #define USB_PIPEnCTR_A_F_RESERVED1_SHIFT (2) */ +#define USB_PIPEnCTR_A_F_PBUSY_SHIFT (5) +#define USB_PIPEnCTR_A_F_SQMON_SHIFT (6) +#define USB_PIPEnCTR_A_F_SQSET_SHIFT (7) +#define USB_PIPEnCTR_A_F_SQCLR_SHIFT (8) +#define USB_PIPEnCTR_A_F_ACLRM_SHIFT (9) +#define USB_PIPEnCTR_A_F_ATREPM_SHIFT (10) +/* #define USB_PIPEnCTR_A_F_RESERVED2_SHIFT (11) */ +#define USB_PIPEnCTR_A_F_INBUFM_SHIFT (14) +#define USB_PIPEnCTR_A_F_BSTS_SHIFT (15) + +/*==============================================*/ +/* PIPEnTRE */ +/*==============================================*/ +/* #define USB_PIPEnTRE_RESERVED1 (0x00FFu) */ +#define USB_PIPEnTRE_TRCLR (0x0100u) +#define USB_PIPEnTRE_TRENB (0x0200u) +/* #define USB_PIPEnTRE_RESERVED2 (0xFC00u) */ + +/* #define USB_PIPEnTRE_RESERVED1_SHIFT (0) */ +#define USB_PIPEnTRE_TRCLR_SHIFT (8) +#define USB_PIPEnTRE_TRENB_SHIFT (9) +/* #define USB_PIPEnTRE_RESERVED2_SHIFT (10) */ + +/*==============================================*/ +/* PIPEnTRN */ +/*==============================================*/ +#define USB_PIPEnTRN (0xFFFFu) + +#define USB_PIPEnTRN_SHIFT (0) + +/*==============================================*/ +/* DEVADDn */ +/*==============================================*/ +/* #define USB_DEVADDn_RESERVED1 (0x003Fu) */ +#define USB_DEVADDn_USBSPD (0x00C0u) +#define USB_DEVADDn_HUBPORT (0x0700u) +#define USB_DEVADDn_UPPHUB (0x7800u) +/* #define USB_DEVADDn_RESERVED2 (0x8000u) */ + +/* #define USB_DEVADDn_RESERVED1_SHIFT (0) */ +#define USB_DEVADDn_USBSPD_SHIFT (6) +#define USB_DEVADDn_HUBPORT_SHIFT (8) +#define USB_DEVADDn_UPPHUB_SHIFT (11) +/* #define USB_DEVADDn_RESERVED2_SHIFT (15) */ + +/*==============================================*/ +/* SUSPMODE */ +/*==============================================*/ +/* #define USB_SUSPMODE_RESERVED1 (0x3FFFu) */ +#define USB_SUSPMODE_SUSPM (0x4000u) +/* #define USB_SUSPMODE_RESERVED2 (0x8000u) */ + +/* #define USB_SUSPMODE_RESERVED1_SHIFT (0) */ +#define USB_SUSPMODE_SUSPM_SHIFT (14) +/* #define USB_SUSPMODE_RESERVED2_SHIFT (15) */ + +/*==============================================*/ +/* DnFIFOBm */ +/*==============================================*/ +#define USB_DnFIFOBm (0xFFFFu) + +#define USB_DnFIFOBm_SHIFT (0) + +#endif /* USB_IOBITMASK_H */ + +/* End of File */ diff --git a/targets/TARGET_RENESAS/TARGET_RZ_A1XX/TARGET_GR_LYCHEE/device/inc/iodefine.h b/targets/TARGET_RENESAS/TARGET_RZ_A1XX/TARGET_GR_LYCHEE/device/inc/iodefine.h new file mode 100644 index 0000000..6a8b1ae --- /dev/null +++ b/targets/TARGET_RENESAS/TARGET_RZ_A1XX/TARGET_GR_LYCHEE/device/inc/iodefine.h @@ -0,0 +1,63 @@ +/******************************************************************************* +* DISCLAIMER +* This software is supplied by Renesas Electronics Corporation and is only +* intended for use with Renesas products. No other uses are authorized. This +* software is owned by Renesas Electronics Corporation and is protected under +* all applicable laws, including copyright laws. +* THIS SOFTWARE IS PROVIDED "AS IS" AND RENESAS MAKES NO WARRANTIES REGARDING +* THIS SOFTWARE, WHETHER EXPRESS, IMPLIED OR STATUTORY, INCLUDING BUT NOT +* LIMITED TO WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE +* AND NON-INFRINGEMENT. ALL SUCH WARRANTIES ARE EXPRESSLY DISCLAIMED. +* TO THE MAXIMUM EXTENT PERMITTED NOT PROHIBITED BY LAW, NEITHER RENESAS +* ELECTRONICS CORPORATION NOR ANY OF ITS AFFILIATED COMPANIES SHALL BE LIABLE +* FOR ANY DIRECT, INDIRECT, SPECIAL, INCIDENTAL OR CONSEQUENTIAL DAMAGES FOR +* ANY REASON RELATED TO THIS SOFTWARE, EVEN IF RENESAS OR ITS AFFILIATES HAVE +* BEEN ADVISED OF THE POSSIBILITY OF SUCH DAMAGES. +* Renesas reserves the right, without notice, to make changes to this software +* and to discontinue the availability of this software. By using this software, +* you agree to the additional terms and conditions found by accessing the +* following link: +* http://www.renesas.com/disclaimer* +* Copyright (C) 2013-2016 Renesas Electronics Corporation. All rights reserved. +*******************************************************************************/ +/******************************************************************************* +* File Name : iodefine.h +* $Rev: $ +* $Date:: $ +* Description : Definition of I/O Register for RZ/A1LU (V3.00l) +******************************************************************************/ +#ifndef R7S721030_IODEFINE_H +#define R7S721030_IODEFINE_H + +#include "iodefines/iodefine_typedef.h" /* (V3.00l) */ + +#include "iodefines/adc_iodefine.h" /* (V3.00l) */ +#include "iodefines/bsc_iodefine.h" /* (V3.00l) */ +#include "iodefines/ceu_iodefine.h" /* (V3.00l) */ +#include "iodefines/cpg_iodefine.h" /* (V3.00l) */ +#include "iodefines/dmac_iodefine.h" /* (V3.00l) */ +#include "iodefines/ethavb_iodefine.h" /* (V3.00l) */ +#include "iodefines/ether_iodefine.h" /* (V3.00l) */ +#include "iodefines/gpio_iodefine.h" /* (V3.00l) */ +#include "iodefines/inb_iodefine.h" /* (V3.00l) */ +#include "iodefines/intc_iodefine.h" /* (V3.00l) */ +#include "iodefines/irda_iodefine.h" /* (V3.00l) */ +#include "iodefines/jcu_iodefine.h" /* (V3.00l) */ +#include "iodefines/l2c_iodefine.h" /* (V3.00l) */ +#include "iodefines/mmc_iodefine.h" /* (V3.00l) */ +#include "iodefines/mtu2_iodefine.h" /* (V3.00l) */ +#include "iodefines/ostm_iodefine.h" /* (V3.00l) */ +#include "iodefines/riic_iodefine.h" /* (V3.00l) */ +#include "iodefines/rscan0_iodefine.h" /* (V3.00l) */ +#include "iodefines/rspi_iodefine.h" /* (V3.00l) */ +#include "iodefines/rtc_iodefine.h" /* (V3.00l) */ +#include "iodefines/scif_iodefine.h" /* (V3.00l) */ +#include "iodefines/scim_iodefine.h" /* (V3.00l) */ +#include "iodefines/scux_iodefine.h" /* (V3.00l) */ +#include "iodefines/spdif_iodefine.h" /* (V3.00l) */ +#include "iodefines/spibsc_iodefine.h" /* (V3.00l) */ +#include "iodefines/ssif_iodefine.h" /* (V3.00l) */ +#include "iodefines/usb20_iodefine.h" /* (V3.00l) */ +#include "iodefines/vdc5_iodefine.h" /* (V3.00l) */ +#include "iodefines/wdt_iodefine.h" /* (V3.00l) */ +#endif diff --git a/targets/TARGET_RENESAS/TARGET_RZ_A1XX/TARGET_GR_LYCHEE/device/inc/iodefines/adc_iodefine.h b/targets/TARGET_RENESAS/TARGET_RZ_A1XX/TARGET_GR_LYCHEE/device/inc/iodefines/adc_iodefine.h new file mode 100644 index 0000000..6dc5408 --- /dev/null +++ b/targets/TARGET_RENESAS/TARGET_RZ_A1XX/TARGET_GR_LYCHEE/device/inc/iodefines/adc_iodefine.h @@ -0,0 +1,107 @@ +/******************************************************************************* +* DISCLAIMER +* This software is supplied by Renesas Electronics Corporation and is only +* intended for use with Renesas products. No other uses are authorized. This +* software is owned by Renesas Electronics Corporation and is protected under +* all applicable laws, including copyright laws. +* THIS SOFTWARE IS PROVIDED "AS IS" AND RENESAS MAKES NO WARRANTIES REGARDING +* THIS SOFTWARE, WHETHER EXPRESS, IMPLIED OR STATUTORY, INCLUDING BUT NOT +* LIMITED TO WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE +* AND NON-INFRINGEMENT. ALL SUCH WARRANTIES ARE EXPRESSLY DISCLAIMED. +* TO THE MAXIMUM EXTENT PERMITTED NOT PROHIBITED BY LAW, NEITHER RENESAS +* ELECTRONICS CORPORATION NOR ANY OF ITS AFFILIATED COMPANIES SHALL BE LIABLE +* FOR ANY DIRECT, INDIRECT, SPECIAL, INCIDENTAL OR CONSEQUENTIAL DAMAGES FOR +* ANY REASON RELATED TO THIS SOFTWARE, EVEN IF RENESAS OR ITS AFFILIATES HAVE +* BEEN ADVISED OF THE POSSIBILITY OF SUCH DAMAGES. +* Renesas reserves the right, without notice, to make changes to this software +* and to discontinue the availability of this software. By using this software, +* you agree to the additional terms and conditions found by accessing the +* following link: +* http://www.renesas.com/disclaimer* +* Copyright (C) 2013-2016 Renesas Electronics Corporation. All rights reserved. +*******************************************************************************/ +/******************************************************************************* +* File Name : adc_iodefine.h +* $Rev: $ +* $Date:: $ +* Description : Definition of I/O Register for RZ/A1LU (V3.00l) +******************************************************************************/ +#ifndef ADC_IODEFINE_H +#define ADC_IODEFINE_H +/* ->QAC 0639 : Over 127 members (C90) */ +/* ->QAC 0857 : Over 1024 #define (C90) */ +/* ->MISRA 18.4 : Pack unpack union */ /* ->SEC M1.6.2 */ +/* ->SEC M1.10.1 : Not magic number */ + +#define ADC (*(struct st_adc *)0xE8005800uL) /* ADC */ + + +#define ADCADDRA (ADC.ADDRA) +#define ADCADDRB (ADC.ADDRB) +#define ADCADDRC (ADC.ADDRC) +#define ADCADDRD (ADC.ADDRD) +#define ADCADDRE (ADC.ADDRE) +#define ADCADDRF (ADC.ADDRF) +#define ADCADDRG (ADC.ADDRG) +#define ADCADDRH (ADC.ADDRH) +#define ADCADCMPHA (ADC.ADCMPHA) +#define ADCADCMPLA (ADC.ADCMPLA) +#define ADCADCMPHB (ADC.ADCMPHB) +#define ADCADCMPLB (ADC.ADCMPLB) +#define ADCADCMPHC (ADC.ADCMPHC) +#define ADCADCMPLC (ADC.ADCMPLC) +#define ADCADCMPHD (ADC.ADCMPHD) +#define ADCADCMPLD (ADC.ADCMPLD) +#define ADCADCMPHE (ADC.ADCMPHE) +#define ADCADCMPLE (ADC.ADCMPLE) +#define ADCADCMPHF (ADC.ADCMPHF) +#define ADCADCMPLF (ADC.ADCMPLF) +#define ADCADCMPHG (ADC.ADCMPHG) +#define ADCADCMPLG (ADC.ADCMPLG) +#define ADCADCMPHH (ADC.ADCMPHH) +#define ADCADCMPLH (ADC.ADCMPLH) +#define ADCADCSR (ADC.ADCSR) +#define ADCADCMPER (ADC.ADCMPER) +#define ADCADCMPSR (ADC.ADCMPSR) + + +typedef struct st_adc +{ + /* ADC */ + volatile uint16_t ADDRA; /* ADDRA */ + volatile uint16_t ADDRB; /* ADDRB */ + volatile uint16_t ADDRC; /* ADDRC */ + volatile uint16_t ADDRD; /* ADDRD */ + volatile uint16_t ADDRE; /* ADDRE */ + volatile uint16_t ADDRF; /* ADDRF */ + volatile uint16_t ADDRG; /* ADDRG */ + volatile uint16_t ADDRH; /* ADDRH */ + volatile uint8_t dummy32[16]; /* */ + volatile uint16_t ADCMPHA; /* ADCMPHA */ + volatile uint16_t ADCMPLA; /* ADCMPLA */ + volatile uint16_t ADCMPHB; /* ADCMPHB */ + volatile uint16_t ADCMPLB; /* ADCMPLB */ + volatile uint16_t ADCMPHC; /* ADCMPHC */ + volatile uint16_t ADCMPLC; /* ADCMPLC */ + volatile uint16_t ADCMPHD; /* ADCMPHD */ + volatile uint16_t ADCMPLD; /* ADCMPLD */ + volatile uint16_t ADCMPHE; /* ADCMPHE */ + volatile uint16_t ADCMPLE; /* ADCMPLE */ + volatile uint16_t ADCMPHF; /* ADCMPHF */ + volatile uint16_t ADCMPLF; /* ADCMPLF */ + volatile uint16_t ADCMPHG; /* ADCMPHG */ + volatile uint16_t ADCMPLG; /* ADCMPLG */ + volatile uint16_t ADCMPHH; /* ADCMPHH */ + volatile uint16_t ADCMPLH; /* ADCMPLH */ + volatile uint8_t dummy33[32]; /* */ + volatile uint16_t ADCSR; /* ADCSR */ + volatile uint16_t ADCMPER; /* ADCMPER */ + volatile uint16_t ADCMPSR; /* ADCMPSR */ +} r_io_adc_t; + + +/* <-SEC M1.10.1 */ +/* <-MISRA 18.4 */ /* <-SEC M1.6.2 */ +/* <-QAC 0857 */ +/* <-QAC 0639 */ +#endif diff --git a/targets/TARGET_RENESAS/TARGET_RZ_A1XX/TARGET_GR_LYCHEE/device/inc/iodefines/bsc_iodefine.h b/targets/TARGET_RENESAS/TARGET_RZ_A1XX/TARGET_GR_LYCHEE/device/inc/iodefines/bsc_iodefine.h new file mode 100644 index 0000000..75897fd --- /dev/null +++ b/targets/TARGET_RENESAS/TARGET_RZ_A1XX/TARGET_GR_LYCHEE/device/inc/iodefines/bsc_iodefine.h @@ -0,0 +1,115 @@ +/******************************************************************************* +* DISCLAIMER +* This software is supplied by Renesas Electronics Corporation and is only +* intended for use with Renesas products. No other uses are authorized. This +* software is owned by Renesas Electronics Corporation and is protected under +* all applicable laws, including copyright laws. +* THIS SOFTWARE IS PROVIDED "AS IS" AND RENESAS MAKES NO WARRANTIES REGARDING +* THIS SOFTWARE, WHETHER EXPRESS, IMPLIED OR STATUTORY, INCLUDING BUT NOT +* LIMITED TO WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE +* AND NON-INFRINGEMENT. ALL SUCH WARRANTIES ARE EXPRESSLY DISCLAIMED. +* TO THE MAXIMUM EXTENT PERMITTED NOT PROHIBITED BY LAW, NEITHER RENESAS +* ELECTRONICS CORPORATION NOR ANY OF ITS AFFILIATED COMPANIES SHALL BE LIABLE +* FOR ANY DIRECT, INDIRECT, SPECIAL, INCIDENTAL OR CONSEQUENTIAL DAMAGES FOR +* ANY REASON RELATED TO THIS SOFTWARE, EVEN IF RENESAS OR ITS AFFILIATES HAVE +* BEEN ADVISED OF THE POSSIBILITY OF SUCH DAMAGES. +* Renesas reserves the right, without notice, to make changes to this software +* and to discontinue the availability of this software. By using this software, +* you agree to the additional terms and conditions found by accessing the +* following link: +* http://www.renesas.com/disclaimer* +* Copyright (C) 2013-2016 Renesas Electronics Corporation. All rights reserved. +*******************************************************************************/ +/******************************************************************************* +* File Name : bsc_iodefine.h +* $Rev: $ +* $Date:: $ +* Description : Definition of I/O Register for RZ/A1LU (V3.00l) +******************************************************************************/ +#ifndef BSC_IODEFINE_H +#define BSC_IODEFINE_H +/* ->QAC 0639 : Over 127 members (C90) */ +/* ->QAC 0857 : Over 1024 #define (C90) */ +/* ->MISRA 18.4 : Pack unpack union */ /* ->SEC M1.6.2 */ +/* ->SEC M1.10.1 : Not magic number */ + +#define BSC (*(struct st_bsc *)0x3FFFC000uL) /* BSC */ + + +#define BSCCMNCR (BSC.CMNCR) +#define BSCCS0BCR (BSC.CS0BCR) +#define BSCCS1BCR (BSC.CS1BCR) +#define BSCCS2BCR (BSC.CS2BCR) +#define BSCCS3BCR (BSC.CS3BCR) +#define BSCCS4BCR (BSC.CS4BCR) +#define BSCCS5BCR (BSC.CS5BCR) +#define BSCCS0WCR (BSC.CS0WCR) +#define BSCCS1WCR (BSC.CS1WCR) +#define BSCCS2WCR (BSC.CS2WCR) +#define BSCCS3WCR (BSC.CS3WCR) +#define BSCCS4WCR (BSC.CS4WCR) +#define BSCCS5WCR (BSC.CS5WCR) +#define BSCSDCR (BSC.SDCR) +#define BSCRTCSR (BSC.RTCSR) +#define BSCRTCNT (BSC.RTCNT) +#define BSCRTCOR (BSC.RTCOR) +#define BSCTOSCOR0 (BSC.TOSCOR0) +#define BSCTOSCOR1 (BSC.TOSCOR1) +#define BSCTOSCOR2 (BSC.TOSCOR2) +#define BSCTOSCOR3 (BSC.TOSCOR3) +#define BSCTOSCOR4 (BSC.TOSCOR4) +#define BSCTOSCOR5 (BSC.TOSCOR5) +#define BSCTOSTR (BSC.TOSTR) +#define BSCTOENR (BSC.TOENR) + +#define BSC_CSnBCR_COUNT (6) +#define BSC_CSnWCR_COUNT (6) +#define BSC_TOSCORn_COUNT (6) + + +typedef struct st_bsc +{ + /* BSC */ + volatile uint32_t CMNCR; /* CMNCR */ + +/* #define BSC_CSnBCR_COUNT (6) */ + volatile uint32_t CS0BCR; /* CS0BCR */ + volatile uint32_t CS1BCR; /* CS1BCR */ + volatile uint32_t CS2BCR; /* CS2BCR */ + volatile uint32_t CS3BCR; /* CS3BCR */ + volatile uint32_t CS4BCR; /* CS4BCR */ + volatile uint32_t CS5BCR; /* CS5BCR */ + volatile uint8_t dummy4[12]; /* */ + +/* #define BSC_CSnWCR_COUNT (6) */ + volatile uint32_t CS0WCR; /* CS0WCR */ + volatile uint32_t CS1WCR; /* CS1WCR */ + volatile uint32_t CS2WCR; /* CS2WCR */ + volatile uint32_t CS3WCR; /* CS3WCR */ + volatile uint32_t CS4WCR; /* CS4WCR */ + volatile uint32_t CS5WCR; /* CS5WCR */ + volatile uint8_t dummy5[12]; /* */ + volatile uint32_t SDCR; /* SDCR */ + volatile uint32_t RTCSR; /* RTCSR */ + volatile uint32_t RTCNT; /* RTCNT */ + volatile uint32_t RTCOR; /* RTCOR */ + volatile uint8_t dummy6[4]; /* */ + +/* #define BSC_TOSCORn_COUNT (6) */ + volatile uint32_t TOSCOR0; /* TOSCOR0 */ + volatile uint32_t TOSCOR1; /* TOSCOR1 */ + volatile uint32_t TOSCOR2; /* TOSCOR2 */ + volatile uint32_t TOSCOR3; /* TOSCOR3 */ + volatile uint32_t TOSCOR4; /* TOSCOR4 */ + volatile uint32_t TOSCOR5; /* TOSCOR5 */ + volatile uint8_t dummy7[8]; /* */ + volatile uint32_t TOSTR; /* TOSTR */ + volatile uint32_t TOENR; /* TOENR */ +} r_io_bsc_t; + + +/* <-SEC M1.10.1 */ +/* <-MISRA 18.4 */ /* <-SEC M1.6.2 */ +/* <-QAC 0857 */ +/* <-QAC 0639 */ +#endif diff --git a/targets/TARGET_RENESAS/TARGET_RZ_A1XX/TARGET_GR_LYCHEE/device/inc/iodefines/ceu_iodefine.h b/targets/TARGET_RENESAS/TARGET_RZ_A1XX/TARGET_GR_LYCHEE/device/inc/iodefines/ceu_iodefine.h new file mode 100644 index 0000000..2a40d0e --- /dev/null +++ b/targets/TARGET_RENESAS/TARGET_RZ_A1XX/TARGET_GR_LYCHEE/device/inc/iodefines/ceu_iodefine.h @@ -0,0 +1,295 @@ +/******************************************************************************* +* DISCLAIMER +* This software is supplied by Renesas Electronics Corporation and is only +* intended for use with Renesas products. No other uses are authorized. This +* software is owned by Renesas Electronics Corporation and is protected under +* all applicable laws, including copyright laws. +* THIS SOFTWARE IS PROVIDED "AS IS" AND RENESAS MAKES NO WARRANTIES REGARDING +* THIS SOFTWARE, WHETHER EXPRESS, IMPLIED OR STATUTORY, INCLUDING BUT NOT +* LIMITED TO WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE +* AND NON-INFRINGEMENT. ALL SUCH WARRANTIES ARE EXPRESSLY DISCLAIMED. +* TO THE MAXIMUM EXTENT PERMITTED NOT PROHIBITED BY LAW, NEITHER RENESAS +* ELECTRONICS CORPORATION NOR ANY OF ITS AFFILIATED COMPANIES SHALL BE LIABLE +* FOR ANY DIRECT, INDIRECT, SPECIAL, INCIDENTAL OR CONSEQUENTIAL DAMAGES FOR +* ANY REASON RELATED TO THIS SOFTWARE, EVEN IF RENESAS OR ITS AFFILIATES HAVE +* BEEN ADVISED OF THE POSSIBILITY OF SUCH DAMAGES. +* Renesas reserves the right, without notice, to make changes to this software +* and to discontinue the availability of this software. By using this software, +* you agree to the additional terms and conditions found by accessing the +* following link: +* http://www.renesas.com/disclaimer* +* Copyright (C) 2013-2016 Renesas Electronics Corporation. All rights reserved. +*******************************************************************************/ +/******************************************************************************* +* File Name : ceu_iodefine.h +* $Rev: $ +* $Date:: $ +* Description : Definition of I/O Register for RZ/A1LU (V3.00l) +******************************************************************************/ +#ifndef CEU_IODEFINE_H +#define CEU_IODEFINE_H +/* ->QAC 0639 : Over 127 members (C90) */ +/* ->QAC 0857 : Over 1024 #define (C90) */ +/* ->MISRA 18.4 : Pack unpack union */ /* ->SEC M1.6.2 */ +/* ->SEC M1.10.1 : Not magic number */ + +#define CEU (*(struct st_ceu *)0xE8210000uL) /* CEU */ + + +/* Start of channel array defines of CEU */ + +/* Channel array defines of CEUn */ +/*(Sample) value = CEUn[ channel ]->CAMOR; */ +#define CEUn_COUNT (3) +#define CEUn_ADDRESS_LIST \ +{ /* ->MISRA 11.3 */ /* ->SEC R2.7.1 */ \ + (volatile struct st_ceu_n*)&CEU_A, \ + (volatile struct st_ceu_n*)&CEU_B, \ + (volatile struct st_ceu_n*)&CEU_M \ +} /* <-MISRA 11.3 */ /* <-SEC R2.7.1 */ /* { } is for MISRA 19.4 */ +#define CEU_A (*(struct st_ceu_n *)&CEU.CAPSR) /* CEU_A */ +#define CEU_B (*(struct st_ceu_n *)&CEU.dummy3111) /* CEU_B */ +#define CEU_M (*(struct st_ceu_n *)&CEU.dummy3151) /* CEU_M */ + +/* End of channel array defines of CEU */ + + +#define CEUCAPSR (CEU.CAPSR) +#define CEUCAPCR (CEU.CAPCR) +#define CEUCAMCR (CEU.CAMCR) +#define CEUCMCYR (CEU.CMCYR) +#define CEUCAMOR_A (CEU.CAMOR_A) +#define CEUCAPWR_A (CEU.CAPWR_A) +#define CEUCAIFR (CEU.CAIFR) +#define CEUCRCNTR (CEU.CRCNTR) +#define CEUCRCMPR (CEU.CRCMPR) +#define CEUCFLCR_A (CEU.CFLCR_A) +#define CEUCFSZR_A (CEU.CFSZR_A) +#define CEUCDWDR_A (CEU.CDWDR_A) +#define CEUCDAYR_A (CEU.CDAYR_A) +#define CEUCDACR_A (CEU.CDACR_A) +#define CEUCDBYR_A (CEU.CDBYR_A) +#define CEUCDBCR_A (CEU.CDBCR_A) +#define CEUCBDSR_A (CEU.CBDSR_A) +#define CEUCFWCR (CEU.CFWCR) +#define CEUCLFCR_A (CEU.CLFCR_A) +#define CEUCDOCR_A (CEU.CDOCR_A) +#define CEUCEIER (CEU.CEIER) +#define CEUCETCR (CEU.CETCR) +#define CEUCSTSR (CEU.CSTSR) +#define CEUCDSSR (CEU.CDSSR) +#define CEUCDAYR2_A (CEU.CDAYR2_A) +#define CEUCDACR2_A (CEU.CDACR2_A) +#define CEUCDBYR2_A (CEU.CDBYR2_A) +#define CEUCDBCR2_A (CEU.CDBCR2_A) +#define CEUCAMOR_B (CEU.CAMOR_B) +#define CEUCAPWR_B (CEU.CAPWR_B) +#define CEUCFLCR_B (CEU.CFLCR_B) +#define CEUCFSZR_B (CEU.CFSZR_B) +#define CEUCDWDR_B (CEU.CDWDR_B) +#define CEUCDAYR_B (CEU.CDAYR_B) +#define CEUCDACR_B (CEU.CDACR_B) +#define CEUCDBYR_B (CEU.CDBYR_B) +#define CEUCDBCR_B (CEU.CDBCR_B) +#define CEUCBDSR_B (CEU.CBDSR_B) +#define CEUCLFCR_B (CEU.CLFCR_B) +#define CEUCDOCR_B (CEU.CDOCR_B) +#define CEUCDAYR2_B (CEU.CDAYR2_B) +#define CEUCDACR2_B (CEU.CDACR2_B) +#define CEUCDBYR2_B (CEU.CDBYR2_B) +#define CEUCDBCR2_B (CEU.CDBCR2_B) +#define CEUCAMOR_M (CEU.CAMOR_M) +#define CEUCAPWR_M (CEU.CAPWR_M) +#define CEUCFLCR_M (CEU.CFLCR_M) +#define CEUCFSZR_M (CEU.CFSZR_M) +#define CEUCDWDR_M (CEU.CDWDR_M) +#define CEUCDAYR_M (CEU.CDAYR_M) +#define CEUCDACR_M (CEU.CDACR_M) +#define CEUCDBYR_M (CEU.CDBYR_M) +#define CEUCDBCR_M (CEU.CDBCR_M) +#define CEUCBDSR_M (CEU.CBDSR_M) +#define CEUCLFCR_M (CEU.CLFCR_M) +#define CEUCDOCR_M (CEU.CDOCR_M) +#define CEUCDAYR2_M (CEU.CDAYR2_M) +#define CEUCDACR2_M (CEU.CDACR2_M) +#define CEUCDBYR2_M (CEU.CDBYR2_M) +#define CEUCDBCR2_M (CEU.CDBCR2_M) + + +typedef struct st_ceu +{ + /* CEU */ + +/* start of struct st_ceu_n */ + volatile uint32_t CAPSR; /* CAPSR */ + volatile uint32_t CAPCR; /* CAPCR */ + volatile uint32_t CAMCR; /* CAMCR */ + volatile uint32_t CMCYR; /* CMCYR */ + volatile uint32_t CAMOR_A; /* CAMOR_A */ + volatile uint32_t CAPWR_A; /* CAPWR_A */ + volatile uint32_t CAIFR; /* CAIFR */ + volatile uint8_t dummy305[12]; /* */ + volatile uint32_t CRCNTR; /* CRCNTR */ + volatile uint32_t CRCMPR; /* CRCMPR */ + volatile uint32_t CFLCR_A; /* CFLCR_A */ + volatile uint32_t CFSZR_A; /* CFSZR_A */ + volatile uint32_t CDWDR_A; /* CDWDR_A */ + volatile uint32_t CDAYR_A; /* CDAYR_A */ + volatile uint32_t CDACR_A; /* CDACR_A */ + volatile uint32_t CDBYR_A; /* CDBYR_A */ + volatile uint32_t CDBCR_A; /* CDBCR_A */ + volatile uint32_t CBDSR_A; /* CBDSR_A */ + volatile uint8_t dummy306[12]; /* */ + volatile uint32_t CFWCR; /* CFWCR */ + volatile uint32_t CLFCR_A; /* CLFCR_A */ + volatile uint32_t CDOCR_A; /* CDOCR_A */ + volatile uint8_t dummy307[8]; /* */ + volatile uint32_t CEIER; /* CEIER */ + volatile uint32_t CETCR; /* CETCR */ + volatile uint8_t dummy308[4]; /* */ + volatile uint32_t CSTSR; /* CSTSR */ + volatile uint8_t dummy309[4]; /* */ + volatile uint32_t CDSSR; /* CDSSR */ + volatile uint8_t dummy310[8]; /* */ + volatile uint32_t CDAYR2_A; /* CDAYR2_A */ + volatile uint32_t CDACR2_A; /* CDACR2_A */ + volatile uint32_t CDBYR2_A; /* CDBYR2_A */ + volatile uint32_t CDBCR2_A; /* CDBCR2_A */ + +/* end of struct st_ceu_n */ + volatile uint8_t dummy3110[3936]; /* */ + +/* start of struct st_ceu_n */ + volatile uint8_t dummy3111[4]; /* */ + volatile uint8_t dummy3112[4]; /* */ + volatile uint8_t dummy3113[4]; /* */ + volatile uint8_t dummy3114[4]; /* */ + volatile uint32_t CAMOR_B; /* CAMOR_B */ + volatile uint32_t CAPWR_B; /* CAPWR_B */ + volatile uint8_t dummy3120[4]; /* */ + volatile uint8_t dummy3121[12]; /* */ + volatile uint8_t dummy3122[4]; /* */ + volatile uint8_t dummy3123[4]; /* */ + volatile uint32_t CFLCR_B; /* CFLCR_B */ + volatile uint32_t CFSZR_B; /* CFSZR_B */ + volatile uint32_t CDWDR_B; /* CDWDR_B */ + volatile uint32_t CDAYR_B; /* CDAYR_B */ + volatile uint32_t CDACR_B; /* CDACR_B */ + volatile uint32_t CDBYR_B; /* CDBYR_B */ + volatile uint32_t CDBCR_B; /* CDBCR_B */ + volatile uint32_t CBDSR_B; /* CBDSR_B */ + volatile uint8_t dummy3130[12]; /* */ + volatile uint8_t dummy3131[4]; /* */ + volatile uint32_t CLFCR_B; /* CLFCR_B */ + volatile uint32_t CDOCR_B; /* CDOCR_B */ + volatile uint8_t dummy3140[8]; /* */ + volatile uint8_t dummy3141[4]; /* */ + volatile uint8_t dummy3142[4]; /* */ + volatile uint8_t dummy3143[4]; /* */ + volatile uint8_t dummy3144[4]; /* */ + volatile uint8_t dummy3145[4]; /* */ + volatile uint8_t dummy3146[4]; /* */ + volatile uint8_t dummy3147[8]; /* */ + volatile uint32_t CDAYR2_B; /* CDAYR2_B */ + volatile uint32_t CDACR2_B; /* CDACR2_B */ + volatile uint32_t CDBYR2_B; /* CDBYR2_B */ + volatile uint32_t CDBCR2_B; /* CDBCR2_B */ + +/* end of struct st_ceu_n */ + volatile uint8_t dummy3150[3936]; /* */ + +/* start of struct st_ceu_n */ + volatile uint8_t dummy3151[4]; /* */ + volatile uint8_t dummy3152[4]; /* */ + volatile uint8_t dummy3153[4]; /* */ + volatile uint8_t dummy3154[4]; /* */ + volatile uint32_t CAMOR_M; /* CAMOR_M */ + volatile uint32_t CAPWR_M; /* CAPWR_M */ + volatile uint8_t dummy3160[4]; /* */ + volatile uint8_t dummy3161[12]; /* */ + volatile uint8_t dummy3162[4]; /* */ + volatile uint8_t dummy3163[4]; /* */ + volatile uint32_t CFLCR_M; /* CFLCR_M */ + volatile uint32_t CFSZR_M; /* CFSZR_M */ + volatile uint32_t CDWDR_M; /* CDWDR_M */ + volatile uint32_t CDAYR_M; /* CDAYR_M */ + volatile uint32_t CDACR_M; /* CDACR_M */ + volatile uint32_t CDBYR_M; /* CDBYR_M */ + volatile uint32_t CDBCR_M; /* CDBCR_M */ + volatile uint32_t CBDSR_M; /* CBDSR_M */ + volatile uint8_t dummy3170[12]; /* */ + volatile uint8_t dummy3171[4]; /* */ + volatile uint32_t CLFCR_M; /* CLFCR_M */ + volatile uint32_t CDOCR_M; /* CDOCR_M */ + volatile uint8_t dummy3180[8]; /* */ + volatile uint8_t dummy3181[4]; /* */ + volatile uint8_t dummy3182[4]; /* */ + volatile uint8_t dummy3183[4]; /* */ + volatile uint8_t dummy3184[4]; /* */ + volatile uint8_t dummy3185[4]; /* */ + volatile uint8_t dummy3186[4]; /* */ + volatile uint8_t dummy3187[8]; /* */ + volatile uint32_t CDAYR2_M; /* CDAYR2_M */ + volatile uint32_t CDACR2_M; /* CDACR2_M */ + volatile uint32_t CDBYR2_M; /* CDBYR2_M */ + volatile uint32_t CDBCR2_M; /* CDBCR2_M */ + +/* end of struct st_ceu_n */ +} r_io_ceu_t; + + +typedef struct st_ceu_n +{ + + volatile uint32_t not_common1; /* */ + volatile uint32_t not_common2; /* */ + volatile uint32_t not_common3; /* */ + volatile uint32_t not_common4; /* */ + volatile uint32_t CAMOR; /* CAMOR */ + volatile uint32_t CAPWR; /* CAPWR */ + volatile uint32_t not_common5; /* */ + volatile uint8_t dummy322[12]; /* */ + volatile uint32_t not_common6; /* */ + volatile uint32_t not_common7; /* */ + volatile uint32_t CFLCR; /* CFLCR */ + volatile uint32_t CFSZR; /* CFSZR */ + volatile uint32_t CDWDR; /* CDWDR */ + volatile uint32_t CDAYR; /* CDAYR */ + volatile uint32_t CDACR; /* CDACR */ + volatile uint32_t CDBYR; /* CDBYR */ + volatile uint32_t CDBCR; /* CDBCR */ + volatile uint32_t CBDSR; /* CBDSR */ + volatile uint8_t dummy323[12]; /* */ + volatile uint32_t not_common8; /* */ + volatile uint32_t CLFCR; /* CLFCR */ + volatile uint32_t CDOCR; /* CDOCR */ + volatile uint8_t dummy324[8]; /* */ + volatile uint32_t not_common9; /* */ + volatile uint32_t not_common10; /* */ + volatile uint8_t dummy325[4]; /* */ + volatile uint32_t not_common11; /* */ + volatile uint8_t dummy326[4]; /* */ + volatile uint32_t not_common12; /* */ + volatile uint8_t dummy327[8]; /* */ + volatile uint32_t CDAYR2; /* CDAYR2 */ + volatile uint32_t CDACR2; /* CDACR2 */ + volatile uint32_t CDBYR2; /* CDBYR2 */ + volatile uint32_t CDBCR2; /* CDBCR2 */ +} r_io_ceu_n_t; + + +/* Channel array defines of CEUn (2)*/ +#ifdef DECLARE_CEUn_CHANNELS +volatile struct st_ceu_n* CEUn[ CEUn_COUNT ] = + /* ->MISRA 11.3 */ /* ->SEC R2.7.1 */ + CEUn_ADDRESS_LIST; + /* <-MISRA 11.3 */ /* <-SEC R2.7.1 */ +#endif /* DECLARE_CEUn_CHANNELS */ +/* End of channel array defines of CEUn (2)*/ + + +/* <-SEC M1.10.1 */ +/* <-MISRA 18.4 */ /* <-SEC M1.6.2 */ +/* <-QAC 0857 */ +/* <-QAC 0639 */ +#endif diff --git a/targets/TARGET_RENESAS/TARGET_RZ_A1XX/TARGET_GR_LYCHEE/device/inc/iodefines/cpg_iodefine.h b/targets/TARGET_RENESAS/TARGET_RZ_A1XX/TARGET_GR_LYCHEE/device/inc/iodefines/cpg_iodefine.h new file mode 100644 index 0000000..965a17c --- /dev/null +++ b/targets/TARGET_RENESAS/TARGET_RZ_A1XX/TARGET_GR_LYCHEE/device/inc/iodefines/cpg_iodefine.h @@ -0,0 +1,258 @@ +/******************************************************************************* +* DISCLAIMER +* This software is supplied by Renesas Electronics Corporation and is only +* intended for use with Renesas products. No other uses are authorized. This +* software is owned by Renesas Electronics Corporation and is protected under +* all applicable laws, including copyright laws. +* THIS SOFTWARE IS PROVIDED "AS IS" AND RENESAS MAKES NO WARRANTIES REGARDING +* THIS SOFTWARE, WHETHER EXPRESS, IMPLIED OR STATUTORY, INCLUDING BUT NOT +* LIMITED TO WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE +* AND NON-INFRINGEMENT. ALL SUCH WARRANTIES ARE EXPRESSLY DISCLAIMED. +* TO THE MAXIMUM EXTENT PERMITTED NOT PROHIBITED BY LAW, NEITHER RENESAS +* ELECTRONICS CORPORATION NOR ANY OF ITS AFFILIATED COMPANIES SHALL BE LIABLE +* FOR ANY DIRECT, INDIRECT, SPECIAL, INCIDENTAL OR CONSEQUENTIAL DAMAGES FOR +* ANY REASON RELATED TO THIS SOFTWARE, EVEN IF RENESAS OR ITS AFFILIATES HAVE +* BEEN ADVISED OF THE POSSIBILITY OF SUCH DAMAGES. +* Renesas reserves the right, without notice, to make changes to this software +* and to discontinue the availability of this software. By using this software, +* you agree to the additional terms and conditions found by accessing the +* following link: +* http://www.renesas.com/disclaimer* +* Copyright (C) 2013-2016 Renesas Electronics Corporation. All rights reserved. +*******************************************************************************/ +/******************************************************************************* +* File Name : cpg_iodefine.h +* $Rev: $ +* $Date:: $ +* Description : Definition of I/O Register for RZ/A1LU (V3.00l) +******************************************************************************/ +#ifndef CPG_IODEFINE_H +#define CPG_IODEFINE_H +/* ->QAC 0639 : Over 127 members (C90) */ +/* ->QAC 0857 : Over 1024 #define (C90) */ +/* ->MISRA 18.4 : Pack unpack union */ /* ->SEC M1.6.2 */ +/* ->SEC M1.10.1 : Not magic number */ + +#define CPG (*(struct st_cpg *)0xFCFE0010uL) /* CPG */ + + +/* Start of channel array defines of CPG */ + +/* Channel array defines of CPG_FROM_STBCR3_ARRAY */ +/*(Sample) value = CPG_FROM_STBCR3_ARRAY[ channel ]->STBCR3; */ +#define CPG_FROM_STBCR3_ARRAY_COUNT (10) +#define CPG_FROM_STBCR3_ARRAY_ADDRESS_LIST \ +{ /* ->MISRA 11.3 */ /* ->SEC R2.7.1 */ \ + &CPG_FROM_STBCR3, &CPG_FROM_STBCR4, &CPG_FROM_STBCR5, &CPG_FROM_STBCR6, &CPG_FROM_STBCR7, &CPG_FROM_STBCR8, &CPG_FROM_STBCR9, &CPG_FROM_STBCR10, \ + &CPG_FROM_STBCR11, &CPG_FROM_STBCR12 \ +} /* <-MISRA 11.3 */ /* <-SEC R2.7.1 */ /* { } is for MISRA 19.4 */ +#define CPG_FROM_STBCR3 (*(struct st_cpg_from_stbcr3 *)&CPG.STBCR3) /* CPG_FROM_STBCR3 */ +#define CPG_FROM_STBCR4 (*(struct st_cpg_from_stbcr3 *)&CPG.STBCR4) /* CPG_FROM_STBCR4 */ +#define CPG_FROM_STBCR5 (*(struct st_cpg_from_stbcr3 *)&CPG.STBCR5) /* CPG_FROM_STBCR5 */ +#define CPG_FROM_STBCR6 (*(struct st_cpg_from_stbcr3 *)&CPG.STBCR6) /* CPG_FROM_STBCR6 */ +#define CPG_FROM_STBCR7 (*(struct st_cpg_from_stbcr3 *)&CPG.STBCR7) /* CPG_FROM_STBCR7 */ +#define CPG_FROM_STBCR8 (*(struct st_cpg_from_stbcr3 *)&CPG.STBCR8) /* CPG_FROM_STBCR8 */ +#define CPG_FROM_STBCR9 (*(struct st_cpg_from_stbcr3 *)&CPG.STBCR9) /* CPG_FROM_STBCR9 */ +#define CPG_FROM_STBCR10 (*(struct st_cpg_from_stbcr3 *)&CPG.STBCR10) /* CPG_FROM_STBCR10 */ +#define CPG_FROM_STBCR11 (*(struct st_cpg_from_stbcr3 *)&CPG.STBCR11) /* CPG_FROM_STBCR11 */ +#define CPG_FROM_STBCR12 (*(struct st_cpg_from_stbcr3 *)&CPG.STBCR12) /* CPG_FROM_STBCR12 */ + + +/* Channel array defines of CPG_FROM_SYSCR1_ARRAY */ +/*(Sample) value = CPG_FROM_SYSCR1_ARRAY[ channel ]->SYSCR1; */ +#define CPG_FROM_SYSCR1_ARRAY_COUNT (3) +#define CPG_FROM_SYSCR1_ARRAY_ADDRESS_LIST \ +{ /* ->MISRA 11.3 */ /* ->SEC R2.7.1 */ \ + &CPG_FROM_SYSCR1, &CPG_FROM_SYSCR2, &CPG_FROM_SYSCR3 \ +} /* <-MISRA 11.3 */ /* <-SEC R2.7.1 */ /* { } is for MISRA 19.4 */ +#define CPG_FROM_SYSCR1 (*(struct st_cpg_from_syscr1 *)&CPG.SYSCR1) /* CPG_FROM_SYSCR1 */ +#define CPG_FROM_SYSCR2 (*(struct st_cpg_from_syscr1 *)&CPG.SYSCR2) /* CPG_FROM_SYSCR2 */ +#define CPG_FROM_SYSCR3 (*(struct st_cpg_from_syscr1 *)&CPG.SYSCR3) /* CPG_FROM_SYSCR3 */ + +/* End of channel array defines of CPG */ + + +#define CPGFRQCR (CPG.FRQCR) +#define CPGCPUSTS (CPG.CPUSTS) +#define CPGSTBCR1 (CPG.STBCR1) +#define CPGSTBCR2 (CPG.STBCR2) +#define CPGSTBREQ1 (CPG.STBREQ1) +#define CPGSTBREQ2 (CPG.STBREQ2) +#define CPGSTBACK1 (CPG.STBACK1) +#define CPGSTBACK2 (CPG.STBACK2) +#define CPGSYSCR1 (CPG.SYSCR1) +#define CPGSYSCR2 (CPG.SYSCR2) +#define CPGSYSCR3 (CPG.SYSCR3) +#define CPGSTBCR3 (CPG.STBCR3) +#define CPGSTBCR4 (CPG.STBCR4) +#define CPGSTBCR5 (CPG.STBCR5) +#define CPGSTBCR6 (CPG.STBCR6) +#define CPGSTBCR7 (CPG.STBCR7) +#define CPGSTBCR8 (CPG.STBCR8) +#define CPGSTBCR9 (CPG.STBCR9) +#define CPGSTBCR10 (CPG.STBCR10) +#define CPGSTBCR11 (CPG.STBCR11) +#define CPGSTBCR12 (CPG.STBCR12) +#define CPGSWRSTCR1 (CPG.SWRSTCR1) +#define CPGSWRSTCR2 (CPG.SWRSTCR2) +#define CPGRRAMKP (CPG.RRAMKP) +#define CPGDSCTR (CPG.DSCTR) +#define CPGDSSSR (CPG.DSSSR) +#define CPGDSESR (CPG.DSESR) +#define CPGDSFR (CPG.DSFR) +#define CPGXTALCTR (CPG.XTALCTR) + + +typedef struct st_cpg +{ + /* CPG */ + volatile uint16_t FRQCR; /* FRQCR */ + volatile uint8_t dummy319[6]; /* */ + volatile uint8_t CPUSTS; /* CPUSTS */ + volatile uint8_t dummy320[7]; /* */ + volatile uint8_t STBCR1; /* STBCR1 */ + volatile uint8_t dummy321[3]; /* */ + volatile uint8_t STBCR2; /* STBCR2 */ + volatile uint8_t dummy322[11]; /* */ + volatile uint8_t STBREQ1; /* STBREQ1 */ + volatile uint8_t dummy323[3]; /* */ + volatile uint8_t STBREQ2; /* STBREQ2 */ + volatile uint8_t dummy324[11]; /* */ + volatile uint8_t STBACK1; /* STBACK1 */ + volatile uint8_t dummy325[3]; /* */ + volatile uint8_t STBACK2; /* STBACK2 */ + volatile uint8_t dummy326[955]; /* */ + +/* start of struct st_cpg_from_syscr1 */ + volatile uint8_t SYSCR1; /* SYSCR1 */ + volatile uint8_t dummy327[3]; /* */ + +/* end of struct st_cpg_from_syscr1 */ + +/* start of struct st_cpg_from_syscr1 */ + volatile uint8_t SYSCR2; /* SYSCR2 */ + volatile uint8_t dummy328[3]; /* */ + +/* end of struct st_cpg_from_syscr1 */ + +/* start of struct st_cpg_from_syscr1 */ + volatile uint8_t SYSCR3; /* SYSCR3 */ + volatile uint8_t dummy3290[3]; /* */ + +/* end of struct st_cpg_from_syscr1 */ + volatile uint8_t dummy3291[20]; /* */ + +/* start of struct st_cpg_from_stbcr3 */ + volatile uint8_t STBCR3; /* STBCR3 */ + volatile uint8_t dummy330[3]; /* */ + +/* end of struct st_cpg_from_stbcr3 */ + +/* start of struct st_cpg_from_stbcr3 */ + volatile uint8_t STBCR4; /* STBCR4 */ + volatile uint8_t dummy331[3]; /* */ + +/* end of struct st_cpg_from_stbcr3 */ + +/* start of struct st_cpg_from_stbcr3 */ + volatile uint8_t STBCR5; /* STBCR5 */ + volatile uint8_t dummy332[3]; /* */ + +/* end of struct st_cpg_from_stbcr3 */ + +/* start of struct st_cpg_from_stbcr3 */ + volatile uint8_t STBCR6; /* STBCR6 */ + volatile uint8_t dummy333[3]; /* */ + +/* end of struct st_cpg_from_stbcr3 */ + +/* start of struct st_cpg_from_stbcr3 */ + volatile uint8_t STBCR7; /* STBCR7 */ + volatile uint8_t dummy334[3]; /* */ + +/* end of struct st_cpg_from_stbcr3 */ + +/* start of struct st_cpg_from_stbcr3 */ + volatile uint8_t STBCR8; /* STBCR8 */ + volatile uint8_t dummy335[3]; /* */ + +/* end of struct st_cpg_from_stbcr3 */ + +/* start of struct st_cpg_from_stbcr3 */ + volatile uint8_t STBCR9; /* STBCR9 */ + volatile uint8_t dummy336[3]; /* */ + +/* end of struct st_cpg_from_stbcr3 */ + +/* start of struct st_cpg_from_stbcr3 */ + volatile uint8_t STBCR10; /* STBCR10 */ + volatile uint8_t dummy337[3]; /* */ + +/* end of struct st_cpg_from_stbcr3 */ + +/* start of struct st_cpg_from_stbcr3 */ + volatile uint8_t STBCR11; /* STBCR11 */ + volatile uint8_t dummy338[3]; /* */ + +/* end of struct st_cpg_from_stbcr3 */ + +/* start of struct st_cpg_from_stbcr3 */ + volatile uint8_t STBCR12; /* STBCR12 */ + volatile uint8_t dummy3390[3]; /* */ + +/* end of struct st_cpg_from_stbcr3 */ + volatile uint8_t dummy3391[24]; /* */ + volatile uint8_t SWRSTCR1; /* SWRSTCR1 */ + volatile uint8_t dummy340[3]; /* */ + volatile uint8_t SWRSTCR2; /* SWRSTCR2 */ + volatile uint8_t dummy341[70555]; /* */ + volatile uint8_t RRAMKP; /* RRAMKP */ + volatile uint8_t dummy342[1]; /* */ + volatile uint8_t DSCTR; /* DSCTR */ + volatile uint8_t dummy343[1]; /* */ + volatile uint16_t DSSSR; /* DSSSR */ + volatile uint16_t DSESR; /* DSESR */ + volatile uint16_t DSFR; /* DSFR */ + volatile uint8_t dummy344[6]; /* */ + volatile uint8_t XTALCTR; /* XTALCTR */ +} r_io_cpg_t; + + +typedef struct st_cpg_from_syscr1 +{ + + volatile uint8_t SYSCR1; /* SYSCR1 */ + volatile uint8_t dummy1[3]; /* */ +} r_io_cpg_from_syscr1_t; + + +typedef struct st_cpg_from_stbcr3 +{ + + volatile uint8_t STBCR3; /* STBCR3 */ + volatile uint8_t dummy1[3]; /* */ +} r_io_cpg_from_stbcr3_t; + + +/* Channel array defines of CPG (2)*/ +#ifdef DECLARE_CPG_FROM_STBCR3_ARRAY_CHANNELS +volatile struct st_cpg_from_stbcr3* CPG_FROM_STBCR3_ARRAY[ CPG_FROM_STBCR3_ARRAY_COUNT ] = + /* ->MISRA 11.3 */ /* ->SEC R2.7.1 */ + CPG_FROM_STBCR3_ARRAY_ADDRESS_LIST; + /* <-MISRA 11.3 */ /* <-SEC R2.7.1 */ +#endif /* DECLARE_CPG_FROM_STBCR3_ARRAY_CHANNELS */ + +#ifdef DECLARE_CPG_FROM_SYSCR1_ARRAY_CHANNELS +volatile struct st_cpg_from_syscr1* CPG_FROM_SYSCR1_ARRAY[ CPG_FROM_SYSCR1_ARRAY_COUNT ] = + /* ->MISRA 11.3 */ /* ->SEC R2.7.1 */ + CPG_FROM_SYSCR1_ARRAY_ADDRESS_LIST; + /* <-MISRA 11.3 */ /* <-SEC R2.7.1 */ +#endif /* DECLARE_CPG_FROM_SYSCR1_ARRAY_CHANNELS */ +/* End of channel array defines of CPG (2)*/ + + +/* <-SEC M1.10.1 */ +/* <-MISRA 18.4 */ /* <-SEC M1.6.2 */ +/* <-QAC 0857 */ +/* <-QAC 0639 */ +#endif diff --git a/targets/TARGET_RENESAS/TARGET_RZ_A1XX/TARGET_GR_LYCHEE/device/inc/iodefines/dmac_iodefine.h b/targets/TARGET_RENESAS/TARGET_RZ_A1XX/TARGET_GR_LYCHEE/device/inc/iodefines/dmac_iodefine.h new file mode 100644 index 0000000..1eefb63 --- /dev/null +++ b/targets/TARGET_RENESAS/TARGET_RZ_A1XX/TARGET_GR_LYCHEE/device/inc/iodefines/dmac_iodefine.h @@ -0,0 +1,807 @@ +/******************************************************************************* +* DISCLAIMER +* This software is supplied by Renesas Electronics Corporation and is only +* intended for use with Renesas products. No other uses are authorized. This +* software is owned by Renesas Electronics Corporation and is protected under +* all applicable laws, including copyright laws. +* THIS SOFTWARE IS PROVIDED "AS IS" AND RENESAS MAKES NO WARRANTIES REGARDING +* THIS SOFTWARE, WHETHER EXPRESS, IMPLIED OR STATUTORY, INCLUDING BUT NOT +* LIMITED TO WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE +* AND NON-INFRINGEMENT. ALL SUCH WARRANTIES ARE EXPRESSLY DISCLAIMED. +* TO THE MAXIMUM EXTENT PERMITTED NOT PROHIBITED BY LAW, NEITHER RENESAS +* ELECTRONICS CORPORATION NOR ANY OF ITS AFFILIATED COMPANIES SHALL BE LIABLE +* FOR ANY DIRECT, INDIRECT, SPECIAL, INCIDENTAL OR CONSEQUENTIAL DAMAGES FOR +* ANY REASON RELATED TO THIS SOFTWARE, EVEN IF RENESAS OR ITS AFFILIATES HAVE +* BEEN ADVISED OF THE POSSIBILITY OF SUCH DAMAGES. +* Renesas reserves the right, without notice, to make changes to this software +* and to discontinue the availability of this software. By using this software, +* you agree to the additional terms and conditions found by accessing the +* following link: +* http://www.renesas.com/disclaimer* +* Copyright (C) 2013-2016 Renesas Electronics Corporation. All rights reserved. +*******************************************************************************/ +/******************************************************************************* +* File Name : dmac_iodefine.h +* $Rev: $ +* $Date:: $ +* Description : Definition of I/O Register for RZ/A1LU (V3.00l) +******************************************************************************/ +#ifndef DMAC_IODEFINE_H +#define DMAC_IODEFINE_H +/* ->QAC 0639 : Over 127 members (C90) */ +/* ->QAC 0857 : Over 1024 #define (C90) */ +/* ->MISRA 18.4 : Pack unpack union */ /* ->SEC M1.6.2 */ +/* ->SEC M1.10.1 : Not magic number */ + + + +/* Channel array defines of DMACmm */ +#define DMACmm_COUNT (8) +#define DMACmm_ADDRESS_LIST \ +{ /* ->MISRA 11.3 */ /* ->SEC R2.7.1 */ \ + &DMAC01, &DMAC23, &DMAC45, &DMAC67, &DMAC89, &DMAC1011, &DMAC1213, &DMAC1415 \ +} /* <-MISRA 11.3 */ /* <-SEC R2.7.1 */ /* { } is for MISRA 19.4 */ +#define DMAC01 (*(struct st_dmars_mm *)&DMAC.DMARS0) /* DMAC0-1 */ +#define DMAC23 (*(struct st_dmars_mm *)&DMAC.DMARS1) /* DMAC2-3 */ +#define DMAC45 (*(struct st_dmars_mm *)&DMAC.DMARS2) /* DMAC4-5 */ +#define DMAC67 (*(struct st_dmars_mm *)&DMAC.DMARS3) /* DMAC6-7 */ +#define DMAC89 (*(struct st_dmars_mm *)&DMAC.DMARS4) /* DMAC8-9 */ +#define DMAC1011 (*(struct st_dmars_mm *)&DMAC.DMARS5) /* DMAC10-11 */ +#define DMAC1213 (*(struct st_dmars_mm *)&DMAC.DMARS6) /* DMAC12-13 */ +#define DMAC1415 (*(struct st_dmars_mm *)&DMAC.DMARS7) /* DMAC14-15 */ + + +/*(Sample) value = DMACmm[ channel / 2 ]->DMARS; */ +#define DMAC (*(struct st_dmac *)0xE8200000uL) /* DMAC */ + + +/* Start of channel array defines of DMAC */ + +/* Channel array defines of DMACn */ +/*(Sample) value = DMACn[ channel ]->N0SA_n; */ +#define DMACn_COUNT (16) +#define DMACn_ADDRESS_LIST \ +{ /* ->MISRA 11.3 */ /* ->SEC R2.7.1 */ \ + &DMAC0, &DMAC1, &DMAC2, &DMAC3, &DMAC4, &DMAC5, &DMAC6, &DMAC7, \ + &DMAC8, &DMAC9, &DMAC10, &DMAC11, &DMAC12, &DMAC13, &DMAC14, &DMAC15 \ +} /* <-MISRA 11.3 */ /* <-SEC R2.7.1 */ /* { } is for MISRA 19.4 */ +#define DMAC0 (*(struct st_dmac_n *)&DMAC.N0SA_0) /* DMAC0 */ +#define DMAC1 (*(struct st_dmac_n *)&DMAC.N0SA_1) /* DMAC1 */ +#define DMAC2 (*(struct st_dmac_n *)&DMAC.N0SA_2) /* DMAC2 */ +#define DMAC3 (*(struct st_dmac_n *)&DMAC.N0SA_3) /* DMAC3 */ +#define DMAC4 (*(struct st_dmac_n *)&DMAC.N0SA_4) /* DMAC4 */ +#define DMAC5 (*(struct st_dmac_n *)&DMAC.N0SA_5) /* DMAC5 */ +#define DMAC6 (*(struct st_dmac_n *)&DMAC.N0SA_6) /* DMAC6 */ +#define DMAC7 (*(struct st_dmac_n *)&DMAC.N0SA_7) /* DMAC7 */ +#define DMAC8 (*(struct st_dmac_n *)&DMAC.N0SA_8) /* DMAC8 */ +#define DMAC9 (*(struct st_dmac_n *)&DMAC.N0SA_9) /* DMAC9 */ +#define DMAC10 (*(struct st_dmac_n *)&DMAC.N0SA_10) /* DMAC10 */ +#define DMAC11 (*(struct st_dmac_n *)&DMAC.N0SA_11) /* DMAC11 */ +#define DMAC12 (*(struct st_dmac_n *)&DMAC.N0SA_12) /* DMAC12 */ +#define DMAC13 (*(struct st_dmac_n *)&DMAC.N0SA_13) /* DMAC13 */ +#define DMAC14 (*(struct st_dmac_n *)&DMAC.N0SA_14) /* DMAC14 */ +#define DMAC15 (*(struct st_dmac_n *)&DMAC.N0SA_15) /* DMAC15 */ + + +/* Channel array defines of DMACnn */ +/*(Sample) value = DMACnn[ channel / 8 ]->DCTRL_0_7; */ +#define DMACnn_COUNT (2) +#define DMACnn_ADDRESS_LIST \ +{ /* ->MISRA 11.3 */ /* ->SEC R2.7.1 */ \ + &DMAC07, &DMAC815 \ +} /* <-MISRA 11.3 */ /* <-SEC R2.7.1 */ /* { } is for MISRA 19.4 */ +#define DMAC07 (*(struct st_dmaccommon_n *)&DMAC.DCTRL_0_7) /* DMAC07 */ +#define DMAC815 (*(struct st_dmaccommon_n *)&DMAC.DCTRL_8_15) /* DMAC815 */ + +/* End of channel array defines of DMAC */ + + +#define DMACN0SA_0 (DMAC.N0SA_0) +#define DMACN0DA_0 (DMAC.N0DA_0) +#define DMACN0TB_0 (DMAC.N0TB_0) +#define DMACN1SA_0 (DMAC.N1SA_0) +#define DMACN1DA_0 (DMAC.N1DA_0) +#define DMACN1TB_0 (DMAC.N1TB_0) +#define DMACCRSA_0 (DMAC.CRSA_0) +#define DMACCRDA_0 (DMAC.CRDA_0) +#define DMACCRTB_0 (DMAC.CRTB_0) +#define DMACCHSTAT_0 (DMAC.CHSTAT_0) +#define DMACCHCTRL_0 (DMAC.CHCTRL_0) +#define DMACCHCFG_0 (DMAC.CHCFG_0) +#define DMACCHITVL_0 (DMAC.CHITVL_0) +#define DMACCHEXT_0 (DMAC.CHEXT_0) +#define DMACNXLA_0 (DMAC.NXLA_0) +#define DMACCRLA_0 (DMAC.CRLA_0) +#define DMACN0SA_1 (DMAC.N0SA_1) +#define DMACN0DA_1 (DMAC.N0DA_1) +#define DMACN0TB_1 (DMAC.N0TB_1) +#define DMACN1SA_1 (DMAC.N1SA_1) +#define DMACN1DA_1 (DMAC.N1DA_1) +#define DMACN1TB_1 (DMAC.N1TB_1) +#define DMACCRSA_1 (DMAC.CRSA_1) +#define DMACCRDA_1 (DMAC.CRDA_1) +#define DMACCRTB_1 (DMAC.CRTB_1) +#define DMACCHSTAT_1 (DMAC.CHSTAT_1) +#define DMACCHCTRL_1 (DMAC.CHCTRL_1) +#define DMACCHCFG_1 (DMAC.CHCFG_1) +#define DMACCHITVL_1 (DMAC.CHITVL_1) +#define DMACCHEXT_1 (DMAC.CHEXT_1) +#define DMACNXLA_1 (DMAC.NXLA_1) +#define DMACCRLA_1 (DMAC.CRLA_1) +#define DMACN0SA_2 (DMAC.N0SA_2) +#define DMACN0DA_2 (DMAC.N0DA_2) +#define DMACN0TB_2 (DMAC.N0TB_2) +#define DMACN1SA_2 (DMAC.N1SA_2) +#define DMACN1DA_2 (DMAC.N1DA_2) +#define DMACN1TB_2 (DMAC.N1TB_2) +#define DMACCRSA_2 (DMAC.CRSA_2) +#define DMACCRDA_2 (DMAC.CRDA_2) +#define DMACCRTB_2 (DMAC.CRTB_2) +#define DMACCHSTAT_2 (DMAC.CHSTAT_2) +#define DMACCHCTRL_2 (DMAC.CHCTRL_2) +#define DMACCHCFG_2 (DMAC.CHCFG_2) +#define DMACCHITVL_2 (DMAC.CHITVL_2) +#define DMACCHEXT_2 (DMAC.CHEXT_2) +#define DMACNXLA_2 (DMAC.NXLA_2) +#define DMACCRLA_2 (DMAC.CRLA_2) +#define DMACN0SA_3 (DMAC.N0SA_3) +#define DMACN0DA_3 (DMAC.N0DA_3) +#define DMACN0TB_3 (DMAC.N0TB_3) +#define DMACN1SA_3 (DMAC.N1SA_3) +#define DMACN1DA_3 (DMAC.N1DA_3) +#define DMACN1TB_3 (DMAC.N1TB_3) +#define DMACCRSA_3 (DMAC.CRSA_3) +#define DMACCRDA_3 (DMAC.CRDA_3) +#define DMACCRTB_3 (DMAC.CRTB_3) +#define DMACCHSTAT_3 (DMAC.CHSTAT_3) +#define DMACCHCTRL_3 (DMAC.CHCTRL_3) +#define DMACCHCFG_3 (DMAC.CHCFG_3) +#define DMACCHITVL_3 (DMAC.CHITVL_3) +#define DMACCHEXT_3 (DMAC.CHEXT_3) +#define DMACNXLA_3 (DMAC.NXLA_3) +#define DMACCRLA_3 (DMAC.CRLA_3) +#define DMACN0SA_4 (DMAC.N0SA_4) +#define DMACN0DA_4 (DMAC.N0DA_4) +#define DMACN0TB_4 (DMAC.N0TB_4) +#define DMACN1SA_4 (DMAC.N1SA_4) +#define DMACN1DA_4 (DMAC.N1DA_4) +#define DMACN1TB_4 (DMAC.N1TB_4) +#define DMACCRSA_4 (DMAC.CRSA_4) +#define DMACCRDA_4 (DMAC.CRDA_4) +#define DMACCRTB_4 (DMAC.CRTB_4) +#define DMACCHSTAT_4 (DMAC.CHSTAT_4) +#define DMACCHCTRL_4 (DMAC.CHCTRL_4) +#define DMACCHCFG_4 (DMAC.CHCFG_4) +#define DMACCHITVL_4 (DMAC.CHITVL_4) +#define DMACCHEXT_4 (DMAC.CHEXT_4) +#define DMACNXLA_4 (DMAC.NXLA_4) +#define DMACCRLA_4 (DMAC.CRLA_4) +#define DMACN0SA_5 (DMAC.N0SA_5) +#define DMACN0DA_5 (DMAC.N0DA_5) +#define DMACN0TB_5 (DMAC.N0TB_5) +#define DMACN1SA_5 (DMAC.N1SA_5) +#define DMACN1DA_5 (DMAC.N1DA_5) +#define DMACN1TB_5 (DMAC.N1TB_5) +#define DMACCRSA_5 (DMAC.CRSA_5) +#define DMACCRDA_5 (DMAC.CRDA_5) +#define DMACCRTB_5 (DMAC.CRTB_5) +#define DMACCHSTAT_5 (DMAC.CHSTAT_5) +#define DMACCHCTRL_5 (DMAC.CHCTRL_5) +#define DMACCHCFG_5 (DMAC.CHCFG_5) +#define DMACCHITVL_5 (DMAC.CHITVL_5) +#define DMACCHEXT_5 (DMAC.CHEXT_5) +#define DMACNXLA_5 (DMAC.NXLA_5) +#define DMACCRLA_5 (DMAC.CRLA_5) +#define DMACN0SA_6 (DMAC.N0SA_6) +#define DMACN0DA_6 (DMAC.N0DA_6) +#define DMACN0TB_6 (DMAC.N0TB_6) +#define DMACN1SA_6 (DMAC.N1SA_6) +#define DMACN1DA_6 (DMAC.N1DA_6) +#define DMACN1TB_6 (DMAC.N1TB_6) +#define DMACCRSA_6 (DMAC.CRSA_6) +#define DMACCRDA_6 (DMAC.CRDA_6) +#define DMACCRTB_6 (DMAC.CRTB_6) +#define DMACCHSTAT_6 (DMAC.CHSTAT_6) +#define DMACCHCTRL_6 (DMAC.CHCTRL_6) +#define DMACCHCFG_6 (DMAC.CHCFG_6) +#define DMACCHITVL_6 (DMAC.CHITVL_6) +#define DMACCHEXT_6 (DMAC.CHEXT_6) +#define DMACNXLA_6 (DMAC.NXLA_6) +#define DMACCRLA_6 (DMAC.CRLA_6) +#define DMACN0SA_7 (DMAC.N0SA_7) +#define DMACN0DA_7 (DMAC.N0DA_7) +#define DMACN0TB_7 (DMAC.N0TB_7) +#define DMACN1SA_7 (DMAC.N1SA_7) +#define DMACN1DA_7 (DMAC.N1DA_7) +#define DMACN1TB_7 (DMAC.N1TB_7) +#define DMACCRSA_7 (DMAC.CRSA_7) +#define DMACCRDA_7 (DMAC.CRDA_7) +#define DMACCRTB_7 (DMAC.CRTB_7) +#define DMACCHSTAT_7 (DMAC.CHSTAT_7) +#define DMACCHCTRL_7 (DMAC.CHCTRL_7) +#define DMACCHCFG_7 (DMAC.CHCFG_7) +#define DMACCHITVL_7 (DMAC.CHITVL_7) +#define DMACCHEXT_7 (DMAC.CHEXT_7) +#define DMACNXLA_7 (DMAC.NXLA_7) +#define DMACCRLA_7 (DMAC.CRLA_7) +#define DMACDCTRL_0_7 (DMAC.DCTRL_0_7) +#define DMACDSTAT_EN_0_7 (DMAC.DSTAT_EN_0_7) +#define DMACDSTAT_ER_0_7 (DMAC.DSTAT_ER_0_7) +#define DMACDSTAT_END_0_7 (DMAC.DSTAT_END_0_7) +#define DMACDSTAT_TC_0_7 (DMAC.DSTAT_TC_0_7) +#define DMACDSTAT_SUS_0_7 (DMAC.DSTAT_SUS_0_7) +#define DMACN0SA_8 (DMAC.N0SA_8) +#define DMACN0DA_8 (DMAC.N0DA_8) +#define DMACN0TB_8 (DMAC.N0TB_8) +#define DMACN1SA_8 (DMAC.N1SA_8) +#define DMACN1DA_8 (DMAC.N1DA_8) +#define DMACN1TB_8 (DMAC.N1TB_8) +#define DMACCRSA_8 (DMAC.CRSA_8) +#define DMACCRDA_8 (DMAC.CRDA_8) +#define DMACCRTB_8 (DMAC.CRTB_8) +#define DMACCHSTAT_8 (DMAC.CHSTAT_8) +#define DMACCHCTRL_8 (DMAC.CHCTRL_8) +#define DMACCHCFG_8 (DMAC.CHCFG_8) +#define DMACCHITVL_8 (DMAC.CHITVL_8) +#define DMACCHEXT_8 (DMAC.CHEXT_8) +#define DMACNXLA_8 (DMAC.NXLA_8) +#define DMACCRLA_8 (DMAC.CRLA_8) +#define DMACN0SA_9 (DMAC.N0SA_9) +#define DMACN0DA_9 (DMAC.N0DA_9) +#define DMACN0TB_9 (DMAC.N0TB_9) +#define DMACN1SA_9 (DMAC.N1SA_9) +#define DMACN1DA_9 (DMAC.N1DA_9) +#define DMACN1TB_9 (DMAC.N1TB_9) +#define DMACCRSA_9 (DMAC.CRSA_9) +#define DMACCRDA_9 (DMAC.CRDA_9) +#define DMACCRTB_9 (DMAC.CRTB_9) +#define DMACCHSTAT_9 (DMAC.CHSTAT_9) +#define DMACCHCTRL_9 (DMAC.CHCTRL_9) +#define DMACCHCFG_9 (DMAC.CHCFG_9) +#define DMACCHITVL_9 (DMAC.CHITVL_9) +#define DMACCHEXT_9 (DMAC.CHEXT_9) +#define DMACNXLA_9 (DMAC.NXLA_9) +#define DMACCRLA_9 (DMAC.CRLA_9) +#define DMACN0SA_10 (DMAC.N0SA_10) +#define DMACN0DA_10 (DMAC.N0DA_10) +#define DMACN0TB_10 (DMAC.N0TB_10) +#define DMACN1SA_10 (DMAC.N1SA_10) +#define DMACN1DA_10 (DMAC.N1DA_10) +#define DMACN1TB_10 (DMAC.N1TB_10) +#define DMACCRSA_10 (DMAC.CRSA_10) +#define DMACCRDA_10 (DMAC.CRDA_10) +#define DMACCRTB_10 (DMAC.CRTB_10) +#define DMACCHSTAT_10 (DMAC.CHSTAT_10) +#define DMACCHCTRL_10 (DMAC.CHCTRL_10) +#define DMACCHCFG_10 (DMAC.CHCFG_10) +#define DMACCHITVL_10 (DMAC.CHITVL_10) +#define DMACCHEXT_10 (DMAC.CHEXT_10) +#define DMACNXLA_10 (DMAC.NXLA_10) +#define DMACCRLA_10 (DMAC.CRLA_10) +#define DMACN0SA_11 (DMAC.N0SA_11) +#define DMACN0DA_11 (DMAC.N0DA_11) +#define DMACN0TB_11 (DMAC.N0TB_11) +#define DMACN1SA_11 (DMAC.N1SA_11) +#define DMACN1DA_11 (DMAC.N1DA_11) +#define DMACN1TB_11 (DMAC.N1TB_11) +#define DMACCRSA_11 (DMAC.CRSA_11) +#define DMACCRDA_11 (DMAC.CRDA_11) +#define DMACCRTB_11 (DMAC.CRTB_11) +#define DMACCHSTAT_11 (DMAC.CHSTAT_11) +#define DMACCHCTRL_11 (DMAC.CHCTRL_11) +#define DMACCHCFG_11 (DMAC.CHCFG_11) +#define DMACCHITVL_11 (DMAC.CHITVL_11) +#define DMACCHEXT_11 (DMAC.CHEXT_11) +#define DMACNXLA_11 (DMAC.NXLA_11) +#define DMACCRLA_11 (DMAC.CRLA_11) +#define DMACN0SA_12 (DMAC.N0SA_12) +#define DMACN0DA_12 (DMAC.N0DA_12) +#define DMACN0TB_12 (DMAC.N0TB_12) +#define DMACN1SA_12 (DMAC.N1SA_12) +#define DMACN1DA_12 (DMAC.N1DA_12) +#define DMACN1TB_12 (DMAC.N1TB_12) +#define DMACCRSA_12 (DMAC.CRSA_12) +#define DMACCRDA_12 (DMAC.CRDA_12) +#define DMACCRTB_12 (DMAC.CRTB_12) +#define DMACCHSTAT_12 (DMAC.CHSTAT_12) +#define DMACCHCTRL_12 (DMAC.CHCTRL_12) +#define DMACCHCFG_12 (DMAC.CHCFG_12) +#define DMACCHITVL_12 (DMAC.CHITVL_12) +#define DMACCHEXT_12 (DMAC.CHEXT_12) +#define DMACNXLA_12 (DMAC.NXLA_12) +#define DMACCRLA_12 (DMAC.CRLA_12) +#define DMACN0SA_13 (DMAC.N0SA_13) +#define DMACN0DA_13 (DMAC.N0DA_13) +#define DMACN0TB_13 (DMAC.N0TB_13) +#define DMACN1SA_13 (DMAC.N1SA_13) +#define DMACN1DA_13 (DMAC.N1DA_13) +#define DMACN1TB_13 (DMAC.N1TB_13) +#define DMACCRSA_13 (DMAC.CRSA_13) +#define DMACCRDA_13 (DMAC.CRDA_13) +#define DMACCRTB_13 (DMAC.CRTB_13) +#define DMACCHSTAT_13 (DMAC.CHSTAT_13) +#define DMACCHCTRL_13 (DMAC.CHCTRL_13) +#define DMACCHCFG_13 (DMAC.CHCFG_13) +#define DMACCHITVL_13 (DMAC.CHITVL_13) +#define DMACCHEXT_13 (DMAC.CHEXT_13) +#define DMACNXLA_13 (DMAC.NXLA_13) +#define DMACCRLA_13 (DMAC.CRLA_13) +#define DMACN0SA_14 (DMAC.N0SA_14) +#define DMACN0DA_14 (DMAC.N0DA_14) +#define DMACN0TB_14 (DMAC.N0TB_14) +#define DMACN1SA_14 (DMAC.N1SA_14) +#define DMACN1DA_14 (DMAC.N1DA_14) +#define DMACN1TB_14 (DMAC.N1TB_14) +#define DMACCRSA_14 (DMAC.CRSA_14) +#define DMACCRDA_14 (DMAC.CRDA_14) +#define DMACCRTB_14 (DMAC.CRTB_14) +#define DMACCHSTAT_14 (DMAC.CHSTAT_14) +#define DMACCHCTRL_14 (DMAC.CHCTRL_14) +#define DMACCHCFG_14 (DMAC.CHCFG_14) +#define DMACCHITVL_14 (DMAC.CHITVL_14) +#define DMACCHEXT_14 (DMAC.CHEXT_14) +#define DMACNXLA_14 (DMAC.NXLA_14) +#define DMACCRLA_14 (DMAC.CRLA_14) +#define DMACN0SA_15 (DMAC.N0SA_15) +#define DMACN0DA_15 (DMAC.N0DA_15) +#define DMACN0TB_15 (DMAC.N0TB_15) +#define DMACN1SA_15 (DMAC.N1SA_15) +#define DMACN1DA_15 (DMAC.N1DA_15) +#define DMACN1TB_15 (DMAC.N1TB_15) +#define DMACCRSA_15 (DMAC.CRSA_15) +#define DMACCRDA_15 (DMAC.CRDA_15) +#define DMACCRTB_15 (DMAC.CRTB_15) +#define DMACCHSTAT_15 (DMAC.CHSTAT_15) +#define DMACCHCTRL_15 (DMAC.CHCTRL_15) +#define DMACCHCFG_15 (DMAC.CHCFG_15) +#define DMACCHITVL_15 (DMAC.CHITVL_15) +#define DMACCHEXT_15 (DMAC.CHEXT_15) +#define DMACNXLA_15 (DMAC.NXLA_15) +#define DMACCRLA_15 (DMAC.CRLA_15) +#define DMACDCTRL_8_15 (DMAC.DCTRL_8_15) +#define DMACDSTAT_EN_8_15 (DMAC.DSTAT_EN_8_15) +#define DMACDSTAT_ER_8_15 (DMAC.DSTAT_ER_8_15) +#define DMACDSTAT_END_8_15 (DMAC.DSTAT_END_8_15) +#define DMACDSTAT_TC_8_15 (DMAC.DSTAT_TC_8_15) +#define DMACDSTAT_SUS_8_15 (DMAC.DSTAT_SUS_8_15) +#define DMACDMARS0 (DMAC.DMARS0) +#define DMACDMARS1 (DMAC.DMARS1) +#define DMACDMARS2 (DMAC.DMARS2) +#define DMACDMARS3 (DMAC.DMARS3) +#define DMACDMARS4 (DMAC.DMARS4) +#define DMACDMARS5 (DMAC.DMARS5) +#define DMACDMARS6 (DMAC.DMARS6) +#define DMACDMARS7 (DMAC.DMARS7) + + +typedef struct st_dmars_mm +{ + + volatile uint32_t DMARS; /* DMARS */ +} r_io_dmars_mm_t; + + +typedef struct st_dmac +{ + /* DMAC */ + +/* start of struct st_dmac_n */ + volatile uint32_t N0SA_0; /* N0SA_0 */ + volatile uint32_t N0DA_0; /* N0DA_0 */ + volatile uint32_t N0TB_0; /* N0TB_0 */ + volatile uint32_t N1SA_0; /* N1SA_0 */ + volatile uint32_t N1DA_0; /* N1DA_0 */ + volatile uint32_t N1TB_0; /* N1TB_0 */ + volatile uint32_t CRSA_0; /* CRSA_0 */ + volatile uint32_t CRDA_0; /* CRDA_0 */ + volatile uint32_t CRTB_0; /* CRTB_0 */ + volatile uint32_t CHSTAT_0; /* CHSTAT_0 */ + volatile uint32_t CHCTRL_0; /* CHCTRL_0 */ + volatile uint32_t CHCFG_0; /* CHCFG_0 */ + volatile uint32_t CHITVL_0; /* CHITVL_0 */ + volatile uint32_t CHEXT_0; /* CHEXT_0 */ + volatile uint32_t NXLA_0; /* NXLA_0 */ + volatile uint32_t CRLA_0; /* CRLA_0 */ + +/* end of struct st_dmac_n */ + +/* start of struct st_dmac_n */ + volatile uint32_t N0SA_1; /* N0SA_1 */ + volatile uint32_t N0DA_1; /* N0DA_1 */ + volatile uint32_t N0TB_1; /* N0TB_1 */ + volatile uint32_t N1SA_1; /* N1SA_1 */ + volatile uint32_t N1DA_1; /* N1DA_1 */ + volatile uint32_t N1TB_1; /* N1TB_1 */ + volatile uint32_t CRSA_1; /* CRSA_1 */ + volatile uint32_t CRDA_1; /* CRDA_1 */ + volatile uint32_t CRTB_1; /* CRTB_1 */ + volatile uint32_t CHSTAT_1; /* CHSTAT_1 */ + volatile uint32_t CHCTRL_1; /* CHCTRL_1 */ + volatile uint32_t CHCFG_1; /* CHCFG_1 */ + volatile uint32_t CHITVL_1; /* CHITVL_1 */ + volatile uint32_t CHEXT_1; /* CHEXT_1 */ + volatile uint32_t NXLA_1; /* NXLA_1 */ + volatile uint32_t CRLA_1; /* CRLA_1 */ + +/* end of struct st_dmac_n */ + +/* start of struct st_dmac_n */ + volatile uint32_t N0SA_2; /* N0SA_2 */ + volatile uint32_t N0DA_2; /* N0DA_2 */ + volatile uint32_t N0TB_2; /* N0TB_2 */ + volatile uint32_t N1SA_2; /* N1SA_2 */ + volatile uint32_t N1DA_2; /* N1DA_2 */ + volatile uint32_t N1TB_2; /* N1TB_2 */ + volatile uint32_t CRSA_2; /* CRSA_2 */ + volatile uint32_t CRDA_2; /* CRDA_2 */ + volatile uint32_t CRTB_2; /* CRTB_2 */ + volatile uint32_t CHSTAT_2; /* CHSTAT_2 */ + volatile uint32_t CHCTRL_2; /* CHCTRL_2 */ + volatile uint32_t CHCFG_2; /* CHCFG_2 */ + volatile uint32_t CHITVL_2; /* CHITVL_2 */ + volatile uint32_t CHEXT_2; /* CHEXT_2 */ + volatile uint32_t NXLA_2; /* NXLA_2 */ + volatile uint32_t CRLA_2; /* CRLA_2 */ + +/* end of struct st_dmac_n */ + +/* start of struct st_dmac_n */ + volatile uint32_t N0SA_3; /* N0SA_3 */ + volatile uint32_t N0DA_3; /* N0DA_3 */ + volatile uint32_t N0TB_3; /* N0TB_3 */ + volatile uint32_t N1SA_3; /* N1SA_3 */ + volatile uint32_t N1DA_3; /* N1DA_3 */ + volatile uint32_t N1TB_3; /* N1TB_3 */ + volatile uint32_t CRSA_3; /* CRSA_3 */ + volatile uint32_t CRDA_3; /* CRDA_3 */ + volatile uint32_t CRTB_3; /* CRTB_3 */ + volatile uint32_t CHSTAT_3; /* CHSTAT_3 */ + volatile uint32_t CHCTRL_3; /* CHCTRL_3 */ + volatile uint32_t CHCFG_3; /* CHCFG_3 */ + volatile uint32_t CHITVL_3; /* CHITVL_3 */ + volatile uint32_t CHEXT_3; /* CHEXT_3 */ + volatile uint32_t NXLA_3; /* NXLA_3 */ + volatile uint32_t CRLA_3; /* CRLA_3 */ + +/* end of struct st_dmac_n */ + +/* start of struct st_dmac_n */ + volatile uint32_t N0SA_4; /* N0SA_4 */ + volatile uint32_t N0DA_4; /* N0DA_4 */ + volatile uint32_t N0TB_4; /* N0TB_4 */ + volatile uint32_t N1SA_4; /* N1SA_4 */ + volatile uint32_t N1DA_4; /* N1DA_4 */ + volatile uint32_t N1TB_4; /* N1TB_4 */ + volatile uint32_t CRSA_4; /* CRSA_4 */ + volatile uint32_t CRDA_4; /* CRDA_4 */ + volatile uint32_t CRTB_4; /* CRTB_4 */ + volatile uint32_t CHSTAT_4; /* CHSTAT_4 */ + volatile uint32_t CHCTRL_4; /* CHCTRL_4 */ + volatile uint32_t CHCFG_4; /* CHCFG_4 */ + volatile uint32_t CHITVL_4; /* CHITVL_4 */ + volatile uint32_t CHEXT_4; /* CHEXT_4 */ + volatile uint32_t NXLA_4; /* NXLA_4 */ + volatile uint32_t CRLA_4; /* CRLA_4 */ + +/* end of struct st_dmac_n */ + +/* start of struct st_dmac_n */ + volatile uint32_t N0SA_5; /* N0SA_5 */ + volatile uint32_t N0DA_5; /* N0DA_5 */ + volatile uint32_t N0TB_5; /* N0TB_5 */ + volatile uint32_t N1SA_5; /* N1SA_5 */ + volatile uint32_t N1DA_5; /* N1DA_5 */ + volatile uint32_t N1TB_5; /* N1TB_5 */ + volatile uint32_t CRSA_5; /* CRSA_5 */ + volatile uint32_t CRDA_5; /* CRDA_5 */ + volatile uint32_t CRTB_5; /* CRTB_5 */ + volatile uint32_t CHSTAT_5; /* CHSTAT_5 */ + volatile uint32_t CHCTRL_5; /* CHCTRL_5 */ + volatile uint32_t CHCFG_5; /* CHCFG_5 */ + volatile uint32_t CHITVL_5; /* CHITVL_5 */ + volatile uint32_t CHEXT_5; /* CHEXT_5 */ + volatile uint32_t NXLA_5; /* NXLA_5 */ + volatile uint32_t CRLA_5; /* CRLA_5 */ + +/* end of struct st_dmac_n */ + +/* start of struct st_dmac_n */ + volatile uint32_t N0SA_6; /* N0SA_6 */ + volatile uint32_t N0DA_6; /* N0DA_6 */ + volatile uint32_t N0TB_6; /* N0TB_6 */ + volatile uint32_t N1SA_6; /* N1SA_6 */ + volatile uint32_t N1DA_6; /* N1DA_6 */ + volatile uint32_t N1TB_6; /* N1TB_6 */ + volatile uint32_t CRSA_6; /* CRSA_6 */ + volatile uint32_t CRDA_6; /* CRDA_6 */ + volatile uint32_t CRTB_6; /* CRTB_6 */ + volatile uint32_t CHSTAT_6; /* CHSTAT_6 */ + volatile uint32_t CHCTRL_6; /* CHCTRL_6 */ + volatile uint32_t CHCFG_6; /* CHCFG_6 */ + volatile uint32_t CHITVL_6; /* CHITVL_6 */ + volatile uint32_t CHEXT_6; /* CHEXT_6 */ + volatile uint32_t NXLA_6; /* NXLA_6 */ + volatile uint32_t CRLA_6; /* CRLA_6 */ + +/* end of struct st_dmac_n */ + +/* start of struct st_dmac_n */ + volatile uint32_t N0SA_7; /* N0SA_7 */ + volatile uint32_t N0DA_7; /* N0DA_7 */ + volatile uint32_t N0TB_7; /* N0TB_7 */ + volatile uint32_t N1SA_7; /* N1SA_7 */ + volatile uint32_t N1DA_7; /* N1DA_7 */ + volatile uint32_t N1TB_7; /* N1TB_7 */ + volatile uint32_t CRSA_7; /* CRSA_7 */ + volatile uint32_t CRDA_7; /* CRDA_7 */ + volatile uint32_t CRTB_7; /* CRTB_7 */ + volatile uint32_t CHSTAT_7; /* CHSTAT_7 */ + volatile uint32_t CHCTRL_7; /* CHCTRL_7 */ + volatile uint32_t CHCFG_7; /* CHCFG_7 */ + volatile uint32_t CHITVL_7; /* CHITVL_7 */ + volatile uint32_t CHEXT_7; /* CHEXT_7 */ + volatile uint32_t NXLA_7; /* NXLA_7 */ + volatile uint32_t CRLA_7; /* CRLA_7 */ + +/* end of struct st_dmac_n */ + volatile uint8_t dummy187[256]; /* */ + +/* start of struct st_dmaccommon_n */ + volatile uint32_t DCTRL_0_7; /* DCTRL_0_7 */ + volatile uint8_t dummy188[12]; /* */ + volatile uint32_t DSTAT_EN_0_7; /* DSTAT_EN_0_7 */ + volatile uint32_t DSTAT_ER_0_7; /* DSTAT_ER_0_7 */ + volatile uint32_t DSTAT_END_0_7; /* DSTAT_END_0_7 */ + volatile uint32_t DSTAT_TC_0_7; /* DSTAT_TC_0_7 */ + volatile uint32_t DSTAT_SUS_0_7; /* DSTAT_SUS_0_7 */ + +/* end of struct st_dmaccommon_n */ + volatile uint8_t dummy189[220]; /* */ + +/* start of struct st_dmac_n */ + volatile uint32_t N0SA_8; /* N0SA_8 */ + volatile uint32_t N0DA_8; /* N0DA_8 */ + volatile uint32_t N0TB_8; /* N0TB_8 */ + volatile uint32_t N1SA_8; /* N1SA_8 */ + volatile uint32_t N1DA_8; /* N1DA_8 */ + volatile uint32_t N1TB_8; /* N1TB_8 */ + volatile uint32_t CRSA_8; /* CRSA_8 */ + volatile uint32_t CRDA_8; /* CRDA_8 */ + volatile uint32_t CRTB_8; /* CRTB_8 */ + volatile uint32_t CHSTAT_8; /* CHSTAT_8 */ + volatile uint32_t CHCTRL_8; /* CHCTRL_8 */ + volatile uint32_t CHCFG_8; /* CHCFG_8 */ + volatile uint32_t CHITVL_8; /* CHITVL_8 */ + volatile uint32_t CHEXT_8; /* CHEXT_8 */ + volatile uint32_t NXLA_8; /* NXLA_8 */ + volatile uint32_t CRLA_8; /* CRLA_8 */ + +/* end of struct st_dmac_n */ + +/* start of struct st_dmac_n */ + volatile uint32_t N0SA_9; /* N0SA_9 */ + volatile uint32_t N0DA_9; /* N0DA_9 */ + volatile uint32_t N0TB_9; /* N0TB_9 */ + volatile uint32_t N1SA_9; /* N1SA_9 */ + volatile uint32_t N1DA_9; /* N1DA_9 */ + volatile uint32_t N1TB_9; /* N1TB_9 */ + volatile uint32_t CRSA_9; /* CRSA_9 */ + volatile uint32_t CRDA_9; /* CRDA_9 */ + volatile uint32_t CRTB_9; /* CRTB_9 */ + volatile uint32_t CHSTAT_9; /* CHSTAT_9 */ + volatile uint32_t CHCTRL_9; /* CHCTRL_9 */ + volatile uint32_t CHCFG_9; /* CHCFG_9 */ + volatile uint32_t CHITVL_9; /* CHITVL_9 */ + volatile uint32_t CHEXT_9; /* CHEXT_9 */ + volatile uint32_t NXLA_9; /* NXLA_9 */ + volatile uint32_t CRLA_9; /* CRLA_9 */ + +/* end of struct st_dmac_n */ + +/* start of struct st_dmac_n */ + volatile uint32_t N0SA_10; /* N0SA_10 */ + volatile uint32_t N0DA_10; /* N0DA_10 */ + volatile uint32_t N0TB_10; /* N0TB_10 */ + volatile uint32_t N1SA_10; /* N1SA_10 */ + volatile uint32_t N1DA_10; /* N1DA_10 */ + volatile uint32_t N1TB_10; /* N1TB_10 */ + volatile uint32_t CRSA_10; /* CRSA_10 */ + volatile uint32_t CRDA_10; /* CRDA_10 */ + volatile uint32_t CRTB_10; /* CRTB_10 */ + volatile uint32_t CHSTAT_10; /* CHSTAT_10 */ + volatile uint32_t CHCTRL_10; /* CHCTRL_10 */ + volatile uint32_t CHCFG_10; /* CHCFG_10 */ + volatile uint32_t CHITVL_10; /* CHITVL_10 */ + volatile uint32_t CHEXT_10; /* CHEXT_10 */ + volatile uint32_t NXLA_10; /* NXLA_10 */ + volatile uint32_t CRLA_10; /* CRLA_10 */ + +/* end of struct st_dmac_n */ + +/* start of struct st_dmac_n */ + volatile uint32_t N0SA_11; /* N0SA_11 */ + volatile uint32_t N0DA_11; /* N0DA_11 */ + volatile uint32_t N0TB_11; /* N0TB_11 */ + volatile uint32_t N1SA_11; /* N1SA_11 */ + volatile uint32_t N1DA_11; /* N1DA_11 */ + volatile uint32_t N1TB_11; /* N1TB_11 */ + volatile uint32_t CRSA_11; /* CRSA_11 */ + volatile uint32_t CRDA_11; /* CRDA_11 */ + volatile uint32_t CRTB_11; /* CRTB_11 */ + volatile uint32_t CHSTAT_11; /* CHSTAT_11 */ + volatile uint32_t CHCTRL_11; /* CHCTRL_11 */ + volatile uint32_t CHCFG_11; /* CHCFG_11 */ + volatile uint32_t CHITVL_11; /* CHITVL_11 */ + volatile uint32_t CHEXT_11; /* CHEXT_11 */ + volatile uint32_t NXLA_11; /* NXLA_11 */ + volatile uint32_t CRLA_11; /* CRLA_11 */ + +/* end of struct st_dmac_n */ + +/* start of struct st_dmac_n */ + volatile uint32_t N0SA_12; /* N0SA_12 */ + volatile uint32_t N0DA_12; /* N0DA_12 */ + volatile uint32_t N0TB_12; /* N0TB_12 */ + volatile uint32_t N1SA_12; /* N1SA_12 */ + volatile uint32_t N1DA_12; /* N1DA_12 */ + volatile uint32_t N1TB_12; /* N1TB_12 */ + volatile uint32_t CRSA_12; /* CRSA_12 */ + volatile uint32_t CRDA_12; /* CRDA_12 */ + volatile uint32_t CRTB_12; /* CRTB_12 */ + volatile uint32_t CHSTAT_12; /* CHSTAT_12 */ + volatile uint32_t CHCTRL_12; /* CHCTRL_12 */ + volatile uint32_t CHCFG_12; /* CHCFG_12 */ + volatile uint32_t CHITVL_12; /* CHITVL_12 */ + volatile uint32_t CHEXT_12; /* CHEXT_12 */ + volatile uint32_t NXLA_12; /* NXLA_12 */ + volatile uint32_t CRLA_12; /* CRLA_12 */ + +/* end of struct st_dmac_n */ + +/* start of struct st_dmac_n */ + volatile uint32_t N0SA_13; /* N0SA_13 */ + volatile uint32_t N0DA_13; /* N0DA_13 */ + volatile uint32_t N0TB_13; /* N0TB_13 */ + volatile uint32_t N1SA_13; /* N1SA_13 */ + volatile uint32_t N1DA_13; /* N1DA_13 */ + volatile uint32_t N1TB_13; /* N1TB_13 */ + volatile uint32_t CRSA_13; /* CRSA_13 */ + volatile uint32_t CRDA_13; /* CRDA_13 */ + volatile uint32_t CRTB_13; /* CRTB_13 */ + volatile uint32_t CHSTAT_13; /* CHSTAT_13 */ + volatile uint32_t CHCTRL_13; /* CHCTRL_13 */ + volatile uint32_t CHCFG_13; /* CHCFG_13 */ + volatile uint32_t CHITVL_13; /* CHITVL_13 */ + volatile uint32_t CHEXT_13; /* CHEXT_13 */ + volatile uint32_t NXLA_13; /* NXLA_13 */ + volatile uint32_t CRLA_13; /* CRLA_13 */ + +/* end of struct st_dmac_n */ + +/* start of struct st_dmac_n */ + volatile uint32_t N0SA_14; /* N0SA_14 */ + volatile uint32_t N0DA_14; /* N0DA_14 */ + volatile uint32_t N0TB_14; /* N0TB_14 */ + volatile uint32_t N1SA_14; /* N1SA_14 */ + volatile uint32_t N1DA_14; /* N1DA_14 */ + volatile uint32_t N1TB_14; /* N1TB_14 */ + volatile uint32_t CRSA_14; /* CRSA_14 */ + volatile uint32_t CRDA_14; /* CRDA_14 */ + volatile uint32_t CRTB_14; /* CRTB_14 */ + volatile uint32_t CHSTAT_14; /* CHSTAT_14 */ + volatile uint32_t CHCTRL_14; /* CHCTRL_14 */ + volatile uint32_t CHCFG_14; /* CHCFG_14 */ + volatile uint32_t CHITVL_14; /* CHITVL_14 */ + volatile uint32_t CHEXT_14; /* CHEXT_14 */ + volatile uint32_t NXLA_14; /* NXLA_14 */ + volatile uint32_t CRLA_14; /* CRLA_14 */ + +/* end of struct st_dmac_n */ + +/* start of struct st_dmac_n */ + volatile uint32_t N0SA_15; /* N0SA_15 */ + volatile uint32_t N0DA_15; /* N0DA_15 */ + volatile uint32_t N0TB_15; /* N0TB_15 */ + volatile uint32_t N1SA_15; /* N1SA_15 */ + volatile uint32_t N1DA_15; /* N1DA_15 */ + volatile uint32_t N1TB_15; /* N1TB_15 */ + volatile uint32_t CRSA_15; /* CRSA_15 */ + volatile uint32_t CRDA_15; /* CRDA_15 */ + volatile uint32_t CRTB_15; /* CRTB_15 */ + volatile uint32_t CHSTAT_15; /* CHSTAT_15 */ + volatile uint32_t CHCTRL_15; /* CHCTRL_15 */ + volatile uint32_t CHCFG_15; /* CHCFG_15 */ + volatile uint32_t CHITVL_15; /* CHITVL_15 */ + volatile uint32_t CHEXT_15; /* CHEXT_15 */ + volatile uint32_t NXLA_15; /* NXLA_15 */ + volatile uint32_t CRLA_15; /* CRLA_15 */ + +/* end of struct st_dmac_n */ + volatile uint8_t dummy190[256]; /* */ + +/* start of struct st_dmaccommon_n */ + volatile uint32_t DCTRL_8_15; /* DCTRL_8_15 */ + volatile uint8_t dummy191[12]; /* */ + volatile uint32_t DSTAT_EN_8_15; /* DSTAT_EN_8_15 */ + volatile uint32_t DSTAT_ER_8_15; /* DSTAT_ER_8_15 */ + volatile uint32_t DSTAT_END_8_15; /* DSTAT_END_8_15 */ + volatile uint32_t DSTAT_TC_8_15; /* DSTAT_TC_8_15 */ + volatile uint32_t DSTAT_SUS_8_15; /* DSTAT_SUS_8_15 */ + +/* end of struct st_dmaccommon_n */ + volatile uint8_t dummy192[350095580]; /* */ + volatile uint32_t DMARS0; /* DMARS0 */ + volatile uint32_t DMARS1; /* DMARS1 */ + volatile uint32_t DMARS2; /* DMARS2 */ + volatile uint32_t DMARS3; /* DMARS3 */ + volatile uint32_t DMARS4; /* DMARS4 */ + volatile uint32_t DMARS5; /* DMARS5 */ + volatile uint32_t DMARS6; /* DMARS6 */ + volatile uint32_t DMARS7; /* DMARS7 */ +} r_io_dmac_t; + + +typedef struct st_dmaccommon_n +{ + + volatile uint32_t DCTRL_0_7; /* DCTRL_0_7 */ + volatile uint8_t dummy1[12]; /* */ + volatile uint32_t DSTAT_EN_0_7; /* DSTAT_EN_0_7 */ + volatile uint32_t DSTAT_ER_0_7; /* DSTAT_ER_0_7 */ + volatile uint32_t DSTAT_END_0_7; /* DSTAT_END_0_7 */ + volatile uint32_t DSTAT_TC_0_7; /* DSTAT_TC_0_7 */ + volatile uint32_t DSTAT_SUS_0_7; /* DSTAT_SUS_0_7 */ +} r_io_dmaccommon_n_t; + + +typedef struct st_dmac_n +{ + + volatile uint32_t N0SA_n; /* N0SA_n */ + volatile uint32_t N0DA_n; /* N0DA_n */ + volatile uint32_t N0TB_n; /* N0TB_n */ + volatile uint32_t N1SA_n; /* N1SA_n */ + volatile uint32_t N1DA_n; /* N1DA_n */ + volatile uint32_t N1TB_n; /* N1TB_n */ + volatile uint32_t CRSA_n; /* CRSA_n */ + volatile uint32_t CRDA_n; /* CRDA_n */ + volatile uint32_t CRTB_n; /* CRTB_n */ + volatile uint32_t CHSTAT_n; /* CHSTAT_n */ + volatile uint32_t CHCTRL_n; /* CHCTRL_n */ + volatile uint32_t CHCFG_n; /* CHCFG_n */ + volatile uint32_t CHITVL_n; /* CHITVL_n */ + volatile uint32_t CHEXT_n; /* CHEXT_n */ + volatile uint32_t NXLA_n; /* NXLA_n */ + volatile uint32_t CRLA_n; /* CRLA_n */ +} r_io_dmac_n_t; + + +/* Channel array defines of DMAC (2)*/ +#ifdef DECLARE_DMACmm_CHANNELS +volatile struct st_dmars_mm* DMACmm[ DMACmm_COUNT ] = + /* ->MISRA 11.3 */ /* ->SEC R2.7.1 */ + DMACmm_ADDRESS_LIST; + /* <-MISRA 11.3 */ /* <-SEC R2.7.1 */ +#endif /* DECLARE_DMACmm_CHANNELS */ + +#ifdef DECLARE_DMACn_CHANNELS +volatile struct st_dmac_n* DMACn[ DMACn_COUNT ] = + /* ->MISRA 11.3 */ /* ->SEC R2.7.1 */ + DMACn_ADDRESS_LIST; + /* <-MISRA 11.3 */ /* <-SEC R2.7.1 */ +#endif /* DECLARE_DMACn_CHANNELS */ + +#ifdef DECLARE_DMACnn_CHANNELS +volatile struct st_dmaccommon_n* DMACnn[ DMACnn_COUNT ] = + /* ->MISRA 11.3 */ /* ->SEC R2.7.1 */ + DMACnn_ADDRESS_LIST; + /* <-MISRA 11.3 */ /* <-SEC R2.7.1 */ +#endif /* DECLARE_DMACnn_CHANNELS */ +/* End of channel array defines of DMAC (2)*/ + + +/* <-SEC M1.10.1 */ +/* <-MISRA 18.4 */ /* <-SEC M1.6.2 */ +/* <-QAC 0857 */ +/* <-QAC 0639 */ +#endif diff --git a/targets/TARGET_RENESAS/TARGET_RZ_A1XX/TARGET_GR_LYCHEE/device/inc/iodefines/ethavb_iodefine.h b/targets/TARGET_RENESAS/TARGET_RZ_A1XX/TARGET_GR_LYCHEE/device/inc/iodefines/ethavb_iodefine.h new file mode 100644 index 0000000..55e469a --- /dev/null +++ b/targets/TARGET_RENESAS/TARGET_RZ_A1XX/TARGET_GR_LYCHEE/device/inc/iodefines/ethavb_iodefine.h @@ -0,0 +1,388 @@ +/******************************************************************************* +* DISCLAIMER +* This software is supplied by Renesas Electronics Corporation and is only +* intended for use with Renesas products. No other uses are authorized. This +* software is owned by Renesas Electronics Corporation and is protected under +* all applicable laws, including copyright laws. +* THIS SOFTWARE IS PROVIDED "AS IS" AND RENESAS MAKES NO WARRANTIES REGARDING +* THIS SOFTWARE, WHETHER EXPRESS, IMPLIED OR STATUTORY, INCLUDING BUT NOT +* LIMITED TO WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE +* AND NON-INFRINGEMENT. ALL SUCH WARRANTIES ARE EXPRESSLY DISCLAIMED. +* TO THE MAXIMUM EXTENT PERMITTED NOT PROHIBITED BY LAW, NEITHER RENESAS +* ELECTRONICS CORPORATION NOR ANY OF ITS AFFILIATED COMPANIES SHALL BE LIABLE +* FOR ANY DIRECT, INDIRECT, SPECIAL, INCIDENTAL OR CONSEQUENTIAL DAMAGES FOR +* ANY REASON RELATED TO THIS SOFTWARE, EVEN IF RENESAS OR ITS AFFILIATES HAVE +* BEEN ADVISED OF THE POSSIBILITY OF SUCH DAMAGES. +* Renesas reserves the right, without notice, to make changes to this software +* and to discontinue the availability of this software. By using this software, +* you agree to the additional terms and conditions found by accessing the +* following link: +* http://www.renesas.com/disclaimer* +* Copyright (C) 2013-2016 Renesas Electronics Corporation. All rights reserved. +*******************************************************************************/ +/******************************************************************************* +* File Name : ethavb_iodefine.h +* $Rev: $ +* $Date:: $ +* Description : Definition of I/O Register for RZ/A1LU (V3.00l) +******************************************************************************/ +#ifndef ETHAVB_IODEFINE_H +#define ETHAVB_IODEFINE_H + +#define ETHAVB (*(struct st_ethavb *)0xE8215000uL) /* ETHAVB */ + + +#define ETHAVBCCC (ETHAVB.CCC) +#define ETHAVBDBAT (ETHAVB.DBAT) +#define ETHAVBDLR (ETHAVB.DLR) +#define ETHAVBCSR (ETHAVB.CSR) +#define ETHAVBCDAR0 (ETHAVB.CDAR0) +#define ETHAVBCDAR1 (ETHAVB.CDAR1) +#define ETHAVBCDAR2 (ETHAVB.CDAR2) +#define ETHAVBCDAR3 (ETHAVB.CDAR3) +#define ETHAVBCDAR4 (ETHAVB.CDAR4) +#define ETHAVBCDAR5 (ETHAVB.CDAR5) +#define ETHAVBCDAR6 (ETHAVB.CDAR6) +#define ETHAVBCDAR7 (ETHAVB.CDAR7) +#define ETHAVBCDAR8 (ETHAVB.CDAR8) +#define ETHAVBCDAR9 (ETHAVB.CDAR9) +#define ETHAVBCDAR10 (ETHAVB.CDAR10) +#define ETHAVBCDAR11 (ETHAVB.CDAR11) +#define ETHAVBCDAR12 (ETHAVB.CDAR12) +#define ETHAVBCDAR13 (ETHAVB.CDAR13) +#define ETHAVBCDAR14 (ETHAVB.CDAR14) +#define ETHAVBCDAR15 (ETHAVB.CDAR15) +#define ETHAVBCDAR16 (ETHAVB.CDAR16) +#define ETHAVBCDAR17 (ETHAVB.CDAR17) +#define ETHAVBCDAR18 (ETHAVB.CDAR18) +#define ETHAVBCDAR19 (ETHAVB.CDAR19) +#define ETHAVBCDAR20 (ETHAVB.CDAR20) +#define ETHAVBCDAR21 (ETHAVB.CDAR21) +#define ETHAVBESR (ETHAVB.ESR) +#define ETHAVBRCR (ETHAVB.RCR) +#define ETHAVBRQC0 (ETHAVB.RQC0) +#define ETHAVBRQC1 (ETHAVB.RQC1) +#define ETHAVBRQC2 (ETHAVB.RQC2) +#define ETHAVBRQC3 (ETHAVB.RQC3) +#define ETHAVBRQC4 (ETHAVB.RQC4) +#define ETHAVBRPC (ETHAVB.RPC) +#define ETHAVBUFCS (ETHAVB.UFCS) +#define ETHAVBUFCV0 (ETHAVB.UFCV0) +#define ETHAVBUFCV1 (ETHAVB.UFCV1) +#define ETHAVBUFCV2 (ETHAVB.UFCV2) +#define ETHAVBUFCV3 (ETHAVB.UFCV3) +#define ETHAVBUFCV4 (ETHAVB.UFCV4) +#define ETHAVBUFCD0 (ETHAVB.UFCD0) +#define ETHAVBUFCD1 (ETHAVB.UFCD1) +#define ETHAVBUFCD2 (ETHAVB.UFCD2) +#define ETHAVBUFCD3 (ETHAVB.UFCD3) +#define ETHAVBUFCD4 (ETHAVB.UFCD4) +#define ETHAVBSFO (ETHAVB.SFO) +#define ETHAVBSFP0 (ETHAVB.SFP0) +#define ETHAVBSFP1 (ETHAVB.SFP1) +#define ETHAVBSFP2 (ETHAVB.SFP2) +#define ETHAVBSFP3 (ETHAVB.SFP3) +#define ETHAVBSFP4 (ETHAVB.SFP4) +#define ETHAVBSFP5 (ETHAVB.SFP5) +#define ETHAVBSFP6 (ETHAVB.SFP6) +#define ETHAVBSFP7 (ETHAVB.SFP7) +#define ETHAVBSFP8 (ETHAVB.SFP8) +#define ETHAVBSFP9 (ETHAVB.SFP9) +#define ETHAVBSFP10 (ETHAVB.SFP10) +#define ETHAVBSFP11 (ETHAVB.SFP11) +#define ETHAVBSFP12 (ETHAVB.SFP12) +#define ETHAVBSFP13 (ETHAVB.SFP13) +#define ETHAVBSFP14 (ETHAVB.SFP14) +#define ETHAVBSFP15 (ETHAVB.SFP15) +#define ETHAVBSFP16 (ETHAVB.SFP16) +#define ETHAVBSFP17 (ETHAVB.SFP17) +#define ETHAVBSFP18 (ETHAVB.SFP18) +#define ETHAVBSFP19 (ETHAVB.SFP19) +#define ETHAVBSFP20 (ETHAVB.SFP20) +#define ETHAVBSFP21 (ETHAVB.SFP21) +#define ETHAVBSFP22 (ETHAVB.SFP22) +#define ETHAVBSFP23 (ETHAVB.SFP23) +#define ETHAVBSFP24 (ETHAVB.SFP24) +#define ETHAVBSFP25 (ETHAVB.SFP25) +#define ETHAVBSFP26 (ETHAVB.SFP26) +#define ETHAVBSFP27 (ETHAVB.SFP27) +#define ETHAVBSFP28 (ETHAVB.SFP28) +#define ETHAVBSFP29 (ETHAVB.SFP29) +#define ETHAVBSFP30 (ETHAVB.SFP30) +#define ETHAVBSFP31 (ETHAVB.SFP31) +#define ETHAVBSFM0 (ETHAVB.SFM0) +#define ETHAVBSFM1 (ETHAVB.SFM1) +#define ETHAVBTGC (ETHAVB.TGC) +#define ETHAVBTCCR (ETHAVB.TCCR) +#define ETHAVBTSR (ETHAVB.TSR) +#define ETHAVBTFA0 (ETHAVB.TFA0) +#define ETHAVBTFA1 (ETHAVB.TFA1) +#define ETHAVBTFA2 (ETHAVB.TFA2) +#define ETHAVBCIVR0 (ETHAVB.CIVR0) +#define ETHAVBCIVR1 (ETHAVB.CIVR1) +#define ETHAVBCDVR0 (ETHAVB.CDVR0) +#define ETHAVBCDVR1 (ETHAVB.CDVR1) +#define ETHAVBCUL0 (ETHAVB.CUL0) +#define ETHAVBCUL1 (ETHAVB.CUL1) +#define ETHAVBCLL0 (ETHAVB.CLL0) +#define ETHAVBCLL1 (ETHAVB.CLL1) +#define ETHAVBDIC (ETHAVB.DIC) +#define ETHAVBDIS (ETHAVB.DIS) +#define ETHAVBEIC (ETHAVB.EIC) +#define ETHAVBEIS (ETHAVB.EIS) +#define ETHAVBRIC0 (ETHAVB.RIC0) +#define ETHAVBRIS0 (ETHAVB.RIS0) +#define ETHAVBRIC1 (ETHAVB.RIC1) +#define ETHAVBRIS1 (ETHAVB.RIS1) +#define ETHAVBRIC2 (ETHAVB.RIC2) +#define ETHAVBRIS2 (ETHAVB.RIS2) +#define ETHAVBTIC (ETHAVB.TIC) +#define ETHAVBTIS (ETHAVB.TIS) +#define ETHAVBISS (ETHAVB.ISS) +#define ETHAVBGCCR (ETHAVB.GCCR) +#define ETHAVBGMTT (ETHAVB.GMTT) +#define ETHAVBGPTC (ETHAVB.GPTC) +#define ETHAVBGTI (ETHAVB.GTI) +#define ETHAVBGTO0 (ETHAVB.GTO0) +#define ETHAVBGTO1 (ETHAVB.GTO1) +#define ETHAVBGTO2 (ETHAVB.GTO2) +#define ETHAVBGIC (ETHAVB.GIC) +#define ETHAVBGIS (ETHAVB.GIS) +#define ETHAVBGCPT (ETHAVB.GCPT) +#define ETHAVBGCT0 (ETHAVB.GCT0) +#define ETHAVBGCT1 (ETHAVB.GCT1) +#define ETHAVBGCT2 (ETHAVB.GCT2) +#define ETHAVBGCEC (ETHAVB.GCEC) +#define ETHAVBECMR (ETHAVB.ECMR) +#define ETHAVBRFLR (ETHAVB.RFLR) +#define ETHAVBECSR (ETHAVB.ECSR) +#define ETHAVBECSIPR (ETHAVB.ECSIPR) +#define ETHAVBPIR (ETHAVB.PIR) +#define ETHAVBAPR (ETHAVB.APR) +#define ETHAVBMPR (ETHAVB.MPR) +#define ETHAVBPFTCR (ETHAVB.PFTCR) +#define ETHAVBPFRCR (ETHAVB.PFRCR) +#define ETHAVBTPAUSER (ETHAVB.TPAUSER) +#define ETHAVBMAHR (ETHAVB.MAHR) +#define ETHAVBMALR (ETHAVB.MALR) +#define ETHAVBCEFCR (ETHAVB.CEFCR) +#define ETHAVBFRECR (ETHAVB.FRECR) +#define ETHAVBTSFRCR (ETHAVB.TSFRCR) +#define ETHAVBTLFRCR (ETHAVB.TLFRCR) +#define ETHAVBRFCR (ETHAVB.RFCR) +#define ETHAVBMAFCR (ETHAVB.MAFCR) + +#define ETHAVB_CDAR_COUNT 22 +#define ETHAVB_RQC_COUNT 5 +#define ETHAVB_UFCV_COUNT 5 +#define ETHAVB_UFCD_COUNT 5 +#define ETHAVB_SFP_COUNT 32 +#define ETHAVB_SFM_COUNT 2 +#define ETHAVB_TFA_COUNT 3 +#define ETHAVB_CIVR_COUNT 2 +#define ETHAVB_CDVR_COUNT 2 +#define ETHAVB_CUL_COUNT 2 +#define ETHAVB_CLL_COUNT 2 +#define ETHAVB_GTO_COUNT 3 +#define ETHAVB_GCT_COUNT 3 + + +typedef struct st_ethavb +{ + /* ETHAVB */ + volatile uint32_t CCC; /* CCC */ + volatile uint32_t DBAT; /* DBAT */ + volatile uint32_t DLR; /* DLR */ + volatile uint32_t CSR; /* CSR */ + +/* #define ETHAVB_CDAR_COUNT 22 */ + volatile uint32_t CDAR0; /* CDAR0 */ + volatile uint32_t CDAR1; /* CDAR1 */ + volatile uint32_t CDAR2; /* CDAR2 */ + volatile uint32_t CDAR3; /* CDAR3 */ + volatile uint32_t CDAR4; /* CDAR4 */ + volatile uint32_t CDAR5; /* CDAR5 */ + volatile uint32_t CDAR6; /* CDAR6 */ + volatile uint32_t CDAR7; /* CDAR7 */ + volatile uint32_t CDAR8; /* CDAR8 */ + volatile uint32_t CDAR9; /* CDAR9 */ + volatile uint32_t CDAR10; /* CDAR10 */ + volatile uint32_t CDAR11; /* CDAR11 */ + volatile uint32_t CDAR12; /* CDAR12 */ + volatile uint32_t CDAR13; /* CDAR13 */ + volatile uint32_t CDAR14; /* CDAR14 */ + volatile uint32_t CDAR15; /* CDAR15 */ + volatile uint32_t CDAR16; /* CDAR16 */ + volatile uint32_t CDAR17; /* CDAR17 */ + volatile uint32_t CDAR18; /* CDAR18 */ + volatile uint32_t CDAR19; /* CDAR19 */ + volatile uint32_t CDAR20; /* CDAR20 */ + volatile uint32_t CDAR21; /* CDAR21 */ + volatile uint8_t dummy319[32]; /* */ + volatile uint32_t ESR; /* ESR */ + volatile uint8_t dummy320[4]; /* */ + volatile uint32_t RCR; /* RCR */ + +/* #define ETHAVB_RQC_COUNT 5 */ + volatile uint32_t RQC0; /* RQC0 */ + volatile uint32_t RQC1; /* RQC1 */ + volatile uint32_t RQC2; /* RQC2 */ + volatile uint32_t RQC3; /* RQC3 */ + volatile uint32_t RQC4; /* RQC4 */ + volatile uint8_t dummy321[8]; /* */ + volatile uint32_t RPC; /* RPC */ + volatile uint8_t dummy322[12]; /* */ + volatile uint32_t UFCS; /* UFCS */ + +/* #define ETHAVB_UFCV_COUNT 5 */ + volatile uint32_t UFCV0; /* UFCV0 */ + volatile uint32_t UFCV1; /* UFCV1 */ + volatile uint32_t UFCV2; /* UFCV2 */ + volatile uint32_t UFCV3; /* UFCV3 */ + volatile uint32_t UFCV4; /* UFCV4 */ + volatile uint8_t dummy323[8]; /* */ + +/* #define ETHAVB_UFCD_COUNT 5 */ + volatile uint32_t UFCD0; /* UFCD0 */ + volatile uint32_t UFCD1; /* UFCD1 */ + volatile uint32_t UFCD2; /* UFCD2 */ + volatile uint32_t UFCD3; /* UFCD3 */ + volatile uint32_t UFCD4; /* UFCD4 */ + volatile uint8_t dummy324[8]; /* */ + volatile uint32_t SFO; /* SFO */ + +/* #define ETHAVB_SFP_COUNT 32 */ + volatile uint32_t SFP0; /* SFP0 */ + volatile uint32_t SFP1; /* SFP1 */ + volatile uint32_t SFP2; /* SFP2 */ + volatile uint32_t SFP3; /* SFP3 */ + volatile uint32_t SFP4; /* SFP4 */ + volatile uint32_t SFP5; /* SFP5 */ + volatile uint32_t SFP6; /* SFP6 */ + volatile uint32_t SFP7; /* SFP7 */ + volatile uint32_t SFP8; /* SFP8 */ + volatile uint32_t SFP9; /* SFP9 */ + volatile uint32_t SFP10; /* SFP10 */ + volatile uint32_t SFP11; /* SFP11 */ + volatile uint32_t SFP12; /* SFP12 */ + volatile uint32_t SFP13; /* SFP13 */ + volatile uint32_t SFP14; /* SFP14 */ + volatile uint32_t SFP15; /* SFP15 */ + volatile uint32_t SFP16; /* SFP16 */ + volatile uint32_t SFP17; /* SFP17 */ + volatile uint32_t SFP18; /* SFP18 */ + volatile uint32_t SFP19; /* SFP19 */ + volatile uint32_t SFP20; /* SFP20 */ + volatile uint32_t SFP21; /* SFP21 */ + volatile uint32_t SFP22; /* SFP22 */ + volatile uint32_t SFP23; /* SFP23 */ + volatile uint32_t SFP24; /* SFP24 */ + volatile uint32_t SFP25; /* SFP25 */ + volatile uint32_t SFP26; /* SFP26 */ + volatile uint32_t SFP27; /* SFP27 */ + volatile uint32_t SFP28; /* SFP28 */ + volatile uint32_t SFP29; /* SFP29 */ + volatile uint32_t SFP30; /* SFP30 */ + volatile uint32_t SFP31; /* SFP31 */ + volatile uint8_t dummy325[64]; /* */ + +/* #define ETHAVB_SFM_COUNT 2 */ + volatile uint32_t SFM0; /* SFM0 */ + volatile uint32_t SFM1; /* SFM1 */ + volatile uint8_t dummy326[312]; /* */ + volatile uint32_t TGC; /* TGC */ + volatile uint32_t TCCR; /* TCCR */ + volatile uint32_t TSR; /* TSR */ + volatile uint8_t dummy327[4]; /* */ + +/* #define ETHAVB_TFA_COUNT 3 */ + volatile uint32_t TFA0; /* TFA0 */ + volatile uint32_t TFA1; /* TFA1 */ + volatile uint32_t TFA2; /* TFA2 */ + volatile uint8_t dummy328[4]; /* */ + +/* #define ETHAVB_CIVR_COUNT 2 */ + volatile uint32_t CIVR0; /* CIVR0 */ + volatile uint32_t CIVR1; /* CIVR1 */ + +/* #define ETHAVB_CDVR_COUNT 2 */ + volatile uint32_t CDVR0; /* CDVR0 */ + volatile uint32_t CDVR1; /* CDVR1 */ + +/* #define ETHAVB_CUL_COUNT 2 */ + volatile uint32_t CUL0; /* CUL0 */ + volatile uint32_t CUL1; /* CUL1 */ + +/* #define ETHAVB_CLL_COUNT 2 */ + volatile uint32_t CLL0; /* CLL0 */ + volatile uint32_t CLL1; /* CLL1 */ + volatile uint8_t dummy329[16]; /* */ + volatile uint32_t DIC; /* DIC */ + volatile uint32_t DIS; /* DIS */ + volatile uint32_t EIC; /* EIC */ + volatile uint32_t EIS; /* EIS */ + volatile uint32_t RIC0; /* RIC0 */ + volatile uint32_t RIS0; /* RIS0 */ + volatile uint32_t RIC1; /* RIC1 */ + volatile uint32_t RIS1; /* RIS1 */ + volatile uint32_t RIC2; /* RIC2 */ + volatile uint32_t RIS2; /* RIS2 */ + volatile uint32_t TIC; /* TIC */ + volatile uint32_t TIS; /* TIS */ + volatile uint32_t ISS; /* ISS */ + volatile uint8_t dummy330[12]; /* */ + volatile uint32_t GCCR; /* GCCR */ + volatile uint32_t GMTT; /* GMTT */ + volatile uint32_t GPTC; /* GPTC */ + volatile uint32_t GTI; /* GTI */ + +/* #define ETHAVB_GTO_COUNT 3 */ + volatile uint32_t GTO0; /* GTO0 */ + volatile uint32_t GTO1; /* GTO1 */ + volatile uint32_t GTO2; /* GTO2 */ + volatile uint32_t GIC; /* GIC */ + volatile uint32_t GIS; /* GIS */ + volatile uint32_t GCPT; /* GCPT */ + +/* #define ETHAVB_GCT_COUNT 3 */ + volatile uint32_t GCT0; /* GCT0 */ + volatile uint32_t GCT1; /* GCT1 */ + volatile uint32_t GCT2; /* GCT2 */ + volatile uint8_t dummy331[20]; /* */ + volatile uint32_t GCEC; /* GCEC */ + volatile uint8_t dummy332[292]; /* */ + volatile uint32_t ECMR; /* ECMR */ + volatile uint8_t dummy333[4]; /* */ + volatile uint32_t RFLR; /* RFLR */ + volatile uint8_t dummy334[4]; /* */ + volatile uint32_t ECSR; /* ECSR */ + volatile uint8_t dummy335[4]; /* */ + volatile uint32_t ECSIPR; /* ECSIPR */ + volatile uint8_t dummy336[4]; /* */ + volatile uint32_t PIR; /* PIR */ + volatile uint8_t dummy337[48]; /* */ + volatile uint32_t APR; /* APR */ + volatile uint32_t MPR; /* MPR */ + volatile uint32_t PFTCR; /* PFTCR */ + volatile uint32_t PFRCR; /* PFRCR */ + volatile uint32_t TPAUSER; /* TPAUSER */ + volatile uint8_t dummy338[88]; /* */ + volatile uint32_t MAHR; /* MAHR */ + volatile uint8_t dummy339[4]; /* */ + volatile uint32_t MALR; /* MALR */ + volatile uint8_t dummy340[372]; /* */ + volatile uint32_t CEFCR; /* CEFCR */ + volatile uint8_t dummy341[4]; /* */ + volatile uint32_t FRECR; /* FRECR */ + volatile uint8_t dummy342[4]; /* */ + volatile uint32_t TSFRCR; /* TSFRCR */ + volatile uint8_t dummy343[4]; /* */ + volatile uint32_t TLFRCR; /* TLFRCR */ + volatile uint8_t dummy344[4]; /* */ + volatile uint32_t RFCR; /* RFCR */ + volatile uint8_t dummy345[20]; /* */ + volatile uint32_t MAFCR; /* MAFCR */ +} r_io_ethavb_t; + + +#endif diff --git a/targets/TARGET_RENESAS/TARGET_RZ_A1XX/TARGET_GR_LYCHEE/device/inc/iodefines/ether_iodefine.h b/targets/TARGET_RENESAS/TARGET_RZ_A1XX/TARGET_GR_LYCHEE/device/inc/iodefines/ether_iodefine.h new file mode 100644 index 0000000..4b4cce8 --- /dev/null +++ b/targets/TARGET_RENESAS/TARGET_RZ_A1XX/TARGET_GR_LYCHEE/device/inc/iodefines/ether_iodefine.h @@ -0,0 +1,509 @@ +/******************************************************************************* +* DISCLAIMER +* This software is supplied by Renesas Electronics Corporation and is only +* intended for use with Renesas products. No other uses are authorized. This +* software is owned by Renesas Electronics Corporation and is protected under +* all applicable laws, including copyright laws. +* THIS SOFTWARE IS PROVIDED "AS IS" AND RENESAS MAKES NO WARRANTIES REGARDING +* THIS SOFTWARE, WHETHER EXPRESS, IMPLIED OR STATUTORY, INCLUDING BUT NOT +* LIMITED TO WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE +* AND NON-INFRINGEMENT. ALL SUCH WARRANTIES ARE EXPRESSLY DISCLAIMED. +* TO THE MAXIMUM EXTENT PERMITTED NOT PROHIBITED BY LAW, NEITHER RENESAS +* ELECTRONICS CORPORATION NOR ANY OF ITS AFFILIATED COMPANIES SHALL BE LIABLE +* FOR ANY DIRECT, INDIRECT, SPECIAL, INCIDENTAL OR CONSEQUENTIAL DAMAGES FOR +* ANY REASON RELATED TO THIS SOFTWARE, EVEN IF RENESAS OR ITS AFFILIATES HAVE +* BEEN ADVISED OF THE POSSIBILITY OF SUCH DAMAGES. +* Renesas reserves the right, without notice, to make changes to this software +* and to discontinue the availability of this software. By using this software, +* you agree to the additional terms and conditions found by accessing the +* following link: +* http://www.renesas.com/disclaimer* +* Copyright (C) 2013-2016 Renesas Electronics Corporation. All rights reserved. +*******************************************************************************/ +/******************************************************************************* +* File Name : ether_iodefine.h +* $Rev: $ +* $Date:: $ +* Description : Definition of I/O Register for RZ/A1LU (V3.00l) +******************************************************************************/ +#ifndef ETHER_IODEFINE_H +#define ETHER_IODEFINE_H +/* ->QAC 0639 : Over 127 members (C90) */ +/* ->QAC 0857 : Over 1024 #define (C90) */ +/* ->MISRA 18.4 : Pack unpack union */ /* ->SEC M1.6.2 */ +/* ->SEC M1.10.1 : Not magic number */ + +#define ETHER (*(struct st_ether *)0xE8203000uL) /* ETHER */ + + +/* Start of channel array defines of ETHER */ + +/* Channel array defines of ETHER_FROM_TSU_ADRH0_ARRAY */ +/*(Sample) value = ETHER_FROM_TSU_ADRH0_ARRAY[ channel ]->TSU_ADRH0; */ +#define ETHER_FROM_TSU_ADRH0_ARRAY_COUNT (32) +#define ETHER_FROM_TSU_ADRH0_ARRAY_ADDRESS_LIST \ +{ /* ->MISRA 11.3 */ /* ->SEC R2.7.1 */ \ + ÐER_FROM_TSU_ADRH0, ÐER_FROM_TSU_ADRH1, ÐER_FROM_TSU_ADRH2, ÐER_FROM_TSU_ADRH3, ÐER_FROM_TSU_ADRH4, ÐER_FROM_TSU_ADRH5, ÐER_FROM_TSU_ADRH6, ÐER_FROM_TSU_ADRH7, \ + ÐER_FROM_TSU_ADRH8, ÐER_FROM_TSU_ADRH9, ÐER_FROM_TSU_ADRH10, ÐER_FROM_TSU_ADRH11, ÐER_FROM_TSU_ADRH12, ÐER_FROM_TSU_ADRH13, ÐER_FROM_TSU_ADRH14, ÐER_FROM_TSU_ADRH15, \ + ÐER_FROM_TSU_ADRH16, ÐER_FROM_TSU_ADRH17, ÐER_FROM_TSU_ADRH18, ÐER_FROM_TSU_ADRH19, ÐER_FROM_TSU_ADRH20, ÐER_FROM_TSU_ADRH21, ÐER_FROM_TSU_ADRH22, ÐER_FROM_TSU_ADRH23, \ + ÐER_FROM_TSU_ADRH24, ÐER_FROM_TSU_ADRH25, ÐER_FROM_TSU_ADRH26, ÐER_FROM_TSU_ADRH27, ÐER_FROM_TSU_ADRH28, ÐER_FROM_TSU_ADRH29, ÐER_FROM_TSU_ADRH30, ÐER_FROM_TSU_ADRH31 \ +} /* <-MISRA 11.3 */ /* <-SEC R2.7.1 */ /* { } is for MISRA 19.4 */ +#define ETHER_FROM_TSU_ADRH0 (*(struct st_ether_from_tsu_adrh0 *)ÐER.TSU_ADRH0) /* ETHER_FROM_TSU_ADRH0 */ +#define ETHER_FROM_TSU_ADRH1 (*(struct st_ether_from_tsu_adrh0 *)ÐER.TSU_ADRH1) /* ETHER_FROM_TSU_ADRH1 */ +#define ETHER_FROM_TSU_ADRH2 (*(struct st_ether_from_tsu_adrh0 *)ÐER.TSU_ADRH2) /* ETHER_FROM_TSU_ADRH2 */ +#define ETHER_FROM_TSU_ADRH3 (*(struct st_ether_from_tsu_adrh0 *)ÐER.TSU_ADRH3) /* ETHER_FROM_TSU_ADRH3 */ +#define ETHER_FROM_TSU_ADRH4 (*(struct st_ether_from_tsu_adrh0 *)ÐER.TSU_ADRH4) /* ETHER_FROM_TSU_ADRH4 */ +#define ETHER_FROM_TSU_ADRH5 (*(struct st_ether_from_tsu_adrh0 *)ÐER.TSU_ADRH5) /* ETHER_FROM_TSU_ADRH5 */ +#define ETHER_FROM_TSU_ADRH6 (*(struct st_ether_from_tsu_adrh0 *)ÐER.TSU_ADRH6) /* ETHER_FROM_TSU_ADRH6 */ +#define ETHER_FROM_TSU_ADRH7 (*(struct st_ether_from_tsu_adrh0 *)ÐER.TSU_ADRH7) /* ETHER_FROM_TSU_ADRH7 */ +#define ETHER_FROM_TSU_ADRH8 (*(struct st_ether_from_tsu_adrh0 *)ÐER.TSU_ADRH8) /* ETHER_FROM_TSU_ADRH8 */ +#define ETHER_FROM_TSU_ADRH9 (*(struct st_ether_from_tsu_adrh0 *)ÐER.TSU_ADRH9) /* ETHER_FROM_TSU_ADRH9 */ +#define ETHER_FROM_TSU_ADRH10 (*(struct st_ether_from_tsu_adrh0 *)ÐER.TSU_ADRH10) /* ETHER_FROM_TSU_ADRH10 */ +#define ETHER_FROM_TSU_ADRH11 (*(struct st_ether_from_tsu_adrh0 *)ÐER.TSU_ADRH11) /* ETHER_FROM_TSU_ADRH11 */ +#define ETHER_FROM_TSU_ADRH12 (*(struct st_ether_from_tsu_adrh0 *)ÐER.TSU_ADRH12) /* ETHER_FROM_TSU_ADRH12 */ +#define ETHER_FROM_TSU_ADRH13 (*(struct st_ether_from_tsu_adrh0 *)ÐER.TSU_ADRH13) /* ETHER_FROM_TSU_ADRH13 */ +#define ETHER_FROM_TSU_ADRH14 (*(struct st_ether_from_tsu_adrh0 *)ÐER.TSU_ADRH14) /* ETHER_FROM_TSU_ADRH14 */ +#define ETHER_FROM_TSU_ADRH15 (*(struct st_ether_from_tsu_adrh0 *)ÐER.TSU_ADRH15) /* ETHER_FROM_TSU_ADRH15 */ +#define ETHER_FROM_TSU_ADRH16 (*(struct st_ether_from_tsu_adrh0 *)ÐER.TSU_ADRH16) /* ETHER_FROM_TSU_ADRH16 */ +#define ETHER_FROM_TSU_ADRH17 (*(struct st_ether_from_tsu_adrh0 *)ÐER.TSU_ADRH17) /* ETHER_FROM_TSU_ADRH17 */ +#define ETHER_FROM_TSU_ADRH18 (*(struct st_ether_from_tsu_adrh0 *)ÐER.TSU_ADRH18) /* ETHER_FROM_TSU_ADRH18 */ +#define ETHER_FROM_TSU_ADRH19 (*(struct st_ether_from_tsu_adrh0 *)ÐER.TSU_ADRH19) /* ETHER_FROM_TSU_ADRH19 */ +#define ETHER_FROM_TSU_ADRH20 (*(struct st_ether_from_tsu_adrh0 *)ÐER.TSU_ADRH20) /* ETHER_FROM_TSU_ADRH20 */ +#define ETHER_FROM_TSU_ADRH21 (*(struct st_ether_from_tsu_adrh0 *)ÐER.TSU_ADRH21) /* ETHER_FROM_TSU_ADRH21 */ +#define ETHER_FROM_TSU_ADRH22 (*(struct st_ether_from_tsu_adrh0 *)ÐER.TSU_ADRH22) /* ETHER_FROM_TSU_ADRH22 */ +#define ETHER_FROM_TSU_ADRH23 (*(struct st_ether_from_tsu_adrh0 *)ÐER.TSU_ADRH23) /* ETHER_FROM_TSU_ADRH23 */ +#define ETHER_FROM_TSU_ADRH24 (*(struct st_ether_from_tsu_adrh0 *)ÐER.TSU_ADRH24) /* ETHER_FROM_TSU_ADRH24 */ +#define ETHER_FROM_TSU_ADRH25 (*(struct st_ether_from_tsu_adrh0 *)ÐER.TSU_ADRH25) /* ETHER_FROM_TSU_ADRH25 */ +#define ETHER_FROM_TSU_ADRH26 (*(struct st_ether_from_tsu_adrh0 *)ÐER.TSU_ADRH26) /* ETHER_FROM_TSU_ADRH26 */ +#define ETHER_FROM_TSU_ADRH27 (*(struct st_ether_from_tsu_adrh0 *)ÐER.TSU_ADRH27) /* ETHER_FROM_TSU_ADRH27 */ +#define ETHER_FROM_TSU_ADRH28 (*(struct st_ether_from_tsu_adrh0 *)ÐER.TSU_ADRH28) /* ETHER_FROM_TSU_ADRH28 */ +#define ETHER_FROM_TSU_ADRH29 (*(struct st_ether_from_tsu_adrh0 *)ÐER.TSU_ADRH29) /* ETHER_FROM_TSU_ADRH29 */ +#define ETHER_FROM_TSU_ADRH30 (*(struct st_ether_from_tsu_adrh0 *)ÐER.TSU_ADRH30) /* ETHER_FROM_TSU_ADRH30 */ +#define ETHER_FROM_TSU_ADRH31 (*(struct st_ether_from_tsu_adrh0 *)ÐER.TSU_ADRH31) /* ETHER_FROM_TSU_ADRH31 */ + +/* End of channel array defines of ETHER */ + + +#define ETHEREDSR0 (ETHER.EDSR0) +#define ETHERTDLAR0 (ETHER.TDLAR0) +#define ETHERTDFAR0 (ETHER.TDFAR0) +#define ETHERTDFXR0 (ETHER.TDFXR0) +#define ETHERTDFFR0 (ETHER.TDFFR0) +#define ETHERRDLAR0 (ETHER.RDLAR0) +#define ETHERRDFAR0 (ETHER.RDFAR0) +#define ETHERRDFXR0 (ETHER.RDFXR0) +#define ETHERRDFFR0 (ETHER.RDFFR0) +#define ETHEREDMR0 (ETHER.EDMR0) +#define ETHEREDTRR0 (ETHER.EDTRR0) +#define ETHEREDRRR0 (ETHER.EDRRR0) +#define ETHEREESR0 (ETHER.EESR0) +#define ETHEREESIPR0 (ETHER.EESIPR0) +#define ETHERTRSCER0 (ETHER.TRSCER0) +#define ETHERRMFCR0 (ETHER.RMFCR0) +#define ETHERTFTR0 (ETHER.TFTR0) +#define ETHERFDR0 (ETHER.FDR0) +#define ETHERRMCR0 (ETHER.RMCR0) +#define ETHERRPADIR0 (ETHER.RPADIR0) +#define ETHERFCFTR0 (ETHER.FCFTR0) +#define ETHERCSMR (ETHER.CSMR) +#define ETHERCSSBM (ETHER.CSSBM) +#define ETHERCSSMR (ETHER.CSSMR) +#define ETHERECMR0 (ETHER.ECMR0) +#define ETHERRFLR0 (ETHER.RFLR0) +#define ETHERECSR0 (ETHER.ECSR0) +#define ETHERECSIPR0 (ETHER.ECSIPR0) +#define ETHERPIR0 (ETHER.PIR0) +#define ETHERAPR0 (ETHER.APR0) +#define ETHERMPR0 (ETHER.MPR0) +#define ETHERPFTCR0 (ETHER.PFTCR0) +#define ETHERPFRCR0 (ETHER.PFRCR0) +#define ETHERTPAUSER0 (ETHER.TPAUSER0) +#define ETHERMAHR0 (ETHER.MAHR0) +#define ETHERMALR0 (ETHER.MALR0) +#define ETHERCEFCR0 (ETHER.CEFCR0) +#define ETHERFRECR0 (ETHER.FRECR0) +#define ETHERTSFRCR0 (ETHER.TSFRCR0) +#define ETHERTLFRCR0 (ETHER.TLFRCR0) +#define ETHERRFCR0 (ETHER.RFCR0) +#define ETHERMAFCR0 (ETHER.MAFCR0) +#define ETHERARSTR (ETHER.ARSTR) +#define ETHERTSU_CTRST (ETHER.TSU_CTRST) +#define ETHERTSU_VTAG0 (ETHER.TSU_VTAG0) +#define ETHERTSU_ADSBSY (ETHER.TSU_ADSBSY) +#define ETHERTSU_TEN (ETHER.TSU_TEN) +#define ETHERTXNLCR0 (ETHER.TXNLCR0) +#define ETHERTXALCR0 (ETHER.TXALCR0) +#define ETHERRXNLCR0 (ETHER.RXNLCR0) +#define ETHERRXALCR0 (ETHER.RXALCR0) +#define ETHERTSU_ADRH0 (ETHER.TSU_ADRH0) +#define ETHERTSU_ADRL0 (ETHER.TSU_ADRL0) +#define ETHERTSU_ADRH1 (ETHER.TSU_ADRH1) +#define ETHERTSU_ADRL1 (ETHER.TSU_ADRL1) +#define ETHERTSU_ADRH2 (ETHER.TSU_ADRH2) +#define ETHERTSU_ADRL2 (ETHER.TSU_ADRL2) +#define ETHERTSU_ADRH3 (ETHER.TSU_ADRH3) +#define ETHERTSU_ADRL3 (ETHER.TSU_ADRL3) +#define ETHERTSU_ADRH4 (ETHER.TSU_ADRH4) +#define ETHERTSU_ADRL4 (ETHER.TSU_ADRL4) +#define ETHERTSU_ADRH5 (ETHER.TSU_ADRH5) +#define ETHERTSU_ADRL5 (ETHER.TSU_ADRL5) +#define ETHERTSU_ADRH6 (ETHER.TSU_ADRH6) +#define ETHERTSU_ADRL6 (ETHER.TSU_ADRL6) +#define ETHERTSU_ADRH7 (ETHER.TSU_ADRH7) +#define ETHERTSU_ADRL7 (ETHER.TSU_ADRL7) +#define ETHERTSU_ADRH8 (ETHER.TSU_ADRH8) +#define ETHERTSU_ADRL8 (ETHER.TSU_ADRL8) +#define ETHERTSU_ADRH9 (ETHER.TSU_ADRH9) +#define ETHERTSU_ADRL9 (ETHER.TSU_ADRL9) +#define ETHERTSU_ADRH10 (ETHER.TSU_ADRH10) +#define ETHERTSU_ADRL10 (ETHER.TSU_ADRL10) +#define ETHERTSU_ADRH11 (ETHER.TSU_ADRH11) +#define ETHERTSU_ADRL11 (ETHER.TSU_ADRL11) +#define ETHERTSU_ADRH12 (ETHER.TSU_ADRH12) +#define ETHERTSU_ADRL12 (ETHER.TSU_ADRL12) +#define ETHERTSU_ADRH13 (ETHER.TSU_ADRH13) +#define ETHERTSU_ADRL13 (ETHER.TSU_ADRL13) +#define ETHERTSU_ADRH14 (ETHER.TSU_ADRH14) +#define ETHERTSU_ADRL14 (ETHER.TSU_ADRL14) +#define ETHERTSU_ADRH15 (ETHER.TSU_ADRH15) +#define ETHERTSU_ADRL15 (ETHER.TSU_ADRL15) +#define ETHERTSU_ADRH16 (ETHER.TSU_ADRH16) +#define ETHERTSU_ADRL16 (ETHER.TSU_ADRL16) +#define ETHERTSU_ADRH17 (ETHER.TSU_ADRH17) +#define ETHERTSU_ADRL17 (ETHER.TSU_ADRL17) +#define ETHERTSU_ADRH18 (ETHER.TSU_ADRH18) +#define ETHERTSU_ADRL18 (ETHER.TSU_ADRL18) +#define ETHERTSU_ADRH19 (ETHER.TSU_ADRH19) +#define ETHERTSU_ADRL19 (ETHER.TSU_ADRL19) +#define ETHERTSU_ADRH20 (ETHER.TSU_ADRH20) +#define ETHERTSU_ADRL20 (ETHER.TSU_ADRL20) +#define ETHERTSU_ADRH21 (ETHER.TSU_ADRH21) +#define ETHERTSU_ADRL21 (ETHER.TSU_ADRL21) +#define ETHERTSU_ADRH22 (ETHER.TSU_ADRH22) +#define ETHERTSU_ADRL22 (ETHER.TSU_ADRL22) +#define ETHERTSU_ADRH23 (ETHER.TSU_ADRH23) +#define ETHERTSU_ADRL23 (ETHER.TSU_ADRL23) +#define ETHERTSU_ADRH24 (ETHER.TSU_ADRH24) +#define ETHERTSU_ADRL24 (ETHER.TSU_ADRL24) +#define ETHERTSU_ADRH25 (ETHER.TSU_ADRH25) +#define ETHERTSU_ADRL25 (ETHER.TSU_ADRL25) +#define ETHERTSU_ADRH26 (ETHER.TSU_ADRH26) +#define ETHERTSU_ADRL26 (ETHER.TSU_ADRL26) +#define ETHERTSU_ADRH27 (ETHER.TSU_ADRH27) +#define ETHERTSU_ADRL27 (ETHER.TSU_ADRL27) +#define ETHERTSU_ADRH28 (ETHER.TSU_ADRH28) +#define ETHERTSU_ADRL28 (ETHER.TSU_ADRL28) +#define ETHERTSU_ADRH29 (ETHER.TSU_ADRH29) +#define ETHERTSU_ADRL29 (ETHER.TSU_ADRL29) +#define ETHERTSU_ADRH30 (ETHER.TSU_ADRH30) +#define ETHERTSU_ADRL30 (ETHER.TSU_ADRL30) +#define ETHERTSU_ADRH31 (ETHER.TSU_ADRH31) +#define ETHERTSU_ADRL31 (ETHER.TSU_ADRL31) + + +typedef struct st_ether +{ + /* ETHER */ + volatile uint32_t EDSR0; /* EDSR0 */ + volatile uint8_t dummy207[12]; /* */ + volatile uint32_t TDLAR0; /* TDLAR0 */ + volatile uint32_t TDFAR0; /* TDFAR0 */ + volatile uint32_t TDFXR0; /* TDFXR0 */ + volatile uint32_t TDFFR0; /* TDFFR0 */ + volatile uint8_t dummy208[16]; /* */ + volatile uint32_t RDLAR0; /* RDLAR0 */ + volatile uint32_t RDFAR0; /* RDFAR0 */ + volatile uint32_t RDFXR0; /* RDFXR0 */ + volatile uint32_t RDFFR0; /* RDFFR0 */ + volatile uint8_t dummy209[960]; /* */ + volatile uint32_t EDMR0; /* EDMR0 */ + volatile uint8_t dummy210[4]; /* */ + volatile uint32_t EDTRR0; /* EDTRR0 */ + volatile uint8_t dummy211[4]; /* */ + volatile uint32_t EDRRR0; /* EDRRR0 */ + volatile uint8_t dummy212[20]; /* */ + volatile uint32_t EESR0; /* EESR0 */ + volatile uint8_t dummy213[4]; /* */ + volatile uint32_t EESIPR0; /* EESIPR0 */ + volatile uint8_t dummy214[4]; /* */ + volatile uint32_t TRSCER0; /* TRSCER0 */ + volatile uint8_t dummy215[4]; /* */ + volatile uint32_t RMFCR0; /* RMFCR0 */ + volatile uint8_t dummy216[4]; /* */ + volatile uint32_t TFTR0; /* TFTR0 */ + volatile uint8_t dummy217[4]; /* */ + volatile uint32_t FDR0; /* FDR0 */ + volatile uint8_t dummy218[4]; /* */ + volatile uint32_t RMCR0; /* RMCR0 */ + volatile uint8_t dummy219[4]; /* */ + volatile uint32_t RPADIR0; /* RPADIR0 */ + volatile uint8_t dummy220[4]; /* */ + volatile uint32_t FCFTR0; /* FCFTR0 */ + volatile uint8_t dummy221[120]; /* */ + volatile uint32_t CSMR; /* CSMR */ + volatile uint32_t CSSBM; /* CSSBM */ + volatile uint32_t CSSMR; /* CSSMR */ + volatile uint8_t dummy222[16]; /* */ + volatile uint32_t ECMR0; /* ECMR0 */ + volatile uint8_t dummy223[4]; /* */ + volatile uint32_t RFLR0; /* RFLR0 */ + volatile uint8_t dummy224[4]; /* */ + volatile uint32_t ECSR0; /* ECSR0 */ + volatile uint8_t dummy225[4]; /* */ + volatile uint32_t ECSIPR0; /* ECSIPR0 */ + volatile uint8_t dummy226[4]; /* */ + volatile uint32_t PIR0; /* PIR0 */ + volatile uint8_t dummy227[48]; /* */ + volatile uint32_t APR0; /* APR0 */ + volatile uint32_t MPR0; /* MPR0 */ + volatile uint32_t PFTCR0; /* PFTCR0 */ + volatile uint32_t PFRCR0; /* PFRCR0 */ + volatile uint32_t TPAUSER0; /* TPAUSER0 */ + volatile uint8_t dummy228[88]; /* */ + volatile uint32_t MAHR0; /* MAHR0 */ + volatile uint8_t dummy229[4]; /* */ + volatile uint32_t MALR0; /* MALR0 */ + volatile uint8_t dummy230[372]; /* */ + volatile uint32_t CEFCR0; /* CEFCR0 */ + volatile uint8_t dummy231[4]; /* */ + volatile uint32_t FRECR0; /* FRECR0 */ + volatile uint8_t dummy232[4]; /* */ + volatile uint32_t TSFRCR0; /* TSFRCR0 */ + volatile uint8_t dummy233[4]; /* */ + volatile uint32_t TLFRCR0; /* TLFRCR0 */ + volatile uint8_t dummy234[4]; /* */ + volatile uint32_t RFCR0; /* RFCR0 */ + volatile uint8_t dummy235[20]; /* */ + volatile uint32_t MAFCR0; /* MAFCR0 */ + volatile uint8_t dummy236[4228]; /* */ + volatile uint32_t ARSTR; /* ARSTR */ + volatile uint32_t TSU_CTRST; /* TSU_CTRST */ + volatile uint8_t dummy237[80]; /* */ + volatile uint32_t TSU_VTAG0; /* TSU_VTAG0 */ + volatile uint8_t dummy238[4]; /* */ + volatile uint32_t TSU_ADSBSY; /* TSU_ADSBSY */ + volatile uint32_t TSU_TEN; /* TSU_TEN */ + volatile uint8_t dummy239[24]; /* */ + volatile uint32_t TXNLCR0; /* TXNLCR0 */ + volatile uint32_t TXALCR0; /* TXALCR0 */ + volatile uint32_t RXNLCR0; /* RXNLCR0 */ + volatile uint32_t RXALCR0; /* RXALCR0 */ + volatile uint8_t dummy240[112]; /* */ + +/* start of struct st_ether_from_tsu_adrh0 */ + volatile uint32_t TSU_ADRH0; /* TSU_ADRH0 */ + volatile uint32_t TSU_ADRL0; /* TSU_ADRL0 */ + +/* end of struct st_ether_from_tsu_adrh0 */ + +/* start of struct st_ether_from_tsu_adrh0 */ + volatile uint32_t TSU_ADRH1; /* TSU_ADRH1 */ + volatile uint32_t TSU_ADRL1; /* TSU_ADRL1 */ + +/* end of struct st_ether_from_tsu_adrh0 */ + +/* start of struct st_ether_from_tsu_adrh0 */ + volatile uint32_t TSU_ADRH2; /* TSU_ADRH2 */ + volatile uint32_t TSU_ADRL2; /* TSU_ADRL2 */ + +/* end of struct st_ether_from_tsu_adrh0 */ + +/* start of struct st_ether_from_tsu_adrh0 */ + volatile uint32_t TSU_ADRH3; /* TSU_ADRH3 */ + volatile uint32_t TSU_ADRL3; /* TSU_ADRL3 */ + +/* end of struct st_ether_from_tsu_adrh0 */ + +/* start of struct st_ether_from_tsu_adrh0 */ + volatile uint32_t TSU_ADRH4; /* TSU_ADRH4 */ + volatile uint32_t TSU_ADRL4; /* TSU_ADRL4 */ + +/* end of struct st_ether_from_tsu_adrh0 */ + +/* start of struct st_ether_from_tsu_adrh0 */ + volatile uint32_t TSU_ADRH5; /* TSU_ADRH5 */ + volatile uint32_t TSU_ADRL5; /* TSU_ADRL5 */ + +/* end of struct st_ether_from_tsu_adrh0 */ + +/* start of struct st_ether_from_tsu_adrh0 */ + volatile uint32_t TSU_ADRH6; /* TSU_ADRH6 */ + volatile uint32_t TSU_ADRL6; /* TSU_ADRL6 */ + +/* end of struct st_ether_from_tsu_adrh0 */ + +/* start of struct st_ether_from_tsu_adrh0 */ + volatile uint32_t TSU_ADRH7; /* TSU_ADRH7 */ + volatile uint32_t TSU_ADRL7; /* TSU_ADRL7 */ + +/* end of struct st_ether_from_tsu_adrh0 */ + +/* start of struct st_ether_from_tsu_adrh0 */ + volatile uint32_t TSU_ADRH8; /* TSU_ADRH8 */ + volatile uint32_t TSU_ADRL8; /* TSU_ADRL8 */ + +/* end of struct st_ether_from_tsu_adrh0 */ + +/* start of struct st_ether_from_tsu_adrh0 */ + volatile uint32_t TSU_ADRH9; /* TSU_ADRH9 */ + volatile uint32_t TSU_ADRL9; /* TSU_ADRL9 */ + +/* end of struct st_ether_from_tsu_adrh0 */ + +/* start of struct st_ether_from_tsu_adrh0 */ + volatile uint32_t TSU_ADRH10; /* TSU_ADRH10 */ + volatile uint32_t TSU_ADRL10; /* TSU_ADRL10 */ + +/* end of struct st_ether_from_tsu_adrh0 */ + +/* start of struct st_ether_from_tsu_adrh0 */ + volatile uint32_t TSU_ADRH11; /* TSU_ADRH11 */ + volatile uint32_t TSU_ADRL11; /* TSU_ADRL11 */ + +/* end of struct st_ether_from_tsu_adrh0 */ + +/* start of struct st_ether_from_tsu_adrh0 */ + volatile uint32_t TSU_ADRH12; /* TSU_ADRH12 */ + volatile uint32_t TSU_ADRL12; /* TSU_ADRL12 */ + +/* end of struct st_ether_from_tsu_adrh0 */ + +/* start of struct st_ether_from_tsu_adrh0 */ + volatile uint32_t TSU_ADRH13; /* TSU_ADRH13 */ + volatile uint32_t TSU_ADRL13; /* TSU_ADRL13 */ + +/* end of struct st_ether_from_tsu_adrh0 */ + +/* start of struct st_ether_from_tsu_adrh0 */ + volatile uint32_t TSU_ADRH14; /* TSU_ADRH14 */ + volatile uint32_t TSU_ADRL14; /* TSU_ADRL14 */ + +/* end of struct st_ether_from_tsu_adrh0 */ + +/* start of struct st_ether_from_tsu_adrh0 */ + volatile uint32_t TSU_ADRH15; /* TSU_ADRH15 */ + volatile uint32_t TSU_ADRL15; /* TSU_ADRL15 */ + +/* end of struct st_ether_from_tsu_adrh0 */ + +/* start of struct st_ether_from_tsu_adrh0 */ + volatile uint32_t TSU_ADRH16; /* TSU_ADRH16 */ + volatile uint32_t TSU_ADRL16; /* TSU_ADRL16 */ + +/* end of struct st_ether_from_tsu_adrh0 */ + +/* start of struct st_ether_from_tsu_adrh0 */ + volatile uint32_t TSU_ADRH17; /* TSU_ADRH17 */ + volatile uint32_t TSU_ADRL17; /* TSU_ADRL17 */ + +/* end of struct st_ether_from_tsu_adrh0 */ + +/* start of struct st_ether_from_tsu_adrh0 */ + volatile uint32_t TSU_ADRH18; /* TSU_ADRH18 */ + volatile uint32_t TSU_ADRL18; /* TSU_ADRL18 */ + +/* end of struct st_ether_from_tsu_adrh0 */ + +/* start of struct st_ether_from_tsu_adrh0 */ + volatile uint32_t TSU_ADRH19; /* TSU_ADRH19 */ + volatile uint32_t TSU_ADRL19; /* TSU_ADRL19 */ + +/* end of struct st_ether_from_tsu_adrh0 */ + +/* start of struct st_ether_from_tsu_adrh0 */ + volatile uint32_t TSU_ADRH20; /* TSU_ADRH20 */ + volatile uint32_t TSU_ADRL20; /* TSU_ADRL20 */ + +/* end of struct st_ether_from_tsu_adrh0 */ + +/* start of struct st_ether_from_tsu_adrh0 */ + volatile uint32_t TSU_ADRH21; /* TSU_ADRH21 */ + volatile uint32_t TSU_ADRL21; /* TSU_ADRL21 */ + +/* end of struct st_ether_from_tsu_adrh0 */ + +/* start of struct st_ether_from_tsu_adrh0 */ + volatile uint32_t TSU_ADRH22; /* TSU_ADRH22 */ + volatile uint32_t TSU_ADRL22; /* TSU_ADRL22 */ + +/* end of struct st_ether_from_tsu_adrh0 */ + +/* start of struct st_ether_from_tsu_adrh0 */ + volatile uint32_t TSU_ADRH23; /* TSU_ADRH23 */ + volatile uint32_t TSU_ADRL23; /* TSU_ADRL23 */ + +/* end of struct st_ether_from_tsu_adrh0 */ + +/* start of struct st_ether_from_tsu_adrh0 */ + volatile uint32_t TSU_ADRH24; /* TSU_ADRH24 */ + volatile uint32_t TSU_ADRL24; /* TSU_ADRL24 */ + +/* end of struct st_ether_from_tsu_adrh0 */ + +/* start of struct st_ether_from_tsu_adrh0 */ + volatile uint32_t TSU_ADRH25; /* TSU_ADRH25 */ + volatile uint32_t TSU_ADRL25; /* TSU_ADRL25 */ + +/* end of struct st_ether_from_tsu_adrh0 */ + +/* start of struct st_ether_from_tsu_adrh0 */ + volatile uint32_t TSU_ADRH26; /* TSU_ADRH26 */ + volatile uint32_t TSU_ADRL26; /* TSU_ADRL26 */ + +/* end of struct st_ether_from_tsu_adrh0 */ + +/* start of struct st_ether_from_tsu_adrh0 */ + volatile uint32_t TSU_ADRH27; /* TSU_ADRH27 */ + volatile uint32_t TSU_ADRL27; /* TSU_ADRL27 */ + +/* end of struct st_ether_from_tsu_adrh0 */ + +/* start of struct st_ether_from_tsu_adrh0 */ + volatile uint32_t TSU_ADRH28; /* TSU_ADRH28 */ + volatile uint32_t TSU_ADRL28; /* TSU_ADRL28 */ + +/* end of struct st_ether_from_tsu_adrh0 */ + +/* start of struct st_ether_from_tsu_adrh0 */ + volatile uint32_t TSU_ADRH29; /* TSU_ADRH29 */ + volatile uint32_t TSU_ADRL29; /* TSU_ADRL29 */ + +/* end of struct st_ether_from_tsu_adrh0 */ + +/* start of struct st_ether_from_tsu_adrh0 */ + volatile uint32_t TSU_ADRH30; /* TSU_ADRH30 */ + volatile uint32_t TSU_ADRL30; /* TSU_ADRL30 */ + +/* end of struct st_ether_from_tsu_adrh0 */ + +/* start of struct st_ether_from_tsu_adrh0 */ + volatile uint32_t TSU_ADRH31; /* TSU_ADRH31 */ + volatile uint32_t TSU_ADRL31; /* TSU_ADRL31 */ + +/* end of struct st_ether_from_tsu_adrh0 */ +} r_io_ether_t; + + +typedef struct st_ether_from_tsu_adrh0 +{ + + volatile uint32_t TSU_ADRH0; /* TSU_ADRH0 */ + volatile uint32_t TSU_ADRL0; /* TSU_ADRL0 */ +} r_io_ether_from_tsu_adrh0_t; + + +/* Channel array defines of ETHER (2)*/ +#ifdef DECLARE_ETHER_FROM_TSU_ADRH0_ARRAY_CHANNELS +volatile struct st_ether_from_tsu_adrh0* ETHER_FROM_TSU_ADRH0_ARRAY[ ETHER_FROM_TSU_ADRH0_ARRAY_COUNT ] = + /* ->MISRA 11.3 */ /* ->SEC R2.7.1 */ + ETHER_FROM_TSU_ADRH0_ARRAY_ADDRESS_LIST; + /* <-MISRA 11.3 */ /* <-SEC R2.7.1 */ +#endif /* DECLARE_ETHER_FROM_TSU_ADRH0_ARRAY_CHANNELS */ +/* End of channel array defines of ETHER (2)*/ + + +/* <-SEC M1.10.1 */ +/* <-MISRA 18.4 */ /* <-SEC M1.6.2 */ +/* <-QAC 0857 */ +/* <-QAC 0639 */ +#endif diff --git a/targets/TARGET_RENESAS/TARGET_RZ_A1XX/TARGET_GR_LYCHEE/device/inc/iodefines/gpio_iodefine.h b/targets/TARGET_RENESAS/TARGET_RZ_A1XX/TARGET_GR_LYCHEE/device/inc/iodefines/gpio_iodefine.h new file mode 100644 index 0000000..3e37b9b --- /dev/null +++ b/targets/TARGET_RENESAS/TARGET_RZ_A1XX/TARGET_GR_LYCHEE/device/inc/iodefines/gpio_iodefine.h @@ -0,0 +1,1267 @@ +/******************************************************************************* +* DISCLAIMER +* This software is supplied by Renesas Electronics Corporation and is only +* intended for use with Renesas products. No other uses are authorized. This +* software is owned by Renesas Electronics Corporation and is protected under +* all applicable laws, including copyright laws. +* THIS SOFTWARE IS PROVIDED "AS IS" AND RENESAS MAKES NO WARRANTIES REGARDING +* THIS SOFTWARE, WHETHER EXPRESS, IMPLIED OR STATUTORY, INCLUDING BUT NOT +* LIMITED TO WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE +* AND NON-INFRINGEMENT. ALL SUCH WARRANTIES ARE EXPRESSLY DISCLAIMED. +* TO THE MAXIMUM EXTENT PERMITTED NOT PROHIBITED BY LAW, NEITHER RENESAS +* ELECTRONICS CORPORATION NOR ANY OF ITS AFFILIATED COMPANIES SHALL BE LIABLE +* FOR ANY DIRECT, INDIRECT, SPECIAL, INCIDENTAL OR CONSEQUENTIAL DAMAGES FOR +* ANY REASON RELATED TO THIS SOFTWARE, EVEN IF RENESAS OR ITS AFFILIATES HAVE +* BEEN ADVISED OF THE POSSIBILITY OF SUCH DAMAGES. +* Renesas reserves the right, without notice, to make changes to this software +* and to discontinue the availability of this software. By using this software, +* you agree to the additional terms and conditions found by accessing the +* following link: +* http://www.renesas.com/disclaimer* +* Copyright (C) 2013-2016 Renesas Electronics Corporation. All rights reserved. +*******************************************************************************/ +/******************************************************************************* +* File Name : gpio_iodefine.h +* $Rev: $ +* $Date:: $ +* Description : Definition of I/O Register for RZ/A1LU (V3.00l) +******************************************************************************/ +#ifndef GPIO_IODEFINE_H +#define GPIO_IODEFINE_H +/* ->QAC 0639 : Over 127 members (C90) */ +/* ->QAC 0857 : Over 1024 #define (C90) */ +/* ->MISRA 18.4 : Pack unpack union */ /* ->SEC M1.6.2 */ +/* ->SEC M1.10.1 : Not magic number */ + +#define GPIO (*(struct st_gpio *)0xFCFE3004uL) /* GPIO */ + + +/* Start of channel array defines of GPIO */ + +/* Channel array defines of GPIO_FROM_PIPC1_ARRAY */ +/*(Sample) value = GPIO_FROM_PIPC1_ARRAY[ channel ]->PIPC1; */ +#define GPIO_FROM_PIPC1_ARRAY_COUNT (9) +#define GPIO_FROM_PIPC1_ARRAY_ADDRESS_LIST \ +{ /* ->MISRA 11.3 */ /* ->SEC R2.7.1 */ \ + &GPIO_FROM_PIPC1, &GPIO_FROM_PIPC2, &GPIO_FROM_PIPC3, &GPIO_FROM_PIPC4, &GPIO_FROM_PIPC5, &GPIO_FROM_PIPC6, &GPIO_FROM_PIPC7, &GPIO_FROM_PIPC8, \ + &GPIO_FROM_PIPC9 \ +} /* <-MISRA 11.3 */ /* <-SEC R2.7.1 */ /* { } is for MISRA 19.4 */ +#define GPIO_FROM_PIPC1 (*(struct st_gpio_from_pipc1 *)&GPIO.PIPC1) /* GPIO_FROM_PIPC1 */ +#define GPIO_FROM_PIPC2 (*(struct st_gpio_from_pipc1 *)&GPIO.PIPC2) /* GPIO_FROM_PIPC2 */ +#define GPIO_FROM_PIPC3 (*(struct st_gpio_from_pipc1 *)&GPIO.PIPC3) /* GPIO_FROM_PIPC3 */ +#define GPIO_FROM_PIPC4 (*(struct st_gpio_from_pipc1 *)&GPIO.PIPC4) /* GPIO_FROM_PIPC4 */ +#define GPIO_FROM_PIPC5 (*(struct st_gpio_from_pipc1 *)&GPIO.PIPC5) /* GPIO_FROM_PIPC5 */ +#define GPIO_FROM_PIPC6 (*(struct st_gpio_from_pipc1 *)&GPIO.PIPC6) /* GPIO_FROM_PIPC6 */ +#define GPIO_FROM_PIPC7 (*(struct st_gpio_from_pipc1 *)&GPIO.PIPC7) /* GPIO_FROM_PIPC7 */ +#define GPIO_FROM_PIPC8 (*(struct st_gpio_from_pipc1 *)&GPIO.PIPC8) /* GPIO_FROM_PIPC8 */ +#define GPIO_FROM_PIPC9 (*(struct st_gpio_from_pipc1 *)&GPIO.PIPC9) /* GPIO_FROM_PIPC9 */ + + +/* Channel array defines of GPIO_FROM_PBDC1_ARRAY */ +/*(Sample) value = GPIO_FROM_PBDC1_ARRAY[ channel ]->PBDC1; */ +#define GPIO_FROM_PBDC1_ARRAY_COUNT (9) +#define GPIO_FROM_PBDC1_ARRAY_ADDRESS_LIST \ +{ /* ->MISRA 11.3 */ /* ->SEC R2.7.1 */ \ + &GPIO_FROM_PBDC1, &GPIO_FROM_PBDC2, &GPIO_FROM_PBDC3, &GPIO_FROM_PBDC4, &GPIO_FROM_PBDC5, &GPIO_FROM_PBDC6, &GPIO_FROM_PBDC7, &GPIO_FROM_PBDC8, \ + &GPIO_FROM_PBDC9 \ +} /* <-MISRA 11.3 */ /* <-SEC R2.7.1 */ /* { } is for MISRA 19.4 */ +#define GPIO_FROM_PBDC1 (*(struct st_gpio_from_pbdc1 *)&GPIO.PBDC1) /* GPIO_FROM_PBDC1 */ +#define GPIO_FROM_PBDC2 (*(struct st_gpio_from_pbdc1 *)&GPIO.PBDC2) /* GPIO_FROM_PBDC2 */ +#define GPIO_FROM_PBDC3 (*(struct st_gpio_from_pbdc1 *)&GPIO.PBDC3) /* GPIO_FROM_PBDC3 */ +#define GPIO_FROM_PBDC4 (*(struct st_gpio_from_pbdc1 *)&GPIO.PBDC4) /* GPIO_FROM_PBDC4 */ +#define GPIO_FROM_PBDC5 (*(struct st_gpio_from_pbdc1 *)&GPIO.PBDC5) /* GPIO_FROM_PBDC5 */ +#define GPIO_FROM_PBDC6 (*(struct st_gpio_from_pbdc1 *)&GPIO.PBDC6) /* GPIO_FROM_PBDC6 */ +#define GPIO_FROM_PBDC7 (*(struct st_gpio_from_pbdc1 *)&GPIO.PBDC7) /* GPIO_FROM_PBDC7 */ +#define GPIO_FROM_PBDC8 (*(struct st_gpio_from_pbdc1 *)&GPIO.PBDC8) /* GPIO_FROM_PBDC8 */ +#define GPIO_FROM_PBDC9 (*(struct st_gpio_from_pbdc1 *)&GPIO.PBDC9) /* GPIO_FROM_PBDC9 */ + + +/* Channel array defines of GPIO_FROM_PIBC1_ARRAY */ +/*(Sample) value = GPIO_FROM_PIBC1_ARRAY[ channel ]->PIBC1; */ +#define GPIO_FROM_PIBC1_ARRAY_COUNT (10) +#define GPIO_FROM_PIBC1_ARRAY_ADDRESS_LIST \ +{ /* ->MISRA 11.3 */ /* ->SEC R2.7.1 */ \ + &GPIO_FROM_PIBC0, &GPIO_FROM_PIBC1, &GPIO_FROM_PIBC2, &GPIO_FROM_PIBC3, &GPIO_FROM_PIBC4, &GPIO_FROM_PIBC5, &GPIO_FROM_PIBC6, &GPIO_FROM_PIBC7, \ + &GPIO_FROM_PIBC8, &GPIO_FROM_PIBC9 \ +} /* <-MISRA 11.3 */ /* <-SEC R2.7.1 */ /* { } is for MISRA 19.4 */ +#define GPIO_FROM_PIBC0 (*(struct st_gpio_from_pibc1 *)&GPIO.PIBC0) /* GPIO_FROM_PIBC0 */ +#define GPIO_FROM_PIBC1 (*(struct st_gpio_from_pibc1 *)&GPIO.PIBC1) /* GPIO_FROM_PIBC1 */ +#define GPIO_FROM_PIBC2 (*(struct st_gpio_from_pibc1 *)&GPIO.PIBC2) /* GPIO_FROM_PIBC2 */ +#define GPIO_FROM_PIBC3 (*(struct st_gpio_from_pibc1 *)&GPIO.PIBC3) /* GPIO_FROM_PIBC3 */ +#define GPIO_FROM_PIBC4 (*(struct st_gpio_from_pibc1 *)&GPIO.PIBC4) /* GPIO_FROM_PIBC4 */ +#define GPIO_FROM_PIBC5 (*(struct st_gpio_from_pibc1 *)&GPIO.PIBC5) /* GPIO_FROM_PIBC5 */ +#define GPIO_FROM_PIBC6 (*(struct st_gpio_from_pibc1 *)&GPIO.PIBC6) /* GPIO_FROM_PIBC6 */ +#define GPIO_FROM_PIBC7 (*(struct st_gpio_from_pibc1 *)&GPIO.PIBC7) /* GPIO_FROM_PIBC7 */ +#define GPIO_FROM_PIBC8 (*(struct st_gpio_from_pibc1 *)&GPIO.PIBC8) /* GPIO_FROM_PIBC8 */ +#define GPIO_FROM_PIBC9 (*(struct st_gpio_from_pibc1 *)&GPIO.PIBC9) /* GPIO_FROM_PIBC9 */ + + +/* Channel array defines of GPIO_FROM_PFCAE1_ARRAY */ +/*(Sample) value = GPIO_FROM_PFCAE1_ARRAY[ channel ]->PFCAE1; */ +#define GPIO_FROM_PFCAE1_ARRAY_COUNT (10) +#define GPIO_FROM_PFCAE1_ARRAY_ADDRESS_LIST \ +{ /* ->MISRA 11.3 */ /* ->SEC R2.7.1 */ \ + &GPIO_FROM_PFCAE0, &GPIO_FROM_PFCAE1, &GPIO_FROM_PFCAE2, &GPIO_FROM_PFCAE3, &GPIO_FROM_PFCAE4, &GPIO_FROM_PFCAE5, &GPIO_FROM_PFCAE6, &GPIO_FROM_PFCAE7, \ + &GPIO_FROM_PFCAE8, &GPIO_FROM_PFCAE9 \ +} /* <-MISRA 11.3 */ /* <-SEC R2.7.1 */ /* { } is for MISRA 19.4 */ +#define GPIO_FROM_PFCAE0 (*(struct st_gpio_from_pfcae1 *)&GPIO.PFCAE0) /* GPIO_FROM_PFCAE0 */ +#define GPIO_FROM_PFCAE1 (*(struct st_gpio_from_pfcae1 *)&GPIO.PFCAE1) /* GPIO_FROM_PFCAE1 */ +#define GPIO_FROM_PFCAE2 (*(struct st_gpio_from_pfcae1 *)&GPIO.PFCAE2) /* GPIO_FROM_PFCAE2 */ +#define GPIO_FROM_PFCAE3 (*(struct st_gpio_from_pfcae1 *)&GPIO.PFCAE3) /* GPIO_FROM_PFCAE3 */ +#define GPIO_FROM_PFCAE4 (*(struct st_gpio_from_pfcae1 *)&GPIO.PFCAE4) /* GPIO_FROM_PFCAE4 */ +#define GPIO_FROM_PFCAE5 (*(struct st_gpio_from_pfcae1 *)&GPIO.PFCAE5) /* GPIO_FROM_PFCAE5 */ +#define GPIO_FROM_PFCAE6 (*(struct st_gpio_from_pfcae1 *)&GPIO.PFCAE6) /* GPIO_FROM_PFCAE6 */ +#define GPIO_FROM_PFCAE7 (*(struct st_gpio_from_pfcae1 *)&GPIO.PFCAE7) /* GPIO_FROM_PFCAE7 */ +#define GPIO_FROM_PFCAE8 (*(struct st_gpio_from_pfcae1 *)&GPIO.PFCAE8) /* GPIO_FROM_PFCAE8 */ +#define GPIO_FROM_PFCAE9 (*(struct st_gpio_from_pfcae1 *)&GPIO.PFCAE9) /* GPIO_FROM_PFCAE9 */ + + +/* Channel array defines of GPIO_FROM_PNOT1_ARRAY */ +/*(Sample) value = GPIO_FROM_PNOT1_ARRAY[ channel ]->PNOT1; */ +#define GPIO_FROM_PNOT1_ARRAY_COUNT (9) +#define GPIO_FROM_PNOT1_ARRAY_ADDRESS_LIST \ +{ /* ->MISRA 11.3 */ /* ->SEC R2.7.1 */ \ + &GPIO_FROM_PNOT1, &GPIO_FROM_PNOT2, &GPIO_FROM_PNOT3, &GPIO_FROM_PNOT4, &GPIO_FROM_PNOT5, &GPIO_FROM_PNOT6, &GPIO_FROM_PNOT7, &GPIO_FROM_PNOT8, \ + &GPIO_FROM_PNOT9 \ +} /* <-MISRA 11.3 */ /* <-SEC R2.7.1 */ /* { } is for MISRA 19.4 */ +#define GPIO_FROM_PNOT1 (*(struct st_gpio_from_pnot1 *)&GPIO.PNOT1) /* GPIO_FROM_PNOT1 */ +#define GPIO_FROM_PNOT2 (*(struct st_gpio_from_pnot1 *)&GPIO.PNOT2) /* GPIO_FROM_PNOT2 */ +#define GPIO_FROM_PNOT3 (*(struct st_gpio_from_pnot1 *)&GPIO.PNOT3) /* GPIO_FROM_PNOT3 */ +#define GPIO_FROM_PNOT4 (*(struct st_gpio_from_pnot1 *)&GPIO.PNOT4) /* GPIO_FROM_PNOT4 */ +#define GPIO_FROM_PNOT5 (*(struct st_gpio_from_pnot1 *)&GPIO.PNOT5) /* GPIO_FROM_PNOT5 */ +#define GPIO_FROM_PNOT6 (*(struct st_gpio_from_pnot1 *)&GPIO.PNOT6) /* GPIO_FROM_PNOT6 */ +#define GPIO_FROM_PNOT7 (*(struct st_gpio_from_pnot1 *)&GPIO.PNOT7) /* GPIO_FROM_PNOT7 */ +#define GPIO_FROM_PNOT8 (*(struct st_gpio_from_pnot1 *)&GPIO.PNOT8) /* GPIO_FROM_PNOT8 */ +#define GPIO_FROM_PNOT9 (*(struct st_gpio_from_pnot1 *)&GPIO.PNOT9) /* GPIO_FROM_PNOT9 */ + + +/* Channel array defines of GPIO_FROM_PFCE1_ARRAY */ +/*(Sample) value = GPIO_FROM_PFCE1_ARRAY[ channel ]->PFCE1; */ +#define GPIO_FROM_PFCE1_ARRAY_COUNT (10) +#define GPIO_FROM_PFCE1_ARRAY_ADDRESS_LIST \ +{ /* ->MISRA 11.3 */ /* ->SEC R2.7.1 */ \ + &GPIO_FROM_PFCE0, &GPIO_FROM_PFCE1, &GPIO_FROM_PFCE2, &GPIO_FROM_PFCE3, &GPIO_FROM_PFCE4, &GPIO_FROM_PFCE5, &GPIO_FROM_PFCE6, &GPIO_FROM_PFCE7, \ + &GPIO_FROM_PFCE8, &GPIO_FROM_PFCE9 \ +} /* <-MISRA 11.3 */ /* <-SEC R2.7.1 */ /* { } is for MISRA 19.4 */ +#define GPIO_FROM_PFCE0 (*(struct st_gpio_from_pfce1 *)&GPIO.PFCE0) /* GPIO_FROM_PFCE0 */ +#define GPIO_FROM_PFCE1 (*(struct st_gpio_from_pfce1 *)&GPIO.PFCE1) /* GPIO_FROM_PFCE1 */ +#define GPIO_FROM_PFCE2 (*(struct st_gpio_from_pfce1 *)&GPIO.PFCE2) /* GPIO_FROM_PFCE2 */ +#define GPIO_FROM_PFCE3 (*(struct st_gpio_from_pfce1 *)&GPIO.PFCE3) /* GPIO_FROM_PFCE3 */ +#define GPIO_FROM_PFCE4 (*(struct st_gpio_from_pfce1 *)&GPIO.PFCE4) /* GPIO_FROM_PFCE4 */ +#define GPIO_FROM_PFCE5 (*(struct st_gpio_from_pfce1 *)&GPIO.PFCE5) /* GPIO_FROM_PFCE5 */ +#define GPIO_FROM_PFCE6 (*(struct st_gpio_from_pfce1 *)&GPIO.PFCE6) /* GPIO_FROM_PFCE6 */ +#define GPIO_FROM_PFCE7 (*(struct st_gpio_from_pfce1 *)&GPIO.PFCE7) /* GPIO_FROM_PFCE7 */ +#define GPIO_FROM_PFCE8 (*(struct st_gpio_from_pfce1 *)&GPIO.PFCE8) /* GPIO_FROM_PFCE8 */ +#define GPIO_FROM_PFCE9 (*(struct st_gpio_from_pfce1 *)&GPIO.PFCE9) /* GPIO_FROM_PFCE9 */ + + +/* Channel array defines of GPIO_FROM_PFC1_ARRAY */ +/*(Sample) value = GPIO_FROM_PFC1_ARRAY[ channel ]->PFC1; */ +#define GPIO_FROM_PFC1_ARRAY_COUNT (10) +#define GPIO_FROM_PFC1_ARRAY_ADDRESS_LIST \ +{ /* ->MISRA 11.3 */ /* ->SEC R2.7.1 */ \ + &GPIO_FROM_PFC0, &GPIO_FROM_PFC1, &GPIO_FROM_PFC2, &GPIO_FROM_PFC3, &GPIO_FROM_PFC4, &GPIO_FROM_PFC5, &GPIO_FROM_PFC6, &GPIO_FROM_PFC7, \ + &GPIO_FROM_PFC8, &GPIO_FROM_PFC9 \ +} /* <-MISRA 11.3 */ /* <-SEC R2.7.1 */ /* { } is for MISRA 19.4 */ +#define GPIO_FROM_PFC0 (*(struct st_gpio_from_pfc1 *)&GPIO.PFC0) /* GPIO_FROM_PFC0 */ +#define GPIO_FROM_PFC1 (*(struct st_gpio_from_pfc1 *)&GPIO.PFC1) /* GPIO_FROM_PFC1 */ +#define GPIO_FROM_PFC2 (*(struct st_gpio_from_pfc1 *)&GPIO.PFC2) /* GPIO_FROM_PFC2 */ +#define GPIO_FROM_PFC3 (*(struct st_gpio_from_pfc1 *)&GPIO.PFC3) /* GPIO_FROM_PFC3 */ +#define GPIO_FROM_PFC4 (*(struct st_gpio_from_pfc1 *)&GPIO.PFC4) /* GPIO_FROM_PFC4 */ +#define GPIO_FROM_PFC5 (*(struct st_gpio_from_pfc1 *)&GPIO.PFC5) /* GPIO_FROM_PFC5 */ +#define GPIO_FROM_PFC6 (*(struct st_gpio_from_pfc1 *)&GPIO.PFC6) /* GPIO_FROM_PFC6 */ +#define GPIO_FROM_PFC7 (*(struct st_gpio_from_pfc1 *)&GPIO.PFC7) /* GPIO_FROM_PFC7 */ +#define GPIO_FROM_PFC8 (*(struct st_gpio_from_pfc1 *)&GPIO.PFC8) /* GPIO_FROM_PFC8 */ +#define GPIO_FROM_PFC9 (*(struct st_gpio_from_pfc1 *)&GPIO.PFC9) /* GPIO_FROM_PFC9 */ + + +/* Channel array defines of GPIO_FROM_PMC0_ARRAY */ +/*(Sample) value = GPIO_FROM_PMC0_ARRAY[ channel ]->PMC0; */ +#define GPIO_FROM_PMC0_ARRAY_COUNT (10) +#define GPIO_FROM_PMC0_ARRAY_ADDRESS_LIST \ +{ /* ->MISRA 11.3 */ /* ->SEC R2.7.1 */ \ + &GPIO_FROM_PMC0, &GPIO_FROM_PMC1, &GPIO_FROM_PMC2, &GPIO_FROM_PMC3, &GPIO_FROM_PMC4, &GPIO_FROM_PMC5, &GPIO_FROM_PMC6, &GPIO_FROM_PMC7, \ + &GPIO_FROM_PMC8, &GPIO_FROM_PMC9 \ +} /* <-MISRA 11.3 */ /* <-SEC R2.7.1 */ /* { } is for MISRA 19.4 */ +#define GPIO_FROM_PMC0 (*(struct st_gpio_from_pmc0 *)&GPIO.PMC0) /* GPIO_FROM_PMC0 */ +#define GPIO_FROM_PMC1 (*(struct st_gpio_from_pmc0 *)&GPIO.PMC1) /* GPIO_FROM_PMC1 */ +#define GPIO_FROM_PMC2 (*(struct st_gpio_from_pmc0 *)&GPIO.PMC2) /* GPIO_FROM_PMC2 */ +#define GPIO_FROM_PMC3 (*(struct st_gpio_from_pmc0 *)&GPIO.PMC3) /* GPIO_FROM_PMC3 */ +#define GPIO_FROM_PMC4 (*(struct st_gpio_from_pmc0 *)&GPIO.PMC4) /* GPIO_FROM_PMC4 */ +#define GPIO_FROM_PMC5 (*(struct st_gpio_from_pmc0 *)&GPIO.PMC5) /* GPIO_FROM_PMC5 */ +#define GPIO_FROM_PMC6 (*(struct st_gpio_from_pmc0 *)&GPIO.PMC6) /* GPIO_FROM_PMC6 */ +#define GPIO_FROM_PMC7 (*(struct st_gpio_from_pmc0 *)&GPIO.PMC7) /* GPIO_FROM_PMC7 */ +#define GPIO_FROM_PMC8 (*(struct st_gpio_from_pmc0 *)&GPIO.PMC8) /* GPIO_FROM_PMC8 */ +#define GPIO_FROM_PMC9 (*(struct st_gpio_from_pmc0 *)&GPIO.PMC9) /* GPIO_FROM_PMC9 */ + + +/* Channel array defines of GPIO_FROM_PM1_ARRAY */ +/*(Sample) value = GPIO_FROM_PM1_ARRAY[ channel ]->PM1; */ +#define GPIO_FROM_PM1_ARRAY_COUNT (9) +#define GPIO_FROM_PM1_ARRAY_ADDRESS_LIST \ +{ /* ->MISRA 11.3 */ /* ->SEC R2.7.1 */ \ + &GPIO_FROM_PM1, &GPIO_FROM_PM2, &GPIO_FROM_PM3, &GPIO_FROM_PM4, &GPIO_FROM_PM5, &GPIO_FROM_PM6, &GPIO_FROM_PM7, &GPIO_FROM_PM8, \ + &GPIO_FROM_PM9 \ +} /* <-MISRA 11.3 */ /* <-SEC R2.7.1 */ /* { } is for MISRA 19.4 */ +#define GPIO_FROM_PM1 (*(struct st_gpio_from_pm1 *)&GPIO.PM1) /* GPIO_FROM_PM1 */ +#define GPIO_FROM_PM2 (*(struct st_gpio_from_pm1 *)&GPIO.PM2) /* GPIO_FROM_PM2 */ +#define GPIO_FROM_PM3 (*(struct st_gpio_from_pm1 *)&GPIO.PM3) /* GPIO_FROM_PM3 */ +#define GPIO_FROM_PM4 (*(struct st_gpio_from_pm1 *)&GPIO.PM4) /* GPIO_FROM_PM4 */ +#define GPIO_FROM_PM5 (*(struct st_gpio_from_pm1 *)&GPIO.PM5) /* GPIO_FROM_PM5 */ +#define GPIO_FROM_PM6 (*(struct st_gpio_from_pm1 *)&GPIO.PM6) /* GPIO_FROM_PM6 */ +#define GPIO_FROM_PM7 (*(struct st_gpio_from_pm1 *)&GPIO.PM7) /* GPIO_FROM_PM7 */ +#define GPIO_FROM_PM8 (*(struct st_gpio_from_pm1 *)&GPIO.PM8) /* GPIO_FROM_PM8 */ +#define GPIO_FROM_PM9 (*(struct st_gpio_from_pm1 *)&GPIO.PM9) /* GPIO_FROM_PM9 */ + + +/* Channel array defines of GPIO_FROM_PPR0_ARRAY */ +/*(Sample) value = GPIO_FROM_PPR0_ARRAY[ channel ]->PPR0; */ +#define GPIO_FROM_PPR0_ARRAY_COUNT (10) +#define GPIO_FROM_PPR0_ARRAY_ADDRESS_LIST \ +{ /* ->MISRA 11.3 */ /* ->SEC R2.7.1 */ \ + &GPIO_FROM_PPR0, &GPIO_FROM_PPR1, &GPIO_FROM_PPR2, &GPIO_FROM_PPR3, &GPIO_FROM_PPR4, &GPIO_FROM_PPR5, &GPIO_FROM_PPR6, &GPIO_FROM_PPR7, \ + &GPIO_FROM_PPR8, &GPIO_FROM_PPR9 \ +} /* <-MISRA 11.3 */ /* <-SEC R2.7.1 */ /* { } is for MISRA 19.4 */ +#define GPIO_FROM_PPR0 (*(struct st_gpio_from_ppr0 *)&GPIO.PPR0) /* GPIO_FROM_PPR0 */ +#define GPIO_FROM_PPR1 (*(struct st_gpio_from_ppr0 *)&GPIO.PPR1) /* GPIO_FROM_PPR1 */ +#define GPIO_FROM_PPR2 (*(struct st_gpio_from_ppr0 *)&GPIO.PPR2) /* GPIO_FROM_PPR2 */ +#define GPIO_FROM_PPR3 (*(struct st_gpio_from_ppr0 *)&GPIO.PPR3) /* GPIO_FROM_PPR3 */ +#define GPIO_FROM_PPR4 (*(struct st_gpio_from_ppr0 *)&GPIO.PPR4) /* GPIO_FROM_PPR4 */ +#define GPIO_FROM_PPR5 (*(struct st_gpio_from_ppr0 *)&GPIO.PPR5) /* GPIO_FROM_PPR5 */ +#define GPIO_FROM_PPR6 (*(struct st_gpio_from_ppr0 *)&GPIO.PPR6) /* GPIO_FROM_PPR6 */ +#define GPIO_FROM_PPR7 (*(struct st_gpio_from_ppr0 *)&GPIO.PPR7) /* GPIO_FROM_PPR7 */ +#define GPIO_FROM_PPR8 (*(struct st_gpio_from_ppr0 *)&GPIO.PPR8) /* GPIO_FROM_PPR8 */ +#define GPIO_FROM_PPR9 (*(struct st_gpio_from_ppr0 *)&GPIO.PPR9) /* GPIO_FROM_PPR9 */ + + +/* Channel array defines of GPIO_FROM_P1_ARRAY */ +/*(Sample) value = GPIO_FROM_P1_ARRAY[ channel ]->P1; */ +#define GPIO_FROM_P1_ARRAY_COUNT (9) +#define GPIO_FROM_P1_ARRAY_ADDRESS_LIST \ +{ /* ->MISRA 11.3 */ /* ->SEC R2.7.1 */ \ + &GPIO_FROM_P1, &GPIO_FROM_P2, &GPIO_FROM_P3, &GPIO_FROM_P4, &GPIO_FROM_P5, &GPIO_FROM_P6, &GPIO_FROM_P7, &GPIO_FROM_P8, \ + &GPIO_FROM_P9 \ +} /* <-MISRA 11.3 */ /* <-SEC R2.7.1 */ /* { } is for MISRA 19.4 */ +#define GPIO_FROM_P1 (*(struct st_gpio_from_p1 *)&GPIO.P1) /* GPIO_FROM_P1 */ +#define GPIO_FROM_P2 (*(struct st_gpio_from_p1 *)&GPIO.P2) /* GPIO_FROM_P2 */ +#define GPIO_FROM_P3 (*(struct st_gpio_from_p1 *)&GPIO.P3) /* GPIO_FROM_P3 */ +#define GPIO_FROM_P4 (*(struct st_gpio_from_p1 *)&GPIO.P4) /* GPIO_FROM_P4 */ +#define GPIO_FROM_P5 (*(struct st_gpio_from_p1 *)&GPIO.P5) /* GPIO_FROM_P5 */ +#define GPIO_FROM_P6 (*(struct st_gpio_from_p1 *)&GPIO.P6) /* GPIO_FROM_P6 */ +#define GPIO_FROM_P7 (*(struct st_gpio_from_p1 *)&GPIO.P7) /* GPIO_FROM_P7 */ +#define GPIO_FROM_P8 (*(struct st_gpio_from_p1 *)&GPIO.P8) /* GPIO_FROM_P8 */ +#define GPIO_FROM_P9 (*(struct st_gpio_from_p1 *)&GPIO.P9) /* GPIO_FROM_P9 */ + +/* End of channel array defines of GPIO */ + + +#define GPIOP1 (GPIO.P1) +#define GPIOP2 (GPIO.P2) +#define GPIOP3 (GPIO.P3) +#define GPIOP4 (GPIO.P4) +#define GPIOP5 (GPIO.P5) +#define GPIOP6 (GPIO.P6) +#define GPIOP7 (GPIO.P7) +#define GPIOP8 (GPIO.P8) +#define GPIOP9 (GPIO.P9) +#define GPIOPSR1 (GPIO.PSR1) +#define GPIOPSR2 (GPIO.PSR2) +#define GPIOPSR3 (GPIO.PSR3) +#define GPIOPSR4 (GPIO.PSR4) +#define GPIOPSR5 (GPIO.PSR5) +#define GPIOPSR6 (GPIO.PSR6) +#define GPIOPSR7 (GPIO.PSR7) +#define GPIOPSR8 (GPIO.PSR8) +#define GPIOPSR9 (GPIO.PSR9) +#define GPIOPPR0 (GPIO.PPR0) +#define GPIOPPR1 (GPIO.PPR1) +#define GPIOPPR2 (GPIO.PPR2) +#define GPIOPPR3 (GPIO.PPR3) +#define GPIOPPR4 (GPIO.PPR4) +#define GPIOPPR5 (GPIO.PPR5) +#define GPIOPPR6 (GPIO.PPR6) +#define GPIOPPR7 (GPIO.PPR7) +#define GPIOPPR8 (GPIO.PPR8) +#define GPIOPPR9 (GPIO.PPR9) +#define GPIOPM1 (GPIO.PM1) +#define GPIOPM2 (GPIO.PM2) +#define GPIOPM3 (GPIO.PM3) +#define GPIOPM4 (GPIO.PM4) +#define GPIOPM5 (GPIO.PM5) +#define GPIOPM6 (GPIO.PM6) +#define GPIOPM7 (GPIO.PM7) +#define GPIOPM8 (GPIO.PM8) +#define GPIOPM9 (GPIO.PM9) +#define GPIOPMC0 (GPIO.PMC0) +#define GPIOPMC1 (GPIO.PMC1) +#define GPIOPMC2 (GPIO.PMC2) +#define GPIOPMC3 (GPIO.PMC3) +#define GPIOPMC4 (GPIO.PMC4) +#define GPIOPMC5 (GPIO.PMC5) +#define GPIOPMC6 (GPIO.PMC6) +#define GPIOPMC7 (GPIO.PMC7) +#define GPIOPMC8 (GPIO.PMC8) +#define GPIOPMC9 (GPIO.PMC9) +#define GPIOPFC0 (GPIO.PFC0) +#define GPIOPFC1 (GPIO.PFC1) +#define GPIOPFC2 (GPIO.PFC2) +#define GPIOPFC3 (GPIO.PFC3) +#define GPIOPFC4 (GPIO.PFC4) +#define GPIOPFC5 (GPIO.PFC5) +#define GPIOPFC6 (GPIO.PFC6) +#define GPIOPFC7 (GPIO.PFC7) +#define GPIOPFC8 (GPIO.PFC8) +#define GPIOPFC9 (GPIO.PFC9) +#define GPIOPFCE0 (GPIO.PFCE0) +#define GPIOPFCE1 (GPIO.PFCE1) +#define GPIOPFCE2 (GPIO.PFCE2) +#define GPIOPFCE3 (GPIO.PFCE3) +#define GPIOPFCE4 (GPIO.PFCE4) +#define GPIOPFCE5 (GPIO.PFCE5) +#define GPIOPFCE6 (GPIO.PFCE6) +#define GPIOPFCE7 (GPIO.PFCE7) +#define GPIOPFCE8 (GPIO.PFCE8) +#define GPIOPFCE9 (GPIO.PFCE9) +#define GPIOPNOT1 (GPIO.PNOT1) +#define GPIOPNOT2 (GPIO.PNOT2) +#define GPIOPNOT3 (GPIO.PNOT3) +#define GPIOPNOT4 (GPIO.PNOT4) +#define GPIOPNOT5 (GPIO.PNOT5) +#define GPIOPNOT6 (GPIO.PNOT6) +#define GPIOPNOT7 (GPIO.PNOT7) +#define GPIOPNOT8 (GPIO.PNOT8) +#define GPIOPNOT9 (GPIO.PNOT9) +#define GPIOPMSR1 (GPIO.PMSR1) +#define GPIOPMSR2 (GPIO.PMSR2) +#define GPIOPMSR3 (GPIO.PMSR3) +#define GPIOPMSR4 (GPIO.PMSR4) +#define GPIOPMSR5 (GPIO.PMSR5) +#define GPIOPMSR6 (GPIO.PMSR6) +#define GPIOPMSR7 (GPIO.PMSR7) +#define GPIOPMSR8 (GPIO.PMSR8) +#define GPIOPMSR9 (GPIO.PMSR9) +#define GPIOPMCSR0 (GPIO.PMCSR0) +#define GPIOPMCSR1 (GPIO.PMCSR1) +#define GPIOPMCSR2 (GPIO.PMCSR2) +#define GPIOPMCSR3 (GPIO.PMCSR3) +#define GPIOPMCSR4 (GPIO.PMCSR4) +#define GPIOPMCSR5 (GPIO.PMCSR5) +#define GPIOPMCSR6 (GPIO.PMCSR6) +#define GPIOPMCSR7 (GPIO.PMCSR7) +#define GPIOPMCSR8 (GPIO.PMCSR8) +#define GPIOPMCSR9 (GPIO.PMCSR9) +#define GPIOPFCAE0 (GPIO.PFCAE0) +#define GPIOPFCAE1 (GPIO.PFCAE1) +#define GPIOPFCAE2 (GPIO.PFCAE2) +#define GPIOPFCAE3 (GPIO.PFCAE3) +#define GPIOPFCAE4 (GPIO.PFCAE4) +#define GPIOPFCAE5 (GPIO.PFCAE5) +#define GPIOPFCAE6 (GPIO.PFCAE6) +#define GPIOPFCAE7 (GPIO.PFCAE7) +#define GPIOPFCAE8 (GPIO.PFCAE8) +#define GPIOPFCAE9 (GPIO.PFCAE9) +#define GPIOSNCR (GPIO.SNCR) +#define GPIOPIBC0 (GPIO.PIBC0) +#define GPIOPIBC1 (GPIO.PIBC1) +#define GPIOPIBC2 (GPIO.PIBC2) +#define GPIOPIBC3 (GPIO.PIBC3) +#define GPIOPIBC4 (GPIO.PIBC4) +#define GPIOPIBC5 (GPIO.PIBC5) +#define GPIOPIBC6 (GPIO.PIBC6) +#define GPIOPIBC7 (GPIO.PIBC7) +#define GPIOPIBC8 (GPIO.PIBC8) +#define GPIOPIBC9 (GPIO.PIBC9) +#define GPIOPBDC1 (GPIO.PBDC1) +#define GPIOPBDC2 (GPIO.PBDC2) +#define GPIOPBDC3 (GPIO.PBDC3) +#define GPIOPBDC4 (GPIO.PBDC4) +#define GPIOPBDC5 (GPIO.PBDC5) +#define GPIOPBDC6 (GPIO.PBDC6) +#define GPIOPBDC7 (GPIO.PBDC7) +#define GPIOPBDC8 (GPIO.PBDC8) +#define GPIOPBDC9 (GPIO.PBDC9) +#define GPIOPIPC1 (GPIO.PIPC1) +#define GPIOPIPC2 (GPIO.PIPC2) +#define GPIOPIPC3 (GPIO.PIPC3) +#define GPIOPIPC4 (GPIO.PIPC4) +#define GPIOPIPC5 (GPIO.PIPC5) +#define GPIOPIPC6 (GPIO.PIPC6) +#define GPIOPIPC7 (GPIO.PIPC7) +#define GPIOPIPC8 (GPIO.PIPC8) +#define GPIOPIPC9 (GPIO.PIPC9) +#define GPIOJPPR0 (GPIO.JPPR0) +#define GPIOJPMC0 (GPIO.JPMC0) +#define GPIOJPMCSR0 (GPIO.JPMCSR0) +#define GPIOJPIBC0 (GPIO.JPIBC0) + +#define GPIO_PSRn_COUNT (9) +#define GPIO_PMSRn_COUNT (9) +#define GPIO_PMCSRn_COUNT (10) + + +typedef struct st_gpio +{ + /* GPIO */ + +/* start of struct st_gpio_from_p1 */ + volatile uint16_t P1; /* P1 */ + volatile uint8_t dummy348[2]; /* */ + +/* end of struct st_gpio_from_p1 */ + +/* start of struct st_gpio_from_p1 */ + volatile uint16_t P2; /* P2 */ + volatile uint8_t dummy349[2]; /* */ + +/* end of struct st_gpio_from_p1 */ + +/* start of struct st_gpio_from_p1 */ + volatile uint16_t P3; /* P3 */ + volatile uint8_t dummy350[2]; /* */ + +/* end of struct st_gpio_from_p1 */ + +/* start of struct st_gpio_from_p1 */ + volatile uint16_t P4; /* P4 */ + volatile uint8_t dummy351[2]; /* */ + +/* end of struct st_gpio_from_p1 */ + +/* start of struct st_gpio_from_p1 */ + volatile uint16_t P5; /* P5 */ + volatile uint8_t dummy352[2]; /* */ + +/* end of struct st_gpio_from_p1 */ + +/* start of struct st_gpio_from_p1 */ + volatile uint16_t P6; /* P6 */ + volatile uint8_t dummy353[2]; /* */ + +/* end of struct st_gpio_from_p1 */ + +/* start of struct st_gpio_from_p1 */ + volatile uint16_t P7; /* P7 */ + volatile uint8_t dummy354[2]; /* */ + +/* end of struct st_gpio_from_p1 */ + +/* start of struct st_gpio_from_p1 */ + volatile uint16_t P8; /* P8 */ + volatile uint8_t dummy355[2]; /* */ + +/* end of struct st_gpio_from_p1 */ + +/* start of struct st_gpio_from_p1 */ + volatile uint16_t P9; /* P9 */ + volatile uint8_t dummy3560[2]; /* */ + +/* end of struct st_gpio_from_p1 */ + volatile uint8_t dummy3561[220]; /* */ + +/* #define GPIO_PSRn_COUNT (9) */ + volatile uint32_t PSR1; /* PSR1 */ + volatile uint32_t PSR2; /* PSR2 */ + volatile uint32_t PSR3; /* PSR3 */ + volatile uint32_t PSR4; /* PSR4 */ + volatile uint32_t PSR5; /* PSR5 */ + volatile uint32_t PSR6; /* PSR6 */ + volatile uint32_t PSR7; /* PSR7 */ + volatile uint32_t PSR8; /* PSR8 */ + volatile uint32_t PSR9; /* PSR9 */ + volatile uint8_t dummy357[216]; /* */ + +/* start of struct st_gpio_from_ppr0 */ + volatile uint16_t PPR0; /* PPR0 */ + volatile uint8_t dummy358[2]; /* */ + +/* end of struct st_gpio_from_ppr0 */ + +/* start of struct st_gpio_from_ppr0 */ + volatile uint16_t PPR1; /* PPR1 */ + volatile uint8_t dummy359[2]; /* */ + +/* end of struct st_gpio_from_ppr0 */ + +/* start of struct st_gpio_from_ppr0 */ + volatile uint16_t PPR2; /* PPR2 */ + volatile uint8_t dummy360[2]; /* */ + +/* end of struct st_gpio_from_ppr0 */ + +/* start of struct st_gpio_from_ppr0 */ + volatile uint16_t PPR3; /* PPR3 */ + volatile uint8_t dummy361[2]; /* */ + +/* end of struct st_gpio_from_ppr0 */ + +/* start of struct st_gpio_from_ppr0 */ + volatile uint16_t PPR4; /* PPR4 */ + volatile uint8_t dummy362[2]; /* */ + +/* end of struct st_gpio_from_ppr0 */ + +/* start of struct st_gpio_from_ppr0 */ + volatile uint16_t PPR5; /* PPR5 */ + volatile uint8_t dummy363[2]; /* */ + +/* end of struct st_gpio_from_ppr0 */ + +/* start of struct st_gpio_from_ppr0 */ + volatile uint16_t PPR6; /* PPR6 */ + volatile uint8_t dummy364[2]; /* */ + +/* end of struct st_gpio_from_ppr0 */ + +/* start of struct st_gpio_from_ppr0 */ + volatile uint16_t PPR7; /* PPR7 */ + volatile uint8_t dummy365[2]; /* */ + +/* end of struct st_gpio_from_ppr0 */ + +/* start of struct st_gpio_from_ppr0 */ + volatile uint16_t PPR8; /* PPR8 */ + volatile uint8_t dummy366[2]; /* */ + +/* end of struct st_gpio_from_ppr0 */ + +/* start of struct st_gpio_from_ppr0 */ + volatile uint16_t PPR9; /* PPR9 */ + volatile uint8_t dummy3670[2]; /* */ + +/* end of struct st_gpio_from_ppr0 */ + volatile uint8_t dummy3671[220]; /* */ + +/* start of struct st_gpio_from_pm1 */ + volatile uint16_t PM1; /* PM1 */ + volatile uint8_t dummy368[2]; /* */ + +/* end of struct st_gpio_from_pm1 */ + +/* start of struct st_gpio_from_pm1 */ + volatile uint16_t PM2; /* PM2 */ + volatile uint8_t dummy369[2]; /* */ + +/* end of struct st_gpio_from_pm1 */ + +/* start of struct st_gpio_from_pm1 */ + volatile uint16_t PM3; /* PM3 */ + volatile uint8_t dummy370[2]; /* */ + +/* end of struct st_gpio_from_pm1 */ + +/* start of struct st_gpio_from_pm1 */ + volatile uint16_t PM4; /* PM4 */ + volatile uint8_t dummy371[2]; /* */ + +/* end of struct st_gpio_from_pm1 */ + +/* start of struct st_gpio_from_pm1 */ + volatile uint16_t PM5; /* PM5 */ + volatile uint8_t dummy372[2]; /* */ + +/* end of struct st_gpio_from_pm1 */ + +/* start of struct st_gpio_from_pm1 */ + volatile uint16_t PM6; /* PM6 */ + volatile uint8_t dummy373[2]; /* */ + +/* end of struct st_gpio_from_pm1 */ + +/* start of struct st_gpio_from_pm1 */ + volatile uint16_t PM7; /* PM7 */ + volatile uint8_t dummy374[2]; /* */ + +/* end of struct st_gpio_from_pm1 */ + +/* start of struct st_gpio_from_pm1 */ + volatile uint16_t PM8; /* PM8 */ + volatile uint8_t dummy375[2]; /* */ + +/* end of struct st_gpio_from_pm1 */ + +/* start of struct st_gpio_from_pm1 */ + volatile uint16_t PM9; /* PM9 */ + volatile uint8_t dummy3760[2]; /* */ + +/* end of struct st_gpio_from_pm1 */ + volatile uint8_t dummy3761[216]; /* */ + +/* start of struct st_gpio_from_pmc0 */ + volatile uint16_t PMC0; /* PMC0 */ + volatile uint8_t dummy377[2]; /* */ + +/* end of struct st_gpio_from_pmc0 */ + +/* start of struct st_gpio_from_pmc0 */ + volatile uint16_t PMC1; /* PMC1 */ + volatile uint8_t dummy378[2]; /* */ + +/* end of struct st_gpio_from_pmc0 */ + +/* start of struct st_gpio_from_pmc0 */ + volatile uint16_t PMC2; /* PMC2 */ + volatile uint8_t dummy379[2]; /* */ + +/* end of struct st_gpio_from_pmc0 */ + +/* start of struct st_gpio_from_pmc0 */ + volatile uint16_t PMC3; /* PMC3 */ + volatile uint8_t dummy380[2]; /* */ + +/* end of struct st_gpio_from_pmc0 */ + +/* start of struct st_gpio_from_pmc0 */ + volatile uint16_t PMC4; /* PMC4 */ + volatile uint8_t dummy381[2]; /* */ + +/* end of struct st_gpio_from_pmc0 */ + +/* start of struct st_gpio_from_pmc0 */ + volatile uint16_t PMC5; /* PMC5 */ + volatile uint8_t dummy382[2]; /* */ + +/* end of struct st_gpio_from_pmc0 */ + +/* start of struct st_gpio_from_pmc0 */ + volatile uint16_t PMC6; /* PMC6 */ + volatile uint8_t dummy383[2]; /* */ + +/* end of struct st_gpio_from_pmc0 */ + +/* start of struct st_gpio_from_pmc0 */ + volatile uint16_t PMC7; /* PMC7 */ + volatile uint8_t dummy384[2]; /* */ + +/* end of struct st_gpio_from_pmc0 */ + +/* start of struct st_gpio_from_pmc0 */ + volatile uint16_t PMC8; /* PMC8 */ + volatile uint8_t dummy385[2]; /* */ + +/* end of struct st_gpio_from_pmc0 */ + +/* start of struct st_gpio_from_pmc0 */ + volatile uint16_t PMC9; /* PMC9 */ + volatile uint8_t dummy3860[2]; /* */ + +/* end of struct st_gpio_from_pmc0 */ + volatile uint8_t dummy3861[216]; /* */ + +/* start of struct st_gpio_from_pfc1 */ + volatile uint16_t PFC0; /* PFC0 */ + volatile uint8_t dummy387[2]; /* */ + +/* end of struct st_gpio_from_pfc1 */ + +/* start of struct st_gpio_from_pfc1 */ + volatile uint16_t PFC1; /* PFC1 */ + volatile uint8_t dummy388[2]; /* */ + +/* end of struct st_gpio_from_pfc1 */ + +/* start of struct st_gpio_from_pfc1 */ + volatile uint16_t PFC2; /* PFC2 */ + volatile uint8_t dummy389[2]; /* */ + +/* end of struct st_gpio_from_pfc1 */ + +/* start of struct st_gpio_from_pfc1 */ + volatile uint16_t PFC3; /* PFC3 */ + volatile uint8_t dummy390[2]; /* */ + +/* end of struct st_gpio_from_pfc1 */ + +/* start of struct st_gpio_from_pfc1 */ + volatile uint16_t PFC4; /* PFC4 */ + volatile uint8_t dummy391[2]; /* */ + +/* end of struct st_gpio_from_pfc1 */ + +/* start of struct st_gpio_from_pfc1 */ + volatile uint16_t PFC5; /* PFC5 */ + volatile uint8_t dummy392[2]; /* */ + +/* end of struct st_gpio_from_pfc1 */ + +/* start of struct st_gpio_from_pfc1 */ + volatile uint16_t PFC6; /* PFC6 */ + volatile uint8_t dummy393[2]; /* */ + +/* end of struct st_gpio_from_pfc1 */ + +/* start of struct st_gpio_from_pfc1 */ + volatile uint16_t PFC7; /* PFC7 */ + volatile uint8_t dummy394[2]; /* */ + +/* end of struct st_gpio_from_pfc1 */ + +/* start of struct st_gpio_from_pfc1 */ + volatile uint16_t PFC8; /* PFC8 */ + volatile uint8_t dummy395[2]; /* */ + +/* end of struct st_gpio_from_pfc1 */ + +/* start of struct st_gpio_from_pfc1 */ + volatile uint16_t PFC9; /* PFC9 */ + volatile uint8_t dummy3960[2]; /* */ + +/* end of struct st_gpio_from_pfc1 */ + volatile uint8_t dummy3961[216]; /* */ + +/* start of struct st_gpio_from_pfce1 */ + volatile uint16_t PFCE0; /* PFCE0 */ + volatile uint8_t dummy397[2]; /* */ + +/* end of struct st_gpio_from_pfce1 */ + +/* start of struct st_gpio_from_pfce1 */ + volatile uint16_t PFCE1; /* PFCE1 */ + volatile uint8_t dummy398[2]; /* */ + +/* end of struct st_gpio_from_pfce1 */ + +/* start of struct st_gpio_from_pfce1 */ + volatile uint16_t PFCE2; /* PFCE2 */ + volatile uint8_t dummy399[2]; /* */ + +/* end of struct st_gpio_from_pfce1 */ + +/* start of struct st_gpio_from_pfce1 */ + volatile uint16_t PFCE3; /* PFCE3 */ + volatile uint8_t dummy400[2]; /* */ + +/* end of struct st_gpio_from_pfce1 */ + +/* start of struct st_gpio_from_pfce1 */ + volatile uint16_t PFCE4; /* PFCE4 */ + volatile uint8_t dummy401[2]; /* */ + +/* end of struct st_gpio_from_pfce1 */ + +/* start of struct st_gpio_from_pfce1 */ + volatile uint16_t PFCE5; /* PFCE5 */ + volatile uint8_t dummy402[2]; /* */ + +/* end of struct st_gpio_from_pfce1 */ + +/* start of struct st_gpio_from_pfce1 */ + volatile uint16_t PFCE6; /* PFCE6 */ + volatile uint8_t dummy403[2]; /* */ + +/* end of struct st_gpio_from_pfce1 */ + +/* start of struct st_gpio_from_pfce1 */ + volatile uint16_t PFCE7; /* PFCE7 */ + volatile uint8_t dummy404[2]; /* */ + +/* end of struct st_gpio_from_pfce1 */ + +/* start of struct st_gpio_from_pfce1 */ + volatile uint16_t PFCE8; /* PFCE8 */ + volatile uint8_t dummy405[2]; /* */ + +/* end of struct st_gpio_from_pfce1 */ + +/* start of struct st_gpio_from_pfce1 */ + volatile uint16_t PFCE9; /* PFCE9 */ + volatile uint8_t dummy4060[2]; /* */ + +/* end of struct st_gpio_from_pfce1 */ + volatile uint8_t dummy4061[220]; /* */ + +/* start of struct st_gpio_from_pnot1 */ + volatile uint16_t PNOT1; /* PNOT1 */ + volatile uint8_t dummy407[2]; /* */ + +/* end of struct st_gpio_from_pnot1 */ + +/* start of struct st_gpio_from_pnot1 */ + volatile uint16_t PNOT2; /* PNOT2 */ + volatile uint8_t dummy408[2]; /* */ + +/* end of struct st_gpio_from_pnot1 */ + +/* start of struct st_gpio_from_pnot1 */ + volatile uint16_t PNOT3; /* PNOT3 */ + volatile uint8_t dummy409[2]; /* */ + +/* end of struct st_gpio_from_pnot1 */ + +/* start of struct st_gpio_from_pnot1 */ + volatile uint16_t PNOT4; /* PNOT4 */ + volatile uint8_t dummy410[2]; /* */ + +/* end of struct st_gpio_from_pnot1 */ + +/* start of struct st_gpio_from_pnot1 */ + volatile uint16_t PNOT5; /* PNOT5 */ + volatile uint8_t dummy411[2]; /* */ + +/* end of struct st_gpio_from_pnot1 */ + +/* start of struct st_gpio_from_pnot1 */ + volatile uint16_t PNOT6; /* PNOT6 */ + volatile uint8_t dummy412[2]; /* */ + +/* end of struct st_gpio_from_pnot1 */ + +/* start of struct st_gpio_from_pnot1 */ + volatile uint16_t PNOT7; /* PNOT7 */ + volatile uint8_t dummy413[2]; /* */ + +/* end of struct st_gpio_from_pnot1 */ + +/* start of struct st_gpio_from_pnot1 */ + volatile uint16_t PNOT8; /* PNOT8 */ + volatile uint8_t dummy414[2]; /* */ + +/* end of struct st_gpio_from_pnot1 */ + +/* start of struct st_gpio_from_pnot1 */ + volatile uint16_t PNOT9; /* PNOT9 */ + volatile uint8_t dummy4150[2]; /* */ + +/* end of struct st_gpio_from_pnot1 */ + volatile uint8_t dummy4151[220]; /* */ + +/* #define GPIO_PMSRn_COUNT (9) */ + volatile uint32_t PMSR1; /* PMSR1 */ + volatile uint32_t PMSR2; /* PMSR2 */ + volatile uint32_t PMSR3; /* PMSR3 */ + volatile uint32_t PMSR4; /* PMSR4 */ + volatile uint32_t PMSR5; /* PMSR5 */ + volatile uint32_t PMSR6; /* PMSR6 */ + volatile uint32_t PMSR7; /* PMSR7 */ + volatile uint32_t PMSR8; /* PMSR8 */ + volatile uint32_t PMSR9; /* PMSR9 */ + volatile uint8_t dummy416[216]; /* */ + +/* #define GPIO_PMCSRn_COUNT (10) */ + volatile uint32_t PMCSR0; /* PMCSR0 */ + volatile uint32_t PMCSR1; /* PMCSR1 */ + volatile uint32_t PMCSR2; /* PMCSR2 */ + volatile uint32_t PMCSR3; /* PMCSR3 */ + volatile uint32_t PMCSR4; /* PMCSR4 */ + volatile uint32_t PMCSR5; /* PMCSR5 */ + volatile uint32_t PMCSR6; /* PMCSR6 */ + volatile uint32_t PMCSR7; /* PMCSR7 */ + volatile uint32_t PMCSR8; /* PMCSR8 */ + volatile uint32_t PMCSR9; /* PMCSR9 */ + volatile uint8_t dummy417[216]; /* */ + +/* start of struct st_gpio_from_pfcae1 */ + volatile uint16_t PFCAE0; /* PFCAE0 */ + volatile uint8_t dummy418[2]; /* */ + +/* end of struct st_gpio_from_pfcae1 */ + +/* start of struct st_gpio_from_pfcae1 */ + volatile uint16_t PFCAE1; /* PFCAE1 */ + volatile uint8_t dummy419[2]; /* */ + +/* end of struct st_gpio_from_pfcae1 */ + +/* start of struct st_gpio_from_pfcae1 */ + volatile uint16_t PFCAE2; /* PFCAE2 */ + volatile uint8_t dummy420[2]; /* */ + +/* end of struct st_gpio_from_pfcae1 */ + +/* start of struct st_gpio_from_pfcae1 */ + volatile uint16_t PFCAE3; /* PFCAE3 */ + volatile uint8_t dummy421[2]; /* */ + +/* end of struct st_gpio_from_pfcae1 */ + +/* start of struct st_gpio_from_pfcae1 */ + volatile uint16_t PFCAE4; /* PFCAE4 */ + volatile uint8_t dummy422[2]; /* */ + +/* end of struct st_gpio_from_pfcae1 */ + +/* start of struct st_gpio_from_pfcae1 */ + volatile uint16_t PFCAE5; /* PFCAE5 */ + volatile uint8_t dummy423[2]; /* */ + +/* end of struct st_gpio_from_pfcae1 */ + +/* start of struct st_gpio_from_pfcae1 */ + volatile uint16_t PFCAE6; /* PFCAE6 */ + volatile uint8_t dummy424[2]; /* */ + +/* end of struct st_gpio_from_pfcae1 */ + +/* start of struct st_gpio_from_pfcae1 */ + volatile uint16_t PFCAE7; /* PFCAE7 */ + volatile uint8_t dummy425[2]; /* */ + +/* end of struct st_gpio_from_pfcae1 */ + +/* start of struct st_gpio_from_pfcae1 */ + volatile uint16_t PFCAE8; /* PFCAE8 */ + volatile uint8_t dummy426[2]; /* */ + +/* end of struct st_gpio_from_pfcae1 */ + +/* start of struct st_gpio_from_pfcae1 */ + volatile uint16_t PFCAE9; /* PFCAE9 */ + volatile uint8_t dummy4270[2]; /* */ + +/* end of struct st_gpio_from_pfcae1 */ + volatile uint8_t dummy4271[472]; /* */ + volatile uint32_t SNCR; /* SNCR */ + volatile uint8_t dummy428[13308]; /* */ + +/* start of struct st_gpio_from_pibc1 */ + volatile uint16_t PIBC0; /* PIBC0 */ + volatile uint8_t dummy429[2]; /* */ + +/* end of struct st_gpio_from_pibc1 */ + +/* start of struct st_gpio_from_pibc1 */ + volatile uint16_t PIBC1; /* PIBC1 */ + volatile uint8_t dummy430[2]; /* */ + +/* end of struct st_gpio_from_pibc1 */ + +/* start of struct st_gpio_from_pibc1 */ + volatile uint16_t PIBC2; /* PIBC2 */ + volatile uint8_t dummy431[2]; /* */ + +/* end of struct st_gpio_from_pibc1 */ + +/* start of struct st_gpio_from_pibc1 */ + volatile uint16_t PIBC3; /* PIBC3 */ + volatile uint8_t dummy432[2]; /* */ + +/* end of struct st_gpio_from_pibc1 */ + +/* start of struct st_gpio_from_pibc1 */ + volatile uint16_t PIBC4; /* PIBC4 */ + volatile uint8_t dummy433[2]; /* */ + +/* end of struct st_gpio_from_pibc1 */ + +/* start of struct st_gpio_from_pibc1 */ + volatile uint16_t PIBC5; /* PIBC5 */ + volatile uint8_t dummy434[2]; /* */ + +/* end of struct st_gpio_from_pibc1 */ + +/* start of struct st_gpio_from_pibc1 */ + volatile uint16_t PIBC6; /* PIBC6 */ + volatile uint8_t dummy435[2]; /* */ + +/* end of struct st_gpio_from_pibc1 */ + +/* start of struct st_gpio_from_pibc1 */ + volatile uint16_t PIBC7; /* PIBC7 */ + volatile uint8_t dummy436[2]; /* */ + +/* end of struct st_gpio_from_pibc1 */ + +/* start of struct st_gpio_from_pibc1 */ + volatile uint16_t PIBC8; /* PIBC8 */ + volatile uint8_t dummy437[2]; /* */ + +/* end of struct st_gpio_from_pibc1 */ + +/* start of struct st_gpio_from_pibc1 */ + volatile uint16_t PIBC9; /* PIBC9 */ + volatile uint8_t dummy4380[2]; /* */ + +/* end of struct st_gpio_from_pibc1 */ + volatile uint8_t dummy4381[220]; /* */ + +/* start of struct st_gpio_from_pbdc1 */ + volatile uint16_t PBDC1; /* PBDC1 */ + volatile uint8_t dummy439[2]; /* */ + +/* end of struct st_gpio_from_pbdc1 */ + +/* start of struct st_gpio_from_pbdc1 */ + volatile uint16_t PBDC2; /* PBDC2 */ + volatile uint8_t dummy440[2]; /* */ + +/* end of struct st_gpio_from_pbdc1 */ + +/* start of struct st_gpio_from_pbdc1 */ + volatile uint16_t PBDC3; /* PBDC3 */ + volatile uint8_t dummy441[2]; /* */ + +/* end of struct st_gpio_from_pbdc1 */ + +/* start of struct st_gpio_from_pbdc1 */ + volatile uint16_t PBDC4; /* PBDC4 */ + volatile uint8_t dummy442[2]; /* */ + +/* end of struct st_gpio_from_pbdc1 */ + +/* start of struct st_gpio_from_pbdc1 */ + volatile uint16_t PBDC5; /* PBDC5 */ + volatile uint8_t dummy443[2]; /* */ + +/* end of struct st_gpio_from_pbdc1 */ + +/* start of struct st_gpio_from_pbdc1 */ + volatile uint16_t PBDC6; /* PBDC6 */ + volatile uint8_t dummy444[2]; /* */ + +/* end of struct st_gpio_from_pbdc1 */ + +/* start of struct st_gpio_from_pbdc1 */ + volatile uint16_t PBDC7; /* PBDC7 */ + volatile uint8_t dummy445[2]; /* */ + +/* end of struct st_gpio_from_pbdc1 */ + +/* start of struct st_gpio_from_pbdc1 */ + volatile uint16_t PBDC8; /* PBDC8 */ + volatile uint8_t dummy446[2]; /* */ + +/* end of struct st_gpio_from_pbdc1 */ + +/* start of struct st_gpio_from_pbdc1 */ + volatile uint16_t PBDC9; /* PBDC9 */ + volatile uint8_t dummy4470[2]; /* */ + +/* end of struct st_gpio_from_pbdc1 */ + volatile uint8_t dummy4471[220]; /* */ + +/* start of struct st_gpio_from_pipc1 */ + volatile uint16_t PIPC1; /* PIPC1 */ + volatile uint8_t dummy448[2]; /* */ + +/* end of struct st_gpio_from_pipc1 */ + +/* start of struct st_gpio_from_pipc1 */ + volatile uint16_t PIPC2; /* PIPC2 */ + volatile uint8_t dummy449[2]; /* */ + +/* end of struct st_gpio_from_pipc1 */ + +/* start of struct st_gpio_from_pipc1 */ + volatile uint16_t PIPC3; /* PIPC3 */ + volatile uint8_t dummy450[2]; /* */ + +/* end of struct st_gpio_from_pipc1 */ + +/* start of struct st_gpio_from_pipc1 */ + volatile uint16_t PIPC4; /* PIPC4 */ + volatile uint8_t dummy451[2]; /* */ + +/* end of struct st_gpio_from_pipc1 */ + +/* start of struct st_gpio_from_pipc1 */ + volatile uint16_t PIPC5; /* PIPC5 */ + volatile uint8_t dummy452[2]; /* */ + +/* end of struct st_gpio_from_pipc1 */ + +/* start of struct st_gpio_from_pipc1 */ + volatile uint16_t PIPC6; /* PIPC6 */ + volatile uint8_t dummy453[2]; /* */ + +/* end of struct st_gpio_from_pipc1 */ + +/* start of struct st_gpio_from_pipc1 */ + volatile uint16_t PIPC7; /* PIPC7 */ + volatile uint8_t dummy454[2]; /* */ + +/* end of struct st_gpio_from_pipc1 */ + +/* start of struct st_gpio_from_pipc1 */ + volatile uint16_t PIPC8; /* PIPC8 */ + volatile uint8_t dummy455[2]; /* */ + +/* end of struct st_gpio_from_pipc1 */ + +/* start of struct st_gpio_from_pipc1 */ + volatile uint16_t PIPC9; /* PIPC9 */ + volatile uint8_t dummy4560[2]; /* */ + +/* end of struct st_gpio_from_pipc1 */ + volatile uint8_t dummy4561[2296]; /* */ + volatile uint16_t JPPR0; /* JPPR0 */ + volatile uint8_t dummy457[30]; /* */ + volatile uint16_t JPMC0; /* JPMC0 */ + volatile uint8_t dummy458[78]; /* */ + volatile uint32_t JPMCSR0; /* JPMCSR0 */ + volatile uint8_t dummy459[876]; /* */ + volatile uint16_t JPIBC0; /* JPIBC0 */ +} r_io_gpio_t; + + +typedef struct st_gpio_from_p1 +{ + + volatile uint16_t P1; /* P1 */ + volatile uint8_t dummy1[3]; /* */ +} r_io_gpio_from_p1_t; + + +typedef struct st_gpio_from_ppr0 +{ + + volatile uint16_t PPR0; /* PPR0 */ + volatile uint8_t dummy1[2]; /* */ +} r_io_gpio_from_ppr0_t; + + +typedef struct st_gpio_from_pm1 +{ + + volatile uint16_t PM1; /* PM1 */ + volatile uint8_t dummy1[2]; /* */ +} r_io_gpio_from_pm1_t; + + +typedef struct st_gpio_from_pmc0 +{ + + volatile uint16_t PMC0; /* PMC0 */ + volatile uint8_t dummy1[2]; /* */ +} r_io_gpio_from_pmc0_t; + + +typedef struct st_gpio_from_pfc1 +{ + + volatile uint16_t PFC1; /* PFC1 */ + volatile uint8_t dummy1[2]; /* */ +} r_io_gpio_from_pfc1_t; + + +typedef struct st_gpio_from_pfce1 +{ + + volatile uint16_t PFCE1; /* PFCE1 */ + volatile uint8_t dummy1[2]; /* */ +} r_io_gpio_from_pfce1_t; + + +typedef struct st_gpio_from_pnot1 +{ + + volatile uint16_t PNOT1; /* PNOT1 */ + volatile uint8_t dummy1[2]; /* */ +} r_io_gpio_from_pnot1_t; + + +typedef struct st_gpio_from_pfcae1 +{ + + volatile uint16_t PFCAE1; /* PFCAE1 */ + volatile uint8_t dummy1[2]; /* */ +} r_io_gpio_from_pfcae1_t; + + +typedef struct st_gpio_from_pibc1 +{ + + volatile uint16_t PIBC1; /* PIBC1 */ + volatile uint8_t dummy1[2]; /* */ +} r_io_gpio_from_pibc1_t; + + +typedef struct st_gpio_from_pbdc1 +{ + + volatile uint16_t PBDC1; /* PBDC1 */ + volatile uint8_t dummy1[2]; /* */ +} r_io_gpio_from_pbdc1_t; + + +typedef struct st_gpio_from_pipc1 +{ + + volatile uint16_t PIPC1; /* PIPC1 */ + volatile uint8_t dummy1[2]; /* */ +} r_io_gpio_from_pipc1_t; + + +/* Channel array defines of GPIO (2)*/ +#ifdef DECLARE_GPIO_FROM_PIPC1_ARRAY_CHANNELS +volatile struct st_gpio_from_pipc1* GPIO_FROM_PIPC1_ARRAY[ GPIO_FROM_PIPC1_ARRAY_COUNT ] = + /* ->MISRA 11.3 */ /* ->SEC R2.7.1 */ + GPIO_FROM_PIPC1_ARRAY_ADDRESS_LIST; + /* <-MISRA 11.3 */ /* <-SEC R2.7.1 */ +#endif /* DECLARE_GPIO_FROM_PIPC1_ARRAY_CHANNELS */ + +#ifdef DECLARE_GPIO_FROM_PBDC1_ARRAY_CHANNELS +volatile struct st_gpio_from_pbdc1* GPIO_FROM_PBDC1_ARRAY[ GPIO_FROM_PBDC1_ARRAY_COUNT ] = + /* ->MISRA 11.3 */ /* ->SEC R2.7.1 */ + GPIO_FROM_PBDC1_ARRAY_ADDRESS_LIST; + /* <-MISRA 11.3 */ /* <-SEC R2.7.1 */ +#endif /* DECLARE_GPIO_FROM_PBDC1_ARRAY_CHANNELS */ + +#ifdef DECLARE_GPIO_FROM_PIBC1_ARRAY_CHANNELS +volatile struct st_gpio_from_pibc1* GPIO_FROM_PIBC1_ARRAY[ GPIO_FROM_PIBC1_ARRAY_COUNT ] = + /* ->MISRA 11.3 */ /* ->SEC R2.7.1 */ + GPIO_FROM_PIBC1_ARRAY_ADDRESS_LIST; + /* <-MISRA 11.3 */ /* <-SEC R2.7.1 */ +#endif /* DECLARE_GPIO_FROM_PIBC1_ARRAY_CHANNELS */ + +#ifdef DECLARE_GPIO_FROM_PFCAE1_ARRAY_CHANNELS +volatile struct st_gpio_from_pfcae1* GPIO_FROM_PFCAE1_ARRAY[ GPIO_FROM_PFCAE1_ARRAY_COUNT ] = + /* ->MISRA 11.3 */ /* ->SEC R2.7.1 */ + GPIO_FROM_PFCAE1_ARRAY_ADDRESS_LIST; + /* <-MISRA 11.3 */ /* <-SEC R2.7.1 */ +#endif /* DECLARE_GPIO_FROM_PFCAE1_ARRAY_CHANNELS */ + +#ifdef DECLARE_GPIO_FROM_PNOT1_ARRAY_CHANNELS +volatile struct st_gpio_from_pnot1* GPIO_FROM_PNOT1_ARRAY[ GPIO_FROM_PNOT1_ARRAY_COUNT ] = + /* ->MISRA 11.3 */ /* ->SEC R2.7.1 */ + GPIO_FROM_PNOT1_ARRAY_ADDRESS_LIST; + /* <-MISRA 11.3 */ /* <-SEC R2.7.1 */ +#endif /* DECLARE_GPIO_FROM_PNOT1_ARRAY_CHANNELS */ + +#ifdef DECLARE_GPIO_FROM_PFCE1_ARRAY_CHANNELS +volatile struct st_gpio_from_pfce1* GPIO_FROM_PFCE1_ARRAY[ GPIO_FROM_PFCE1_ARRAY_COUNT ] = + /* ->MISRA 11.3 */ /* ->SEC R2.7.1 */ + GPIO_FROM_PFCE1_ARRAY_ADDRESS_LIST; + /* <-MISRA 11.3 */ /* <-SEC R2.7.1 */ +#endif /* DECLARE_GPIO_FROM_PFCE1_ARRAY_CHANNELS */ + +#ifdef DECLARE_GPIO_FROM_PFC1_ARRAY_CHANNELS +volatile struct st_gpio_from_pfc1* GPIO_FROM_PFC1_ARRAY[ GPIO_FROM_PFC1_ARRAY_COUNT ] = + /* ->MISRA 11.3 */ /* ->SEC R2.7.1 */ + GPIO_FROM_PFC1_ARRAY_ADDRESS_LIST; + /* <-MISRA 11.3 */ /* <-SEC R2.7.1 */ +#endif /* DECLARE_GPIO_FROM_PFC1_ARRAY_CHANNELS */ + +#ifdef DECLARE_GPIO_FROM_PMC0_ARRAY_CHANNELS +volatile struct st_gpio_from_pmc0* GPIO_FROM_PMC0_ARRAY[ GPIO_FROM_PMC0_ARRAY_COUNT ] = + /* ->MISRA 11.3 */ /* ->SEC R2.7.1 */ + GPIO_FROM_PMC0_ARRAY_ADDRESS_LIST; + /* <-MISRA 11.3 */ /* <-SEC R2.7.1 */ +#endif /* DECLARE_GPIO_FROM_PMC0_ARRAY_CHANNELS */ + +#ifdef DECLARE_GPIO_FROM_PM1_ARRAY_CHANNELS +volatile struct st_gpio_from_pm1* GPIO_FROM_PM1_ARRAY[ GPIO_FROM_PM1_ARRAY_COUNT ] = + /* ->MISRA 11.3 */ /* ->SEC R2.7.1 */ + GPIO_FROM_PM1_ARRAY_ADDRESS_LIST; + /* <-MISRA 11.3 */ /* <-SEC R2.7.1 */ +#endif /* DECLARE_GPIO_FROM_PM1_ARRAY_CHANNELS */ + +#ifdef DECLARE_GPIO_FROM_PPR0_ARRAY_CHANNELS +volatile struct st_gpio_from_ppr0* GPIO_FROM_PPR0_ARRAY[ GPIO_FROM_PPR0_ARRAY_COUNT ] = + /* ->MISRA 11.3 */ /* ->SEC R2.7.1 */ + GPIO_FROM_PPR0_ARRAY_ADDRESS_LIST; + /* <-MISRA 11.3 */ /* <-SEC R2.7.1 */ +#endif /* DECLARE_GPIO_FROM_PPR0_ARRAY_CHANNELS */ + +#ifdef DECLARE_GPIO_FROM_P1_ARRAY_CHANNELS +volatile struct st_gpio_from_p1* GPIO_FROM_P1_ARRAY[ GPIO_FROM_P1_ARRAY_COUNT ] = + /* ->MISRA 11.3 */ /* ->SEC R2.7.1 */ + GPIO_FROM_P1_ARRAY_ADDRESS_LIST; + /* <-MISRA 11.3 */ /* <-SEC R2.7.1 */ +#endif /* DECLARE_GPIO_FROM_P1_ARRAY_CHANNELS */ +/* End of channel array defines of GPIO (2)*/ + + +/* <-SEC M1.10.1 */ +/* <-MISRA 18.4 */ /* <-SEC M1.6.2 */ +/* <-QAC 0857 */ +/* <-QAC 0639 */ +#endif diff --git a/targets/TARGET_RENESAS/TARGET_RZ_A1XX/TARGET_GR_LYCHEE/device/inc/iodefines/inb_iodefine.h b/targets/TARGET_RENESAS/TARGET_RZ_A1XX/TARGET_GR_LYCHEE/device/inc/iodefines/inb_iodefine.h new file mode 100644 index 0000000..da822c5 --- /dev/null +++ b/targets/TARGET_RENESAS/TARGET_RZ_A1XX/TARGET_GR_LYCHEE/device/inc/iodefines/inb_iodefine.h @@ -0,0 +1,96 @@ +/******************************************************************************* +* DISCLAIMER +* This software is supplied by Renesas Electronics Corporation and is only +* intended for use with Renesas products. No other uses are authorized. This +* software is owned by Renesas Electronics Corporation and is protected under +* all applicable laws, including copyright laws. +* THIS SOFTWARE IS PROVIDED "AS IS" AND RENESAS MAKES NO WARRANTIES REGARDING +* THIS SOFTWARE, WHETHER EXPRESS, IMPLIED OR STATUTORY, INCLUDING BUT NOT +* LIMITED TO WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE +* AND NON-INFRINGEMENT. ALL SUCH WARRANTIES ARE EXPRESSLY DISCLAIMED. +* TO THE MAXIMUM EXTENT PERMITTED NOT PROHIBITED BY LAW, NEITHER RENESAS +* ELECTRONICS CORPORATION NOR ANY OF ITS AFFILIATED COMPANIES SHALL BE LIABLE +* FOR ANY DIRECT, INDIRECT, SPECIAL, INCIDENTAL OR CONSEQUENTIAL DAMAGES FOR +* ANY REASON RELATED TO THIS SOFTWARE, EVEN IF RENESAS OR ITS AFFILIATES HAVE +* BEEN ADVISED OF THE POSSIBILITY OF SUCH DAMAGES. +* Renesas reserves the right, without notice, to make changes to this software +* and to discontinue the availability of this software. By using this software, +* you agree to the additional terms and conditions found by accessing the +* following link: +* http://www.renesas.com/disclaimer* +* Copyright (C) 2013-2016 Renesas Electronics Corporation. All rights reserved. +*******************************************************************************/ +/******************************************************************************* +* File Name : inb_iodefine.h +* $Rev: $ +* $Date:: $ +* Description : Definition of I/O Register for RZ/A1LU (V3.00l) +******************************************************************************/ +#ifndef INB_IODEFINE_H +#define INB_IODEFINE_H +/* ->QAC 0639 : Over 127 members (C90) */ +/* ->QAC 0857 : Over 1024 #define (C90) */ +/* ->MISRA 18.4 : Pack unpack union */ /* ->SEC M1.6.2 */ +/* ->SEC M1.10.1 : Not magic number */ + +#define INB (*(struct st_inb *)0xFCFE1A00uL) /* INB */ + + +#define INBRMPR (INB.RMPR) +#define INBAXIBUSCTL0 (INB.AXIBUSCTL0) +#define INBAXIBUSCTL2 (INB.AXIBUSCTL2) +#define INBAXIBUSCTL5 (INB.AXIBUSCTL5) +#define INBAXIBUSCTL6 (INB.AXIBUSCTL6) +#define INBAXIBUSCTL7 (INB.AXIBUSCTL7) +#define INBAXIRERRCTL0 (INB.AXIRERRCTL0) +#define INBAXIRERRCTL2 (INB.AXIRERRCTL2) +#define INBAXIRERRST0 (INB.AXIRERRST0) +#define INBAXIRERRST2 (INB.AXIRERRST2) +#define INBAXIRERRCLR0 (INB.AXIRERRCLR0) +#define INBAXIRERRCLR2 (INB.AXIRERRCLR2) + +#define INB_AXIBUSCTLn_COUNT (1) +#define INB_AXIRERRCTLn_COUNT (1) +#define INB_AXIRERRSTn_COUNT (1) +#define INB_AXIRERRCLRn_COUNT (1) + + +typedef struct st_inb +{ + /* INB */ + volatile uint32_t RMPR; /* RMPR */ + +/* #define INB_AXIBUSCTLn_COUNT (1) */ + volatile uint32_t AXIBUSCTL0; /* AXIBUSCTL0 */ + volatile uint8_t dummy318[4]; /* */ + volatile uint32_t AXIBUSCTL2; /* AXIBUSCTL2 */ + volatile uint8_t dummy319[8]; /* */ + volatile uint32_t AXIBUSCTL5; /* AXIBUSCTL5 */ + volatile uint32_t AXIBUSCTL6; /* AXIBUSCTL6 */ + volatile uint32_t AXIBUSCTL7; /* AXIBUSCTL7 */ + volatile uint8_t dummy320[12]; /* */ + +/* #define INB_AXIRERRCTLn_COUNT (1) */ + volatile uint32_t AXIRERRCTL0; /* AXIRERRCTL0 */ + volatile uint8_t dummy321[4]; /* */ + volatile uint32_t AXIRERRCTL2; /* AXIRERRCTL2 */ + volatile uint8_t dummy322[4]; /* */ + +/* #define INB_AXIRERRSTn_COUNT (1) */ + volatile uint32_t AXIRERRST0; /* AXIRERRST0 */ + volatile uint8_t dummy323[4]; /* */ + volatile uint32_t AXIRERRST2; /* AXIRERRST2 */ + volatile uint8_t dummy324[4]; /* */ + +/* #define INB_AXIRERRCLRn_COUNT (1) */ + volatile uint32_t AXIRERRCLR0; /* AXIRERRCLR0 */ + volatile uint8_t dummy325[4]; /* */ + volatile uint32_t AXIRERRCLR2; /* AXIRERRCLR2 */ +} r_io_inb_t; + + +/* <-SEC M1.10.1 */ +/* <-MISRA 18.4 */ /* <-SEC M1.6.2 */ +/* <-QAC 0857 */ +/* <-QAC 0639 */ +#endif diff --git a/targets/TARGET_RENESAS/TARGET_RZ_A1XX/TARGET_GR_LYCHEE/device/inc/iodefines/intc_iodefine.h b/targets/TARGET_RENESAS/TARGET_RZ_A1XX/TARGET_GR_LYCHEE/device/inc/iodefines/intc_iodefine.h new file mode 100644 index 0000000..2871107 --- /dev/null +++ b/targets/TARGET_RENESAS/TARGET_RZ_A1XX/TARGET_GR_LYCHEE/device/inc/iodefines/intc_iodefine.h @@ -0,0 +1,977 @@ +/******************************************************************************* +* DISCLAIMER +* This software is supplied by Renesas Electronics Corporation and is only +* intended for use with Renesas products. No other uses are authorized. This +* software is owned by Renesas Electronics Corporation and is protected under +* all applicable laws, including copyright laws. +* THIS SOFTWARE IS PROVIDED "AS IS" AND RENESAS MAKES NO WARRANTIES REGARDING +* THIS SOFTWARE, WHETHER EXPRESS, IMPLIED OR STATUTORY, INCLUDING BUT NOT +* LIMITED TO WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE +* AND NON-INFRINGEMENT. ALL SUCH WARRANTIES ARE EXPRESSLY DISCLAIMED. +* TO THE MAXIMUM EXTENT PERMITTED NOT PROHIBITED BY LAW, NEITHER RENESAS +* ELECTRONICS CORPORATION NOR ANY OF ITS AFFILIATED COMPANIES SHALL BE LIABLE +* FOR ANY DIRECT, INDIRECT, SPECIAL, INCIDENTAL OR CONSEQUENTIAL DAMAGES FOR +* ANY REASON RELATED TO THIS SOFTWARE, EVEN IF RENESAS OR ITS AFFILIATES HAVE +* BEEN ADVISED OF THE POSSIBILITY OF SUCH DAMAGES. +* Renesas reserves the right, without notice, to make changes to this software +* and to discontinue the availability of this software. By using this software, +* you agree to the additional terms and conditions found by accessing the +* following link: +* http://www.renesas.com/disclaimer* +* Copyright (C) 2013-2016 Renesas Electronics Corporation. All rights reserved. +*******************************************************************************/ +/******************************************************************************* +* File Name : intc_iodefine.h +* $Rev: $ +* $Date:: $ +* Description : Definition of I/O Register for RZ/A1LU (V3.00l) +******************************************************************************/ +#ifndef INTC_IODEFINE_H +#define INTC_IODEFINE_H +/* ->QAC 0639 : Over 127 members (C90) */ +/* ->QAC 0857 : Over 1024 #define (C90) */ +/* ->MISRA 18.4 : Pack unpack union */ /* ->SEC M1.6.2 */ +/* ->SEC M1.10.1 : Not magic number */ + +#define INTC (*(struct st_intc *)0xE8201000uL) /* INTC */ + + +#define INTCICDDCR (INTC.ICDDCR) +#define INTCICDICTR (INTC.ICDICTR) +#define INTCICDIIDR (INTC.ICDIIDR) +#define INTCICDISR0 (INTC.ICDISR0) +#define INTCICDISR1 (INTC.ICDISR1) +#define INTCICDISR2 (INTC.ICDISR2) +#define INTCICDISR3 (INTC.ICDISR3) +#define INTCICDISR4 (INTC.ICDISR4) +#define INTCICDISR5 (INTC.ICDISR5) +#define INTCICDISR6 (INTC.ICDISR6) +#define INTCICDISR7 (INTC.ICDISR7) +#define INTCICDISR8 (INTC.ICDISR8) +#define INTCICDISR9 (INTC.ICDISR9) +#define INTCICDISR10 (INTC.ICDISR10) +#define INTCICDISR11 (INTC.ICDISR11) +#define INTCICDISR12 (INTC.ICDISR12) +#define INTCICDISR13 (INTC.ICDISR13) +#define INTCICDISR14 (INTC.ICDISR14) +#define INTCICDISR15 (INTC.ICDISR15) +#define INTCICDISR16 (INTC.ICDISR16) +#define INTCICDISER0 (INTC.ICDISER0) +#define INTCICDISER1 (INTC.ICDISER1) +#define INTCICDISER2 (INTC.ICDISER2) +#define INTCICDISER3 (INTC.ICDISER3) +#define INTCICDISER4 (INTC.ICDISER4) +#define INTCICDISER5 (INTC.ICDISER5) +#define INTCICDISER6 (INTC.ICDISER6) +#define INTCICDISER7 (INTC.ICDISER7) +#define INTCICDISER8 (INTC.ICDISER8) +#define INTCICDISER9 (INTC.ICDISER9) +#define INTCICDISER10 (INTC.ICDISER10) +#define INTCICDISER11 (INTC.ICDISER11) +#define INTCICDISER12 (INTC.ICDISER12) +#define INTCICDISER13 (INTC.ICDISER13) +#define INTCICDISER14 (INTC.ICDISER14) +#define INTCICDISER15 (INTC.ICDISER15) +#define INTCICDISER16 (INTC.ICDISER16) +#define INTCICDICER0 (INTC.ICDICER0) +#define INTCICDICER1 (INTC.ICDICER1) +#define INTCICDICER2 (INTC.ICDICER2) +#define INTCICDICER3 (INTC.ICDICER3) +#define INTCICDICER4 (INTC.ICDICER4) +#define INTCICDICER5 (INTC.ICDICER5) +#define INTCICDICER6 (INTC.ICDICER6) +#define INTCICDICER7 (INTC.ICDICER7) +#define INTCICDICER8 (INTC.ICDICER8) +#define INTCICDICER9 (INTC.ICDICER9) +#define INTCICDICER10 (INTC.ICDICER10) +#define INTCICDICER11 (INTC.ICDICER11) +#define INTCICDICER12 (INTC.ICDICER12) +#define INTCICDICER13 (INTC.ICDICER13) +#define INTCICDICER14 (INTC.ICDICER14) +#define INTCICDICER15 (INTC.ICDICER15) +#define INTCICDICER16 (INTC.ICDICER16) +#define INTCICDISPR0 (INTC.ICDISPR0) +#define INTCICDISPR1 (INTC.ICDISPR1) +#define INTCICDISPR2 (INTC.ICDISPR2) +#define INTCICDISPR3 (INTC.ICDISPR3) +#define INTCICDISPR4 (INTC.ICDISPR4) +#define INTCICDISPR5 (INTC.ICDISPR5) +#define INTCICDISPR6 (INTC.ICDISPR6) +#define INTCICDISPR7 (INTC.ICDISPR7) +#define INTCICDISPR8 (INTC.ICDISPR8) +#define INTCICDISPR9 (INTC.ICDISPR9) +#define INTCICDISPR10 (INTC.ICDISPR10) +#define INTCICDISPR11 (INTC.ICDISPR11) +#define INTCICDISPR12 (INTC.ICDISPR12) +#define INTCICDISPR13 (INTC.ICDISPR13) +#define INTCICDISPR14 (INTC.ICDISPR14) +#define INTCICDISPR15 (INTC.ICDISPR15) +#define INTCICDISPR16 (INTC.ICDISPR16) +#define INTCICDICPR0 (INTC.ICDICPR0) +#define INTCICDICPR1 (INTC.ICDICPR1) +#define INTCICDICPR2 (INTC.ICDICPR2) +#define INTCICDICPR3 (INTC.ICDICPR3) +#define INTCICDICPR4 (INTC.ICDICPR4) +#define INTCICDICPR5 (INTC.ICDICPR5) +#define INTCICDICPR6 (INTC.ICDICPR6) +#define INTCICDICPR7 (INTC.ICDICPR7) +#define INTCICDICPR8 (INTC.ICDICPR8) +#define INTCICDICPR9 (INTC.ICDICPR9) +#define INTCICDICPR10 (INTC.ICDICPR10) +#define INTCICDICPR11 (INTC.ICDICPR11) +#define INTCICDICPR12 (INTC.ICDICPR12) +#define INTCICDICPR13 (INTC.ICDICPR13) +#define INTCICDICPR14 (INTC.ICDICPR14) +#define INTCICDICPR15 (INTC.ICDICPR15) +#define INTCICDICPR16 (INTC.ICDICPR16) +#define INTCICDABR0 (INTC.ICDABR0) +#define INTCICDABR1 (INTC.ICDABR1) +#define INTCICDABR2 (INTC.ICDABR2) +#define INTCICDABR3 (INTC.ICDABR3) +#define INTCICDABR4 (INTC.ICDABR4) +#define INTCICDABR5 (INTC.ICDABR5) +#define INTCICDABR6 (INTC.ICDABR6) +#define INTCICDABR7 (INTC.ICDABR7) +#define INTCICDABR8 (INTC.ICDABR8) +#define INTCICDABR9 (INTC.ICDABR9) +#define INTCICDABR10 (INTC.ICDABR10) +#define INTCICDABR11 (INTC.ICDABR11) +#define INTCICDABR12 (INTC.ICDABR12) +#define INTCICDABR13 (INTC.ICDABR13) +#define INTCICDABR14 (INTC.ICDABR14) +#define INTCICDABR15 (INTC.ICDABR15) +#define INTCICDABR16 (INTC.ICDABR16) +#define INTCICDIPR0 (INTC.ICDIPR0) +#define INTCICDIPR1 (INTC.ICDIPR1) +#define INTCICDIPR2 (INTC.ICDIPR2) +#define INTCICDIPR3 (INTC.ICDIPR3) +#define INTCICDIPR4 (INTC.ICDIPR4) +#define INTCICDIPR5 (INTC.ICDIPR5) +#define INTCICDIPR6 (INTC.ICDIPR6) +#define INTCICDIPR7 (INTC.ICDIPR7) +#define INTCICDIPR8 (INTC.ICDIPR8) +#define INTCICDIPR9 (INTC.ICDIPR9) +#define INTCICDIPR10 (INTC.ICDIPR10) +#define INTCICDIPR11 (INTC.ICDIPR11) +#define INTCICDIPR12 (INTC.ICDIPR12) +#define INTCICDIPR13 (INTC.ICDIPR13) +#define INTCICDIPR14 (INTC.ICDIPR14) +#define INTCICDIPR15 (INTC.ICDIPR15) +#define INTCICDIPR16 (INTC.ICDIPR16) +#define INTCICDIPR17 (INTC.ICDIPR17) +#define INTCICDIPR18 (INTC.ICDIPR18) +#define INTCICDIPR19 (INTC.ICDIPR19) +#define INTCICDIPR20 (INTC.ICDIPR20) +#define INTCICDIPR21 (INTC.ICDIPR21) +#define INTCICDIPR22 (INTC.ICDIPR22) +#define INTCICDIPR23 (INTC.ICDIPR23) +#define INTCICDIPR24 (INTC.ICDIPR24) +#define INTCICDIPR25 (INTC.ICDIPR25) +#define INTCICDIPR26 (INTC.ICDIPR26) +#define INTCICDIPR27 (INTC.ICDIPR27) +#define INTCICDIPR28 (INTC.ICDIPR28) +#define INTCICDIPR29 (INTC.ICDIPR29) +#define INTCICDIPR30 (INTC.ICDIPR30) +#define INTCICDIPR31 (INTC.ICDIPR31) +#define INTCICDIPR32 (INTC.ICDIPR32) +#define INTCICDIPR33 (INTC.ICDIPR33) +#define INTCICDIPR34 (INTC.ICDIPR34) +#define INTCICDIPR35 (INTC.ICDIPR35) +#define INTCICDIPR36 (INTC.ICDIPR36) +#define INTCICDIPR37 (INTC.ICDIPR37) +#define INTCICDIPR38 (INTC.ICDIPR38) +#define INTCICDIPR39 (INTC.ICDIPR39) +#define INTCICDIPR40 (INTC.ICDIPR40) +#define INTCICDIPR41 (INTC.ICDIPR41) +#define INTCICDIPR42 (INTC.ICDIPR42) +#define INTCICDIPR43 (INTC.ICDIPR43) +#define INTCICDIPR44 (INTC.ICDIPR44) +#define INTCICDIPR45 (INTC.ICDIPR45) +#define INTCICDIPR46 (INTC.ICDIPR46) +#define INTCICDIPR47 (INTC.ICDIPR47) +#define INTCICDIPR48 (INTC.ICDIPR48) +#define INTCICDIPR49 (INTC.ICDIPR49) +#define INTCICDIPR50 (INTC.ICDIPR50) +#define INTCICDIPR51 (INTC.ICDIPR51) +#define INTCICDIPR52 (INTC.ICDIPR52) +#define INTCICDIPR53 (INTC.ICDIPR53) +#define INTCICDIPR54 (INTC.ICDIPR54) +#define INTCICDIPR55 (INTC.ICDIPR55) +#define INTCICDIPR56 (INTC.ICDIPR56) +#define INTCICDIPR57 (INTC.ICDIPR57) +#define INTCICDIPR58 (INTC.ICDIPR58) +#define INTCICDIPR59 (INTC.ICDIPR59) +#define INTCICDIPR60 (INTC.ICDIPR60) +#define INTCICDIPR61 (INTC.ICDIPR61) +#define INTCICDIPR62 (INTC.ICDIPR62) +#define INTCICDIPR63 (INTC.ICDIPR63) +#define INTCICDIPR64 (INTC.ICDIPR64) +#define INTCICDIPR65 (INTC.ICDIPR65) +#define INTCICDIPR66 (INTC.ICDIPR66) +#define INTCICDIPR67 (INTC.ICDIPR67) +#define INTCICDIPR68 (INTC.ICDIPR68) +#define INTCICDIPR69 (INTC.ICDIPR69) +#define INTCICDIPR70 (INTC.ICDIPR70) +#define INTCICDIPR71 (INTC.ICDIPR71) +#define INTCICDIPR72 (INTC.ICDIPR72) +#define INTCICDIPR73 (INTC.ICDIPR73) +#define INTCICDIPR74 (INTC.ICDIPR74) +#define INTCICDIPR75 (INTC.ICDIPR75) +#define INTCICDIPR76 (INTC.ICDIPR76) +#define INTCICDIPR77 (INTC.ICDIPR77) +#define INTCICDIPR78 (INTC.ICDIPR78) +#define INTCICDIPR79 (INTC.ICDIPR79) +#define INTCICDIPR80 (INTC.ICDIPR80) +#define INTCICDIPR81 (INTC.ICDIPR81) +#define INTCICDIPR82 (INTC.ICDIPR82) +#define INTCICDIPR83 (INTC.ICDIPR83) +#define INTCICDIPR84 (INTC.ICDIPR84) +#define INTCICDIPR85 (INTC.ICDIPR85) +#define INTCICDIPR86 (INTC.ICDIPR86) +#define INTCICDIPR87 (INTC.ICDIPR87) +#define INTCICDIPR88 (INTC.ICDIPR88) +#define INTCICDIPR89 (INTC.ICDIPR89) +#define INTCICDIPR90 (INTC.ICDIPR90) +#define INTCICDIPR91 (INTC.ICDIPR91) +#define INTCICDIPR92 (INTC.ICDIPR92) +#define INTCICDIPR93 (INTC.ICDIPR93) +#define INTCICDIPR94 (INTC.ICDIPR94) +#define INTCICDIPR95 (INTC.ICDIPR95) +#define INTCICDIPR96 (INTC.ICDIPR96) +#define INTCICDIPR97 (INTC.ICDIPR97) +#define INTCICDIPR98 (INTC.ICDIPR98) +#define INTCICDIPR99 (INTC.ICDIPR99) +#define INTCICDIPR100 (INTC.ICDIPR100) +#define INTCICDIPR101 (INTC.ICDIPR101) +#define INTCICDIPR102 (INTC.ICDIPR102) +#define INTCICDIPR103 (INTC.ICDIPR103) +#define INTCICDIPR104 (INTC.ICDIPR104) +#define INTCICDIPR105 (INTC.ICDIPR105) +#define INTCICDIPR106 (INTC.ICDIPR106) +#define INTCICDIPR107 (INTC.ICDIPR107) +#define INTCICDIPR108 (INTC.ICDIPR108) +#define INTCICDIPR109 (INTC.ICDIPR109) +#define INTCICDIPR110 (INTC.ICDIPR110) +#define INTCICDIPR111 (INTC.ICDIPR111) +#define INTCICDIPR112 (INTC.ICDIPR112) +#define INTCICDIPR113 (INTC.ICDIPR113) +#define INTCICDIPR114 (INTC.ICDIPR114) +#define INTCICDIPR115 (INTC.ICDIPR115) +#define INTCICDIPR116 (INTC.ICDIPR116) +#define INTCICDIPR117 (INTC.ICDIPR117) +#define INTCICDIPR118 (INTC.ICDIPR118) +#define INTCICDIPR119 (INTC.ICDIPR119) +#define INTCICDIPR120 (INTC.ICDIPR120) +#define INTCICDIPR121 (INTC.ICDIPR121) +#define INTCICDIPR122 (INTC.ICDIPR122) +#define INTCICDIPR123 (INTC.ICDIPR123) +#define INTCICDIPR124 (INTC.ICDIPR124) +#define INTCICDIPR125 (INTC.ICDIPR125) +#define INTCICDIPR126 (INTC.ICDIPR126) +#define INTCICDIPR127 (INTC.ICDIPR127) +#define INTCICDIPR128 (INTC.ICDIPR128) +#define INTCICDIPR129 (INTC.ICDIPR129) +#define INTCICDIPR130 (INTC.ICDIPR130) +#define INTCICDIPR131 (INTC.ICDIPR131) +#define INTCICDIPR132 (INTC.ICDIPR132) +#define INTCICDIPR133 (INTC.ICDIPR133) +#define INTCICDIPR134 (INTC.ICDIPR134) +#define INTCICDIPTR0 (INTC.ICDIPTR0) +#define INTCICDIPTR1 (INTC.ICDIPTR1) +#define INTCICDIPTR2 (INTC.ICDIPTR2) +#define INTCICDIPTR3 (INTC.ICDIPTR3) +#define INTCICDIPTR4 (INTC.ICDIPTR4) +#define INTCICDIPTR5 (INTC.ICDIPTR5) +#define INTCICDIPTR6 (INTC.ICDIPTR6) +#define INTCICDIPTR7 (INTC.ICDIPTR7) +#define INTCICDIPTR8 (INTC.ICDIPTR8) +#define INTCICDIPTR9 (INTC.ICDIPTR9) +#define INTCICDIPTR10 (INTC.ICDIPTR10) +#define INTCICDIPTR11 (INTC.ICDIPTR11) +#define INTCICDIPTR12 (INTC.ICDIPTR12) +#define INTCICDIPTR13 (INTC.ICDIPTR13) +#define INTCICDIPTR14 (INTC.ICDIPTR14) +#define INTCICDIPTR15 (INTC.ICDIPTR15) +#define INTCICDIPTR16 (INTC.ICDIPTR16) +#define INTCICDIPTR17 (INTC.ICDIPTR17) +#define INTCICDIPTR18 (INTC.ICDIPTR18) +#define INTCICDIPTR19 (INTC.ICDIPTR19) +#define INTCICDIPTR20 (INTC.ICDIPTR20) +#define INTCICDIPTR21 (INTC.ICDIPTR21) +#define INTCICDIPTR22 (INTC.ICDIPTR22) +#define INTCICDIPTR23 (INTC.ICDIPTR23) +#define INTCICDIPTR24 (INTC.ICDIPTR24) +#define INTCICDIPTR25 (INTC.ICDIPTR25) +#define INTCICDIPTR26 (INTC.ICDIPTR26) +#define INTCICDIPTR27 (INTC.ICDIPTR27) +#define INTCICDIPTR28 (INTC.ICDIPTR28) +#define INTCICDIPTR29 (INTC.ICDIPTR29) +#define INTCICDIPTR30 (INTC.ICDIPTR30) +#define INTCICDIPTR31 (INTC.ICDIPTR31) +#define INTCICDIPTR32 (INTC.ICDIPTR32) +#define INTCICDIPTR33 (INTC.ICDIPTR33) +#define INTCICDIPTR34 (INTC.ICDIPTR34) +#define INTCICDIPTR35 (INTC.ICDIPTR35) +#define INTCICDIPTR36 (INTC.ICDIPTR36) +#define INTCICDIPTR37 (INTC.ICDIPTR37) +#define INTCICDIPTR38 (INTC.ICDIPTR38) +#define INTCICDIPTR39 (INTC.ICDIPTR39) +#define INTCICDIPTR40 (INTC.ICDIPTR40) +#define INTCICDIPTR41 (INTC.ICDIPTR41) +#define INTCICDIPTR42 (INTC.ICDIPTR42) +#define INTCICDIPTR43 (INTC.ICDIPTR43) +#define INTCICDIPTR44 (INTC.ICDIPTR44) +#define INTCICDIPTR45 (INTC.ICDIPTR45) +#define INTCICDIPTR46 (INTC.ICDIPTR46) +#define INTCICDIPTR47 (INTC.ICDIPTR47) +#define INTCICDIPTR48 (INTC.ICDIPTR48) +#define INTCICDIPTR49 (INTC.ICDIPTR49) +#define INTCICDIPTR50 (INTC.ICDIPTR50) +#define INTCICDIPTR51 (INTC.ICDIPTR51) +#define INTCICDIPTR52 (INTC.ICDIPTR52) +#define INTCICDIPTR53 (INTC.ICDIPTR53) +#define INTCICDIPTR54 (INTC.ICDIPTR54) +#define INTCICDIPTR55 (INTC.ICDIPTR55) +#define INTCICDIPTR56 (INTC.ICDIPTR56) +#define INTCICDIPTR57 (INTC.ICDIPTR57) +#define INTCICDIPTR58 (INTC.ICDIPTR58) +#define INTCICDIPTR59 (INTC.ICDIPTR59) +#define INTCICDIPTR60 (INTC.ICDIPTR60) +#define INTCICDIPTR61 (INTC.ICDIPTR61) +#define INTCICDIPTR62 (INTC.ICDIPTR62) +#define INTCICDIPTR63 (INTC.ICDIPTR63) +#define INTCICDIPTR64 (INTC.ICDIPTR64) +#define INTCICDIPTR65 (INTC.ICDIPTR65) +#define INTCICDIPTR66 (INTC.ICDIPTR66) +#define INTCICDIPTR67 (INTC.ICDIPTR67) +#define INTCICDIPTR68 (INTC.ICDIPTR68) +#define INTCICDIPTR69 (INTC.ICDIPTR69) +#define INTCICDIPTR70 (INTC.ICDIPTR70) +#define INTCICDIPTR71 (INTC.ICDIPTR71) +#define INTCICDIPTR72 (INTC.ICDIPTR72) +#define INTCICDIPTR73 (INTC.ICDIPTR73) +#define INTCICDIPTR74 (INTC.ICDIPTR74) +#define INTCICDIPTR75 (INTC.ICDIPTR75) +#define INTCICDIPTR76 (INTC.ICDIPTR76) +#define INTCICDIPTR77 (INTC.ICDIPTR77) +#define INTCICDIPTR78 (INTC.ICDIPTR78) +#define INTCICDIPTR79 (INTC.ICDIPTR79) +#define INTCICDIPTR80 (INTC.ICDIPTR80) +#define INTCICDIPTR81 (INTC.ICDIPTR81) +#define INTCICDIPTR82 (INTC.ICDIPTR82) +#define INTCICDIPTR83 (INTC.ICDIPTR83) +#define INTCICDIPTR84 (INTC.ICDIPTR84) +#define INTCICDIPTR85 (INTC.ICDIPTR85) +#define INTCICDIPTR86 (INTC.ICDIPTR86) +#define INTCICDIPTR87 (INTC.ICDIPTR87) +#define INTCICDIPTR88 (INTC.ICDIPTR88) +#define INTCICDIPTR89 (INTC.ICDIPTR89) +#define INTCICDIPTR90 (INTC.ICDIPTR90) +#define INTCICDIPTR91 (INTC.ICDIPTR91) +#define INTCICDIPTR92 (INTC.ICDIPTR92) +#define INTCICDIPTR93 (INTC.ICDIPTR93) +#define INTCICDIPTR94 (INTC.ICDIPTR94) +#define INTCICDIPTR95 (INTC.ICDIPTR95) +#define INTCICDIPTR96 (INTC.ICDIPTR96) +#define INTCICDIPTR97 (INTC.ICDIPTR97) +#define INTCICDIPTR98 (INTC.ICDIPTR98) +#define INTCICDIPTR99 (INTC.ICDIPTR99) +#define INTCICDIPTR100 (INTC.ICDIPTR100) +#define INTCICDIPTR101 (INTC.ICDIPTR101) +#define INTCICDIPTR102 (INTC.ICDIPTR102) +#define INTCICDIPTR103 (INTC.ICDIPTR103) +#define INTCICDIPTR104 (INTC.ICDIPTR104) +#define INTCICDIPTR105 (INTC.ICDIPTR105) +#define INTCICDIPTR106 (INTC.ICDIPTR106) +#define INTCICDIPTR107 (INTC.ICDIPTR107) +#define INTCICDIPTR108 (INTC.ICDIPTR108) +#define INTCICDIPTR109 (INTC.ICDIPTR109) +#define INTCICDIPTR110 (INTC.ICDIPTR110) +#define INTCICDIPTR111 (INTC.ICDIPTR111) +#define INTCICDIPTR112 (INTC.ICDIPTR112) +#define INTCICDIPTR113 (INTC.ICDIPTR113) +#define INTCICDIPTR114 (INTC.ICDIPTR114) +#define INTCICDIPTR115 (INTC.ICDIPTR115) +#define INTCICDIPTR116 (INTC.ICDIPTR116) +#define INTCICDIPTR117 (INTC.ICDIPTR117) +#define INTCICDIPTR118 (INTC.ICDIPTR118) +#define INTCICDIPTR119 (INTC.ICDIPTR119) +#define INTCICDIPTR120 (INTC.ICDIPTR120) +#define INTCICDIPTR121 (INTC.ICDIPTR121) +#define INTCICDIPTR122 (INTC.ICDIPTR122) +#define INTCICDIPTR123 (INTC.ICDIPTR123) +#define INTCICDIPTR124 (INTC.ICDIPTR124) +#define INTCICDIPTR125 (INTC.ICDIPTR125) +#define INTCICDIPTR126 (INTC.ICDIPTR126) +#define INTCICDIPTR127 (INTC.ICDIPTR127) +#define INTCICDIPTR128 (INTC.ICDIPTR128) +#define INTCICDIPTR129 (INTC.ICDIPTR129) +#define INTCICDIPTR130 (INTC.ICDIPTR130) +#define INTCICDIPTR131 (INTC.ICDIPTR131) +#define INTCICDIPTR132 (INTC.ICDIPTR132) +#define INTCICDIPTR133 (INTC.ICDIPTR133) +#define INTCICDIPTR134 (INTC.ICDIPTR134) +#define INTCICDICFR0 (INTC.ICDICFR0) +#define INTCICDICFR1 (INTC.ICDICFR1) +#define INTCICDICFR2 (INTC.ICDICFR2) +#define INTCICDICFR3 (INTC.ICDICFR3) +#define INTCICDICFR4 (INTC.ICDICFR4) +#define INTCICDICFR5 (INTC.ICDICFR5) +#define INTCICDICFR6 (INTC.ICDICFR6) +#define INTCICDICFR7 (INTC.ICDICFR7) +#define INTCICDICFR8 (INTC.ICDICFR8) +#define INTCICDICFR9 (INTC.ICDICFR9) +#define INTCICDICFR10 (INTC.ICDICFR10) +#define INTCICDICFR11 (INTC.ICDICFR11) +#define INTCICDICFR12 (INTC.ICDICFR12) +#define INTCICDICFR13 (INTC.ICDICFR13) +#define INTCICDICFR14 (INTC.ICDICFR14) +#define INTCICDICFR15 (INTC.ICDICFR15) +#define INTCICDICFR16 (INTC.ICDICFR16) +#define INTCICDICFR17 (INTC.ICDICFR17) +#define INTCICDICFR18 (INTC.ICDICFR18) +#define INTCICDICFR19 (INTC.ICDICFR19) +#define INTCICDICFR20 (INTC.ICDICFR20) +#define INTCICDICFR21 (INTC.ICDICFR21) +#define INTCICDICFR22 (INTC.ICDICFR22) +#define INTCICDICFR23 (INTC.ICDICFR23) +#define INTCICDICFR24 (INTC.ICDICFR24) +#define INTCICDICFR25 (INTC.ICDICFR25) +#define INTCICDICFR26 (INTC.ICDICFR26) +#define INTCICDICFR27 (INTC.ICDICFR27) +#define INTCICDICFR28 (INTC.ICDICFR28) +#define INTCICDICFR29 (INTC.ICDICFR29) +#define INTCICDICFR30 (INTC.ICDICFR30) +#define INTCICDICFR31 (INTC.ICDICFR31) +#define INTCICDICFR32 (INTC.ICDICFR32) +#define INTCICDICFR33 (INTC.ICDICFR33) +#define INTCPPI_STATUS (INTC.PPI_STATUS) +#define INTCSPI_STATUS0 (INTC.SPI_STATUS0) +#define INTCSPI_STATUS1 (INTC.SPI_STATUS1) +#define INTCSPI_STATUS2 (INTC.SPI_STATUS2) +#define INTCSPI_STATUS3 (INTC.SPI_STATUS3) +#define INTCSPI_STATUS4 (INTC.SPI_STATUS4) +#define INTCSPI_STATUS5 (INTC.SPI_STATUS5) +#define INTCSPI_STATUS6 (INTC.SPI_STATUS6) +#define INTCSPI_STATUS7 (INTC.SPI_STATUS7) +#define INTCSPI_STATUS8 (INTC.SPI_STATUS8) +#define INTCSPI_STATUS9 (INTC.SPI_STATUS9) +#define INTCSPI_STATUS10 (INTC.SPI_STATUS10) +#define INTCSPI_STATUS11 (INTC.SPI_STATUS11) +#define INTCSPI_STATUS12 (INTC.SPI_STATUS12) +#define INTCSPI_STATUS13 (INTC.SPI_STATUS13) +#define INTCSPI_STATUS14 (INTC.SPI_STATUS14) +#define INTCICDSGIR (INTC.ICDSGIR) +#define INTCICCICR (INTC.ICCICR) +#define INTCICCPMR (INTC.ICCPMR) +#define INTCICCBPR (INTC.ICCBPR) +#define INTCICCIAR (INTC.ICCIAR) +#define INTCICCEOIR (INTC.ICCEOIR) +#define INTCICCRPR (INTC.ICCRPR) +#define INTCICCHPIR (INTC.ICCHPIR) +#define INTCICCABPR (INTC.ICCABPR) +#define INTCICCIIDR (INTC.ICCIIDR) +#define INTCICR0 (INTC.ICR0) +#define INTCICR1 (INTC.ICR1) +#define INTCIRQRR (INTC.IRQRR) +#define INTCUSBSSCR0 (INTC.USBSSCR0) +#define INTCUSBSSCR1 (INTC.USBSSCR1) + +#define INTC_ICDISR0_COUNT (17) +#define INTC_ICDISER0_COUNT (17) +#define INTC_ICDICER0_COUNT (17) +#define INTC_ICDISPR0_COUNT (17) +#define INTC_ICDICPR0_COUNT (17) +#define INTC_ICDABR0_COUNT (17) +#define INTC_ICDIPR0_COUNT (135) +#define INTC_ICDIPTR0_COUNT (135) +#define INTC_ICDICFR0_COUNT (34) +#define INTC_SPI_STATUS0_COUNT (15) + + +typedef struct st_intc +{ + /* INTC */ + volatile uint32_t ICDDCR; /* ICDDCR */ + volatile uint32_t ICDICTR; /* ICDICTR */ + volatile uint32_t ICDIIDR; /* ICDIIDR */ + volatile uint8_t dummy193[116]; /* */ + +/* #define INTC_ICDISR0_COUNT (17) */ + volatile uint32_t ICDISR0; /* ICDISR0 */ + volatile uint32_t ICDISR1; /* ICDISR1 */ + volatile uint32_t ICDISR2; /* ICDISR2 */ + volatile uint32_t ICDISR3; /* ICDISR3 */ + volatile uint32_t ICDISR4; /* ICDISR4 */ + volatile uint32_t ICDISR5; /* ICDISR5 */ + volatile uint32_t ICDISR6; /* ICDISR6 */ + volatile uint32_t ICDISR7; /* ICDISR7 */ + volatile uint32_t ICDISR8; /* ICDISR8 */ + volatile uint32_t ICDISR9; /* ICDISR9 */ + volatile uint32_t ICDISR10; /* ICDISR10 */ + volatile uint32_t ICDISR11; /* ICDISR11 */ + volatile uint32_t ICDISR12; /* ICDISR12 */ + volatile uint32_t ICDISR13; /* ICDISR13 */ + volatile uint32_t ICDISR14; /* ICDISR14 */ + volatile uint32_t ICDISR15; /* ICDISR15 */ + volatile uint32_t ICDISR16; /* ICDISR16 */ + volatile uint8_t dummy194[60]; /* */ + +/* #define INTC_ICDISER0_COUNT (17) */ + volatile uint32_t ICDISER0; /* ICDISER0 */ + volatile uint32_t ICDISER1; /* ICDISER1 */ + volatile uint32_t ICDISER2; /* ICDISER2 */ + volatile uint32_t ICDISER3; /* ICDISER3 */ + volatile uint32_t ICDISER4; /* ICDISER4 */ + volatile uint32_t ICDISER5; /* ICDISER5 */ + volatile uint32_t ICDISER6; /* ICDISER6 */ + volatile uint32_t ICDISER7; /* ICDISER7 */ + volatile uint32_t ICDISER8; /* ICDISER8 */ + volatile uint32_t ICDISER9; /* ICDISER9 */ + volatile uint32_t ICDISER10; /* ICDISER10 */ + volatile uint32_t ICDISER11; /* ICDISER11 */ + volatile uint32_t ICDISER12; /* ICDISER12 */ + volatile uint32_t ICDISER13; /* ICDISER13 */ + volatile uint32_t ICDISER14; /* ICDISER14 */ + volatile uint32_t ICDISER15; /* ICDISER15 */ + volatile uint32_t ICDISER16; /* ICDISER16 */ + volatile uint8_t dummy195[60]; /* */ + +/* #define INTC_ICDICER0_COUNT (17) */ + volatile uint32_t ICDICER0; /* ICDICER0 */ + volatile uint32_t ICDICER1; /* ICDICER1 */ + volatile uint32_t ICDICER2; /* ICDICER2 */ + volatile uint32_t ICDICER3; /* ICDICER3 */ + volatile uint32_t ICDICER4; /* ICDICER4 */ + volatile uint32_t ICDICER5; /* ICDICER5 */ + volatile uint32_t ICDICER6; /* ICDICER6 */ + volatile uint32_t ICDICER7; /* ICDICER7 */ + volatile uint32_t ICDICER8; /* ICDICER8 */ + volatile uint32_t ICDICER9; /* ICDICER9 */ + volatile uint32_t ICDICER10; /* ICDICER10 */ + volatile uint32_t ICDICER11; /* ICDICER11 */ + volatile uint32_t ICDICER12; /* ICDICER12 */ + volatile uint32_t ICDICER13; /* ICDICER13 */ + volatile uint32_t ICDICER14; /* ICDICER14 */ + volatile uint32_t ICDICER15; /* ICDICER15 */ + volatile uint32_t ICDICER16; /* ICDICER16 */ + volatile uint8_t dummy196[60]; /* */ + +/* #define INTC_ICDISPR0_COUNT (17) */ + volatile uint32_t ICDISPR0; /* ICDISPR0 */ + volatile uint32_t ICDISPR1; /* ICDISPR1 */ + volatile uint32_t ICDISPR2; /* ICDISPR2 */ + volatile uint32_t ICDISPR3; /* ICDISPR3 */ + volatile uint32_t ICDISPR4; /* ICDISPR4 */ + volatile uint32_t ICDISPR5; /* ICDISPR5 */ + volatile uint32_t ICDISPR6; /* ICDISPR6 */ + volatile uint32_t ICDISPR7; /* ICDISPR7 */ + volatile uint32_t ICDISPR8; /* ICDISPR8 */ + volatile uint32_t ICDISPR9; /* ICDISPR9 */ + volatile uint32_t ICDISPR10; /* ICDISPR10 */ + volatile uint32_t ICDISPR11; /* ICDISPR11 */ + volatile uint32_t ICDISPR12; /* ICDISPR12 */ + volatile uint32_t ICDISPR13; /* ICDISPR13 */ + volatile uint32_t ICDISPR14; /* ICDISPR14 */ + volatile uint32_t ICDISPR15; /* ICDISPR15 */ + volatile uint32_t ICDISPR16; /* ICDISPR16 */ + volatile uint8_t dummy197[60]; /* */ + +/* #define INTC_ICDICPR0_COUNT (17) */ + volatile uint32_t ICDICPR0; /* ICDICPR0 */ + volatile uint32_t ICDICPR1; /* ICDICPR1 */ + volatile uint32_t ICDICPR2; /* ICDICPR2 */ + volatile uint32_t ICDICPR3; /* ICDICPR3 */ + volatile uint32_t ICDICPR4; /* ICDICPR4 */ + volatile uint32_t ICDICPR5; /* ICDICPR5 */ + volatile uint32_t ICDICPR6; /* ICDICPR6 */ + volatile uint32_t ICDICPR7; /* ICDICPR7 */ + volatile uint32_t ICDICPR8; /* ICDICPR8 */ + volatile uint32_t ICDICPR9; /* ICDICPR9 */ + volatile uint32_t ICDICPR10; /* ICDICPR10 */ + volatile uint32_t ICDICPR11; /* ICDICPR11 */ + volatile uint32_t ICDICPR12; /* ICDICPR12 */ + volatile uint32_t ICDICPR13; /* ICDICPR13 */ + volatile uint32_t ICDICPR14; /* ICDICPR14 */ + volatile uint32_t ICDICPR15; /* ICDICPR15 */ + volatile uint32_t ICDICPR16; /* ICDICPR16 */ + volatile uint8_t dummy198[60]; /* */ + +/* #define INTC_ICDABR0_COUNT (17) */ + volatile uint32_t ICDABR0; /* ICDABR0 */ + volatile uint32_t ICDABR1; /* ICDABR1 */ + volatile uint32_t ICDABR2; /* ICDABR2 */ + volatile uint32_t ICDABR3; /* ICDABR3 */ + volatile uint32_t ICDABR4; /* ICDABR4 */ + volatile uint32_t ICDABR5; /* ICDABR5 */ + volatile uint32_t ICDABR6; /* ICDABR6 */ + volatile uint32_t ICDABR7; /* ICDABR7 */ + volatile uint32_t ICDABR8; /* ICDABR8 */ + volatile uint32_t ICDABR9; /* ICDABR9 */ + volatile uint32_t ICDABR10; /* ICDABR10 */ + volatile uint32_t ICDABR11; /* ICDABR11 */ + volatile uint32_t ICDABR12; /* ICDABR12 */ + volatile uint32_t ICDABR13; /* ICDABR13 */ + volatile uint32_t ICDABR14; /* ICDABR14 */ + volatile uint32_t ICDABR15; /* ICDABR15 */ + volatile uint32_t ICDABR16; /* ICDABR16 */ + volatile uint8_t dummy199[188]; /* */ + +/* #define INTC_ICDIPR0_COUNT (135) */ + volatile uint32_t ICDIPR0; /* ICDIPR0 */ + volatile uint32_t ICDIPR1; /* ICDIPR1 */ + volatile uint32_t ICDIPR2; /* ICDIPR2 */ + volatile uint32_t ICDIPR3; /* ICDIPR3 */ + volatile uint32_t ICDIPR4; /* ICDIPR4 */ + volatile uint32_t ICDIPR5; /* ICDIPR5 */ + volatile uint32_t ICDIPR6; /* ICDIPR6 */ + volatile uint32_t ICDIPR7; /* ICDIPR7 */ + volatile uint32_t ICDIPR8; /* ICDIPR8 */ + volatile uint32_t ICDIPR9; /* ICDIPR9 */ + volatile uint32_t ICDIPR10; /* ICDIPR10 */ + volatile uint32_t ICDIPR11; /* ICDIPR11 */ + volatile uint32_t ICDIPR12; /* ICDIPR12 */ + volatile uint32_t ICDIPR13; /* ICDIPR13 */ + volatile uint32_t ICDIPR14; /* ICDIPR14 */ + volatile uint32_t ICDIPR15; /* ICDIPR15 */ + volatile uint32_t ICDIPR16; /* ICDIPR16 */ + volatile uint32_t ICDIPR17; /* ICDIPR17 */ + volatile uint32_t ICDIPR18; /* ICDIPR18 */ + volatile uint32_t ICDIPR19; /* ICDIPR19 */ + volatile uint32_t ICDIPR20; /* ICDIPR20 */ + volatile uint32_t ICDIPR21; /* ICDIPR21 */ + volatile uint32_t ICDIPR22; /* ICDIPR22 */ + volatile uint32_t ICDIPR23; /* ICDIPR23 */ + volatile uint32_t ICDIPR24; /* ICDIPR24 */ + volatile uint32_t ICDIPR25; /* ICDIPR25 */ + volatile uint32_t ICDIPR26; /* ICDIPR26 */ + volatile uint32_t ICDIPR27; /* ICDIPR27 */ + volatile uint32_t ICDIPR28; /* ICDIPR28 */ + volatile uint32_t ICDIPR29; /* ICDIPR29 */ + volatile uint32_t ICDIPR30; /* ICDIPR30 */ + volatile uint32_t ICDIPR31; /* ICDIPR31 */ + volatile uint32_t ICDIPR32; /* ICDIPR32 */ + volatile uint32_t ICDIPR33; /* ICDIPR33 */ + volatile uint32_t ICDIPR34; /* ICDIPR34 */ + volatile uint32_t ICDIPR35; /* ICDIPR35 */ + volatile uint32_t ICDIPR36; /* ICDIPR36 */ + volatile uint32_t ICDIPR37; /* ICDIPR37 */ + volatile uint32_t ICDIPR38; /* ICDIPR38 */ + volatile uint32_t ICDIPR39; /* ICDIPR39 */ + volatile uint32_t ICDIPR40; /* ICDIPR40 */ + volatile uint32_t ICDIPR41; /* ICDIPR41 */ + volatile uint32_t ICDIPR42; /* ICDIPR42 */ + volatile uint32_t ICDIPR43; /* ICDIPR43 */ + volatile uint32_t ICDIPR44; /* ICDIPR44 */ + volatile uint32_t ICDIPR45; /* ICDIPR45 */ + volatile uint32_t ICDIPR46; /* ICDIPR46 */ + volatile uint32_t ICDIPR47; /* ICDIPR47 */ + volatile uint32_t ICDIPR48; /* ICDIPR48 */ + volatile uint32_t ICDIPR49; /* ICDIPR49 */ + volatile uint32_t ICDIPR50; /* ICDIPR50 */ + volatile uint32_t ICDIPR51; /* ICDIPR51 */ + volatile uint32_t ICDIPR52; /* ICDIPR52 */ + volatile uint32_t ICDIPR53; /* ICDIPR53 */ + volatile uint32_t ICDIPR54; /* ICDIPR54 */ + volatile uint32_t ICDIPR55; /* ICDIPR55 */ + volatile uint32_t ICDIPR56; /* ICDIPR56 */ + volatile uint32_t ICDIPR57; /* ICDIPR57 */ + volatile uint32_t ICDIPR58; /* ICDIPR58 */ + volatile uint32_t ICDIPR59; /* ICDIPR59 */ + volatile uint32_t ICDIPR60; /* ICDIPR60 */ + volatile uint32_t ICDIPR61; /* ICDIPR61 */ + volatile uint32_t ICDIPR62; /* ICDIPR62 */ + volatile uint32_t ICDIPR63; /* ICDIPR63 */ + volatile uint32_t ICDIPR64; /* ICDIPR64 */ + volatile uint32_t ICDIPR65; /* ICDIPR65 */ + volatile uint32_t ICDIPR66; /* ICDIPR66 */ + volatile uint32_t ICDIPR67; /* ICDIPR67 */ + volatile uint32_t ICDIPR68; /* ICDIPR68 */ + volatile uint32_t ICDIPR69; /* ICDIPR69 */ + volatile uint32_t ICDIPR70; /* ICDIPR70 */ + volatile uint32_t ICDIPR71; /* ICDIPR71 */ + volatile uint32_t ICDIPR72; /* ICDIPR72 */ + volatile uint32_t ICDIPR73; /* ICDIPR73 */ + volatile uint32_t ICDIPR74; /* ICDIPR74 */ + volatile uint32_t ICDIPR75; /* ICDIPR75 */ + volatile uint32_t ICDIPR76; /* ICDIPR76 */ + volatile uint32_t ICDIPR77; /* ICDIPR77 */ + volatile uint32_t ICDIPR78; /* ICDIPR78 */ + volatile uint32_t ICDIPR79; /* ICDIPR79 */ + volatile uint32_t ICDIPR80; /* ICDIPR80 */ + volatile uint32_t ICDIPR81; /* ICDIPR81 */ + volatile uint32_t ICDIPR82; /* ICDIPR82 */ + volatile uint32_t ICDIPR83; /* ICDIPR83 */ + volatile uint32_t ICDIPR84; /* ICDIPR84 */ + volatile uint32_t ICDIPR85; /* ICDIPR85 */ + volatile uint32_t ICDIPR86; /* ICDIPR86 */ + volatile uint32_t ICDIPR87; /* ICDIPR87 */ + volatile uint32_t ICDIPR88; /* ICDIPR88 */ + volatile uint32_t ICDIPR89; /* ICDIPR89 */ + volatile uint32_t ICDIPR90; /* ICDIPR90 */ + volatile uint32_t ICDIPR91; /* ICDIPR91 */ + volatile uint32_t ICDIPR92; /* ICDIPR92 */ + volatile uint32_t ICDIPR93; /* ICDIPR93 */ + volatile uint32_t ICDIPR94; /* ICDIPR94 */ + volatile uint32_t ICDIPR95; /* ICDIPR95 */ + volatile uint32_t ICDIPR96; /* ICDIPR96 */ + volatile uint32_t ICDIPR97; /* ICDIPR97 */ + volatile uint32_t ICDIPR98; /* ICDIPR98 */ + volatile uint32_t ICDIPR99; /* ICDIPR99 */ + volatile uint32_t ICDIPR100; /* ICDIPR100 */ + volatile uint32_t ICDIPR101; /* ICDIPR101 */ + volatile uint32_t ICDIPR102; /* ICDIPR102 */ + volatile uint32_t ICDIPR103; /* ICDIPR103 */ + volatile uint32_t ICDIPR104; /* ICDIPR104 */ + volatile uint32_t ICDIPR105; /* ICDIPR105 */ + volatile uint32_t ICDIPR106; /* ICDIPR106 */ + volatile uint32_t ICDIPR107; /* ICDIPR107 */ + volatile uint32_t ICDIPR108; /* ICDIPR108 */ + volatile uint32_t ICDIPR109; /* ICDIPR109 */ + volatile uint32_t ICDIPR110; /* ICDIPR110 */ + volatile uint32_t ICDIPR111; /* ICDIPR111 */ + volatile uint32_t ICDIPR112; /* ICDIPR112 */ + volatile uint32_t ICDIPR113; /* ICDIPR113 */ + volatile uint32_t ICDIPR114; /* ICDIPR114 */ + volatile uint32_t ICDIPR115; /* ICDIPR115 */ + volatile uint32_t ICDIPR116; /* ICDIPR116 */ + volatile uint32_t ICDIPR117; /* ICDIPR117 */ + volatile uint32_t ICDIPR118; /* ICDIPR118 */ + volatile uint32_t ICDIPR119; /* ICDIPR119 */ + volatile uint32_t ICDIPR120; /* ICDIPR120 */ + volatile uint32_t ICDIPR121; /* ICDIPR121 */ + volatile uint32_t ICDIPR122; /* ICDIPR122 */ + volatile uint32_t ICDIPR123; /* ICDIPR123 */ + volatile uint32_t ICDIPR124; /* ICDIPR124 */ + volatile uint32_t ICDIPR125; /* ICDIPR125 */ + volatile uint32_t ICDIPR126; /* ICDIPR126 */ + volatile uint32_t ICDIPR127; /* ICDIPR127 */ + volatile uint32_t ICDIPR128; /* ICDIPR128 */ + volatile uint32_t ICDIPR129; /* ICDIPR129 */ + volatile uint32_t ICDIPR130; /* ICDIPR130 */ + volatile uint32_t ICDIPR131; /* ICDIPR131 */ + volatile uint32_t ICDIPR132; /* ICDIPR132 */ + volatile uint32_t ICDIPR133; /* ICDIPR133 */ + volatile uint32_t ICDIPR134; /* ICDIPR134 */ + volatile uint8_t dummy200[484]; /* */ + +/* #define INTC_ICDIPTR0_COUNT (135) */ + volatile uint32_t ICDIPTR0; /* ICDIPTR0 */ + volatile uint32_t ICDIPTR1; /* ICDIPTR1 */ + volatile uint32_t ICDIPTR2; /* ICDIPTR2 */ + volatile uint32_t ICDIPTR3; /* ICDIPTR3 */ + volatile uint32_t ICDIPTR4; /* ICDIPTR4 */ + volatile uint32_t ICDIPTR5; /* ICDIPTR5 */ + volatile uint32_t ICDIPTR6; /* ICDIPTR6 */ + volatile uint32_t ICDIPTR7; /* ICDIPTR7 */ + volatile uint32_t ICDIPTR8; /* ICDIPTR8 */ + volatile uint32_t ICDIPTR9; /* ICDIPTR9 */ + volatile uint32_t ICDIPTR10; /* ICDIPTR10 */ + volatile uint32_t ICDIPTR11; /* ICDIPTR11 */ + volatile uint32_t ICDIPTR12; /* ICDIPTR12 */ + volatile uint32_t ICDIPTR13; /* ICDIPTR13 */ + volatile uint32_t ICDIPTR14; /* ICDIPTR14 */ + volatile uint32_t ICDIPTR15; /* ICDIPTR15 */ + volatile uint32_t ICDIPTR16; /* ICDIPTR16 */ + volatile uint32_t ICDIPTR17; /* ICDIPTR17 */ + volatile uint32_t ICDIPTR18; /* ICDIPTR18 */ + volatile uint32_t ICDIPTR19; /* ICDIPTR19 */ + volatile uint32_t ICDIPTR20; /* ICDIPTR20 */ + volatile uint32_t ICDIPTR21; /* ICDIPTR21 */ + volatile uint32_t ICDIPTR22; /* ICDIPTR22 */ + volatile uint32_t ICDIPTR23; /* ICDIPTR23 */ + volatile uint32_t ICDIPTR24; /* ICDIPTR24 */ + volatile uint32_t ICDIPTR25; /* ICDIPTR25 */ + volatile uint32_t ICDIPTR26; /* ICDIPTR26 */ + volatile uint32_t ICDIPTR27; /* ICDIPTR27 */ + volatile uint32_t ICDIPTR28; /* ICDIPTR28 */ + volatile uint32_t ICDIPTR29; /* ICDIPTR29 */ + volatile uint32_t ICDIPTR30; /* ICDIPTR30 */ + volatile uint32_t ICDIPTR31; /* ICDIPTR31 */ + volatile uint32_t ICDIPTR32; /* ICDIPTR32 */ + volatile uint32_t ICDIPTR33; /* ICDIPTR33 */ + volatile uint32_t ICDIPTR34; /* ICDIPTR34 */ + volatile uint32_t ICDIPTR35; /* ICDIPTR35 */ + volatile uint32_t ICDIPTR36; /* ICDIPTR36 */ + volatile uint32_t ICDIPTR37; /* ICDIPTR37 */ + volatile uint32_t ICDIPTR38; /* ICDIPTR38 */ + volatile uint32_t ICDIPTR39; /* ICDIPTR39 */ + volatile uint32_t ICDIPTR40; /* ICDIPTR40 */ + volatile uint32_t ICDIPTR41; /* ICDIPTR41 */ + volatile uint32_t ICDIPTR42; /* ICDIPTR42 */ + volatile uint32_t ICDIPTR43; /* ICDIPTR43 */ + volatile uint32_t ICDIPTR44; /* ICDIPTR44 */ + volatile uint32_t ICDIPTR45; /* ICDIPTR45 */ + volatile uint32_t ICDIPTR46; /* ICDIPTR46 */ + volatile uint32_t ICDIPTR47; /* ICDIPTR47 */ + volatile uint32_t ICDIPTR48; /* ICDIPTR48 */ + volatile uint32_t ICDIPTR49; /* ICDIPTR49 */ + volatile uint32_t ICDIPTR50; /* ICDIPTR50 */ + volatile uint32_t ICDIPTR51; /* ICDIPTR51 */ + volatile uint32_t ICDIPTR52; /* ICDIPTR52 */ + volatile uint32_t ICDIPTR53; /* ICDIPTR53 */ + volatile uint32_t ICDIPTR54; /* ICDIPTR54 */ + volatile uint32_t ICDIPTR55; /* ICDIPTR55 */ + volatile uint32_t ICDIPTR56; /* ICDIPTR56 */ + volatile uint32_t ICDIPTR57; /* ICDIPTR57 */ + volatile uint32_t ICDIPTR58; /* ICDIPTR58 */ + volatile uint32_t ICDIPTR59; /* ICDIPTR59 */ + volatile uint32_t ICDIPTR60; /* ICDIPTR60 */ + volatile uint32_t ICDIPTR61; /* ICDIPTR61 */ + volatile uint32_t ICDIPTR62; /* ICDIPTR62 */ + volatile uint32_t ICDIPTR63; /* ICDIPTR63 */ + volatile uint32_t ICDIPTR64; /* ICDIPTR64 */ + volatile uint32_t ICDIPTR65; /* ICDIPTR65 */ + volatile uint32_t ICDIPTR66; /* ICDIPTR66 */ + volatile uint32_t ICDIPTR67; /* ICDIPTR67 */ + volatile uint32_t ICDIPTR68; /* ICDIPTR68 */ + volatile uint32_t ICDIPTR69; /* ICDIPTR69 */ + volatile uint32_t ICDIPTR70; /* ICDIPTR70 */ + volatile uint32_t ICDIPTR71; /* ICDIPTR71 */ + volatile uint32_t ICDIPTR72; /* ICDIPTR72 */ + volatile uint32_t ICDIPTR73; /* ICDIPTR73 */ + volatile uint32_t ICDIPTR74; /* ICDIPTR74 */ + volatile uint32_t ICDIPTR75; /* ICDIPTR75 */ + volatile uint32_t ICDIPTR76; /* ICDIPTR76 */ + volatile uint32_t ICDIPTR77; /* ICDIPTR77 */ + volatile uint32_t ICDIPTR78; /* ICDIPTR78 */ + volatile uint32_t ICDIPTR79; /* ICDIPTR79 */ + volatile uint32_t ICDIPTR80; /* ICDIPTR80 */ + volatile uint32_t ICDIPTR81; /* ICDIPTR81 */ + volatile uint32_t ICDIPTR82; /* ICDIPTR82 */ + volatile uint32_t ICDIPTR83; /* ICDIPTR83 */ + volatile uint32_t ICDIPTR84; /* ICDIPTR84 */ + volatile uint32_t ICDIPTR85; /* ICDIPTR85 */ + volatile uint32_t ICDIPTR86; /* ICDIPTR86 */ + volatile uint32_t ICDIPTR87; /* ICDIPTR87 */ + volatile uint32_t ICDIPTR88; /* ICDIPTR88 */ + volatile uint32_t ICDIPTR89; /* ICDIPTR89 */ + volatile uint32_t ICDIPTR90; /* ICDIPTR90 */ + volatile uint32_t ICDIPTR91; /* ICDIPTR91 */ + volatile uint32_t ICDIPTR92; /* ICDIPTR92 */ + volatile uint32_t ICDIPTR93; /* ICDIPTR93 */ + volatile uint32_t ICDIPTR94; /* ICDIPTR94 */ + volatile uint32_t ICDIPTR95; /* ICDIPTR95 */ + volatile uint32_t ICDIPTR96; /* ICDIPTR96 */ + volatile uint32_t ICDIPTR97; /* ICDIPTR97 */ + volatile uint32_t ICDIPTR98; /* ICDIPTR98 */ + volatile uint32_t ICDIPTR99; /* ICDIPTR99 */ + volatile uint32_t ICDIPTR100; /* ICDIPTR100 */ + volatile uint32_t ICDIPTR101; /* ICDIPTR101 */ + volatile uint32_t ICDIPTR102; /* ICDIPTR102 */ + volatile uint32_t ICDIPTR103; /* ICDIPTR103 */ + volatile uint32_t ICDIPTR104; /* ICDIPTR104 */ + volatile uint32_t ICDIPTR105; /* ICDIPTR105 */ + volatile uint32_t ICDIPTR106; /* ICDIPTR106 */ + volatile uint32_t ICDIPTR107; /* ICDIPTR107 */ + volatile uint32_t ICDIPTR108; /* ICDIPTR108 */ + volatile uint32_t ICDIPTR109; /* ICDIPTR109 */ + volatile uint32_t ICDIPTR110; /* ICDIPTR110 */ + volatile uint32_t ICDIPTR111; /* ICDIPTR111 */ + volatile uint32_t ICDIPTR112; /* ICDIPTR112 */ + volatile uint32_t ICDIPTR113; /* ICDIPTR113 */ + volatile uint32_t ICDIPTR114; /* ICDIPTR114 */ + volatile uint32_t ICDIPTR115; /* ICDIPTR115 */ + volatile uint32_t ICDIPTR116; /* ICDIPTR116 */ + volatile uint32_t ICDIPTR117; /* ICDIPTR117 */ + volatile uint32_t ICDIPTR118; /* ICDIPTR118 */ + volatile uint32_t ICDIPTR119; /* ICDIPTR119 */ + volatile uint32_t ICDIPTR120; /* ICDIPTR120 */ + volatile uint32_t ICDIPTR121; /* ICDIPTR121 */ + volatile uint32_t ICDIPTR122; /* ICDIPTR122 */ + volatile uint32_t ICDIPTR123; /* ICDIPTR123 */ + volatile uint32_t ICDIPTR124; /* ICDIPTR124 */ + volatile uint32_t ICDIPTR125; /* ICDIPTR125 */ + volatile uint32_t ICDIPTR126; /* ICDIPTR126 */ + volatile uint32_t ICDIPTR127; /* ICDIPTR127 */ + volatile uint32_t ICDIPTR128; /* ICDIPTR128 */ + volatile uint32_t ICDIPTR129; /* ICDIPTR129 */ + volatile uint32_t ICDIPTR130; /* ICDIPTR130 */ + volatile uint32_t ICDIPTR131; /* ICDIPTR131 */ + volatile uint32_t ICDIPTR132; /* ICDIPTR132 */ + volatile uint32_t ICDIPTR133; /* ICDIPTR133 */ + volatile uint32_t ICDIPTR134; /* ICDIPTR134 */ + volatile uint8_t dummy201[484]; /* */ + +/* #define INTC_ICDICFR0_COUNT (34) */ + volatile uint32_t ICDICFR0; /* ICDICFR0 */ + volatile uint32_t ICDICFR1; /* ICDICFR1 */ + volatile uint32_t ICDICFR2; /* ICDICFR2 */ + volatile uint32_t ICDICFR3; /* ICDICFR3 */ + volatile uint32_t ICDICFR4; /* ICDICFR4 */ + volatile uint32_t ICDICFR5; /* ICDICFR5 */ + volatile uint32_t ICDICFR6; /* ICDICFR6 */ + volatile uint32_t ICDICFR7; /* ICDICFR7 */ + volatile uint32_t ICDICFR8; /* ICDICFR8 */ + volatile uint32_t ICDICFR9; /* ICDICFR9 */ + volatile uint32_t ICDICFR10; /* ICDICFR10 */ + volatile uint32_t ICDICFR11; /* ICDICFR11 */ + volatile uint32_t ICDICFR12; /* ICDICFR12 */ + volatile uint32_t ICDICFR13; /* ICDICFR13 */ + volatile uint32_t ICDICFR14; /* ICDICFR14 */ + volatile uint32_t ICDICFR15; /* ICDICFR15 */ + volatile uint32_t ICDICFR16; /* ICDICFR16 */ + volatile uint32_t ICDICFR17; /* ICDICFR17 */ + volatile uint32_t ICDICFR18; /* ICDICFR18 */ + volatile uint32_t ICDICFR19; /* ICDICFR19 */ + volatile uint32_t ICDICFR20; /* ICDICFR20 */ + volatile uint32_t ICDICFR21; /* ICDICFR21 */ + volatile uint32_t ICDICFR22; /* ICDICFR22 */ + volatile uint32_t ICDICFR23; /* ICDICFR23 */ + volatile uint32_t ICDICFR24; /* ICDICFR24 */ + volatile uint32_t ICDICFR25; /* ICDICFR25 */ + volatile uint32_t ICDICFR26; /* ICDICFR26 */ + volatile uint32_t ICDICFR27; /* ICDICFR27 */ + volatile uint32_t ICDICFR28; /* ICDICFR28 */ + volatile uint32_t ICDICFR29; /* ICDICFR29 */ + volatile uint32_t ICDICFR30; /* ICDICFR30 */ + volatile uint32_t ICDICFR31; /* ICDICFR31 */ + volatile uint32_t ICDICFR32; /* ICDICFR32 */ + volatile uint32_t ICDICFR33; /* ICDICFR33 */ + volatile uint8_t dummy202[120]; /* */ + volatile uint32_t PPI_STATUS; /* PPI_STATUS */ + +/* #define INTC_SPI_STATUS0_COUNT (15) */ + volatile uint32_t SPI_STATUS0; /* SPI_STATUS0 */ + volatile uint32_t SPI_STATUS1; /* SPI_STATUS1 */ + volatile uint32_t SPI_STATUS2; /* SPI_STATUS2 */ + volatile uint32_t SPI_STATUS3; /* SPI_STATUS3 */ + volatile uint32_t SPI_STATUS4; /* SPI_STATUS4 */ + volatile uint32_t SPI_STATUS5; /* SPI_STATUS5 */ + volatile uint32_t SPI_STATUS6; /* SPI_STATUS6 */ + volatile uint32_t SPI_STATUS7; /* SPI_STATUS7 */ + volatile uint32_t SPI_STATUS8; /* SPI_STATUS8 */ + volatile uint32_t SPI_STATUS9; /* SPI_STATUS9 */ + volatile uint32_t SPI_STATUS10; /* SPI_STATUS10 */ + volatile uint32_t SPI_STATUS11; /* SPI_STATUS11 */ + volatile uint32_t SPI_STATUS12; /* SPI_STATUS12 */ + volatile uint32_t SPI_STATUS13; /* SPI_STATUS13 */ + volatile uint32_t SPI_STATUS14; /* SPI_STATUS14 */ + volatile uint8_t dummy203[448]; /* */ + volatile uint32_t ICDSGIR; /* ICDSGIR */ + volatile uint8_t dummy204[252]; /* */ + volatile uint32_t ICCICR; /* ICCICR */ + volatile uint32_t ICCPMR; /* ICCPMR */ + volatile uint32_t ICCBPR; /* ICCBPR */ + volatile uint32_t ICCIAR; /* ICCIAR */ + volatile uint32_t ICCEOIR; /* ICCEOIR */ + volatile uint32_t ICCRPR; /* ICCRPR */ + volatile uint32_t ICCHPIR; /* ICCHPIR */ + volatile uint32_t ICCABPR; /* ICCABPR */ + volatile uint8_t dummy205[220]; /* */ + volatile uint32_t ICCIIDR; /* ICCIIDR */ + volatile uint8_t dummy206[350148352]; /* */ + volatile uint16_t ICR0; /* ICR0 */ + volatile uint16_t ICR1; /* ICR1 */ + volatile uint16_t IRQRR; /* IRQRR */ + volatile uint8_t dummy207[4]; /* */ + volatile uint16_t USBSSCR0; /* USBSSCR0 */ + volatile uint16_t USBSSCR1; /* USBSSCR1 */ +} r_io_intc_t; + + +/* <-SEC M1.10.1 */ +/* <-MISRA 18.4 */ /* <-SEC M1.6.2 */ +/* <-QAC 0857 */ +/* <-QAC 0639 */ +#endif diff --git a/targets/TARGET_RENESAS/TARGET_RZ_A1XX/TARGET_GR_LYCHEE/device/inc/iodefines/iodefine_typedef.h b/targets/TARGET_RENESAS/TARGET_RZ_A1XX/TARGET_GR_LYCHEE/device/inc/iodefines/iodefine_typedef.h new file mode 100644 index 0000000..96211f6 --- /dev/null +++ b/targets/TARGET_RENESAS/TARGET_RZ_A1XX/TARGET_GR_LYCHEE/device/inc/iodefines/iodefine_typedef.h @@ -0,0 +1,121 @@ +/******************************************************************************* +* DISCLAIMER +* This software is supplied by Renesas Electronics Corporation and is only +* intended for use with Renesas products. No other uses are authorized. This +* software is owned by Renesas Electronics Corporation and is protected under +* all applicable laws, including copyright laws. +* THIS SOFTWARE IS PROVIDED "AS IS" AND RENESAS MAKES NO WARRANTIES REGARDING +* THIS SOFTWARE, WHETHER EXPRESS, IMPLIED OR STATUTORY, INCLUDING BUT NOT +* LIMITED TO WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE +* AND NON-INFRINGEMENT. ALL SUCH WARRANTIES ARE EXPRESSLY DISCLAIMED. +* TO THE MAXIMUM EXTENT PERMITTED NOT PROHIBITED BY LAW, NEITHER RENESAS +* ELECTRONICS CORPORATION NOR ANY OF ITS AFFILIATED COMPANIES SHALL BE LIABLE +* FOR ANY DIRECT, INDIRECT, SPECIAL, INCIDENTAL OR CONSEQUENTIAL DAMAGES FOR +* ANY REASON RELATED TO THIS SOFTWARE, EVEN IF RENESAS OR ITS AFFILIATES HAVE +* BEEN ADVISED OF THE POSSIBILITY OF SUCH DAMAGES. +* Renesas reserves the right, without notice, to make changes to this software +* and to discontinue the availability of this software. By using this software, +* you agree to the additional terms and conditions found by accessing the +* following link: +* http://www.renesas.com/disclaimer* +* Copyright (C) 2013-2016 Renesas Electronics Corporation. All rights reserved. +*******************************************************************************/ +/******************************************************************************* +* File Name : iodefine_typedef.h +* $Rev: $ +* $Date:: $ +* Description : Definition of I/O Register for RZ/A1LU (V3.00l) +******************************************************************************/ +#ifndef IODEFINE_TYPEDEF_H +#define IODEFINE_TYPEDEF_H +/* ->QAC 0639 : Over 127 members (C90) */ +/* ->QAC 0857 : Over 1024 #define (C90) */ +/* ->MISRA 18.4 : Pack unpack union */ /* ->SEC M1.6.2 */ +/* ->SEC M1.10.1 : Not magic number */ + +/* Shared types and macros for iodefine.h */ + +/*********************************************************************** +* Macro: IODEFINE_H_VERSION +************************************************************************/ +#define IODEFINE_H_VERSION (300) + + +/*********************************************************************** +* Enum: iodefine_byte_select_t +* +* R_IO_L - Low 16bit or Low 8 bit +* R_IO_H - High 16bit or Low 8 bit +* R_IO_LL - Low 8 bit +* R_IO_LH - Middle Low 8 bit +* R_IO_HL - Middle High 8 bit +* R_IO_HH - High 8 bit +************************************************************************/ +typedef enum iodefine_byte_select_t +{ + R_IO_L = 0, R_IO_H = 1, + R_IO_LL= 0, R_IO_LH = 1, R_IO_HL = 2, R_IO_HH = 3 +#if(1) /* mbed */ + , + L = 0, H = 1, + LL= 0, LH = 1, HL = 2, HH = 3 +#endif +} iodefine_byte_select_t; + + +/*********************************************************************** +* Type: iodefine_reg32_t +* 32/16/8 bit access register +* +* - Padding : sizeof(iodefine_reg32_t) == 4 +* - Alignment(Offset) : &UINT32==0, &UINT16[0]==0, &UINT16[1]==2 +* &UINT8[0]==0, &UINT8[1]==1, &UINT8[2]==2, &UINT8[3]==3 +* - Endian : Independent (Same as CPU endian as register endian) +* - Bit-Order : Independent +************************************************************************/ +typedef union iodefine_reg32_t +{ + volatile uint32_t UINT32; /* 32-bit Access */ + volatile uint16_t UINT16[2]; /* 16-bit Access */ + volatile uint8_t UINT8[4]; /* 8-bit Access */ +} iodefine_reg32_t; + + +/*********************************************************************** +* Type: iodefine_reg32_16_t +* 32/16 bit access register +* +* - Padding : sizeof(iodefine_reg32_16_t) == 4 +* - Alignment(Offset) : &UINT32==0, &UINT16[0]==0, &UINT16[1]==2 +* - Endian : Independent (Same as CPU endian as register endian) +* - Bit-Order : Independent +************************************************************************/ +typedef union iodefine_reg32_16_t +{ + volatile uint32_t UINT32; /* 32-bit Access */ + volatile uint16_t UINT16[2]; /* 16-bit Access */ +} iodefine_reg32_16_t; + + +/*********************************************************************** +* Type: iodefine_reg16_8_t +* 16/8 bit access register +* +* - Padding : sizeof(iodefine_reg16_8_t) == 2 +* - Alignment(Offset) : &UINT16==0, &UINT8[0]==0, &UINT8[1]==1 +* - Endian : Independent (Same as CPU endian as register endian) +* - Bit-Order : Independent +************************************************************************/ +typedef union iodefine_reg16_8_t +{ + volatile uint16_t UINT16; /* 16-bit Access */ + volatile uint8_t UINT8[2]; /* 8-bit Access */ +} iodefine_reg16_8_t; + + +/* End of shared types and macros for iodefine.h */ +/* <-SEC M1.10.1 */ +/* <-MISRA 18.4 */ /* <-SEC M1.6.2 */ +/* <-QAC 0857 */ +/* <-QAC 0639 */ +#endif diff --git a/targets/TARGET_RENESAS/TARGET_RZ_A1XX/TARGET_GR_LYCHEE/device/inc/iodefines/irda_iodefine.h b/targets/TARGET_RENESAS/TARGET_RZ_A1XX/TARGET_GR_LYCHEE/device/inc/iodefines/irda_iodefine.h new file mode 100644 index 0000000..27574b7 --- /dev/null +++ b/targets/TARGET_RENESAS/TARGET_RZ_A1XX/TARGET_GR_LYCHEE/device/inc/iodefines/irda_iodefine.h @@ -0,0 +1,53 @@ +/******************************************************************************* +* DISCLAIMER +* This software is supplied by Renesas Electronics Corporation and is only +* intended for use with Renesas products. No other uses are authorized. This +* software is owned by Renesas Electronics Corporation and is protected under +* all applicable laws, including copyright laws. +* THIS SOFTWARE IS PROVIDED "AS IS" AND RENESAS MAKES NO WARRANTIES REGARDING +* THIS SOFTWARE, WHETHER EXPRESS, IMPLIED OR STATUTORY, INCLUDING BUT NOT +* LIMITED TO WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE +* AND NON-INFRINGEMENT. ALL SUCH WARRANTIES ARE EXPRESSLY DISCLAIMED. +* TO THE MAXIMUM EXTENT PERMITTED NOT PROHIBITED BY LAW, NEITHER RENESAS +* ELECTRONICS CORPORATION NOR ANY OF ITS AFFILIATED COMPANIES SHALL BE LIABLE +* FOR ANY DIRECT, INDIRECT, SPECIAL, INCIDENTAL OR CONSEQUENTIAL DAMAGES FOR +* ANY REASON RELATED TO THIS SOFTWARE, EVEN IF RENESAS OR ITS AFFILIATES HAVE +* BEEN ADVISED OF THE POSSIBILITY OF SUCH DAMAGES. +* Renesas reserves the right, without notice, to make changes to this software +* and to discontinue the availability of this software. By using this software, +* you agree to the additional terms and conditions found by accessing the +* following link: +* http://www.renesas.com/disclaimer* +* Copyright (C) 2013-2016 Renesas Electronics Corporation. All rights reserved. +*******************************************************************************/ +/******************************************************************************* +* File Name : irda_iodefine.h +* $Rev: $ +* $Date:: $ +* Description : Definition of I/O Register for RZ/A1LU (V3.00l) +******************************************************************************/ +#ifndef IRDA_IODEFINE_H +#define IRDA_IODEFINE_H +/* ->QAC 0639 : Over 127 members (C90) */ +/* ->QAC 0857 : Over 1024 #define (C90) */ +/* ->MISRA 18.4 : Pack unpack union */ /* ->SEC M1.6.2 */ +/* ->SEC M1.10.1 : Not magic number */ + +#define IRDA (*(struct st_irda *)0xE8014000uL) /* IRDA */ + + +#define IRDAIRCR (IRDA.IRCR) + + +typedef struct st_irda +{ + /* IRDA */ + volatile uint8_t IRCR; /* IRCR */ +} r_io_irda_t; + + +/* <-SEC M1.10.1 */ +/* <-MISRA 18.4 */ /* <-SEC M1.6.2 */ +/* <-QAC 0857 */ +/* <-QAC 0639 */ +#endif diff --git a/targets/TARGET_RENESAS/TARGET_RZ_A1XX/TARGET_GR_LYCHEE/device/inc/iodefines/jcu_iodefine.h b/targets/TARGET_RENESAS/TARGET_RZ_A1XX/TARGET_GR_LYCHEE/device/inc/iodefines/jcu_iodefine.h new file mode 100644 index 0000000..f50157d --- /dev/null +++ b/targets/TARGET_RENESAS/TARGET_RZ_A1XX/TARGET_GR_LYCHEE/device/inc/iodefines/jcu_iodefine.h @@ -0,0 +1,197 @@ +/******************************************************************************* +* DISCLAIMER +* This software is supplied by Renesas Electronics Corporation and is only +* intended for use with Renesas products. No other uses are authorized. This +* software is owned by Renesas Electronics Corporation and is protected under +* all applicable laws, including copyright laws. +* THIS SOFTWARE IS PROVIDED "AS IS" AND RENESAS MAKES NO WARRANTIES REGARDING +* THIS SOFTWARE, WHETHER EXPRESS, IMPLIED OR STATUTORY, INCLUDING BUT NOT +* LIMITED TO WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE +* AND NON-INFRINGEMENT. ALL SUCH WARRANTIES ARE EXPRESSLY DISCLAIMED. +* TO THE MAXIMUM EXTENT PERMITTED NOT PROHIBITED BY LAW, NEITHER RENESAS +* ELECTRONICS CORPORATION NOR ANY OF ITS AFFILIATED COMPANIES SHALL BE LIABLE +* FOR ANY DIRECT, INDIRECT, SPECIAL, INCIDENTAL OR CONSEQUENTIAL DAMAGES FOR +* ANY REASON RELATED TO THIS SOFTWARE, EVEN IF RENESAS OR ITS AFFILIATES HAVE +* BEEN ADVISED OF THE POSSIBILITY OF SUCH DAMAGES. +* Renesas reserves the right, without notice, to make changes to this software +* and to discontinue the availability of this software. By using this software, +* you agree to the additional terms and conditions found by accessing the +* following link: +* http://www.renesas.com/disclaimer* +* Copyright (C) 2013-2016 Renesas Electronics Corporation. All rights reserved. +*******************************************************************************/ +/******************************************************************************* +* File Name : jcu_iodefine.h +* $Rev: $ +* $Date:: $ +* Description : Definition of I/O Register for RZ/A1LU (V3.00l) +******************************************************************************/ +#ifndef JCU_IODEFINE_H +#define JCU_IODEFINE_H +/* ->QAC 0639 : Over 127 members (C90) */ +/* ->QAC 0857 : Over 1024 #define (C90) */ +/* ->MISRA 18.4 : Pack unpack union */ /* ->SEC M1.6.2 */ +/* ->SEC M1.10.1 : Not magic number */ + +#define JCU (*(struct st_jcu *)0xE8017000uL) /* JCU */ + + +/* Start of channel array defines of JCU */ + +/* Channel array defines of JCU_JCQTBL0 */ +/*(Sample) value = JCU_JCQTBL0[ channel ]->JCQTBL0; */ +#define JCU_JCQTBL0_COUNT (4) +#define JCU_JCQTBL0_ADDRESS_LIST \ +{ /* ->MISRA 11.3 */ /* ->SEC R2.7.1 */ \ + &JCU_FROM_JCQTBL0, &JCU_FROM_JCQTBL1, &JCU_FROM_JCQTBL2, &JCU_FROM_JCQTBL3 \ +} /* <-MISRA 11.3 */ /* <-SEC R2.7.1 */ /* { } is for MISRA 19.4 */ +#define JCU_FROM_JCQTBL0 (*(struct st_jcu_from_jcqtbl0 *)&JCU.JCQTBL0) /* JCU_FROM_JCQTBL0 */ +#define JCU_FROM_JCQTBL1 (*(struct st_jcu_from_jcqtbl0 *)&JCU.JCQTBL1) /* JCU_FROM_JCQTBL1 */ +#define JCU_FROM_JCQTBL2 (*(struct st_jcu_from_jcqtbl0 *)&JCU.JCQTBL2) /* JCU_FROM_JCQTBL2 */ +#define JCU_FROM_JCQTBL3 (*(struct st_jcu_from_jcqtbl0 *)&JCU.JCQTBL3) /* JCU_FROM_JCQTBL3 */ + +/* End of channel array defines of JCU */ + + +#define JCUJCMOD (JCU.JCMOD) +#define JCUJCCMD (JCU.JCCMD) +#define JCUJCQTN (JCU.JCQTN) +#define JCUJCHTN (JCU.JCHTN) +#define JCUJCDRIU (JCU.JCDRIU) +#define JCUJCDRID (JCU.JCDRID) +#define JCUJCVSZU (JCU.JCVSZU) +#define JCUJCVSZD (JCU.JCVSZD) +#define JCUJCHSZU (JCU.JCHSZU) +#define JCUJCHSZD (JCU.JCHSZD) +#define JCUJCDTCU (JCU.JCDTCU) +#define JCUJCDTCM (JCU.JCDTCM) +#define JCUJCDTCD (JCU.JCDTCD) +#define JCUJINTE0 (JCU.JINTE0) +#define JCUJINTS0 (JCU.JINTS0) +#define JCUJCDERR (JCU.JCDERR) +#define JCUJCRST (JCU.JCRST) +#define JCUJIFECNT (JCU.JIFECNT) +#define JCUJIFESA (JCU.JIFESA) +#define JCUJIFESOFST (JCU.JIFESOFST) +#define JCUJIFEDA (JCU.JIFEDA) +#define JCUJIFESLC (JCU.JIFESLC) +#define JCUJIFEDDC (JCU.JIFEDDC) +#define JCUJIFDCNT (JCU.JIFDCNT) +#define JCUJIFDSA (JCU.JIFDSA) +#define JCUJIFDDOFST (JCU.JIFDDOFST) +#define JCUJIFDDA (JCU.JIFDDA) +#define JCUJIFDSDC (JCU.JIFDSDC) +#define JCUJIFDDLC (JCU.JIFDDLC) +#define JCUJIFDADT (JCU.JIFDADT) +#define JCUJINTE1 (JCU.JINTE1) +#define JCUJINTS1 (JCU.JINTS1) +#define JCUJIFESVSZ (JCU.JIFESVSZ) +#define JCUJIFESHSZ (JCU.JIFESHSZ) +#define JCUJCQTBL0 (JCU.JCQTBL0) +#define JCUJCQTBL1 (JCU.JCQTBL1) +#define JCUJCQTBL2 (JCU.JCQTBL2) +#define JCUJCQTBL3 (JCU.JCQTBL3) +#define JCUJCHTBD0 (JCU.JCHTBD0) +#define JCUJCHTBA0 (JCU.JCHTBA0) +#define JCUJCHTBD1 (JCU.JCHTBD1) +#define JCUJCHTBA1 (JCU.JCHTBA1) + + +typedef struct st_jcu +{ + /* JCU */ + volatile uint8_t JCMOD; /* JCMOD */ + volatile uint8_t JCCMD; /* JCCMD */ + volatile uint8_t dummy145[1]; /* */ + volatile uint8_t JCQTN; /* JCQTN */ + volatile uint8_t JCHTN; /* JCHTN */ + volatile uint8_t JCDRIU; /* JCDRIU */ + volatile uint8_t JCDRID; /* JCDRID */ + volatile uint8_t JCVSZU; /* JCVSZU */ + volatile uint8_t JCVSZD; /* JCVSZD */ + volatile uint8_t JCHSZU; /* JCHSZU */ + volatile uint8_t JCHSZD; /* JCHSZD */ + volatile uint8_t JCDTCU; /* JCDTCU */ + volatile uint8_t JCDTCM; /* JCDTCM */ + volatile uint8_t JCDTCD; /* JCDTCD */ + volatile uint8_t JINTE0; /* JINTE0 */ + volatile uint8_t JINTS0; /* JINTS0 */ + volatile uint8_t JCDERR; /* JCDERR */ + volatile uint8_t JCRST; /* JCRST */ + volatile uint8_t dummy146[46]; /* */ + volatile uint32_t JIFECNT; /* JIFECNT */ + volatile uint32_t JIFESA; /* JIFESA */ + volatile uint32_t JIFESOFST; /* JIFESOFST */ + volatile uint32_t JIFEDA; /* JIFEDA */ + volatile uint32_t JIFESLC; /* JIFESLC */ + volatile uint32_t JIFEDDC; /* JIFEDDC */ + volatile uint32_t JIFDCNT; /* JIFDCNT */ + volatile uint32_t JIFDSA; /* JIFDSA */ + volatile uint32_t JIFDDOFST; /* JIFDDOFST */ + volatile uint32_t JIFDDA; /* JIFDDA */ + volatile uint32_t JIFDSDC; /* JIFDSDC */ + volatile uint32_t JIFDDLC; /* JIFDDLC */ + volatile uint32_t JIFDADT; /* JIFDADT */ + volatile uint8_t dummy147[24]; /* */ + volatile uint32_t JINTE1; /* JINTE1 */ + volatile uint32_t JINTS1; /* JINTS1 */ + volatile uint32_t JIFESVSZ; /* JIFESVSZ */ + volatile uint32_t JIFESHSZ; /* JIFESHSZ */ + volatile uint8_t dummy148[100]; /* */ + +/* start of struct st_jcu_from_jcqtbl0 */ + volatile uint8_t JCQTBL0; /* JCQTBL0 */ + volatile uint8_t dummy149[63]; /* */ + +/* end of struct st_jcu_from_jcqtbl0 */ + +/* start of struct st_jcu_from_jcqtbl0 */ + volatile uint8_t JCQTBL1; /* JCQTBL1 */ + volatile uint8_t dummy150[63]; /* */ + +/* end of struct st_jcu_from_jcqtbl0 */ + +/* start of struct st_jcu_from_jcqtbl0 */ + volatile uint8_t JCQTBL2; /* JCQTBL2 */ + volatile uint8_t dummy151[63]; /* */ + +/* end of struct st_jcu_from_jcqtbl0 */ + +/* start of struct st_jcu_from_jcqtbl0 */ + volatile uint8_t JCQTBL3; /* JCQTBL3 */ + volatile uint8_t dummy152[63]; /* */ + +/* end of struct st_jcu_from_jcqtbl0 */ + volatile uint8_t JCHTBD0; /* JCHTBD0 */ + volatile uint8_t dummy153[31]; /* */ + volatile uint8_t JCHTBA0; /* JCHTBA0 */ + volatile uint8_t dummy154[223]; /* */ + volatile uint8_t JCHTBD1; /* JCHTBD1 */ + volatile uint8_t dummy155[31]; /* */ + volatile uint8_t JCHTBA1; /* JCHTBA1 */ +} r_io_jcu_t; + + +typedef struct st_jcu_from_jcqtbl0 +{ + + volatile uint8_t JCQTBL0; /* JCQTBL0 */ + volatile uint8_t dummy1[63]; /* */ +} r_io_jcu_from_jcqtbl0_t; + + +/* Channel array defines of JCU (2)*/ +#ifdef DECLARE_JCU_JCQTBL0_CHANNELS +volatile struct st_jcu_from_jcqtbl0* JCU_JCQTBL0[ JCU_JCQTBL0_COUNT ] = + /* ->MISRA 11.3 */ /* ->SEC R2.7.1 */ + JCU_JCQTBL0_ADDRESS_LIST; + /* <-MISRA 11.3 */ /* <-SEC R2.7.1 */ +#endif /* DECLARE_JCU_JCQTBL0_CHANNELS */ +/* End of channel array defines of JCU (2)*/ + + +/* <-SEC M1.10.1 */ +/* <-MISRA 18.4 */ /* <-SEC M1.6.2 */ +/* <-QAC 0857 */ +/* <-QAC 0639 */ +#endif diff --git a/targets/TARGET_RENESAS/TARGET_RZ_A1XX/TARGET_GR_LYCHEE/device/inc/iodefines/l2c_iodefine.h b/targets/TARGET_RENESAS/TARGET_RZ_A1XX/TARGET_GR_LYCHEE/device/inc/iodefines/l2c_iodefine.h new file mode 100644 index 0000000..f0e09fd --- /dev/null +++ b/targets/TARGET_RENESAS/TARGET_RZ_A1XX/TARGET_GR_LYCHEE/device/inc/iodefines/l2c_iodefine.h @@ -0,0 +1,231 @@ +/******************************************************************************* +* DISCLAIMER +* This software is supplied by Renesas Electronics Corporation and is only +* intended for use with Renesas products. No other uses are authorized. This +* software is owned by Renesas Electronics Corporation and is protected under +* all applicable laws, including copyright laws. +* THIS SOFTWARE IS PROVIDED "AS IS" AND RENESAS MAKES NO WARRANTIES REGARDING +* THIS SOFTWARE, WHETHER EXPRESS, IMPLIED OR STATUTORY, INCLUDING BUT NOT +* LIMITED TO WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE +* AND NON-INFRINGEMENT. ALL SUCH WARRANTIES ARE EXPRESSLY DISCLAIMED. +* TO THE MAXIMUM EXTENT PERMITTED NOT PROHIBITED BY LAW, NEITHER RENESAS +* ELECTRONICS CORPORATION NOR ANY OF ITS AFFILIATED COMPANIES SHALL BE LIABLE +* FOR ANY DIRECT, INDIRECT, SPECIAL, INCIDENTAL OR CONSEQUENTIAL DAMAGES FOR +* ANY REASON RELATED TO THIS SOFTWARE, EVEN IF RENESAS OR ITS AFFILIATES HAVE +* BEEN ADVISED OF THE POSSIBILITY OF SUCH DAMAGES. +* Renesas reserves the right, without notice, to make changes to this software +* and to discontinue the availability of this software. By using this software, +* you agree to the additional terms and conditions found by accessing the +* following link: +* http://www.renesas.com/disclaimer* +* Copyright (C) 2013-2016 Renesas Electronics Corporation. All rights reserved. +*******************************************************************************/ +/******************************************************************************* +* File Name : l2c_iodefine.h +* $Rev: $ +* $Date:: $ +* Description : Definition of I/O Register for RZ/A1LU (V3.00l) +******************************************************************************/ +#ifndef L2C_IODEFINE_H +#define L2C_IODEFINE_H +/* ->QAC 0639 : Over 127 members (C90) */ +/* ->QAC 0857 : Over 1024 #define (C90) */ +/* ->MISRA 18.4 : Pack unpack union */ /* ->SEC M1.6.2 */ +/* ->SEC M1.10.1 : Not magic number */ + +#define L2C (*(struct st_l2c *)0x3FFFF000uL) /* L2C */ + + +/* Start of channel array defines of L2C */ + +/* Channel array defines of L2C_FROM_REG9_D_LOCKDOWN0_ARRAY */ +/*(Sample) value = L2C_FROM_REG9_D_LOCKDOWN0_ARRAY[ channel ]->REG9_D_LOCKDOWN0; */ +#define L2C_FROM_REG9_D_LOCKDOWN0_ARRAY_COUNT (8) +#define L2C_FROM_REG9_D_LOCKDOWN0_ARRAY_ADDRESS_LIST \ +{ /* ->MISRA 11.3 */ /* ->SEC R2.7.1 */ \ + &L2C_FROM_REG9_D_LOCKDOWN0, &L2C_FROM_REG9_D_LOCKDOWN1, &L2C_FROM_REG9_D_LOCKDOWN2, &L2C_FROM_REG9_D_LOCKDOWN3, &L2C_FROM_REG9_D_LOCKDOWN4, &L2C_FROM_REG9_D_LOCKDOWN5, &L2C_FROM_REG9_D_LOCKDOWN6, &L2C_FROM_REG9_D_LOCKDOWN7 \ +} /* <-MISRA 11.3 */ /* <-SEC R2.7.1 */ /* { } is for MISRA 19.4 */ +#define L2C_FROM_REG9_D_LOCKDOWN0 (*(struct st_l2c_from_reg9_d_lockdown0 *)&L2C.REG9_D_LOCKDOWN0) /* L2C_FROM_REG9_D_LOCKDOWN0 */ +#define L2C_FROM_REG9_D_LOCKDOWN1 (*(struct st_l2c_from_reg9_d_lockdown0 *)&L2C.REG9_D_LOCKDOWN1) /* L2C_FROM_REG9_D_LOCKDOWN1 */ +#define L2C_FROM_REG9_D_LOCKDOWN2 (*(struct st_l2c_from_reg9_d_lockdown0 *)&L2C.REG9_D_LOCKDOWN2) /* L2C_FROM_REG9_D_LOCKDOWN2 */ +#define L2C_FROM_REG9_D_LOCKDOWN3 (*(struct st_l2c_from_reg9_d_lockdown0 *)&L2C.REG9_D_LOCKDOWN3) /* L2C_FROM_REG9_D_LOCKDOWN3 */ +#define L2C_FROM_REG9_D_LOCKDOWN4 (*(struct st_l2c_from_reg9_d_lockdown0 *)&L2C.REG9_D_LOCKDOWN4) /* L2C_FROM_REG9_D_LOCKDOWN4 */ +#define L2C_FROM_REG9_D_LOCKDOWN5 (*(struct st_l2c_from_reg9_d_lockdown0 *)&L2C.REG9_D_LOCKDOWN5) /* L2C_FROM_REG9_D_LOCKDOWN5 */ +#define L2C_FROM_REG9_D_LOCKDOWN6 (*(struct st_l2c_from_reg9_d_lockdown0 *)&L2C.REG9_D_LOCKDOWN6) /* L2C_FROM_REG9_D_LOCKDOWN6 */ +#define L2C_FROM_REG9_D_LOCKDOWN7 (*(struct st_l2c_from_reg9_d_lockdown0 *)&L2C.REG9_D_LOCKDOWN7) /* L2C_FROM_REG9_D_LOCKDOWN7 */ + +/* End of channel array defines of L2C */ + + +#define L2CREG0_CACHE_ID (L2C.REG0_CACHE_ID) +#define L2CREG0_CACHE_TYPE (L2C.REG0_CACHE_TYPE) +#define L2CREG1_CONTROL (L2C.REG1_CONTROL) +#define L2CREG1_AUX_CONTROL (L2C.REG1_AUX_CONTROL) +#define L2CREG1_TAG_RAM_CONTROL (L2C.REG1_TAG_RAM_CONTROL) +#define L2CREG1_DATA_RAM_CONTROL (L2C.REG1_DATA_RAM_CONTROL) +#define L2CREG2_EV_COUNTER_CTRL (L2C.REG2_EV_COUNTER_CTRL) +#define L2CREG2_EV_COUNTER1_CFG (L2C.REG2_EV_COUNTER1_CFG) +#define L2CREG2_EV_COUNTER0_CFG (L2C.REG2_EV_COUNTER0_CFG) +#define L2CREG2_EV_COUNTER1 (L2C.REG2_EV_COUNTER1) +#define L2CREG2_EV_COUNTER0 (L2C.REG2_EV_COUNTER0) +#define L2CREG2_INT_MASK (L2C.REG2_INT_MASK) +#define L2CREG2_INT_MASK_STATUS (L2C.REG2_INT_MASK_STATUS) +#define L2CREG2_INT_RAW_STATUS (L2C.REG2_INT_RAW_STATUS) +#define L2CREG2_INT_CLEAR (L2C.REG2_INT_CLEAR) +#define L2CREG7_CACHE_SYNC (L2C.REG7_CACHE_SYNC) +#define L2CREG7_INV_PA (L2C.REG7_INV_PA) +#define L2CREG7_INV_WAY (L2C.REG7_INV_WAY) +#define L2CREG7_CLEAN_PA (L2C.REG7_CLEAN_PA) +#define L2CREG7_CLEAN_INDEX (L2C.REG7_CLEAN_INDEX) +#define L2CREG7_CLEAN_WAY (L2C.REG7_CLEAN_WAY) +#define L2CREG7_CLEAN_INV_PA (L2C.REG7_CLEAN_INV_PA) +#define L2CREG7_CLEAN_INV_INDEX (L2C.REG7_CLEAN_INV_INDEX) +#define L2CREG7_CLEAN_INV_WAY (L2C.REG7_CLEAN_INV_WAY) +#define L2CREG9_D_LOCKDOWN0 (L2C.REG9_D_LOCKDOWN0) +#define L2CREG9_I_LOCKDOWN0 (L2C.REG9_I_LOCKDOWN0) +#define L2CREG9_D_LOCKDOWN1 (L2C.REG9_D_LOCKDOWN1) +#define L2CREG9_I_LOCKDOWN1 (L2C.REG9_I_LOCKDOWN1) +#define L2CREG9_D_LOCKDOWN2 (L2C.REG9_D_LOCKDOWN2) +#define L2CREG9_I_LOCKDOWN2 (L2C.REG9_I_LOCKDOWN2) +#define L2CREG9_D_LOCKDOWN3 (L2C.REG9_D_LOCKDOWN3) +#define L2CREG9_I_LOCKDOWN3 (L2C.REG9_I_LOCKDOWN3) +#define L2CREG9_D_LOCKDOWN4 (L2C.REG9_D_LOCKDOWN4) +#define L2CREG9_I_LOCKDOWN4 (L2C.REG9_I_LOCKDOWN4) +#define L2CREG9_D_LOCKDOWN5 (L2C.REG9_D_LOCKDOWN5) +#define L2CREG9_I_LOCKDOWN5 (L2C.REG9_I_LOCKDOWN5) +#define L2CREG9_D_LOCKDOWN6 (L2C.REG9_D_LOCKDOWN6) +#define L2CREG9_I_LOCKDOWN6 (L2C.REG9_I_LOCKDOWN6) +#define L2CREG9_D_LOCKDOWN7 (L2C.REG9_D_LOCKDOWN7) +#define L2CREG9_I_LOCKDOWN7 (L2C.REG9_I_LOCKDOWN7) +#define L2CREG9_LOCK_LINE_EN (L2C.REG9_LOCK_LINE_EN) +#define L2CREG9_UNLOCK_WAY (L2C.REG9_UNLOCK_WAY) +#define L2CREG12_ADDR_FILTERING_START (L2C.REG12_ADDR_FILTERING_START) +#define L2CREG12_ADDR_FILTERING_END (L2C.REG12_ADDR_FILTERING_END) +#define L2CREG15_DEBUG_CTRL (L2C.REG15_DEBUG_CTRL) +#define L2CREG15_PREFETCH_CTRL (L2C.REG15_PREFETCH_CTRL) +#define L2CREG15_POWER_CTRL (L2C.REG15_POWER_CTRL) + + +typedef struct st_l2c +{ + /* L2C */ + volatile uint32_t REG0_CACHE_ID; /* REG0_CACHE_ID */ + volatile uint32_t REG0_CACHE_TYPE; /* REG0_CACHE_TYPE */ + volatile uint8_t dummy8[248]; /* */ + volatile uint32_t REG1_CONTROL; /* REG1_CONTROL */ + volatile uint32_t REG1_AUX_CONTROL; /* REG1_AUX_CONTROL */ + volatile uint32_t REG1_TAG_RAM_CONTROL; /* REG1_TAG_RAM_CONTROL */ + volatile uint32_t REG1_DATA_RAM_CONTROL; /* REG1_DATA_RAM_CONTROL */ + volatile uint8_t dummy9[240]; /* */ + volatile uint32_t REG2_EV_COUNTER_CTRL; /* REG2_EV_COUNTER_CTRL */ + volatile uint32_t REG2_EV_COUNTER1_CFG; /* REG2_EV_COUNTER1_CFG */ + volatile uint32_t REG2_EV_COUNTER0_CFG; /* REG2_EV_COUNTER0_CFG */ + volatile uint32_t REG2_EV_COUNTER1; /* REG2_EV_COUNTER1 */ + volatile uint32_t REG2_EV_COUNTER0; /* REG2_EV_COUNTER0 */ + volatile uint32_t REG2_INT_MASK; /* REG2_INT_MASK */ + volatile uint32_t REG2_INT_MASK_STATUS; /* REG2_INT_MASK_STATUS */ + volatile uint32_t REG2_INT_RAW_STATUS; /* REG2_INT_RAW_STATUS */ + volatile uint32_t REG2_INT_CLEAR; /* REG2_INT_CLEAR */ + volatile uint8_t dummy10[1292]; /* */ + volatile uint32_t REG7_CACHE_SYNC; /* REG7_CACHE_SYNC */ + volatile uint8_t dummy11[60]; /* */ + volatile uint32_t REG7_INV_PA; /* REG7_INV_PA */ + volatile uint8_t dummy12[8]; /* */ + volatile uint32_t REG7_INV_WAY; /* REG7_INV_WAY */ + volatile uint8_t dummy13[48]; /* */ + volatile uint32_t REG7_CLEAN_PA; /* REG7_CLEAN_PA */ + volatile uint8_t dummy14[4]; /* */ + volatile uint32_t REG7_CLEAN_INDEX; /* REG7_CLEAN_INDEX */ + volatile uint32_t REG7_CLEAN_WAY; /* REG7_CLEAN_WAY */ + volatile uint8_t dummy15[48]; /* */ + volatile uint32_t REG7_CLEAN_INV_PA; /* REG7_CLEAN_INV_PA */ + volatile uint8_t dummy16[4]; /* */ + volatile uint32_t REG7_CLEAN_INV_INDEX; /* REG7_CLEAN_INV_INDEX */ + volatile uint32_t REG7_CLEAN_INV_WAY; /* REG7_CLEAN_INV_WAY */ + volatile uint8_t dummy17[256]; /* */ + +/* start of struct st_l2c_from_reg9_d_lockdown0 */ + volatile uint32_t REG9_D_LOCKDOWN0; /* REG9_D_LOCKDOWN0 */ + volatile uint32_t REG9_I_LOCKDOWN0; /* REG9_I_LOCKDOWN0 */ + +/* end of struct st_l2c_from_reg9_d_lockdown0 */ + +/* start of struct st_l2c_from_reg9_d_lockdown0 */ + volatile uint32_t REG9_D_LOCKDOWN1; /* REG9_D_LOCKDOWN1 */ + volatile uint32_t REG9_I_LOCKDOWN1; /* REG9_I_LOCKDOWN1 */ + +/* end of struct st_l2c_from_reg9_d_lockdown0 */ + +/* start of struct st_l2c_from_reg9_d_lockdown0 */ + volatile uint32_t REG9_D_LOCKDOWN2; /* REG9_D_LOCKDOWN2 */ + volatile uint32_t REG9_I_LOCKDOWN2; /* REG9_I_LOCKDOWN2 */ + +/* end of struct st_l2c_from_reg9_d_lockdown0 */ + +/* start of struct st_l2c_from_reg9_d_lockdown0 */ + volatile uint32_t REG9_D_LOCKDOWN3; /* REG9_D_LOCKDOWN3 */ + volatile uint32_t REG9_I_LOCKDOWN3; /* REG9_I_LOCKDOWN3 */ + +/* end of struct st_l2c_from_reg9_d_lockdown0 */ + +/* start of struct st_l2c_from_reg9_d_lockdown0 */ + volatile uint32_t REG9_D_LOCKDOWN4; /* REG9_D_LOCKDOWN4 */ + volatile uint32_t REG9_I_LOCKDOWN4; /* REG9_I_LOCKDOWN4 */ + +/* end of struct st_l2c_from_reg9_d_lockdown0 */ + +/* start of struct st_l2c_from_reg9_d_lockdown0 */ + volatile uint32_t REG9_D_LOCKDOWN5; /* REG9_D_LOCKDOWN5 */ + volatile uint32_t REG9_I_LOCKDOWN5; /* REG9_I_LOCKDOWN5 */ + +/* end of struct st_l2c_from_reg9_d_lockdown0 */ + +/* start of struct st_l2c_from_reg9_d_lockdown0 */ + volatile uint32_t REG9_D_LOCKDOWN6; /* REG9_D_LOCKDOWN6 */ + volatile uint32_t REG9_I_LOCKDOWN6; /* REG9_I_LOCKDOWN6 */ + +/* end of struct st_l2c_from_reg9_d_lockdown0 */ + +/* start of struct st_l2c_from_reg9_d_lockdown0 */ + volatile uint32_t REG9_D_LOCKDOWN7; /* REG9_D_LOCKDOWN7 */ + volatile uint32_t REG9_I_LOCKDOWN7; /* REG9_I_LOCKDOWN7 */ + +/* end of struct st_l2c_from_reg9_d_lockdown0 */ + volatile uint8_t dummy18[16]; /* */ + volatile uint32_t REG9_LOCK_LINE_EN; /* REG9_LOCK_LINE_EN */ + volatile uint32_t REG9_UNLOCK_WAY; /* REG9_UNLOCK_WAY */ + volatile uint8_t dummy19[680]; /* */ + volatile uint32_t REG12_ADDR_FILTERING_START; /* REG12_ADDR_FILTERING_START */ + volatile uint32_t REG12_ADDR_FILTERING_END; /* REG12_ADDR_FILTERING_END */ + volatile uint8_t dummy20[824]; /* */ + volatile uint32_t REG15_DEBUG_CTRL; /* REG15_DEBUG_CTRL */ + volatile uint8_t dummy21[28]; /* */ + volatile uint32_t REG15_PREFETCH_CTRL; /* REG15_PREFETCH_CTRL */ + volatile uint8_t dummy22[28]; /* */ + volatile uint32_t REG15_POWER_CTRL; /* REG15_POWER_CTRL */ +} r_io_l2c_t; + + +typedef struct st_l2c_from_reg9_d_lockdown0 +{ + + volatile uint32_t REG9_D_LOCKDOWN0; /* REG9_D_LOCKDOWN0 */ + volatile uint32_t REG9_I_LOCKDOWN0; /* REG9_I_LOCKDOWN0 */ +} r_io_l2c_from_reg9_d_lockdown_t /* Short of r_io_l2c_from_reg9_d_lockdown0_t */; + + +/* Channel array defines of L2C (2)*/ +#ifdef DECLARE_L2C_FROM_REG9_D_LOCKDOWN0_ARRAY_CHANNELS +volatile struct st_l2c_from_reg9_d_lockdown0* L2C_FROM_REG9_D_LOCKDOWN0_ARRAY[ L2C_FROM_REG9_D_LOCKDOWN0_ARRAY_COUNT ] = + /* ->MISRA 11.3 */ /* ->SEC R2.7.1 */ + L2C_FROM_REG9_D_LOCKDOWN0_ARRAY_ADDRESS_LIST; + /* <-MISRA 11.3 */ /* <-SEC R2.7.1 */ +#endif /* DECLARE_L2C_FROM_REG9_D_LOCKDOWN0_ARRAY_CHANNELS */ +/* End of channel array defines of L2C (2)*/ + + +/* <-SEC M1.10.1 */ +/* <-MISRA 18.4 */ /* <-SEC M1.6.2 */ +/* <-QAC 0857 */ +/* <-QAC 0639 */ +#endif diff --git a/targets/TARGET_RENESAS/TARGET_RZ_A1XX/TARGET_GR_LYCHEE/device/inc/iodefines/mmc_iodefine.h b/targets/TARGET_RENESAS/TARGET_RZ_A1XX/TARGET_GR_LYCHEE/device/inc/iodefines/mmc_iodefine.h new file mode 100644 index 0000000..ba8f4b3 --- /dev/null +++ b/targets/TARGET_RENESAS/TARGET_RZ_A1XX/TARGET_GR_LYCHEE/device/inc/iodefines/mmc_iodefine.h @@ -0,0 +1,104 @@ +/******************************************************************************* +* DISCLAIMER +* This software is supplied by Renesas Electronics Corporation and is only +* intended for use with Renesas products. No other uses are authorized. This +* software is owned by Renesas Electronics Corporation and is protected under +* all applicable laws, including copyright laws. +* THIS SOFTWARE IS PROVIDED "AS IS" AND RENESAS MAKES NO WARRANTIES REGARDING +* THIS SOFTWARE, WHETHER EXPRESS, IMPLIED OR STATUTORY, INCLUDING BUT NOT +* LIMITED TO WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE +* AND NON-INFRINGEMENT. ALL SUCH WARRANTIES ARE EXPRESSLY DISCLAIMED. +* TO THE MAXIMUM EXTENT PERMITTED NOT PROHIBITED BY LAW, NEITHER RENESAS +* ELECTRONICS CORPORATION NOR ANY OF ITS AFFILIATED COMPANIES SHALL BE LIABLE +* FOR ANY DIRECT, INDIRECT, SPECIAL, INCIDENTAL OR CONSEQUENTIAL DAMAGES FOR +* ANY REASON RELATED TO THIS SOFTWARE, EVEN IF RENESAS OR ITS AFFILIATES HAVE +* BEEN ADVISED OF THE POSSIBILITY OF SUCH DAMAGES. +* Renesas reserves the right, without notice, to make changes to this software +* and to discontinue the availability of this software. By using this software, +* you agree to the additional terms and conditions found by accessing the +* following link: +* http://www.renesas.com/disclaimer* +* Copyright (C) 2013-2016 Renesas Electronics Corporation. All rights reserved. +*******************************************************************************/ +/******************************************************************************* +* File Name : mmc_iodefine.h +* $Rev: $ +* $Date:: $ +* Description : Definition of I/O Register for RZ/A1LU (V3.00l) +******************************************************************************/ +#ifndef MMC_IODEFINE_H +#define MMC_IODEFINE_H +/* ->QAC 0639 : Over 127 members (C90) */ +/* ->QAC 0857 : Over 1024 #define (C90) */ +/* ->MISRA 18.4 : Pack unpack union */ /* ->SEC M1.6.2 */ +/* ->SEC M1.10.1 : Not magic number */ + +#define MMC (*(struct st_mmc *)0xE804C800uL) /* MMC */ + + +#define MMCCE_CMD_SETH (MMC.CE_CMD_SETH) +#define MMCCE_CMD_SETL (MMC.CE_CMD_SETL) +#define MMCCE_ARG (MMC.CE_ARG) +#define MMCCE_ARG_CMD12 (MMC.CE_ARG_CMD12) +#define MMCCE_CMD_CTRL (MMC.CE_CMD_CTRL) +#define MMCCE_BLOCK_SET (MMC.CE_BLOCK_SET) +#define MMCCE_CLK_CTRL (MMC.CE_CLK_CTRL) +#define MMCCE_BUF_ACC (MMC.CE_BUF_ACC) +#define MMCCE_RESP3 (MMC.CE_RESP3) +#define MMCCE_RESP2 (MMC.CE_RESP2) +#define MMCCE_RESP1 (MMC.CE_RESP1) +#define MMCCE_RESP0 (MMC.CE_RESP0) +#define MMCCE_RESP_CMD12 (MMC.CE_RESP_CMD12) +#define MMCCE_DATA (MMC.CE_DATA) +#define MMCCE_INT (MMC.CE_INT) +#define MMCCE_INT_EN (MMC.CE_INT_EN) +#define MMCCE_HOST_STS1 (MMC.CE_HOST_STS1) +#define MMCCE_HOST_STS2 (MMC.CE_HOST_STS2) +#define MMCCE_DMA_MODE (MMC.CE_DMA_MODE) +#define MMCCE_DETECT (MMC.CE_DETECT) +#define MMCCE_ADD_MODE (MMC.CE_ADD_MODE) +#define MMCCE_VERSION (MMC.CE_VERSION) + +#define MMC_CE_RESPn_COUNT (4) + + +typedef struct st_mmc +{ + /* MMC */ + volatile uint16_t CE_CMD_SETH; /* CE_CMD_SETH */ + volatile uint16_t CE_CMD_SETL; /* CE_CMD_SETL */ + volatile uint8_t dummy182[4]; /* */ + volatile uint32_t CE_ARG; /* CE_ARG */ + volatile uint32_t CE_ARG_CMD12; /* CE_ARG_CMD12 */ + volatile uint32_t CE_CMD_CTRL; /* CE_CMD_CTRL */ + volatile uint32_t CE_BLOCK_SET; /* CE_BLOCK_SET */ + volatile uint32_t CE_CLK_CTRL; /* CE_CLK_CTRL */ + volatile uint32_t CE_BUF_ACC; /* CE_BUF_ACC */ + +/* #define MMC_CE_RESPn_COUNT (4) */ + volatile uint32_t CE_RESP3; /* CE_RESP3 */ + volatile uint32_t CE_RESP2; /* CE_RESP2 */ + volatile uint32_t CE_RESP1; /* CE_RESP1 */ + volatile uint32_t CE_RESP0; /* CE_RESP0 */ + volatile uint32_t CE_RESP_CMD12; /* CE_RESP_CMD12 */ + volatile uint32_t CE_DATA; /* CE_DATA */ + volatile uint8_t dummy183[8]; /* */ + volatile uint32_t CE_INT; /* CE_INT */ + volatile uint32_t CE_INT_EN; /* CE_INT_EN */ + volatile uint32_t CE_HOST_STS1; /* CE_HOST_STS1 */ + volatile uint32_t CE_HOST_STS2; /* CE_HOST_STS2 */ + volatile uint8_t dummy184[12]; /* */ + volatile uint32_t CE_DMA_MODE; /* CE_DMA_MODE */ + volatile uint8_t dummy185[16]; /* */ + volatile uint32_t CE_DETECT; /* CE_DETECT */ + volatile uint32_t CE_ADD_MODE; /* CE_ADD_MODE */ + volatile uint8_t dummy186[4]; /* */ + volatile uint32_t CE_VERSION; /* CE_VERSION */ +} r_io_mmc_t; + + +/* <-SEC M1.10.1 */ +/* <-MISRA 18.4 */ /* <-SEC M1.6.2 */ +/* <-QAC 0857 */ +/* <-QAC 0639 */ +#endif diff --git a/targets/TARGET_RENESAS/TARGET_RZ_A1XX/TARGET_GR_LYCHEE/device/inc/iodefines/mtu2_iodefine.h b/targets/TARGET_RENESAS/TARGET_RZ_A1XX/TARGET_GR_LYCHEE/device/inc/iodefines/mtu2_iodefine.h new file mode 100644 index 0000000..90eef38 --- /dev/null +++ b/targets/TARGET_RENESAS/TARGET_RZ_A1XX/TARGET_GR_LYCHEE/device/inc/iodefines/mtu2_iodefine.h @@ -0,0 +1,226 @@ +/******************************************************************************* +* DISCLAIMER +* This software is supplied by Renesas Electronics Corporation and is only +* intended for use with Renesas products. No other uses are authorized. This +* software is owned by Renesas Electronics Corporation and is protected under +* all applicable laws, including copyright laws. +* THIS SOFTWARE IS PROVIDED "AS IS" AND RENESAS MAKES NO WARRANTIES REGARDING +* THIS SOFTWARE, WHETHER EXPRESS, IMPLIED OR STATUTORY, INCLUDING BUT NOT +* LIMITED TO WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE +* AND NON-INFRINGEMENT. ALL SUCH WARRANTIES ARE EXPRESSLY DISCLAIMED. +* TO THE MAXIMUM EXTENT PERMITTED NOT PROHIBITED BY LAW, NEITHER RENESAS +* ELECTRONICS CORPORATION NOR ANY OF ITS AFFILIATED COMPANIES SHALL BE LIABLE +* FOR ANY DIRECT, INDIRECT, SPECIAL, INCIDENTAL OR CONSEQUENTIAL DAMAGES FOR +* ANY REASON RELATED TO THIS SOFTWARE, EVEN IF RENESAS OR ITS AFFILIATES HAVE +* BEEN ADVISED OF THE POSSIBILITY OF SUCH DAMAGES. +* Renesas reserves the right, without notice, to make changes to this software +* and to discontinue the availability of this software. By using this software, +* you agree to the additional terms and conditions found by accessing the +* following link: +* http://www.renesas.com/disclaimer* +* Copyright (C) 2013-2016 Renesas Electronics Corporation. All rights reserved. +*******************************************************************************/ +/******************************************************************************* +* File Name : mtu2_iodefine.h +* $Rev: $ +* $Date:: $ +* Description : Definition of I/O Register for RZ/A1LU (V3.00l) +******************************************************************************/ +#ifndef MTU2_IODEFINE_H +#define MTU2_IODEFINE_H +/* ->QAC 0639 : Over 127 members (C90) */ +/* ->QAC 0857 : Over 1024 #define (C90) */ +/* ->MISRA 18.4 : Pack unpack union */ /* ->SEC M1.6.2 */ +/* ->SEC M1.10.1 : Not magic number */ + +#define MTU2 (*(struct st_mtu2 *)0xFCFF0000uL) /* MTU2 */ + + +#define MTU2TCR_2 (MTU2.TCR_2) +#define MTU2TMDR_2 (MTU2.TMDR_2) +#define MTU2TIOR_2 (MTU2.TIOR_2) +#define MTU2TIER_2 (MTU2.TIER_2) +#define MTU2TSR_2 (MTU2.TSR_2) +#define MTU2TCNT_2 (MTU2.TCNT_2) +#define MTU2TGRA_2 (MTU2.TGRA_2) +#define MTU2TGRB_2 (MTU2.TGRB_2) +#define MTU2TCR_3 (MTU2.TCR_3) +#define MTU2TCR_4 (MTU2.TCR_4) +#define MTU2TMDR_3 (MTU2.TMDR_3) +#define MTU2TMDR_4 (MTU2.TMDR_4) +#define MTU2TIORH_3 (MTU2.TIORH_3) +#define MTU2TIORL_3 (MTU2.TIORL_3) +#define MTU2TIORH_4 (MTU2.TIORH_4) +#define MTU2TIORL_4 (MTU2.TIORL_4) +#define MTU2TIER_3 (MTU2.TIER_3) +#define MTU2TIER_4 (MTU2.TIER_4) +#define MTU2TOER (MTU2.TOER) +#define MTU2TGCR (MTU2.TGCR) +#define MTU2TOCR1 (MTU2.TOCR1) +#define MTU2TOCR2 (MTU2.TOCR2) +#define MTU2TCNT_3 (MTU2.TCNT_3) +#define MTU2TCNT_4 (MTU2.TCNT_4) +#define MTU2TCDR (MTU2.TCDR) +#define MTU2TDDR (MTU2.TDDR) +#define MTU2TGRA_3 (MTU2.TGRA_3) +#define MTU2TGRB_3 (MTU2.TGRB_3) +#define MTU2TGRA_4 (MTU2.TGRA_4) +#define MTU2TGRB_4 (MTU2.TGRB_4) +#define MTU2TCNTS (MTU2.TCNTS) +#define MTU2TCBR (MTU2.TCBR) +#define MTU2TGRC_3 (MTU2.TGRC_3) +#define MTU2TGRD_3 (MTU2.TGRD_3) +#define MTU2TGRC_4 (MTU2.TGRC_4) +#define MTU2TGRD_4 (MTU2.TGRD_4) +#define MTU2TSR_3 (MTU2.TSR_3) +#define MTU2TSR_4 (MTU2.TSR_4) +#define MTU2TITCR (MTU2.TITCR) +#define MTU2TITCNT (MTU2.TITCNT) +#define MTU2TBTER (MTU2.TBTER) +#define MTU2TDER (MTU2.TDER) +#define MTU2TOLBR (MTU2.TOLBR) +#define MTU2TBTM_3 (MTU2.TBTM_3) +#define MTU2TBTM_4 (MTU2.TBTM_4) +#define MTU2TADCR (MTU2.TADCR) +#define MTU2TADCORA_4 (MTU2.TADCORA_4) +#define MTU2TADCORB_4 (MTU2.TADCORB_4) +#define MTU2TADCOBRA_4 (MTU2.TADCOBRA_4) +#define MTU2TADCOBRB_4 (MTU2.TADCOBRB_4) +#define MTU2TWCR (MTU2.TWCR) +#define MTU2TSTR (MTU2.TSTR) +#define MTU2TSYR (MTU2.TSYR) +#define MTU2TRWER (MTU2.TRWER) +#define MTU2TCR_0 (MTU2.TCR_0) +#define MTU2TMDR_0 (MTU2.TMDR_0) +#define MTU2TIORH_0 (MTU2.TIORH_0) +#define MTU2TIORL_0 (MTU2.TIORL_0) +#define MTU2TIER_0 (MTU2.TIER_0) +#define MTU2TSR_0 (MTU2.TSR_0) +#define MTU2TCNT_0 (MTU2.TCNT_0) +#define MTU2TGRA_0 (MTU2.TGRA_0) +#define MTU2TGRB_0 (MTU2.TGRB_0) +#define MTU2TGRC_0 (MTU2.TGRC_0) +#define MTU2TGRD_0 (MTU2.TGRD_0) +#define MTU2TGRE_0 (MTU2.TGRE_0) +#define MTU2TGRF_0 (MTU2.TGRF_0) +#define MTU2TIER2_0 (MTU2.TIER2_0) +#define MTU2TSR2_0 (MTU2.TSR2_0) +#define MTU2TBTM_0 (MTU2.TBTM_0) +#define MTU2TCR_1 (MTU2.TCR_1) +#define MTU2TMDR_1 (MTU2.TMDR_1) +#define MTU2TIOR_1 (MTU2.TIOR_1) +#define MTU2TIER_1 (MTU2.TIER_1) +#define MTU2TSR_1 (MTU2.TSR_1) +#define MTU2TCNT_1 (MTU2.TCNT_1) +#define MTU2TGRA_1 (MTU2.TGRA_1) +#define MTU2TGRB_1 (MTU2.TGRB_1) +#define MTU2TICCR (MTU2.TICCR) + + +typedef struct st_mtu2 +{ + /* MTU2 */ + volatile uint8_t TCR_2; /* TCR_2 */ + volatile uint8_t TMDR_2; /* TMDR_2 */ + volatile uint8_t TIOR_2; /* TIOR_2 */ + volatile uint8_t dummy520[1]; /* */ + volatile uint8_t TIER_2; /* TIER_2 */ + volatile uint8_t TSR_2; /* TSR_2 */ + volatile uint16_t TCNT_2; /* TCNT_2 */ + volatile uint16_t TGRA_2; /* TGRA_2 */ + volatile uint16_t TGRB_2; /* TGRB_2 */ + volatile uint8_t dummy521[500]; /* */ + volatile uint8_t TCR_3; /* TCR_3 */ + volatile uint8_t TCR_4; /* TCR_4 */ + volatile uint8_t TMDR_3; /* TMDR_3 */ + volatile uint8_t TMDR_4; /* TMDR_4 */ + volatile uint8_t TIORH_3; /* TIORH_3 */ + volatile uint8_t TIORL_3; /* TIORL_3 */ + volatile uint8_t TIORH_4; /* TIORH_4 */ + volatile uint8_t TIORL_4; /* TIORL_4 */ + volatile uint8_t TIER_3; /* TIER_3 */ + volatile uint8_t TIER_4; /* TIER_4 */ + volatile uint8_t TOER; /* TOER */ + volatile uint8_t dummy522[2]; /* */ + volatile uint8_t TGCR; /* TGCR */ + volatile uint8_t TOCR1; /* TOCR1 */ + volatile uint8_t TOCR2; /* TOCR2 */ + volatile uint16_t TCNT_3; /* TCNT_3 */ + volatile uint16_t TCNT_4; /* TCNT_4 */ + volatile uint16_t TCDR; /* TCDR */ + volatile uint16_t TDDR; /* TDDR */ + volatile uint16_t TGRA_3; /* TGRA_3 */ + volatile uint16_t TGRB_3; /* TGRB_3 */ + volatile uint16_t TGRA_4; /* TGRA_4 */ + volatile uint16_t TGRB_4; /* TGRB_4 */ + volatile uint16_t TCNTS; /* TCNTS */ + volatile uint16_t TCBR; /* TCBR */ + volatile uint16_t TGRC_3; /* TGRC_3 */ + volatile uint16_t TGRD_3; /* TGRD_3 */ + volatile uint16_t TGRC_4; /* TGRC_4 */ + volatile uint16_t TGRD_4; /* TGRD_4 */ + volatile uint8_t TSR_3; /* TSR_3 */ + volatile uint8_t TSR_4; /* TSR_4 */ + volatile uint8_t dummy523[2]; /* */ + volatile uint8_t TITCR; /* TITCR */ + volatile uint8_t TITCNT; /* TITCNT */ + volatile uint8_t TBTER; /* TBTER */ + volatile uint8_t dummy524[1]; /* */ + volatile uint8_t TDER; /* TDER */ + volatile uint8_t dummy525[1]; /* */ + volatile uint8_t TOLBR; /* TOLBR */ + volatile uint8_t dummy526[1]; /* */ + volatile uint8_t TBTM_3; /* TBTM_3 */ + volatile uint8_t TBTM_4; /* TBTM_4 */ + volatile uint8_t dummy527[6]; /* */ + volatile uint16_t TADCR; /* TADCR */ + volatile uint8_t dummy528[2]; /* */ + volatile uint16_t TADCORA_4; /* TADCORA_4 */ + volatile uint16_t TADCORB_4; /* TADCORB_4 */ + volatile uint16_t TADCOBRA_4; /* TADCOBRA_4 */ + volatile uint16_t TADCOBRB_4; /* TADCOBRB_4 */ + volatile uint8_t dummy529[20]; /* */ + volatile uint8_t TWCR; /* TWCR */ + volatile uint8_t dummy530[31]; /* */ + volatile uint8_t TSTR; /* TSTR */ + volatile uint8_t TSYR; /* TSYR */ + volatile uint8_t dummy531[2]; /* */ + volatile uint8_t TRWER; /* TRWER */ + volatile uint8_t dummy532[123]; /* */ + volatile uint8_t TCR_0; /* TCR_0 */ + volatile uint8_t TMDR_0; /* TMDR_0 */ + volatile uint8_t TIORH_0; /* TIORH_0 */ + volatile uint8_t TIORL_0; /* TIORL_0 */ + volatile uint8_t TIER_0; /* TIER_0 */ + volatile uint8_t TSR_0; /* TSR_0 */ + volatile uint16_t TCNT_0; /* TCNT_0 */ + volatile uint16_t TGRA_0; /* TGRA_0 */ + volatile uint16_t TGRB_0; /* TGRB_0 */ + volatile uint16_t TGRC_0; /* TGRC_0 */ + volatile uint16_t TGRD_0; /* TGRD_0 */ + volatile uint8_t dummy533[16]; /* */ + volatile uint16_t TGRE_0; /* TGRE_0 */ + volatile uint16_t TGRF_0; /* TGRF_0 */ + volatile uint8_t TIER2_0; /* TIER2_0 */ + volatile uint8_t TSR2_0; /* TSR2_0 */ + volatile uint8_t TBTM_0; /* TBTM_0 */ + volatile uint8_t dummy534[89]; /* */ + volatile uint8_t TCR_1; /* TCR_1 */ + volatile uint8_t TMDR_1; /* TMDR_1 */ + volatile uint8_t TIOR_1; /* TIOR_1 */ + volatile uint8_t dummy535[1]; /* */ + volatile uint8_t TIER_1; /* TIER_1 */ + volatile uint8_t TSR_1; /* TSR_1 */ + volatile uint16_t TCNT_1; /* TCNT_1 */ + volatile uint16_t TGRA_1; /* TGRA_1 */ + volatile uint16_t TGRB_1; /* TGRB_1 */ + volatile uint8_t dummy536[4]; /* */ + volatile uint8_t TICCR; /* TICCR */ +} r_io_mtu2_t; + + +/* <-SEC M1.10.1 */ +/* <-MISRA 18.4 */ /* <-SEC M1.6.2 */ +/* <-QAC 0857 */ +/* <-QAC 0639 */ +#endif diff --git a/targets/TARGET_RENESAS/TARGET_RZ_A1XX/TARGET_GR_LYCHEE/device/inc/iodefines/ostm_iodefine.h b/targets/TARGET_RENESAS/TARGET_RZ_A1XX/TARGET_GR_LYCHEE/device/inc/iodefines/ostm_iodefine.h new file mode 100644 index 0000000..45c5f9e --- /dev/null +++ b/targets/TARGET_RENESAS/TARGET_RZ_A1XX/TARGET_GR_LYCHEE/device/inc/iodefines/ostm_iodefine.h @@ -0,0 +1,97 @@ +/******************************************************************************* +* DISCLAIMER +* This software is supplied by Renesas Electronics Corporation and is only +* intended for use with Renesas products. No other uses are authorized. This +* software is owned by Renesas Electronics Corporation and is protected under +* all applicable laws, including copyright laws. +* THIS SOFTWARE IS PROVIDED "AS IS" AND RENESAS MAKES NO WARRANTIES REGARDING +* THIS SOFTWARE, WHETHER EXPRESS, IMPLIED OR STATUTORY, INCLUDING BUT NOT +* LIMITED TO WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE +* AND NON-INFRINGEMENT. ALL SUCH WARRANTIES ARE EXPRESSLY DISCLAIMED. +* TO THE MAXIMUM EXTENT PERMITTED NOT PROHIBITED BY LAW, NEITHER RENESAS +* ELECTRONICS CORPORATION NOR ANY OF ITS AFFILIATED COMPANIES SHALL BE LIABLE +* FOR ANY DIRECT, INDIRECT, SPECIAL, INCIDENTAL OR CONSEQUENTIAL DAMAGES FOR +* ANY REASON RELATED TO THIS SOFTWARE, EVEN IF RENESAS OR ITS AFFILIATES HAVE +* BEEN ADVISED OF THE POSSIBILITY OF SUCH DAMAGES. +* Renesas reserves the right, without notice, to make changes to this software +* and to discontinue the availability of this software. By using this software, +* you agree to the additional terms and conditions found by accessing the +* following link: +* http://www.renesas.com/disclaimer* +* Copyright (C) 2013-2016 Renesas Electronics Corporation. All rights reserved. +*******************************************************************************/ +/******************************************************************************* +* File Name : ostm_iodefine.h +* $Rev: $ +* $Date:: $ +* Description : Definition of I/O Register for RZ/A1LU (V3.00l) +******************************************************************************/ +#ifndef OSTM_IODEFINE_H +#define OSTM_IODEFINE_H +/* ->QAC 0639 : Over 127 members (C90) */ +/* ->QAC 0857 : Over 1024 #define (C90) */ +/* ->MISRA 18.4 : Pack unpack union */ /* ->SEC M1.6.2 */ +/* ->SEC M1.10.1 : Not magic number */ + +#define OSTM0 (*(struct st_ostm *)0xFCFEC000uL) /* OSTM0 */ +#define OSTM1 (*(struct st_ostm *)0xFCFEC400uL) /* OSTM1 */ + + +/* Start of channel array defines of OSTM */ + +/* Channel array defines of OSTM */ +/*(Sample) value = OSTM[ channel ]->OSTMnCMP; */ +#define OSTM_COUNT (2) +#define OSTM_ADDRESS_LIST \ +{ /* ->MISRA 11.3 */ /* ->SEC R2.7.1 */ \ + &OSTM0, &OSTM1 \ +} /* <-MISRA 11.3 */ /* <-SEC R2.7.1 */ /* { } is for MISRA 19.4 */ + +/* End of channel array defines of OSTM */ + + +#define OSTM0CMP (OSTM0.OSTMnCMP) +#define OSTM0CNT (OSTM0.OSTMnCNT) +#define OSTM0TE (OSTM0.OSTMnTE) +#define OSTM0TS (OSTM0.OSTMnTS) +#define OSTM0TT (OSTM0.OSTMnTT) +#define OSTM0CTL (OSTM0.OSTMnCTL) +#define OSTM1CMP (OSTM1.OSTMnCMP) +#define OSTM1CNT (OSTM1.OSTMnCNT) +#define OSTM1TE (OSTM1.OSTMnTE) +#define OSTM1TS (OSTM1.OSTMnTS) +#define OSTM1TT (OSTM1.OSTMnTT) +#define OSTM1CTL (OSTM1.OSTMnCTL) + + +typedef struct st_ostm +{ + /* OSTM */ + volatile uint32_t OSTMnCMP; /* OSTMnCMP */ + volatile uint32_t OSTMnCNT; /* OSTMnCNT */ + volatile uint8_t dummy1[8]; /* */ + volatile uint8_t OSTMnTE; /* OSTMnTE */ + volatile uint8_t dummy2[3]; /* */ + volatile uint8_t OSTMnTS; /* OSTMnTS */ + volatile uint8_t dummy3[3]; /* */ + volatile uint8_t OSTMnTT; /* OSTMnTT */ + volatile uint8_t dummy4[7]; /* */ + volatile uint8_t OSTMnCTL; /* OSTMnCTL */ +} r_io_ostm_t; + + +/* Channel array defines of OSTM (2)*/ +#ifdef DECLARE_OSTM_CHANNELS +volatile struct st_ostm* OSTM[ OSTM_COUNT ] = + /* ->MISRA 11.3 */ /* ->SEC R2.7.1 */ + OSTM_ADDRESS_LIST; + /* <-MISRA 11.3 */ /* <-SEC R2.7.1 */ +#endif /* DECLARE_OSTM_CHANNELS */ +/* End of channel array defines of OSTM (2)*/ + + +/* <-SEC M1.10.1 */ +/* <-MISRA 18.4 */ /* <-SEC M1.6.2 */ +/* <-QAC 0857 */ +/* <-QAC 0639 */ +#endif diff --git a/targets/TARGET_RENESAS/TARGET_RZ_A1XX/TARGET_GR_LYCHEE/device/inc/iodefines/riic_iodefine.h b/targets/TARGET_RENESAS/TARGET_RZ_A1XX/TARGET_GR_LYCHEE/device/inc/iodefines/riic_iodefine.h new file mode 100644 index 0000000..7696b93 --- /dev/null +++ b/targets/TARGET_RENESAS/TARGET_RZ_A1XX/TARGET_GR_LYCHEE/device/inc/iodefines/riic_iodefine.h @@ -0,0 +1,584 @@ +/******************************************************************************* +* DISCLAIMER +* This software is supplied by Renesas Electronics Corporation and is only +* intended for use with Renesas products. No other uses are authorized. This +* software is owned by Renesas Electronics Corporation and is protected under +* all applicable laws, including copyright laws. +* THIS SOFTWARE IS PROVIDED "AS IS" AND RENESAS MAKES NO WARRANTIES REGARDING +* THIS SOFTWARE, WHETHER EXPRESS, IMPLIED OR STATUTORY, INCLUDING BUT NOT +* LIMITED TO WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE +* AND NON-INFRINGEMENT. ALL SUCH WARRANTIES ARE EXPRESSLY DISCLAIMED. +* TO THE MAXIMUM EXTENT PERMITTED NOT PROHIBITED BY LAW, NEITHER RENESAS +* ELECTRONICS CORPORATION NOR ANY OF ITS AFFILIATED COMPANIES SHALL BE LIABLE +* FOR ANY DIRECT, INDIRECT, SPECIAL, INCIDENTAL OR CONSEQUENTIAL DAMAGES FOR +* ANY REASON RELATED TO THIS SOFTWARE, EVEN IF RENESAS OR ITS AFFILIATES HAVE +* BEEN ADVISED OF THE POSSIBILITY OF SUCH DAMAGES. +* Renesas reserves the right, without notice, to make changes to this software +* and to discontinue the availability of this software. By using this software, +* you agree to the additional terms and conditions found by accessing the +* following link: +* http://www.renesas.com/disclaimer* +* Copyright (C) 2013-2016 Renesas Electronics Corporation. All rights reserved. +*******************************************************************************/ +/******************************************************************************* +* File Name : riic_iodefine.h +* $Rev: $ +* $Date:: $ +* Description : Definition of I/O Register for RZ/A1LU (V3.00l) +******************************************************************************/ +#ifndef RIIC_IODEFINE_H +#define RIIC_IODEFINE_H +/* ->QAC 0639 : Over 127 members (C90) */ +/* ->QAC 0857 : Over 1024 #define (C90) */ +/* ->MISRA 18.4 : Pack unpack union */ /* ->SEC M1.6.2 */ +/* ->SEC M1.10.1 : Not magic number */ + +#define RIIC0 (*(struct st_riic *)0xFCFEE000uL) /* RIIC0 */ +#define RIIC1 (*(struct st_riic *)0xFCFEE400uL) /* RIIC1 */ +#define RIIC2 (*(struct st_riic *)0xFCFEE800uL) /* RIIC2 */ +#define RIIC3 (*(struct st_riic *)0xFCFEEC00uL) /* RIIC3 */ + + +/* Start of channel array defines of RIIC */ + +/* Channel array defines of RIIC */ +/*(Sample) value = RIIC[ channel ]->RIICnCR1.UINT32; */ +#define RIIC_COUNT (4) +#define RIIC_ADDRESS_LIST \ +{ /* ->MISRA 11.3 */ /* ->SEC R2.7.1 */ \ + &RIIC0, &RIIC1, &RIIC2, &RIIC3 \ +} /* <-MISRA 11.3 */ /* <-SEC R2.7.1 */ /* { } is for MISRA 19.4 */ + +/* End of channel array defines of RIIC */ + + +#define RIIC0CR1 (RIIC0.RIICnCR1.UINT32) +#define RIIC0CR1L (RIIC0.RIICnCR1.UINT16[R_IO_L]) +#define RIIC0CR1LL (RIIC0.RIICnCR1.UINT8[R_IO_LL]) +#define RIIC0CR1LH (RIIC0.RIICnCR1.UINT8[R_IO_LH]) +#define RIIC0CR1H (RIIC0.RIICnCR1.UINT16[R_IO_H]) +#define RIIC0CR1HL (RIIC0.RIICnCR1.UINT8[R_IO_HL]) +#define RIIC0CR1HH (RIIC0.RIICnCR1.UINT8[R_IO_HH]) +#define RIIC0CR2 (RIIC0.RIICnCR2.UINT32) +#define RIIC0CR2L (RIIC0.RIICnCR2.UINT16[R_IO_L]) +#define RIIC0CR2LL (RIIC0.RIICnCR2.UINT8[R_IO_LL]) +#define RIIC0CR2LH (RIIC0.RIICnCR2.UINT8[R_IO_LH]) +#define RIIC0CR2H (RIIC0.RIICnCR2.UINT16[R_IO_H]) +#define RIIC0CR2HL (RIIC0.RIICnCR2.UINT8[R_IO_HL]) +#define RIIC0CR2HH (RIIC0.RIICnCR2.UINT8[R_IO_HH]) +#define RIIC0MR1 (RIIC0.RIICnMR1.UINT32) +#define RIIC0MR1L (RIIC0.RIICnMR1.UINT16[R_IO_L]) +#define RIIC0MR1LL (RIIC0.RIICnMR1.UINT8[R_IO_LL]) +#define RIIC0MR1LH (RIIC0.RIICnMR1.UINT8[R_IO_LH]) +#define RIIC0MR1H (RIIC0.RIICnMR1.UINT16[R_IO_H]) +#define RIIC0MR1HL (RIIC0.RIICnMR1.UINT8[R_IO_HL]) +#define RIIC0MR1HH (RIIC0.RIICnMR1.UINT8[R_IO_HH]) +#define RIIC0MR2 (RIIC0.RIICnMR2.UINT32) +#define RIIC0MR2L (RIIC0.RIICnMR2.UINT16[R_IO_L]) +#define RIIC0MR2LL (RIIC0.RIICnMR2.UINT8[R_IO_LL]) +#define RIIC0MR2LH (RIIC0.RIICnMR2.UINT8[R_IO_LH]) +#define RIIC0MR2H (RIIC0.RIICnMR2.UINT16[R_IO_H]) +#define RIIC0MR2HL (RIIC0.RIICnMR2.UINT8[R_IO_HL]) +#define RIIC0MR2HH (RIIC0.RIICnMR2.UINT8[R_IO_HH]) +#define RIIC0MR3 (RIIC0.RIICnMR3.UINT32) +#define RIIC0MR3L (RIIC0.RIICnMR3.UINT16[R_IO_L]) +#define RIIC0MR3LL (RIIC0.RIICnMR3.UINT8[R_IO_LL]) +#define RIIC0MR3LH (RIIC0.RIICnMR3.UINT8[R_IO_LH]) +#define RIIC0MR3H (RIIC0.RIICnMR3.UINT16[R_IO_H]) +#define RIIC0MR3HL (RIIC0.RIICnMR3.UINT8[R_IO_HL]) +#define RIIC0MR3HH (RIIC0.RIICnMR3.UINT8[R_IO_HH]) +#define RIIC0FER (RIIC0.RIICnFER.UINT32) +#define RIIC0FERL (RIIC0.RIICnFER.UINT16[R_IO_L]) +#define RIIC0FERLL (RIIC0.RIICnFER.UINT8[R_IO_LL]) +#define RIIC0FERLH (RIIC0.RIICnFER.UINT8[R_IO_LH]) +#define RIIC0FERH (RIIC0.RIICnFER.UINT16[R_IO_H]) +#define RIIC0FERHL (RIIC0.RIICnFER.UINT8[R_IO_HL]) +#define RIIC0FERHH (RIIC0.RIICnFER.UINT8[R_IO_HH]) +#define RIIC0SER (RIIC0.RIICnSER.UINT32) +#define RIIC0SERL (RIIC0.RIICnSER.UINT16[R_IO_L]) +#define RIIC0SERLL (RIIC0.RIICnSER.UINT8[R_IO_LL]) +#define RIIC0SERLH (RIIC0.RIICnSER.UINT8[R_IO_LH]) +#define RIIC0SERH (RIIC0.RIICnSER.UINT16[R_IO_H]) +#define RIIC0SERHL (RIIC0.RIICnSER.UINT8[R_IO_HL]) +#define RIIC0SERHH (RIIC0.RIICnSER.UINT8[R_IO_HH]) +#define RIIC0IER (RIIC0.RIICnIER.UINT32) +#define RIIC0IERL (RIIC0.RIICnIER.UINT16[R_IO_L]) +#define RIIC0IERLL (RIIC0.RIICnIER.UINT8[R_IO_LL]) +#define RIIC0IERLH (RIIC0.RIICnIER.UINT8[R_IO_LH]) +#define RIIC0IERH (RIIC0.RIICnIER.UINT16[R_IO_H]) +#define RIIC0IERHL (RIIC0.RIICnIER.UINT8[R_IO_HL]) +#define RIIC0IERHH (RIIC0.RIICnIER.UINT8[R_IO_HH]) +#define RIIC0SR1 (RIIC0.RIICnSR1.UINT32) +#define RIIC0SR1L (RIIC0.RIICnSR1.UINT16[R_IO_L]) +#define RIIC0SR1LL (RIIC0.RIICnSR1.UINT8[R_IO_LL]) +#define RIIC0SR1LH (RIIC0.RIICnSR1.UINT8[R_IO_LH]) +#define RIIC0SR1H (RIIC0.RIICnSR1.UINT16[R_IO_H]) +#define RIIC0SR1HL (RIIC0.RIICnSR1.UINT8[R_IO_HL]) +#define RIIC0SR1HH (RIIC0.RIICnSR1.UINT8[R_IO_HH]) +#define RIIC0SR2 (RIIC0.RIICnSR2.UINT32) +#define RIIC0SR2L (RIIC0.RIICnSR2.UINT16[R_IO_L]) +#define RIIC0SR2LL (RIIC0.RIICnSR2.UINT8[R_IO_LL]) +#define RIIC0SR2LH (RIIC0.RIICnSR2.UINT8[R_IO_LH]) +#define RIIC0SR2H (RIIC0.RIICnSR2.UINT16[R_IO_H]) +#define RIIC0SR2HL (RIIC0.RIICnSR2.UINT8[R_IO_HL]) +#define RIIC0SR2HH (RIIC0.RIICnSR2.UINT8[R_IO_HH]) +#define RIIC0SAR0 (RIIC0.RIICnSAR0.UINT32) +#define RIIC0SAR0L (RIIC0.RIICnSAR0.UINT16[R_IO_L]) +#define RIIC0SAR0LL (RIIC0.RIICnSAR0.UINT8[R_IO_LL]) +#define RIIC0SAR0LH (RIIC0.RIICnSAR0.UINT8[R_IO_LH]) +#define RIIC0SAR0H (RIIC0.RIICnSAR0.UINT16[R_IO_H]) +#define RIIC0SAR0HL (RIIC0.RIICnSAR0.UINT8[R_IO_HL]) +#define RIIC0SAR0HH (RIIC0.RIICnSAR0.UINT8[R_IO_HH]) +#define RIIC0SAR1 (RIIC0.RIICnSAR1.UINT32) +#define RIIC0SAR1L (RIIC0.RIICnSAR1.UINT16[R_IO_L]) +#define RIIC0SAR1LL (RIIC0.RIICnSAR1.UINT8[R_IO_LL]) +#define RIIC0SAR1LH (RIIC0.RIICnSAR1.UINT8[R_IO_LH]) +#define RIIC0SAR1H (RIIC0.RIICnSAR1.UINT16[R_IO_H]) +#define RIIC0SAR1HL (RIIC0.RIICnSAR1.UINT8[R_IO_HL]) +#define RIIC0SAR1HH (RIIC0.RIICnSAR1.UINT8[R_IO_HH]) +#define RIIC0SAR2 (RIIC0.RIICnSAR2.UINT32) +#define RIIC0SAR2L (RIIC0.RIICnSAR2.UINT16[R_IO_L]) +#define RIIC0SAR2LL (RIIC0.RIICnSAR2.UINT8[R_IO_LL]) +#define RIIC0SAR2LH (RIIC0.RIICnSAR2.UINT8[R_IO_LH]) +#define RIIC0SAR2H (RIIC0.RIICnSAR2.UINT16[R_IO_H]) +#define RIIC0SAR2HL (RIIC0.RIICnSAR2.UINT8[R_IO_HL]) +#define RIIC0SAR2HH (RIIC0.RIICnSAR2.UINT8[R_IO_HH]) +#define RIIC0BRL (RIIC0.RIICnBRL.UINT32) +#define RIIC0BRLL (RIIC0.RIICnBRL.UINT16[R_IO_L]) +#define RIIC0BRLLL (RIIC0.RIICnBRL.UINT8[R_IO_LL]) +#define RIIC0BRLLH (RIIC0.RIICnBRL.UINT8[R_IO_LH]) +#define RIIC0BRLH (RIIC0.RIICnBRL.UINT16[R_IO_H]) +#define RIIC0BRLHL (RIIC0.RIICnBRL.UINT8[R_IO_HL]) +#define RIIC0BRLHH (RIIC0.RIICnBRL.UINT8[R_IO_HH]) +#define RIIC0BRH (RIIC0.RIICnBRH.UINT32) +#define RIIC0BRHL (RIIC0.RIICnBRH.UINT16[R_IO_L]) +#define RIIC0BRHLL (RIIC0.RIICnBRH.UINT8[R_IO_LL]) +#define RIIC0BRHLH (RIIC0.RIICnBRH.UINT8[R_IO_LH]) +#define RIIC0BRHH (RIIC0.RIICnBRH.UINT16[R_IO_H]) +#define RIIC0BRHHL (RIIC0.RIICnBRH.UINT8[R_IO_HL]) +#define RIIC0BRHHH (RIIC0.RIICnBRH.UINT8[R_IO_HH]) +#define RIIC0DRT (RIIC0.RIICnDRT.UINT32) +#define RIIC0DRTL (RIIC0.RIICnDRT.UINT16[R_IO_L]) +#define RIIC0DRTLL (RIIC0.RIICnDRT.UINT8[R_IO_LL]) +#define RIIC0DRTLH (RIIC0.RIICnDRT.UINT8[R_IO_LH]) +#define RIIC0DRTH (RIIC0.RIICnDRT.UINT16[R_IO_H]) +#define RIIC0DRTHL (RIIC0.RIICnDRT.UINT8[R_IO_HL]) +#define RIIC0DRTHH (RIIC0.RIICnDRT.UINT8[R_IO_HH]) +#define RIIC0DRR (RIIC0.RIICnDRR.UINT32) +#define RIIC0DRRL (RIIC0.RIICnDRR.UINT16[R_IO_L]) +#define RIIC0DRRLL (RIIC0.RIICnDRR.UINT8[R_IO_LL]) +#define RIIC0DRRLH (RIIC0.RIICnDRR.UINT8[R_IO_LH]) +#define RIIC0DRRH (RIIC0.RIICnDRR.UINT16[R_IO_H]) +#define RIIC0DRRHL (RIIC0.RIICnDRR.UINT8[R_IO_HL]) +#define RIIC0DRRHH (RIIC0.RIICnDRR.UINT8[R_IO_HH]) +#define RIIC1CR1 (RIIC1.RIICnCR1.UINT32) +#define RIIC1CR1L (RIIC1.RIICnCR1.UINT16[R_IO_L]) +#define RIIC1CR1LL (RIIC1.RIICnCR1.UINT8[R_IO_LL]) +#define RIIC1CR1LH (RIIC1.RIICnCR1.UINT8[R_IO_LH]) +#define RIIC1CR1H (RIIC1.RIICnCR1.UINT16[R_IO_H]) +#define RIIC1CR1HL (RIIC1.RIICnCR1.UINT8[R_IO_HL]) +#define RIIC1CR1HH (RIIC1.RIICnCR1.UINT8[R_IO_HH]) +#define RIIC1CR2 (RIIC1.RIICnCR2.UINT32) +#define RIIC1CR2L (RIIC1.RIICnCR2.UINT16[R_IO_L]) +#define RIIC1CR2LL (RIIC1.RIICnCR2.UINT8[R_IO_LL]) +#define RIIC1CR2LH (RIIC1.RIICnCR2.UINT8[R_IO_LH]) +#define RIIC1CR2H (RIIC1.RIICnCR2.UINT16[R_IO_H]) +#define RIIC1CR2HL (RIIC1.RIICnCR2.UINT8[R_IO_HL]) +#define RIIC1CR2HH (RIIC1.RIICnCR2.UINT8[R_IO_HH]) +#define RIIC1MR1 (RIIC1.RIICnMR1.UINT32) +#define RIIC1MR1L (RIIC1.RIICnMR1.UINT16[R_IO_L]) +#define RIIC1MR1LL (RIIC1.RIICnMR1.UINT8[R_IO_LL]) +#define RIIC1MR1LH (RIIC1.RIICnMR1.UINT8[R_IO_LH]) +#define RIIC1MR1H (RIIC1.RIICnMR1.UINT16[R_IO_H]) +#define RIIC1MR1HL (RIIC1.RIICnMR1.UINT8[R_IO_HL]) +#define RIIC1MR1HH (RIIC1.RIICnMR1.UINT8[R_IO_HH]) +#define RIIC1MR2 (RIIC1.RIICnMR2.UINT32) +#define RIIC1MR2L (RIIC1.RIICnMR2.UINT16[R_IO_L]) +#define RIIC1MR2LL (RIIC1.RIICnMR2.UINT8[R_IO_LL]) +#define RIIC1MR2LH (RIIC1.RIICnMR2.UINT8[R_IO_LH]) +#define RIIC1MR2H (RIIC1.RIICnMR2.UINT16[R_IO_H]) +#define RIIC1MR2HL (RIIC1.RIICnMR2.UINT8[R_IO_HL]) +#define RIIC1MR2HH (RIIC1.RIICnMR2.UINT8[R_IO_HH]) +#define RIIC1MR3 (RIIC1.RIICnMR3.UINT32) +#define RIIC1MR3L (RIIC1.RIICnMR3.UINT16[R_IO_L]) +#define RIIC1MR3LL (RIIC1.RIICnMR3.UINT8[R_IO_LL]) +#define RIIC1MR3LH (RIIC1.RIICnMR3.UINT8[R_IO_LH]) +#define RIIC1MR3H (RIIC1.RIICnMR3.UINT16[R_IO_H]) +#define RIIC1MR3HL (RIIC1.RIICnMR3.UINT8[R_IO_HL]) +#define RIIC1MR3HH (RIIC1.RIICnMR3.UINT8[R_IO_HH]) +#define RIIC1FER (RIIC1.RIICnFER.UINT32) +#define RIIC1FERL (RIIC1.RIICnFER.UINT16[R_IO_L]) +#define RIIC1FERLL (RIIC1.RIICnFER.UINT8[R_IO_LL]) +#define RIIC1FERLH (RIIC1.RIICnFER.UINT8[R_IO_LH]) +#define RIIC1FERH (RIIC1.RIICnFER.UINT16[R_IO_H]) +#define RIIC1FERHL (RIIC1.RIICnFER.UINT8[R_IO_HL]) +#define RIIC1FERHH (RIIC1.RIICnFER.UINT8[R_IO_HH]) +#define RIIC1SER (RIIC1.RIICnSER.UINT32) +#define RIIC1SERL (RIIC1.RIICnSER.UINT16[R_IO_L]) +#define RIIC1SERLL (RIIC1.RIICnSER.UINT8[R_IO_LL]) +#define RIIC1SERLH (RIIC1.RIICnSER.UINT8[R_IO_LH]) +#define RIIC1SERH (RIIC1.RIICnSER.UINT16[R_IO_H]) +#define RIIC1SERHL (RIIC1.RIICnSER.UINT8[R_IO_HL]) +#define RIIC1SERHH (RIIC1.RIICnSER.UINT8[R_IO_HH]) +#define RIIC1IER (RIIC1.RIICnIER.UINT32) +#define RIIC1IERL (RIIC1.RIICnIER.UINT16[R_IO_L]) +#define RIIC1IERLL (RIIC1.RIICnIER.UINT8[R_IO_LL]) +#define RIIC1IERLH (RIIC1.RIICnIER.UINT8[R_IO_LH]) +#define RIIC1IERH (RIIC1.RIICnIER.UINT16[R_IO_H]) +#define RIIC1IERHL (RIIC1.RIICnIER.UINT8[R_IO_HL]) +#define RIIC1IERHH (RIIC1.RIICnIER.UINT8[R_IO_HH]) +#define RIIC1SR1 (RIIC1.RIICnSR1.UINT32) +#define RIIC1SR1L (RIIC1.RIICnSR1.UINT16[R_IO_L]) +#define RIIC1SR1LL (RIIC1.RIICnSR1.UINT8[R_IO_LL]) +#define RIIC1SR1LH (RIIC1.RIICnSR1.UINT8[R_IO_LH]) +#define RIIC1SR1H (RIIC1.RIICnSR1.UINT16[R_IO_H]) +#define RIIC1SR1HL (RIIC1.RIICnSR1.UINT8[R_IO_HL]) +#define RIIC1SR1HH (RIIC1.RIICnSR1.UINT8[R_IO_HH]) +#define RIIC1SR2 (RIIC1.RIICnSR2.UINT32) +#define RIIC1SR2L (RIIC1.RIICnSR2.UINT16[R_IO_L]) +#define RIIC1SR2LL (RIIC1.RIICnSR2.UINT8[R_IO_LL]) +#define RIIC1SR2LH (RIIC1.RIICnSR2.UINT8[R_IO_LH]) +#define RIIC1SR2H (RIIC1.RIICnSR2.UINT16[R_IO_H]) +#define RIIC1SR2HL (RIIC1.RIICnSR2.UINT8[R_IO_HL]) +#define RIIC1SR2HH (RIIC1.RIICnSR2.UINT8[R_IO_HH]) +#define RIIC1SAR0 (RIIC1.RIICnSAR0.UINT32) +#define RIIC1SAR0L (RIIC1.RIICnSAR0.UINT16[R_IO_L]) +#define RIIC1SAR0LL (RIIC1.RIICnSAR0.UINT8[R_IO_LL]) +#define RIIC1SAR0LH (RIIC1.RIICnSAR0.UINT8[R_IO_LH]) +#define RIIC1SAR0H (RIIC1.RIICnSAR0.UINT16[R_IO_H]) +#define RIIC1SAR0HL (RIIC1.RIICnSAR0.UINT8[R_IO_HL]) +#define RIIC1SAR0HH (RIIC1.RIICnSAR0.UINT8[R_IO_HH]) +#define RIIC1SAR1 (RIIC1.RIICnSAR1.UINT32) +#define RIIC1SAR1L (RIIC1.RIICnSAR1.UINT16[R_IO_L]) +#define RIIC1SAR1LL (RIIC1.RIICnSAR1.UINT8[R_IO_LL]) +#define RIIC1SAR1LH (RIIC1.RIICnSAR1.UINT8[R_IO_LH]) +#define RIIC1SAR1H (RIIC1.RIICnSAR1.UINT16[R_IO_H]) +#define RIIC1SAR1HL (RIIC1.RIICnSAR1.UINT8[R_IO_HL]) +#define RIIC1SAR1HH (RIIC1.RIICnSAR1.UINT8[R_IO_HH]) +#define RIIC1SAR2 (RIIC1.RIICnSAR2.UINT32) +#define RIIC1SAR2L (RIIC1.RIICnSAR2.UINT16[R_IO_L]) +#define RIIC1SAR2LL (RIIC1.RIICnSAR2.UINT8[R_IO_LL]) +#define RIIC1SAR2LH (RIIC1.RIICnSAR2.UINT8[R_IO_LH]) +#define RIIC1SAR2H (RIIC1.RIICnSAR2.UINT16[R_IO_H]) +#define RIIC1SAR2HL (RIIC1.RIICnSAR2.UINT8[R_IO_HL]) +#define RIIC1SAR2HH (RIIC1.RIICnSAR2.UINT8[R_IO_HH]) +#define RIIC1BRL (RIIC1.RIICnBRL.UINT32) +#define RIIC1BRLL (RIIC1.RIICnBRL.UINT16[R_IO_L]) +#define RIIC1BRLLL (RIIC1.RIICnBRL.UINT8[R_IO_LL]) +#define RIIC1BRLLH (RIIC1.RIICnBRL.UINT8[R_IO_LH]) +#define RIIC1BRLH (RIIC1.RIICnBRL.UINT16[R_IO_H]) +#define RIIC1BRLHL (RIIC1.RIICnBRL.UINT8[R_IO_HL]) +#define RIIC1BRLHH (RIIC1.RIICnBRL.UINT8[R_IO_HH]) +#define RIIC1BRH (RIIC1.RIICnBRH.UINT32) +#define RIIC1BRHL (RIIC1.RIICnBRH.UINT16[R_IO_L]) +#define RIIC1BRHLL (RIIC1.RIICnBRH.UINT8[R_IO_LL]) +#define RIIC1BRHLH (RIIC1.RIICnBRH.UINT8[R_IO_LH]) +#define RIIC1BRHH (RIIC1.RIICnBRH.UINT16[R_IO_H]) +#define RIIC1BRHHL (RIIC1.RIICnBRH.UINT8[R_IO_HL]) +#define RIIC1BRHHH (RIIC1.RIICnBRH.UINT8[R_IO_HH]) +#define RIIC1DRT (RIIC1.RIICnDRT.UINT32) +#define RIIC1DRTL (RIIC1.RIICnDRT.UINT16[R_IO_L]) +#define RIIC1DRTLL (RIIC1.RIICnDRT.UINT8[R_IO_LL]) +#define RIIC1DRTLH (RIIC1.RIICnDRT.UINT8[R_IO_LH]) +#define RIIC1DRTH (RIIC1.RIICnDRT.UINT16[R_IO_H]) +#define RIIC1DRTHL (RIIC1.RIICnDRT.UINT8[R_IO_HL]) +#define RIIC1DRTHH (RIIC1.RIICnDRT.UINT8[R_IO_HH]) +#define RIIC1DRR (RIIC1.RIICnDRR.UINT32) +#define RIIC1DRRL (RIIC1.RIICnDRR.UINT16[R_IO_L]) +#define RIIC1DRRLL (RIIC1.RIICnDRR.UINT8[R_IO_LL]) +#define RIIC1DRRLH (RIIC1.RIICnDRR.UINT8[R_IO_LH]) +#define RIIC1DRRH (RIIC1.RIICnDRR.UINT16[R_IO_H]) +#define RIIC1DRRHL (RIIC1.RIICnDRR.UINT8[R_IO_HL]) +#define RIIC1DRRHH (RIIC1.RIICnDRR.UINT8[R_IO_HH]) +#define RIIC2CR1 (RIIC2.RIICnCR1.UINT32) +#define RIIC2CR1L (RIIC2.RIICnCR1.UINT16[R_IO_L]) +#define RIIC2CR1LL (RIIC2.RIICnCR1.UINT8[R_IO_LL]) +#define RIIC2CR1LH (RIIC2.RIICnCR1.UINT8[R_IO_LH]) +#define RIIC2CR1H (RIIC2.RIICnCR1.UINT16[R_IO_H]) +#define RIIC2CR1HL (RIIC2.RIICnCR1.UINT8[R_IO_HL]) +#define RIIC2CR1HH (RIIC2.RIICnCR1.UINT8[R_IO_HH]) +#define RIIC2CR2 (RIIC2.RIICnCR2.UINT32) +#define RIIC2CR2L (RIIC2.RIICnCR2.UINT16[R_IO_L]) +#define RIIC2CR2LL (RIIC2.RIICnCR2.UINT8[R_IO_LL]) +#define RIIC2CR2LH (RIIC2.RIICnCR2.UINT8[R_IO_LH]) +#define RIIC2CR2H (RIIC2.RIICnCR2.UINT16[R_IO_H]) +#define RIIC2CR2HL (RIIC2.RIICnCR2.UINT8[R_IO_HL]) +#define RIIC2CR2HH (RIIC2.RIICnCR2.UINT8[R_IO_HH]) +#define RIIC2MR1 (RIIC2.RIICnMR1.UINT32) +#define RIIC2MR1L (RIIC2.RIICnMR1.UINT16[R_IO_L]) +#define RIIC2MR1LL (RIIC2.RIICnMR1.UINT8[R_IO_LL]) +#define RIIC2MR1LH (RIIC2.RIICnMR1.UINT8[R_IO_LH]) +#define RIIC2MR1H (RIIC2.RIICnMR1.UINT16[R_IO_H]) +#define RIIC2MR1HL (RIIC2.RIICnMR1.UINT8[R_IO_HL]) +#define RIIC2MR1HH (RIIC2.RIICnMR1.UINT8[R_IO_HH]) +#define RIIC2MR2 (RIIC2.RIICnMR2.UINT32) +#define RIIC2MR2L (RIIC2.RIICnMR2.UINT16[R_IO_L]) +#define RIIC2MR2LL (RIIC2.RIICnMR2.UINT8[R_IO_LL]) +#define RIIC2MR2LH (RIIC2.RIICnMR2.UINT8[R_IO_LH]) +#define RIIC2MR2H (RIIC2.RIICnMR2.UINT16[R_IO_H]) +#define RIIC2MR2HL (RIIC2.RIICnMR2.UINT8[R_IO_HL]) +#define RIIC2MR2HH (RIIC2.RIICnMR2.UINT8[R_IO_HH]) +#define RIIC2MR3 (RIIC2.RIICnMR3.UINT32) +#define RIIC2MR3L (RIIC2.RIICnMR3.UINT16[R_IO_L]) +#define RIIC2MR3LL (RIIC2.RIICnMR3.UINT8[R_IO_LL]) +#define RIIC2MR3LH (RIIC2.RIICnMR3.UINT8[R_IO_LH]) +#define RIIC2MR3H (RIIC2.RIICnMR3.UINT16[R_IO_H]) +#define RIIC2MR3HL (RIIC2.RIICnMR3.UINT8[R_IO_HL]) +#define RIIC2MR3HH (RIIC2.RIICnMR3.UINT8[R_IO_HH]) +#define RIIC2FER (RIIC2.RIICnFER.UINT32) +#define RIIC2FERL (RIIC2.RIICnFER.UINT16[R_IO_L]) +#define RIIC2FERLL (RIIC2.RIICnFER.UINT8[R_IO_LL]) +#define RIIC2FERLH (RIIC2.RIICnFER.UINT8[R_IO_LH]) +#define RIIC2FERH (RIIC2.RIICnFER.UINT16[R_IO_H]) +#define RIIC2FERHL (RIIC2.RIICnFER.UINT8[R_IO_HL]) +#define RIIC2FERHH (RIIC2.RIICnFER.UINT8[R_IO_HH]) +#define RIIC2SER (RIIC2.RIICnSER.UINT32) +#define RIIC2SERL (RIIC2.RIICnSER.UINT16[R_IO_L]) +#define RIIC2SERLL (RIIC2.RIICnSER.UINT8[R_IO_LL]) +#define RIIC2SERLH (RIIC2.RIICnSER.UINT8[R_IO_LH]) +#define RIIC2SERH (RIIC2.RIICnSER.UINT16[R_IO_H]) +#define RIIC2SERHL (RIIC2.RIICnSER.UINT8[R_IO_HL]) +#define RIIC2SERHH (RIIC2.RIICnSER.UINT8[R_IO_HH]) +#define RIIC2IER (RIIC2.RIICnIER.UINT32) +#define RIIC2IERL (RIIC2.RIICnIER.UINT16[R_IO_L]) +#define RIIC2IERLL (RIIC2.RIICnIER.UINT8[R_IO_LL]) +#define RIIC2IERLH (RIIC2.RIICnIER.UINT8[R_IO_LH]) +#define RIIC2IERH (RIIC2.RIICnIER.UINT16[R_IO_H]) +#define RIIC2IERHL (RIIC2.RIICnIER.UINT8[R_IO_HL]) +#define RIIC2IERHH (RIIC2.RIICnIER.UINT8[R_IO_HH]) +#define RIIC2SR1 (RIIC2.RIICnSR1.UINT32) +#define RIIC2SR1L (RIIC2.RIICnSR1.UINT16[R_IO_L]) +#define RIIC2SR1LL (RIIC2.RIICnSR1.UINT8[R_IO_LL]) +#define RIIC2SR1LH (RIIC2.RIICnSR1.UINT8[R_IO_LH]) +#define RIIC2SR1H (RIIC2.RIICnSR1.UINT16[R_IO_H]) +#define RIIC2SR1HL (RIIC2.RIICnSR1.UINT8[R_IO_HL]) +#define RIIC2SR1HH (RIIC2.RIICnSR1.UINT8[R_IO_HH]) +#define RIIC2SR2 (RIIC2.RIICnSR2.UINT32) +#define RIIC2SR2L (RIIC2.RIICnSR2.UINT16[R_IO_L]) +#define RIIC2SR2LL (RIIC2.RIICnSR2.UINT8[R_IO_LL]) +#define RIIC2SR2LH (RIIC2.RIICnSR2.UINT8[R_IO_LH]) +#define RIIC2SR2H (RIIC2.RIICnSR2.UINT16[R_IO_H]) +#define RIIC2SR2HL (RIIC2.RIICnSR2.UINT8[R_IO_HL]) +#define RIIC2SR2HH (RIIC2.RIICnSR2.UINT8[R_IO_HH]) +#define RIIC2SAR0 (RIIC2.RIICnSAR0.UINT32) +#define RIIC2SAR0L (RIIC2.RIICnSAR0.UINT16[R_IO_L]) +#define RIIC2SAR0LL (RIIC2.RIICnSAR0.UINT8[R_IO_LL]) +#define RIIC2SAR0LH (RIIC2.RIICnSAR0.UINT8[R_IO_LH]) +#define RIIC2SAR0H (RIIC2.RIICnSAR0.UINT16[R_IO_H]) +#define RIIC2SAR0HL (RIIC2.RIICnSAR0.UINT8[R_IO_HL]) +#define RIIC2SAR0HH (RIIC2.RIICnSAR0.UINT8[R_IO_HH]) +#define RIIC2SAR1 (RIIC2.RIICnSAR1.UINT32) +#define RIIC2SAR1L (RIIC2.RIICnSAR1.UINT16[R_IO_L]) +#define RIIC2SAR1LL (RIIC2.RIICnSAR1.UINT8[R_IO_LL]) +#define RIIC2SAR1LH (RIIC2.RIICnSAR1.UINT8[R_IO_LH]) +#define RIIC2SAR1H (RIIC2.RIICnSAR1.UINT16[R_IO_H]) +#define RIIC2SAR1HL (RIIC2.RIICnSAR1.UINT8[R_IO_HL]) +#define RIIC2SAR1HH (RIIC2.RIICnSAR1.UINT8[R_IO_HH]) +#define RIIC2SAR2 (RIIC2.RIICnSAR2.UINT32) +#define RIIC2SAR2L (RIIC2.RIICnSAR2.UINT16[R_IO_L]) +#define RIIC2SAR2LL (RIIC2.RIICnSAR2.UINT8[R_IO_LL]) +#define RIIC2SAR2LH (RIIC2.RIICnSAR2.UINT8[R_IO_LH]) +#define RIIC2SAR2H (RIIC2.RIICnSAR2.UINT16[R_IO_H]) +#define RIIC2SAR2HL (RIIC2.RIICnSAR2.UINT8[R_IO_HL]) +#define RIIC2SAR2HH (RIIC2.RIICnSAR2.UINT8[R_IO_HH]) +#define RIIC2BRL (RIIC2.RIICnBRL.UINT32) +#define RIIC2BRLL (RIIC2.RIICnBRL.UINT16[R_IO_L]) +#define RIIC2BRLLL (RIIC2.RIICnBRL.UINT8[R_IO_LL]) +#define RIIC2BRLLH (RIIC2.RIICnBRL.UINT8[R_IO_LH]) +#define RIIC2BRLH (RIIC2.RIICnBRL.UINT16[R_IO_H]) +#define RIIC2BRLHL (RIIC2.RIICnBRL.UINT8[R_IO_HL]) +#define RIIC2BRLHH (RIIC2.RIICnBRL.UINT8[R_IO_HH]) +#define RIIC2BRH (RIIC2.RIICnBRH.UINT32) +#define RIIC2BRHL (RIIC2.RIICnBRH.UINT16[R_IO_L]) +#define RIIC2BRHLL (RIIC2.RIICnBRH.UINT8[R_IO_LL]) +#define RIIC2BRHLH (RIIC2.RIICnBRH.UINT8[R_IO_LH]) +#define RIIC2BRHH (RIIC2.RIICnBRH.UINT16[R_IO_H]) +#define RIIC2BRHHL (RIIC2.RIICnBRH.UINT8[R_IO_HL]) +#define RIIC2BRHHH (RIIC2.RIICnBRH.UINT8[R_IO_HH]) +#define RIIC2DRT (RIIC2.RIICnDRT.UINT32) +#define RIIC2DRTL (RIIC2.RIICnDRT.UINT16[R_IO_L]) +#define RIIC2DRTLL (RIIC2.RIICnDRT.UINT8[R_IO_LL]) +#define RIIC2DRTLH (RIIC2.RIICnDRT.UINT8[R_IO_LH]) +#define RIIC2DRTH (RIIC2.RIICnDRT.UINT16[R_IO_H]) +#define RIIC2DRTHL (RIIC2.RIICnDRT.UINT8[R_IO_HL]) +#define RIIC2DRTHH (RIIC2.RIICnDRT.UINT8[R_IO_HH]) +#define RIIC2DRR (RIIC2.RIICnDRR.UINT32) +#define RIIC2DRRL (RIIC2.RIICnDRR.UINT16[R_IO_L]) +#define RIIC2DRRLL (RIIC2.RIICnDRR.UINT8[R_IO_LL]) +#define RIIC2DRRLH (RIIC2.RIICnDRR.UINT8[R_IO_LH]) +#define RIIC2DRRH (RIIC2.RIICnDRR.UINT16[R_IO_H]) +#define RIIC2DRRHL (RIIC2.RIICnDRR.UINT8[R_IO_HL]) +#define RIIC2DRRHH (RIIC2.RIICnDRR.UINT8[R_IO_HH]) +#define RIIC3CR1 (RIIC3.RIICnCR1.UINT32) +#define RIIC3CR1L (RIIC3.RIICnCR1.UINT16[R_IO_L]) +#define RIIC3CR1LL (RIIC3.RIICnCR1.UINT8[R_IO_LL]) +#define RIIC3CR1LH (RIIC3.RIICnCR1.UINT8[R_IO_LH]) +#define RIIC3CR1H (RIIC3.RIICnCR1.UINT16[R_IO_H]) +#define RIIC3CR1HL (RIIC3.RIICnCR1.UINT8[R_IO_HL]) +#define RIIC3CR1HH (RIIC3.RIICnCR1.UINT8[R_IO_HH]) +#define RIIC3CR2 (RIIC3.RIICnCR2.UINT32) +#define RIIC3CR2L (RIIC3.RIICnCR2.UINT16[R_IO_L]) +#define RIIC3CR2LL (RIIC3.RIICnCR2.UINT8[R_IO_LL]) +#define RIIC3CR2LH (RIIC3.RIICnCR2.UINT8[R_IO_LH]) +#define RIIC3CR2H (RIIC3.RIICnCR2.UINT16[R_IO_H]) +#define RIIC3CR2HL (RIIC3.RIICnCR2.UINT8[R_IO_HL]) +#define RIIC3CR2HH (RIIC3.RIICnCR2.UINT8[R_IO_HH]) +#define RIIC3MR1 (RIIC3.RIICnMR1.UINT32) +#define RIIC3MR1L (RIIC3.RIICnMR1.UINT16[R_IO_L]) +#define RIIC3MR1LL (RIIC3.RIICnMR1.UINT8[R_IO_LL]) +#define RIIC3MR1LH (RIIC3.RIICnMR1.UINT8[R_IO_LH]) +#define RIIC3MR1H (RIIC3.RIICnMR1.UINT16[R_IO_H]) +#define RIIC3MR1HL (RIIC3.RIICnMR1.UINT8[R_IO_HL]) +#define RIIC3MR1HH (RIIC3.RIICnMR1.UINT8[R_IO_HH]) +#define RIIC3MR2 (RIIC3.RIICnMR2.UINT32) +#define RIIC3MR2L (RIIC3.RIICnMR2.UINT16[R_IO_L]) +#define RIIC3MR2LL (RIIC3.RIICnMR2.UINT8[R_IO_LL]) +#define RIIC3MR2LH (RIIC3.RIICnMR2.UINT8[R_IO_LH]) +#define RIIC3MR2H (RIIC3.RIICnMR2.UINT16[R_IO_H]) +#define RIIC3MR2HL (RIIC3.RIICnMR2.UINT8[R_IO_HL]) +#define RIIC3MR2HH (RIIC3.RIICnMR2.UINT8[R_IO_HH]) +#define RIIC3MR3 (RIIC3.RIICnMR3.UINT32) +#define RIIC3MR3L (RIIC3.RIICnMR3.UINT16[R_IO_L]) +#define RIIC3MR3LL (RIIC3.RIICnMR3.UINT8[R_IO_LL]) +#define RIIC3MR3LH (RIIC3.RIICnMR3.UINT8[R_IO_LH]) +#define RIIC3MR3H (RIIC3.RIICnMR3.UINT16[R_IO_H]) +#define RIIC3MR3HL (RIIC3.RIICnMR3.UINT8[R_IO_HL]) +#define RIIC3MR3HH (RIIC3.RIICnMR3.UINT8[R_IO_HH]) +#define RIIC3FER (RIIC3.RIICnFER.UINT32) +#define RIIC3FERL (RIIC3.RIICnFER.UINT16[R_IO_L]) +#define RIIC3FERLL (RIIC3.RIICnFER.UINT8[R_IO_LL]) +#define RIIC3FERLH (RIIC3.RIICnFER.UINT8[R_IO_LH]) +#define RIIC3FERH (RIIC3.RIICnFER.UINT16[R_IO_H]) +#define RIIC3FERHL (RIIC3.RIICnFER.UINT8[R_IO_HL]) +#define RIIC3FERHH (RIIC3.RIICnFER.UINT8[R_IO_HH]) +#define RIIC3SER (RIIC3.RIICnSER.UINT32) +#define RIIC3SERL (RIIC3.RIICnSER.UINT16[R_IO_L]) +#define RIIC3SERLL (RIIC3.RIICnSER.UINT8[R_IO_LL]) +#define RIIC3SERLH (RIIC3.RIICnSER.UINT8[R_IO_LH]) +#define RIIC3SERH (RIIC3.RIICnSER.UINT16[R_IO_H]) +#define RIIC3SERHL (RIIC3.RIICnSER.UINT8[R_IO_HL]) +#define RIIC3SERHH (RIIC3.RIICnSER.UINT8[R_IO_HH]) +#define RIIC3IER (RIIC3.RIICnIER.UINT32) +#define RIIC3IERL (RIIC3.RIICnIER.UINT16[R_IO_L]) +#define RIIC3IERLL (RIIC3.RIICnIER.UINT8[R_IO_LL]) +#define RIIC3IERLH (RIIC3.RIICnIER.UINT8[R_IO_LH]) +#define RIIC3IERH (RIIC3.RIICnIER.UINT16[R_IO_H]) +#define RIIC3IERHL (RIIC3.RIICnIER.UINT8[R_IO_HL]) +#define RIIC3IERHH (RIIC3.RIICnIER.UINT8[R_IO_HH]) +#define RIIC3SR1 (RIIC3.RIICnSR1.UINT32) +#define RIIC3SR1L (RIIC3.RIICnSR1.UINT16[R_IO_L]) +#define RIIC3SR1LL (RIIC3.RIICnSR1.UINT8[R_IO_LL]) +#define RIIC3SR1LH (RIIC3.RIICnSR1.UINT8[R_IO_LH]) +#define RIIC3SR1H (RIIC3.RIICnSR1.UINT16[R_IO_H]) +#define RIIC3SR1HL (RIIC3.RIICnSR1.UINT8[R_IO_HL]) +#define RIIC3SR1HH (RIIC3.RIICnSR1.UINT8[R_IO_HH]) +#define RIIC3SR2 (RIIC3.RIICnSR2.UINT32) +#define RIIC3SR2L (RIIC3.RIICnSR2.UINT16[R_IO_L]) +#define RIIC3SR2LL (RIIC3.RIICnSR2.UINT8[R_IO_LL]) +#define RIIC3SR2LH (RIIC3.RIICnSR2.UINT8[R_IO_LH]) +#define RIIC3SR2H (RIIC3.RIICnSR2.UINT16[R_IO_H]) +#define RIIC3SR2HL (RIIC3.RIICnSR2.UINT8[R_IO_HL]) +#define RIIC3SR2HH (RIIC3.RIICnSR2.UINT8[R_IO_HH]) +#define RIIC3SAR0 (RIIC3.RIICnSAR0.UINT32) +#define RIIC3SAR0L (RIIC3.RIICnSAR0.UINT16[R_IO_L]) +#define RIIC3SAR0LL (RIIC3.RIICnSAR0.UINT8[R_IO_LL]) +#define RIIC3SAR0LH (RIIC3.RIICnSAR0.UINT8[R_IO_LH]) +#define RIIC3SAR0H (RIIC3.RIICnSAR0.UINT16[R_IO_H]) +#define RIIC3SAR0HL (RIIC3.RIICnSAR0.UINT8[R_IO_HL]) +#define RIIC3SAR0HH (RIIC3.RIICnSAR0.UINT8[R_IO_HH]) +#define RIIC3SAR1 (RIIC3.RIICnSAR1.UINT32) +#define RIIC3SAR1L (RIIC3.RIICnSAR1.UINT16[R_IO_L]) +#define RIIC3SAR1LL (RIIC3.RIICnSAR1.UINT8[R_IO_LL]) +#define RIIC3SAR1LH (RIIC3.RIICnSAR1.UINT8[R_IO_LH]) +#define RIIC3SAR1H (RIIC3.RIICnSAR1.UINT16[R_IO_H]) +#define RIIC3SAR1HL (RIIC3.RIICnSAR1.UINT8[R_IO_HL]) +#define RIIC3SAR1HH (RIIC3.RIICnSAR1.UINT8[R_IO_HH]) +#define RIIC3SAR2 (RIIC3.RIICnSAR2.UINT32) +#define RIIC3SAR2L (RIIC3.RIICnSAR2.UINT16[R_IO_L]) +#define RIIC3SAR2LL (RIIC3.RIICnSAR2.UINT8[R_IO_LL]) +#define RIIC3SAR2LH (RIIC3.RIICnSAR2.UINT8[R_IO_LH]) +#define RIIC3SAR2H (RIIC3.RIICnSAR2.UINT16[R_IO_H]) +#define RIIC3SAR2HL (RIIC3.RIICnSAR2.UINT8[R_IO_HL]) +#define RIIC3SAR2HH (RIIC3.RIICnSAR2.UINT8[R_IO_HH]) +#define RIIC3BRL (RIIC3.RIICnBRL.UINT32) +#define RIIC3BRLL (RIIC3.RIICnBRL.UINT16[R_IO_L]) +#define RIIC3BRLLL (RIIC3.RIICnBRL.UINT8[R_IO_LL]) +#define RIIC3BRLLH (RIIC3.RIICnBRL.UINT8[R_IO_LH]) +#define RIIC3BRLH (RIIC3.RIICnBRL.UINT16[R_IO_H]) +#define RIIC3BRLHL (RIIC3.RIICnBRL.UINT8[R_IO_HL]) +#define RIIC3BRLHH (RIIC3.RIICnBRL.UINT8[R_IO_HH]) +#define RIIC3BRH (RIIC3.RIICnBRH.UINT32) +#define RIIC3BRHL (RIIC3.RIICnBRH.UINT16[R_IO_L]) +#define RIIC3BRHLL (RIIC3.RIICnBRH.UINT8[R_IO_LL]) +#define RIIC3BRHLH (RIIC3.RIICnBRH.UINT8[R_IO_LH]) +#define RIIC3BRHH (RIIC3.RIICnBRH.UINT16[R_IO_H]) +#define RIIC3BRHHL (RIIC3.RIICnBRH.UINT8[R_IO_HL]) +#define RIIC3BRHHH (RIIC3.RIICnBRH.UINT8[R_IO_HH]) +#define RIIC3DRT (RIIC3.RIICnDRT.UINT32) +#define RIIC3DRTL (RIIC3.RIICnDRT.UINT16[R_IO_L]) +#define RIIC3DRTLL (RIIC3.RIICnDRT.UINT8[R_IO_LL]) +#define RIIC3DRTLH (RIIC3.RIICnDRT.UINT8[R_IO_LH]) +#define RIIC3DRTH (RIIC3.RIICnDRT.UINT16[R_IO_H]) +#define RIIC3DRTHL (RIIC3.RIICnDRT.UINT8[R_IO_HL]) +#define RIIC3DRTHH (RIIC3.RIICnDRT.UINT8[R_IO_HH]) +#define RIIC3DRR (RIIC3.RIICnDRR.UINT32) +#define RIIC3DRRL (RIIC3.RIICnDRR.UINT16[R_IO_L]) +#define RIIC3DRRLL (RIIC3.RIICnDRR.UINT8[R_IO_LL]) +#define RIIC3DRRLH (RIIC3.RIICnDRR.UINT8[R_IO_LH]) +#define RIIC3DRRH (RIIC3.RIICnDRR.UINT16[R_IO_H]) +#define RIIC3DRRHL (RIIC3.RIICnDRR.UINT8[R_IO_HL]) +#define RIIC3DRRHH (RIIC3.RIICnDRR.UINT8[R_IO_HH]) + +#define RIICnCRm_COUNT (2) +#define RIICnMRm_COUNT (3) +#define RIICnSRm_COUNT (2) +#define RIICnSARm_COUNT (3) + + +typedef struct st_riic +{ + /* RIIC */ + +/* #define RIICnCRm_COUNT (2) */ + union iodefine_reg32_t RIICnCR1; /* RIICnCR1 */ + union iodefine_reg32_t RIICnCR2; /* RIICnCR2 */ + +/* #define RIICnMRm_COUNT (3) */ + union iodefine_reg32_t RIICnMR1; /* RIICnMR1 */ + union iodefine_reg32_t RIICnMR2; /* RIICnMR2 */ + union iodefine_reg32_t RIICnMR3; /* RIICnMR3 */ + union iodefine_reg32_t RIICnFER; /* RIICnFER */ + union iodefine_reg32_t RIICnSER; /* RIICnSER */ + union iodefine_reg32_t RIICnIER; /* RIICnIER */ + +/* #define RIICnSRm_COUNT (2) */ + union iodefine_reg32_t RIICnSR1; /* RIICnSR1 */ + union iodefine_reg32_t RIICnSR2; /* RIICnSR2 */ + +/* #define RIICnSARm_COUNT (3) */ + union iodefine_reg32_t RIICnSAR0; /* RIICnSAR0 */ + union iodefine_reg32_t RIICnSAR1; /* RIICnSAR1 */ + union iodefine_reg32_t RIICnSAR2; /* RIICnSAR2 */ + union iodefine_reg32_t RIICnBRL; /* RIICnBRL */ + union iodefine_reg32_t RIICnBRH; /* RIICnBRH */ + union iodefine_reg32_t RIICnDRT; /* RIICnDRT */ + union iodefine_reg32_t RIICnDRR; /* RIICnDRR */ + +} r_io_riic_t; + + +/* Channel array defines of RIIC (2)*/ +#ifdef DECLARE_RIIC_CHANNELS +volatile struct st_riic* RIIC[ RIIC_COUNT ] = + /* ->MISRA 11.3 */ /* ->SEC R2.7.1 */ + RIIC_ADDRESS_LIST; + /* <-MISRA 11.3 */ /* <-SEC R2.7.1 */ +#endif /* DECLARE_RIIC_CHANNELS */ +/* End of channel array defines of RIIC (2)*/ + + +/* <-SEC M1.10.1 */ +/* <-MISRA 18.4 */ /* <-SEC M1.6.2 */ +/* <-QAC 0857 */ +/* <-QAC 0639 */ +#endif diff --git a/targets/TARGET_RENESAS/TARGET_RZ_A1XX/TARGET_GR_LYCHEE/device/inc/iodefines/rscan0_iodefine.h b/targets/TARGET_RENESAS/TARGET_RZ_A1XX/TARGET_GR_LYCHEE/device/inc/iodefines/rscan0_iodefine.h new file mode 100644 index 0000000..f32e219 --- /dev/null +++ b/targets/TARGET_RENESAS/TARGET_RZ_A1XX/TARGET_GR_LYCHEE/device/inc/iodefines/rscan0_iodefine.h @@ -0,0 +1,4653 @@ +/******************************************************************************* +* DISCLAIMER +* This software is supplied by Renesas Electronics Corporation and is only +* intended for use with Renesas products. No other uses are authorized. This +* software is owned by Renesas Electronics Corporation and is protected under +* all applicable laws, including copyright laws. +* THIS SOFTWARE IS PROVIDED "AS IS" AND RENESAS MAKES NO WARRANTIES REGARDING +* THIS SOFTWARE, WHETHER EXPRESS, IMPLIED OR STATUTORY, INCLUDING BUT NOT +* LIMITED TO WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE +* AND NON-INFRINGEMENT. ALL SUCH WARRANTIES ARE EXPRESSLY DISCLAIMED. +* TO THE MAXIMUM EXTENT PERMITTED NOT PROHIBITED BY LAW, NEITHER RENESAS +* ELECTRONICS CORPORATION NOR ANY OF ITS AFFILIATED COMPANIES SHALL BE LIABLE +* FOR ANY DIRECT, INDIRECT, SPECIAL, INCIDENTAL OR CONSEQUENTIAL DAMAGES FOR +* ANY REASON RELATED TO THIS SOFTWARE, EVEN IF RENESAS OR ITS AFFILIATES HAVE +* BEEN ADVISED OF THE POSSIBILITY OF SUCH DAMAGES. +* Renesas reserves the right, without notice, to make changes to this software +* and to discontinue the availability of this software. By using this software, +* you agree to the additional terms and conditions found by accessing the +* following link: +* http://www.renesas.com/disclaimer* +* Copyright (C) 2013-2016 Renesas Electronics Corporation. All rights reserved. +*******************************************************************************/ +/******************************************************************************* +* File Name : rscan0_iodefine.h +* $Rev: $ +* $Date:: $ +* Description : Definition of I/O Register for RZ/A1LU (V3.00l) +******************************************************************************/ +#ifndef RSCAN0_IODEFINE_H +#define RSCAN0_IODEFINE_H +/* ->QAC 0639 : Over 127 members (C90) */ +/* ->QAC 0857 : Over 1024 #define (C90) */ +/* ->MISRA 18.4 : Pack unpack union */ /* ->SEC M1.6.2 */ +/* ->SEC M1.10.1 : Not magic number */ + +#define RSCAN0 (*(struct st_rscan0 *)0xE803A000uL) /* RSCAN0 */ + + +/* Start of channel array defines of RSCAN0 */ + +/* Channel array defines of RSCAN_FROM_RSCAN0_CFIDm */ +/*(Sample) value = RSCAN_FROM_RSCAN0_CFIDm[ channel ]->CFIDm.UINT32; */ +#define RSCAN_FROM_RSCAN0_CFIDm_COUNT (6) +#define RSCAN_FROM_RSCAN0_CFIDm_ADDRESS_LIST \ +{ /* ->MISRA 11.3 */ /* ->SEC R2.7.1 */ \ + &RSCAN_FROM_RSCAN0CFID0, &RSCAN_FROM_RSCAN0CFID1, &RSCAN_FROM_RSCAN0CFID2, &RSCAN_FROM_RSCAN0CFID3, &RSCAN_FROM_RSCAN0CFID4, &RSCAN_FROM_RSCAN0CFID5 \ +} /* <-MISRA 11.3 */ /* <-SEC R2.7.1 */ /* { } is for MISRA 19.4 */ +#define RSCAN_FROM_RSCAN0CFID0 (*(struct st_rscan_from_rscan0cfidm *)&RSCAN0.CFID0) /* RSCAN_FROM_RSCAN0CFID0 */ +#define RSCAN_FROM_RSCAN0CFID1 (*(struct st_rscan_from_rscan0cfidm *)&RSCAN0.CFID1) /* RSCAN_FROM_RSCAN0CFID1 */ +#define RSCAN_FROM_RSCAN0CFID2 (*(struct st_rscan_from_rscan0cfidm *)&RSCAN0.CFID2) /* RSCAN_FROM_RSCAN0CFID2 */ +#define RSCAN_FROM_RSCAN0CFID3 (*(struct st_rscan_from_rscan0cfidm *)&RSCAN0.CFID3) /* RSCAN_FROM_RSCAN0CFID3 */ +#define RSCAN_FROM_RSCAN0CFID4 (*(struct st_rscan_from_rscan0cfidm *)&RSCAN0.CFID4) /* RSCAN_FROM_RSCAN0CFID4 */ +#define RSCAN_FROM_RSCAN0CFID5 (*(struct st_rscan_from_rscan0cfidm *)&RSCAN0.CFID5) /* RSCAN_FROM_RSCAN0CFID5 */ + + +/* Channel array defines of RSCAN_FROM_RSCAN0_TMIDp */ +/*(Sample) value = RSCAN_FROM_RSCAN0_TMIDp[ channel ]->TMIDp.UINT32; */ +#define RSCAN_FROM_RSCAN0_TMIDp_COUNT (32) +#define RSCAN_FROM_RSCAN0_TMIDp_ADDRESS_LIST \ +{ /* ->MISRA 11.3 */ /* ->SEC R2.7.1 */ \ + &RSCAN_FROM_RSCAN0TMID0, &RSCAN_FROM_RSCAN0TMID1, &RSCAN_FROM_RSCAN0TMID2, &RSCAN_FROM_RSCAN0TMID3, &RSCAN_FROM_RSCAN0TMID4, &RSCAN_FROM_RSCAN0TMID5, &RSCAN_FROM_RSCAN0TMID6, &RSCAN_FROM_RSCAN0TMID7, \ + &RSCAN_FROM_RSCAN0TMID8, &RSCAN_FROM_RSCAN0TMID9, &RSCAN_FROM_RSCAN0TMID10, &RSCAN_FROM_RSCAN0TMID11, &RSCAN_FROM_RSCAN0TMID12, &RSCAN_FROM_RSCAN0TMID13, &RSCAN_FROM_RSCAN0TMID14, &RSCAN_FROM_RSCAN0TMID15, \ + &RSCAN_FROM_RSCAN0TMID16, &RSCAN_FROM_RSCAN0TMID17, &RSCAN_FROM_RSCAN0TMID18, &RSCAN_FROM_RSCAN0TMID19, &RSCAN_FROM_RSCAN0TMID20, &RSCAN_FROM_RSCAN0TMID21, &RSCAN_FROM_RSCAN0TMID22, &RSCAN_FROM_RSCAN0TMID23, \ + &RSCAN_FROM_RSCAN0TMID24, &RSCAN_FROM_RSCAN0TMID25, &RSCAN_FROM_RSCAN0TMID26, &RSCAN_FROM_RSCAN0TMID27, &RSCAN_FROM_RSCAN0TMID28, &RSCAN_FROM_RSCAN0TMID29, &RSCAN_FROM_RSCAN0TMID30, &RSCAN_FROM_RSCAN0TMID31 \ +} /* <-MISRA 11.3 */ /* <-SEC R2.7.1 */ /* { } is for MISRA 19.4 */ +#define RSCAN_FROM_RSCAN0TMID0 (*(struct st_rscan_from_rscan0tmidp *)&RSCAN0.TMID0) /* RSCAN_FROM_RSCAN0TMID0 */ +#define RSCAN_FROM_RSCAN0TMID1 (*(struct st_rscan_from_rscan0tmidp *)&RSCAN0.TMID1) /* RSCAN_FROM_RSCAN0TMID1 */ +#define RSCAN_FROM_RSCAN0TMID2 (*(struct st_rscan_from_rscan0tmidp *)&RSCAN0.TMID2) /* RSCAN_FROM_RSCAN0TMID2 */ +#define RSCAN_FROM_RSCAN0TMID3 (*(struct st_rscan_from_rscan0tmidp *)&RSCAN0.TMID3) /* RSCAN_FROM_RSCAN0TMID3 */ +#define RSCAN_FROM_RSCAN0TMID4 (*(struct st_rscan_from_rscan0tmidp *)&RSCAN0.TMID4) /* RSCAN_FROM_RSCAN0TMID4 */ +#define RSCAN_FROM_RSCAN0TMID5 (*(struct st_rscan_from_rscan0tmidp *)&RSCAN0.TMID5) /* RSCAN_FROM_RSCAN0TMID5 */ +#define RSCAN_FROM_RSCAN0TMID6 (*(struct st_rscan_from_rscan0tmidp *)&RSCAN0.TMID6) /* RSCAN_FROM_RSCAN0TMID6 */ +#define RSCAN_FROM_RSCAN0TMID7 (*(struct st_rscan_from_rscan0tmidp *)&RSCAN0.TMID7) /* RSCAN_FROM_RSCAN0TMID7 */ +#define RSCAN_FROM_RSCAN0TMID8 (*(struct st_rscan_from_rscan0tmidp *)&RSCAN0.TMID8) /* RSCAN_FROM_RSCAN0TMID8 */ +#define RSCAN_FROM_RSCAN0TMID9 (*(struct st_rscan_from_rscan0tmidp *)&RSCAN0.TMID9) /* RSCAN_FROM_RSCAN0TMID9 */ +#define RSCAN_FROM_RSCAN0TMID10 (*(struct st_rscan_from_rscan0tmidp *)&RSCAN0.TMID10) /* RSCAN_FROM_RSCAN0TMID10 */ +#define RSCAN_FROM_RSCAN0TMID11 (*(struct st_rscan_from_rscan0tmidp *)&RSCAN0.TMID11) /* RSCAN_FROM_RSCAN0TMID11 */ +#define RSCAN_FROM_RSCAN0TMID12 (*(struct st_rscan_from_rscan0tmidp *)&RSCAN0.TMID12) /* RSCAN_FROM_RSCAN0TMID12 */ +#define RSCAN_FROM_RSCAN0TMID13 (*(struct st_rscan_from_rscan0tmidp *)&RSCAN0.TMID13) /* RSCAN_FROM_RSCAN0TMID13 */ +#define RSCAN_FROM_RSCAN0TMID14 (*(struct st_rscan_from_rscan0tmidp *)&RSCAN0.TMID14) /* RSCAN_FROM_RSCAN0TMID14 */ +#define RSCAN_FROM_RSCAN0TMID15 (*(struct st_rscan_from_rscan0tmidp *)&RSCAN0.TMID15) /* RSCAN_FROM_RSCAN0TMID15 */ +#define RSCAN_FROM_RSCAN0TMID16 (*(struct st_rscan_from_rscan0tmidp *)&RSCAN0.TMID16) /* RSCAN_FROM_RSCAN0TMID16 */ +#define RSCAN_FROM_RSCAN0TMID17 (*(struct st_rscan_from_rscan0tmidp *)&RSCAN0.TMID17) /* RSCAN_FROM_RSCAN0TMID17 */ +#define RSCAN_FROM_RSCAN0TMID18 (*(struct st_rscan_from_rscan0tmidp *)&RSCAN0.TMID18) /* RSCAN_FROM_RSCAN0TMID18 */ +#define RSCAN_FROM_RSCAN0TMID19 (*(struct st_rscan_from_rscan0tmidp *)&RSCAN0.TMID19) /* RSCAN_FROM_RSCAN0TMID19 */ +#define RSCAN_FROM_RSCAN0TMID20 (*(struct st_rscan_from_rscan0tmidp *)&RSCAN0.TMID20) /* RSCAN_FROM_RSCAN0TMID20 */ +#define RSCAN_FROM_RSCAN0TMID21 (*(struct st_rscan_from_rscan0tmidp *)&RSCAN0.TMID21) /* RSCAN_FROM_RSCAN0TMID21 */ +#define RSCAN_FROM_RSCAN0TMID22 (*(struct st_rscan_from_rscan0tmidp *)&RSCAN0.TMID22) /* RSCAN_FROM_RSCAN0TMID22 */ +#define RSCAN_FROM_RSCAN0TMID23 (*(struct st_rscan_from_rscan0tmidp *)&RSCAN0.TMID23) /* RSCAN_FROM_RSCAN0TMID23 */ +#define RSCAN_FROM_RSCAN0TMID24 (*(struct st_rscan_from_rscan0tmidp *)&RSCAN0.TMID24) /* RSCAN_FROM_RSCAN0TMID24 */ +#define RSCAN_FROM_RSCAN0TMID25 (*(struct st_rscan_from_rscan0tmidp *)&RSCAN0.TMID25) /* RSCAN_FROM_RSCAN0TMID25 */ +#define RSCAN_FROM_RSCAN0TMID26 (*(struct st_rscan_from_rscan0tmidp *)&RSCAN0.TMID26) /* RSCAN_FROM_RSCAN0TMID26 */ +#define RSCAN_FROM_RSCAN0TMID27 (*(struct st_rscan_from_rscan0tmidp *)&RSCAN0.TMID27) /* RSCAN_FROM_RSCAN0TMID27 */ +#define RSCAN_FROM_RSCAN0TMID28 (*(struct st_rscan_from_rscan0tmidp *)&RSCAN0.TMID28) /* RSCAN_FROM_RSCAN0TMID28 */ +#define RSCAN_FROM_RSCAN0TMID29 (*(struct st_rscan_from_rscan0tmidp *)&RSCAN0.TMID29) /* RSCAN_FROM_RSCAN0TMID29 */ +#define RSCAN_FROM_RSCAN0TMID30 (*(struct st_rscan_from_rscan0tmidp *)&RSCAN0.TMID30) /* RSCAN_FROM_RSCAN0TMID30 */ +#define RSCAN_FROM_RSCAN0TMID31 (*(struct st_rscan_from_rscan0tmidp *)&RSCAN0.TMID31) /* RSCAN_FROM_RSCAN0TMID31 */ + + +/* Channel array defines of RSCAN_FROM_RSCAN0_RFIDm */ +/*(Sample) value = RSCAN_FROM_RSCAN0_RFIDm[ channel ]->RFIDm.UINT32; */ +#define RSCAN_FROM_RSCAN0_RFIDm_COUNT (8) +#define RSCAN_FROM_RSCAN0_RFIDm_ADDRESS_LIST \ +{ /* ->MISRA 11.3 */ /* ->SEC R2.7.1 */ \ + &RSCAN_FROM_RSCAN0RFID0, &RSCAN_FROM_RSCAN0RFID1, &RSCAN_FROM_RSCAN0RFID2, &RSCAN_FROM_RSCAN0RFID3, &RSCAN_FROM_RSCAN0RFID4, &RSCAN_FROM_RSCAN0RFID5, &RSCAN_FROM_RSCAN0RFID6, &RSCAN_FROM_RSCAN0RFID7 \ +} /* <-MISRA 11.3 */ /* <-SEC R2.7.1 */ /* { } is for MISRA 19.4 */ +#define RSCAN_FROM_RSCAN0RFID0 (*(struct st_rscan_from_rscan0rfidm *)&RSCAN0.RFID0) /* RSCAN_FROM_RSCAN0RFID0 */ +#define RSCAN_FROM_RSCAN0RFID1 (*(struct st_rscan_from_rscan0rfidm *)&RSCAN0.RFID1) /* RSCAN_FROM_RSCAN0RFID1 */ +#define RSCAN_FROM_RSCAN0RFID2 (*(struct st_rscan_from_rscan0rfidm *)&RSCAN0.RFID2) /* RSCAN_FROM_RSCAN0RFID2 */ +#define RSCAN_FROM_RSCAN0RFID3 (*(struct st_rscan_from_rscan0rfidm *)&RSCAN0.RFID3) /* RSCAN_FROM_RSCAN0RFID3 */ +#define RSCAN_FROM_RSCAN0RFID4 (*(struct st_rscan_from_rscan0rfidm *)&RSCAN0.RFID4) /* RSCAN_FROM_RSCAN0RFID4 */ +#define RSCAN_FROM_RSCAN0RFID5 (*(struct st_rscan_from_rscan0rfidm *)&RSCAN0.RFID5) /* RSCAN_FROM_RSCAN0RFID5 */ +#define RSCAN_FROM_RSCAN0RFID6 (*(struct st_rscan_from_rscan0rfidm *)&RSCAN0.RFID6) /* RSCAN_FROM_RSCAN0RFID6 */ +#define RSCAN_FROM_RSCAN0RFID7 (*(struct st_rscan_from_rscan0rfidm *)&RSCAN0.RFID7) /* RSCAN_FROM_RSCAN0RFID7 */ + + +/* Channel array defines of RSCAN_FROM_RSCAN0_RMIDp */ +/*(Sample) value = RSCAN_FROM_RSCAN0_RMIDp[ channel ]->RMIDp.UINT32; */ +#define RSCAN_FROM_RSCAN0_RMIDp_COUNT (32) +#define RSCAN_FROM_RSCAN0_RMIDp_ADDRESS_LIST \ +{ /* ->MISRA 11.3 */ /* ->SEC R2.7.1 */ \ + &RSCAN_FROM_RSCAN0RMID0, &RSCAN_FROM_RSCAN0RMID1, &RSCAN_FROM_RSCAN0RMID2, &RSCAN_FROM_RSCAN0RMID3, &RSCAN_FROM_RSCAN0RMID4, &RSCAN_FROM_RSCAN0RMID5, &RSCAN_FROM_RSCAN0RMID6, &RSCAN_FROM_RSCAN0RMID7, \ + &RSCAN_FROM_RSCAN0RMID8, &RSCAN_FROM_RSCAN0RMID9, &RSCAN_FROM_RSCAN0RMID10, &RSCAN_FROM_RSCAN0RMID11, &RSCAN_FROM_RSCAN0RMID12, &RSCAN_FROM_RSCAN0RMID13, &RSCAN_FROM_RSCAN0RMID14, &RSCAN_FROM_RSCAN0RMID15, \ + &RSCAN_FROM_RSCAN0RMID16, &RSCAN_FROM_RSCAN0RMID17, &RSCAN_FROM_RSCAN0RMID18, &RSCAN_FROM_RSCAN0RMID19, &RSCAN_FROM_RSCAN0RMID20, &RSCAN_FROM_RSCAN0RMID21, &RSCAN_FROM_RSCAN0RMID22, &RSCAN_FROM_RSCAN0RMID23, \ + &RSCAN_FROM_RSCAN0RMID24, &RSCAN_FROM_RSCAN0RMID25, &RSCAN_FROM_RSCAN0RMID26, &RSCAN_FROM_RSCAN0RMID27, &RSCAN_FROM_RSCAN0RMID28, &RSCAN_FROM_RSCAN0RMID29, &RSCAN_FROM_RSCAN0RMID30, &RSCAN_FROM_RSCAN0RMID31 \ +} /* <-MISRA 11.3 */ /* <-SEC R2.7.1 */ /* { } is for MISRA 19.4 */ +#define RSCAN_FROM_RSCAN0RMID0 (*(struct st_rscan_from_rscan0rmidp *)&RSCAN0.RMID0) /* RSCAN_FROM_RSCAN0RMID0 */ +#define RSCAN_FROM_RSCAN0RMID1 (*(struct st_rscan_from_rscan0rmidp *)&RSCAN0.RMID1) /* RSCAN_FROM_RSCAN0RMID1 */ +#define RSCAN_FROM_RSCAN0RMID2 (*(struct st_rscan_from_rscan0rmidp *)&RSCAN0.RMID2) /* RSCAN_FROM_RSCAN0RMID2 */ +#define RSCAN_FROM_RSCAN0RMID3 (*(struct st_rscan_from_rscan0rmidp *)&RSCAN0.RMID3) /* RSCAN_FROM_RSCAN0RMID3 */ +#define RSCAN_FROM_RSCAN0RMID4 (*(struct st_rscan_from_rscan0rmidp *)&RSCAN0.RMID4) /* RSCAN_FROM_RSCAN0RMID4 */ +#define RSCAN_FROM_RSCAN0RMID5 (*(struct st_rscan_from_rscan0rmidp *)&RSCAN0.RMID5) /* RSCAN_FROM_RSCAN0RMID5 */ +#define RSCAN_FROM_RSCAN0RMID6 (*(struct st_rscan_from_rscan0rmidp *)&RSCAN0.RMID6) /* RSCAN_FROM_RSCAN0RMID6 */ +#define RSCAN_FROM_RSCAN0RMID7 (*(struct st_rscan_from_rscan0rmidp *)&RSCAN0.RMID7) /* RSCAN_FROM_RSCAN0RMID7 */ +#define RSCAN_FROM_RSCAN0RMID8 (*(struct st_rscan_from_rscan0rmidp *)&RSCAN0.RMID8) /* RSCAN_FROM_RSCAN0RMID8 */ +#define RSCAN_FROM_RSCAN0RMID9 (*(struct st_rscan_from_rscan0rmidp *)&RSCAN0.RMID9) /* RSCAN_FROM_RSCAN0RMID9 */ +#define RSCAN_FROM_RSCAN0RMID10 (*(struct st_rscan_from_rscan0rmidp *)&RSCAN0.RMID10) /* RSCAN_FROM_RSCAN0RMID10 */ +#define RSCAN_FROM_RSCAN0RMID11 (*(struct st_rscan_from_rscan0rmidp *)&RSCAN0.RMID11) /* RSCAN_FROM_RSCAN0RMID11 */ +#define RSCAN_FROM_RSCAN0RMID12 (*(struct st_rscan_from_rscan0rmidp *)&RSCAN0.RMID12) /* RSCAN_FROM_RSCAN0RMID12 */ +#define RSCAN_FROM_RSCAN0RMID13 (*(struct st_rscan_from_rscan0rmidp *)&RSCAN0.RMID13) /* RSCAN_FROM_RSCAN0RMID13 */ +#define RSCAN_FROM_RSCAN0RMID14 (*(struct st_rscan_from_rscan0rmidp *)&RSCAN0.RMID14) /* RSCAN_FROM_RSCAN0RMID14 */ +#define RSCAN_FROM_RSCAN0RMID15 (*(struct st_rscan_from_rscan0rmidp *)&RSCAN0.RMID15) /* RSCAN_FROM_RSCAN0RMID15 */ +#define RSCAN_FROM_RSCAN0RMID16 (*(struct st_rscan_from_rscan0rmidp *)&RSCAN0.RMID16) /* RSCAN_FROM_RSCAN0RMID16 */ +#define RSCAN_FROM_RSCAN0RMID17 (*(struct st_rscan_from_rscan0rmidp *)&RSCAN0.RMID17) /* RSCAN_FROM_RSCAN0RMID17 */ +#define RSCAN_FROM_RSCAN0RMID18 (*(struct st_rscan_from_rscan0rmidp *)&RSCAN0.RMID18) /* RSCAN_FROM_RSCAN0RMID18 */ +#define RSCAN_FROM_RSCAN0RMID19 (*(struct st_rscan_from_rscan0rmidp *)&RSCAN0.RMID19) /* RSCAN_FROM_RSCAN0RMID19 */ +#define RSCAN_FROM_RSCAN0RMID20 (*(struct st_rscan_from_rscan0rmidp *)&RSCAN0.RMID20) /* RSCAN_FROM_RSCAN0RMID20 */ +#define RSCAN_FROM_RSCAN0RMID21 (*(struct st_rscan_from_rscan0rmidp *)&RSCAN0.RMID21) /* RSCAN_FROM_RSCAN0RMID21 */ +#define RSCAN_FROM_RSCAN0RMID22 (*(struct st_rscan_from_rscan0rmidp *)&RSCAN0.RMID22) /* RSCAN_FROM_RSCAN0RMID22 */ +#define RSCAN_FROM_RSCAN0RMID23 (*(struct st_rscan_from_rscan0rmidp *)&RSCAN0.RMID23) /* RSCAN_FROM_RSCAN0RMID23 */ +#define RSCAN_FROM_RSCAN0RMID24 (*(struct st_rscan_from_rscan0rmidp *)&RSCAN0.RMID24) /* RSCAN_FROM_RSCAN0RMID24 */ +#define RSCAN_FROM_RSCAN0RMID25 (*(struct st_rscan_from_rscan0rmidp *)&RSCAN0.RMID25) /* RSCAN_FROM_RSCAN0RMID25 */ +#define RSCAN_FROM_RSCAN0RMID26 (*(struct st_rscan_from_rscan0rmidp *)&RSCAN0.RMID26) /* RSCAN_FROM_RSCAN0RMID26 */ +#define RSCAN_FROM_RSCAN0RMID27 (*(struct st_rscan_from_rscan0rmidp *)&RSCAN0.RMID27) /* RSCAN_FROM_RSCAN0RMID27 */ +#define RSCAN_FROM_RSCAN0RMID28 (*(struct st_rscan_from_rscan0rmidp *)&RSCAN0.RMID28) /* RSCAN_FROM_RSCAN0RMID28 */ +#define RSCAN_FROM_RSCAN0RMID29 (*(struct st_rscan_from_rscan0rmidp *)&RSCAN0.RMID29) /* RSCAN_FROM_RSCAN0RMID29 */ +#define RSCAN_FROM_RSCAN0RMID30 (*(struct st_rscan_from_rscan0rmidp *)&RSCAN0.RMID30) /* RSCAN_FROM_RSCAN0RMID30 */ +#define RSCAN_FROM_RSCAN0RMID31 (*(struct st_rscan_from_rscan0rmidp *)&RSCAN0.RMID31) /* RSCAN_FROM_RSCAN0RMID31 */ + + +/* Channel array defines of RSCAN_FROM_RSCAN0_GAFLIDj */ +/*(Sample) value = RSCAN_FROM_RSCAN0_GAFLIDj[ channel ]->GAFLIDj.UINT32; */ +#define RSCAN_FROM_RSCAN0_GAFLIDj_COUNT (16) +#define RSCAN_FROM_RSCAN0_GAFLIDj_ADDRESS_LIST \ +{ /* ->MISRA 11.3 */ /* ->SEC R2.7.1 */ \ + &RSCAN_FROM_RSCAN0GAFLID0, &RSCAN_FROM_RSCAN0GAFLID1, &RSCAN_FROM_RSCAN0GAFLID2, &RSCAN_FROM_RSCAN0GAFLID3, &RSCAN_FROM_RSCAN0GAFLID4, &RSCAN_FROM_RSCAN0GAFLID5, &RSCAN_FROM_RSCAN0GAFLID6, &RSCAN_FROM_RSCAN0GAFLID7, \ + &RSCAN_FROM_RSCAN0GAFLID8, &RSCAN_FROM_RSCAN0GAFLID9, &RSCAN_FROM_RSCAN0GAFLID10, &RSCAN_FROM_RSCAN0GAFLID11, &RSCAN_FROM_RSCAN0GAFLID12, &RSCAN_FROM_RSCAN0GAFLID13, &RSCAN_FROM_RSCAN0GAFLID14, &RSCAN_FROM_RSCAN0GAFLID15 \ +} /* <-MISRA 11.3 */ /* <-SEC R2.7.1 */ /* { } is for MISRA 19.4 */ +#define RSCAN_FROM_RSCAN0GAFLID0 (*(struct st_rscan_from_rscan0gaflidj *)&RSCAN0.GAFLID0) /* RSCAN_FROM_RSCAN0GAFLID0 */ +#define RSCAN_FROM_RSCAN0GAFLID1 (*(struct st_rscan_from_rscan0gaflidj *)&RSCAN0.GAFLID1) /* RSCAN_FROM_RSCAN0GAFLID1 */ +#define RSCAN_FROM_RSCAN0GAFLID2 (*(struct st_rscan_from_rscan0gaflidj *)&RSCAN0.GAFLID2) /* RSCAN_FROM_RSCAN0GAFLID2 */ +#define RSCAN_FROM_RSCAN0GAFLID3 (*(struct st_rscan_from_rscan0gaflidj *)&RSCAN0.GAFLID3) /* RSCAN_FROM_RSCAN0GAFLID3 */ +#define RSCAN_FROM_RSCAN0GAFLID4 (*(struct st_rscan_from_rscan0gaflidj *)&RSCAN0.GAFLID4) /* RSCAN_FROM_RSCAN0GAFLID4 */ +#define RSCAN_FROM_RSCAN0GAFLID5 (*(struct st_rscan_from_rscan0gaflidj *)&RSCAN0.GAFLID5) /* RSCAN_FROM_RSCAN0GAFLID5 */ +#define RSCAN_FROM_RSCAN0GAFLID6 (*(struct st_rscan_from_rscan0gaflidj *)&RSCAN0.GAFLID6) /* RSCAN_FROM_RSCAN0GAFLID6 */ +#define RSCAN_FROM_RSCAN0GAFLID7 (*(struct st_rscan_from_rscan0gaflidj *)&RSCAN0.GAFLID7) /* RSCAN_FROM_RSCAN0GAFLID7 */ +#define RSCAN_FROM_RSCAN0GAFLID8 (*(struct st_rscan_from_rscan0gaflidj *)&RSCAN0.GAFLID8) /* RSCAN_FROM_RSCAN0GAFLID8 */ +#define RSCAN_FROM_RSCAN0GAFLID9 (*(struct st_rscan_from_rscan0gaflidj *)&RSCAN0.GAFLID9) /* RSCAN_FROM_RSCAN0GAFLID9 */ +#define RSCAN_FROM_RSCAN0GAFLID10 (*(struct st_rscan_from_rscan0gaflidj *)&RSCAN0.GAFLID10) /* RSCAN_FROM_RSCAN0GAFLID10 */ +#define RSCAN_FROM_RSCAN0GAFLID11 (*(struct st_rscan_from_rscan0gaflidj *)&RSCAN0.GAFLID11) /* RSCAN_FROM_RSCAN0GAFLID11 */ +#define RSCAN_FROM_RSCAN0GAFLID12 (*(struct st_rscan_from_rscan0gaflidj *)&RSCAN0.GAFLID12) /* RSCAN_FROM_RSCAN0GAFLID12 */ +#define RSCAN_FROM_RSCAN0GAFLID13 (*(struct st_rscan_from_rscan0gaflidj *)&RSCAN0.GAFLID13) /* RSCAN_FROM_RSCAN0GAFLID13 */ +#define RSCAN_FROM_RSCAN0GAFLID14 (*(struct st_rscan_from_rscan0gaflidj *)&RSCAN0.GAFLID14) /* RSCAN_FROM_RSCAN0GAFLID14 */ +#define RSCAN_FROM_RSCAN0GAFLID15 (*(struct st_rscan_from_rscan0gaflidj *)&RSCAN0.GAFLID15) /* RSCAN_FROM_RSCAN0GAFLID15 */ + + +/* Channel array defines of RSCAN_FROM_RSCAN0_CnCFG */ +/*(Sample) value = RSCAN_FROM_RSCAN0_CnCFG[ channel ]->CnCFG.UINT32; */ +#define RSCAN_FROM_RSCAN0_CnCFG_COUNT (2) +#define RSCAN_FROM_RSCAN0_CnCFG_ADDRESS_LIST \ +{ /* ->MISRA 11.3 */ /* ->SEC R2.7.1 */ \ + &RSCAN_FROM_RSCAN0C0CFG, &RSCAN_FROM_RSCAN0C1CFG \ +} /* <-MISRA 11.3 */ /* <-SEC R2.7.1 */ /* { } is for MISRA 19.4 */ +#define RSCAN_FROM_RSCAN0C0CFG (*(struct st_rscan_from_rscan0cncfg *)&RSCAN0.C0CFG) /* RSCAN_FROM_RSCAN0C0CFG */ +#define RSCAN_FROM_RSCAN0C1CFG (*(struct st_rscan_from_rscan0cncfg *)&RSCAN0.C1CFG) /* RSCAN_FROM_RSCAN0C1CFG */ + +/* End of channel array defines of RSCAN0 */ + + +#define RSCAN0C0CFG (RSCAN0.C0CFG.UINT32) +#define RSCAN0C0CFGL (RSCAN0.C0CFG.UINT16[R_IO_L]) +#define RSCAN0C0CFGLL (RSCAN0.C0CFG.UINT8[R_IO_LL]) +#define RSCAN0C0CFGLH (RSCAN0.C0CFG.UINT8[R_IO_LH]) +#define RSCAN0C0CFGH (RSCAN0.C0CFG.UINT16[R_IO_H]) +#define RSCAN0C0CFGHL (RSCAN0.C0CFG.UINT8[R_IO_HL]) +#define RSCAN0C0CFGHH (RSCAN0.C0CFG.UINT8[R_IO_HH]) +#define RSCAN0C0CTR (RSCAN0.C0CTR.UINT32) +#define RSCAN0C0CTRL (RSCAN0.C0CTR.UINT16[R_IO_L]) +#define RSCAN0C0CTRLL (RSCAN0.C0CTR.UINT8[R_IO_LL]) +#define RSCAN0C0CTRLH (RSCAN0.C0CTR.UINT8[R_IO_LH]) +#define RSCAN0C0CTRH (RSCAN0.C0CTR.UINT16[R_IO_H]) +#define RSCAN0C0CTRHL (RSCAN0.C0CTR.UINT8[R_IO_HL]) +#define RSCAN0C0CTRHH (RSCAN0.C0CTR.UINT8[R_IO_HH]) +#define RSCAN0C0STS (RSCAN0.C0STS.UINT32) +#define RSCAN0C0STSL (RSCAN0.C0STS.UINT16[R_IO_L]) +#define RSCAN0C0STSLL (RSCAN0.C0STS.UINT8[R_IO_LL]) +#define RSCAN0C0STSLH (RSCAN0.C0STS.UINT8[R_IO_LH]) +#define RSCAN0C0STSH (RSCAN0.C0STS.UINT16[R_IO_H]) +#define RSCAN0C0STSHL (RSCAN0.C0STS.UINT8[R_IO_HL]) +#define RSCAN0C0STSHH (RSCAN0.C0STS.UINT8[R_IO_HH]) +#define RSCAN0C0ERFL (RSCAN0.C0ERFL.UINT32) +#define RSCAN0C0ERFLL (RSCAN0.C0ERFL.UINT16[R_IO_L]) +#define RSCAN0C0ERFLLL (RSCAN0.C0ERFL.UINT8[R_IO_LL]) +#define RSCAN0C0ERFLLH (RSCAN0.C0ERFL.UINT8[R_IO_LH]) +#define RSCAN0C0ERFLH (RSCAN0.C0ERFL.UINT16[R_IO_H]) +#define RSCAN0C0ERFLHL (RSCAN0.C0ERFL.UINT8[R_IO_HL]) +#define RSCAN0C0ERFLHH (RSCAN0.C0ERFL.UINT8[R_IO_HH]) +#define RSCAN0C1CFG (RSCAN0.C1CFG.UINT32) +#define RSCAN0C1CFGL (RSCAN0.C1CFG.UINT16[R_IO_L]) +#define RSCAN0C1CFGLL (RSCAN0.C1CFG.UINT8[R_IO_LL]) +#define RSCAN0C1CFGLH (RSCAN0.C1CFG.UINT8[R_IO_LH]) +#define RSCAN0C1CFGH (RSCAN0.C1CFG.UINT16[R_IO_H]) +#define RSCAN0C1CFGHL (RSCAN0.C1CFG.UINT8[R_IO_HL]) +#define RSCAN0C1CFGHH (RSCAN0.C1CFG.UINT8[R_IO_HH]) +#define RSCAN0C1CTR (RSCAN0.C1CTR.UINT32) +#define RSCAN0C1CTRL (RSCAN0.C1CTR.UINT16[R_IO_L]) +#define RSCAN0C1CTRLL (RSCAN0.C1CTR.UINT8[R_IO_LL]) +#define RSCAN0C1CTRLH (RSCAN0.C1CTR.UINT8[R_IO_LH]) +#define RSCAN0C1CTRH (RSCAN0.C1CTR.UINT16[R_IO_H]) +#define RSCAN0C1CTRHL (RSCAN0.C1CTR.UINT8[R_IO_HL]) +#define RSCAN0C1CTRHH (RSCAN0.C1CTR.UINT8[R_IO_HH]) +#define RSCAN0C1STS (RSCAN0.C1STS.UINT32) +#define RSCAN0C1STSL (RSCAN0.C1STS.UINT16[R_IO_L]) +#define RSCAN0C1STSLL (RSCAN0.C1STS.UINT8[R_IO_LL]) +#define RSCAN0C1STSLH (RSCAN0.C1STS.UINT8[R_IO_LH]) +#define RSCAN0C1STSH (RSCAN0.C1STS.UINT16[R_IO_H]) +#define RSCAN0C1STSHL (RSCAN0.C1STS.UINT8[R_IO_HL]) +#define RSCAN0C1STSHH (RSCAN0.C1STS.UINT8[R_IO_HH]) +#define RSCAN0C1ERFL (RSCAN0.C1ERFL.UINT32) +#define RSCAN0C1ERFLL (RSCAN0.C1ERFL.UINT16[R_IO_L]) +#define RSCAN0C1ERFLLL (RSCAN0.C1ERFL.UINT8[R_IO_LL]) +#define RSCAN0C1ERFLLH (RSCAN0.C1ERFL.UINT8[R_IO_LH]) +#define RSCAN0C1ERFLH (RSCAN0.C1ERFL.UINT16[R_IO_H]) +#define RSCAN0C1ERFLHL (RSCAN0.C1ERFL.UINT8[R_IO_HL]) +#define RSCAN0C1ERFLHH (RSCAN0.C1ERFL.UINT8[R_IO_HH]) +#define RSCAN0GCFG (RSCAN0.GCFG.UINT32) +#define RSCAN0GCFGL (RSCAN0.GCFG.UINT16[R_IO_L]) +#define RSCAN0GCFGLL (RSCAN0.GCFG.UINT8[R_IO_LL]) +#define RSCAN0GCFGLH (RSCAN0.GCFG.UINT8[R_IO_LH]) +#define RSCAN0GCFGH (RSCAN0.GCFG.UINT16[R_IO_H]) +#define RSCAN0GCFGHL (RSCAN0.GCFG.UINT8[R_IO_HL]) +#define RSCAN0GCFGHH (RSCAN0.GCFG.UINT8[R_IO_HH]) +#define RSCAN0GCTR (RSCAN0.GCTR.UINT32) +#define RSCAN0GCTRL (RSCAN0.GCTR.UINT16[R_IO_L]) +#define RSCAN0GCTRLL (RSCAN0.GCTR.UINT8[R_IO_LL]) +#define RSCAN0GCTRLH (RSCAN0.GCTR.UINT8[R_IO_LH]) +#define RSCAN0GCTRH (RSCAN0.GCTR.UINT16[R_IO_H]) +#define RSCAN0GCTRHL (RSCAN0.GCTR.UINT8[R_IO_HL]) +#define RSCAN0GCTRHH (RSCAN0.GCTR.UINT8[R_IO_HH]) +#define RSCAN0GSTS (RSCAN0.GSTS.UINT32) +#define RSCAN0GSTSL (RSCAN0.GSTS.UINT16[R_IO_L]) +#define RSCAN0GSTSLL (RSCAN0.GSTS.UINT8[R_IO_LL]) +#define RSCAN0GSTSLH (RSCAN0.GSTS.UINT8[R_IO_LH]) +#define RSCAN0GSTSH (RSCAN0.GSTS.UINT16[R_IO_H]) +#define RSCAN0GSTSHL (RSCAN0.GSTS.UINT8[R_IO_HL]) +#define RSCAN0GSTSHH (RSCAN0.GSTS.UINT8[R_IO_HH]) +#define RSCAN0GERFL (RSCAN0.GERFL.UINT32) +#define RSCAN0GERFLL (RSCAN0.GERFL.UINT16[R_IO_L]) +#define RSCAN0GERFLLL (RSCAN0.GERFL.UINT8[R_IO_LL]) +#define RSCAN0GERFLLH (RSCAN0.GERFL.UINT8[R_IO_LH]) +#define RSCAN0GERFLH (RSCAN0.GERFL.UINT16[R_IO_H]) +#define RSCAN0GERFLHL (RSCAN0.GERFL.UINT8[R_IO_HL]) +#define RSCAN0GERFLHH (RSCAN0.GERFL.UINT8[R_IO_HH]) +#define RSCAN0GTSC (RSCAN0.GTSC.UINT32) +#define RSCAN0GTSCL (RSCAN0.GTSC.UINT16[R_IO_L]) +#define RSCAN0GTSCH (RSCAN0.GTSC.UINT16[R_IO_H]) +#define RSCAN0GAFLECTR (RSCAN0.GAFLECTR.UINT32) +#define RSCAN0GAFLECTRL (RSCAN0.GAFLECTR.UINT16[R_IO_L]) +#define RSCAN0GAFLECTRLL (RSCAN0.GAFLECTR.UINT8[R_IO_LL]) +#define RSCAN0GAFLECTRLH (RSCAN0.GAFLECTR.UINT8[R_IO_LH]) +#define RSCAN0GAFLECTRH (RSCAN0.GAFLECTR.UINT16[R_IO_H]) +#define RSCAN0GAFLECTRHL (RSCAN0.GAFLECTR.UINT8[R_IO_HL]) +#define RSCAN0GAFLECTRHH (RSCAN0.GAFLECTR.UINT8[R_IO_HH]) +#define RSCAN0GAFLCFG0 (RSCAN0.GAFLCFG0.UINT32) +#define RSCAN0GAFLCFG0L (RSCAN0.GAFLCFG0.UINT16[R_IO_L]) +#define RSCAN0GAFLCFG0LL (RSCAN0.GAFLCFG0.UINT8[R_IO_LL]) +#define RSCAN0GAFLCFG0LH (RSCAN0.GAFLCFG0.UINT8[R_IO_LH]) +#define RSCAN0GAFLCFG0H (RSCAN0.GAFLCFG0.UINT16[R_IO_H]) +#define RSCAN0GAFLCFG0HL (RSCAN0.GAFLCFG0.UINT8[R_IO_HL]) +#define RSCAN0GAFLCFG0HH (RSCAN0.GAFLCFG0.UINT8[R_IO_HH]) +#define RSCAN0RMNB (RSCAN0.RMNB.UINT32) +#define RSCAN0RMNBL (RSCAN0.RMNB.UINT16[R_IO_L]) +#define RSCAN0RMNBLL (RSCAN0.RMNB.UINT8[R_IO_LL]) +#define RSCAN0RMNBLH (RSCAN0.RMNB.UINT8[R_IO_LH]) +#define RSCAN0RMNBH (RSCAN0.RMNB.UINT16[R_IO_H]) +#define RSCAN0RMNBHL (RSCAN0.RMNB.UINT8[R_IO_HL]) +#define RSCAN0RMNBHH (RSCAN0.RMNB.UINT8[R_IO_HH]) +#define RSCAN0RMND0 (RSCAN0.RMND0.UINT32) +#define RSCAN0RMND0L (RSCAN0.RMND0.UINT16[R_IO_L]) +#define RSCAN0RMND0LL (RSCAN0.RMND0.UINT8[R_IO_LL]) +#define RSCAN0RMND0LH (RSCAN0.RMND0.UINT8[R_IO_LH]) +#define RSCAN0RMND0H (RSCAN0.RMND0.UINT16[R_IO_H]) +#define RSCAN0RMND0HL (RSCAN0.RMND0.UINT8[R_IO_HL]) +#define RSCAN0RMND0HH (RSCAN0.RMND0.UINT8[R_IO_HH]) +#define RSCAN0RFCC0 (RSCAN0.RFCC0.UINT32) +#define RSCAN0RFCC0L (RSCAN0.RFCC0.UINT16[R_IO_L]) +#define RSCAN0RFCC0LL (RSCAN0.RFCC0.UINT8[R_IO_LL]) +#define RSCAN0RFCC0LH (RSCAN0.RFCC0.UINT8[R_IO_LH]) +#define RSCAN0RFCC0H (RSCAN0.RFCC0.UINT16[R_IO_H]) +#define RSCAN0RFCC0HL (RSCAN0.RFCC0.UINT8[R_IO_HL]) +#define RSCAN0RFCC0HH (RSCAN0.RFCC0.UINT8[R_IO_HH]) +#define RSCAN0RFCC1 (RSCAN0.RFCC1.UINT32) +#define RSCAN0RFCC1L (RSCAN0.RFCC1.UINT16[R_IO_L]) +#define RSCAN0RFCC1LL (RSCAN0.RFCC1.UINT8[R_IO_LL]) +#define RSCAN0RFCC1LH (RSCAN0.RFCC1.UINT8[R_IO_LH]) +#define RSCAN0RFCC1H (RSCAN0.RFCC1.UINT16[R_IO_H]) +#define RSCAN0RFCC1HL (RSCAN0.RFCC1.UINT8[R_IO_HL]) +#define RSCAN0RFCC1HH (RSCAN0.RFCC1.UINT8[R_IO_HH]) +#define RSCAN0RFCC2 (RSCAN0.RFCC2.UINT32) +#define RSCAN0RFCC2L (RSCAN0.RFCC2.UINT16[R_IO_L]) +#define RSCAN0RFCC2LL (RSCAN0.RFCC2.UINT8[R_IO_LL]) +#define RSCAN0RFCC2LH (RSCAN0.RFCC2.UINT8[R_IO_LH]) +#define RSCAN0RFCC2H (RSCAN0.RFCC2.UINT16[R_IO_H]) +#define RSCAN0RFCC2HL (RSCAN0.RFCC2.UINT8[R_IO_HL]) +#define RSCAN0RFCC2HH (RSCAN0.RFCC2.UINT8[R_IO_HH]) +#define RSCAN0RFCC3 (RSCAN0.RFCC3.UINT32) +#define RSCAN0RFCC3L (RSCAN0.RFCC3.UINT16[R_IO_L]) +#define RSCAN0RFCC3LL (RSCAN0.RFCC3.UINT8[R_IO_LL]) +#define RSCAN0RFCC3LH (RSCAN0.RFCC3.UINT8[R_IO_LH]) +#define RSCAN0RFCC3H (RSCAN0.RFCC3.UINT16[R_IO_H]) +#define RSCAN0RFCC3HL (RSCAN0.RFCC3.UINT8[R_IO_HL]) +#define RSCAN0RFCC3HH (RSCAN0.RFCC3.UINT8[R_IO_HH]) +#define RSCAN0RFCC4 (RSCAN0.RFCC4.UINT32) +#define RSCAN0RFCC4L (RSCAN0.RFCC4.UINT16[R_IO_L]) +#define RSCAN0RFCC4LL (RSCAN0.RFCC4.UINT8[R_IO_LL]) +#define RSCAN0RFCC4LH (RSCAN0.RFCC4.UINT8[R_IO_LH]) +#define RSCAN0RFCC4H (RSCAN0.RFCC4.UINT16[R_IO_H]) +#define RSCAN0RFCC4HL (RSCAN0.RFCC4.UINT8[R_IO_HL]) +#define RSCAN0RFCC4HH (RSCAN0.RFCC4.UINT8[R_IO_HH]) +#define RSCAN0RFCC5 (RSCAN0.RFCC5.UINT32) +#define RSCAN0RFCC5L (RSCAN0.RFCC5.UINT16[R_IO_L]) +#define RSCAN0RFCC5LL (RSCAN0.RFCC5.UINT8[R_IO_LL]) +#define RSCAN0RFCC5LH (RSCAN0.RFCC5.UINT8[R_IO_LH]) +#define RSCAN0RFCC5H (RSCAN0.RFCC5.UINT16[R_IO_H]) +#define RSCAN0RFCC5HL (RSCAN0.RFCC5.UINT8[R_IO_HL]) +#define RSCAN0RFCC5HH (RSCAN0.RFCC5.UINT8[R_IO_HH]) +#define RSCAN0RFCC6 (RSCAN0.RFCC6.UINT32) +#define RSCAN0RFCC6L (RSCAN0.RFCC6.UINT16[R_IO_L]) +#define RSCAN0RFCC6LL (RSCAN0.RFCC6.UINT8[R_IO_LL]) +#define RSCAN0RFCC6LH (RSCAN0.RFCC6.UINT8[R_IO_LH]) +#define RSCAN0RFCC6H (RSCAN0.RFCC6.UINT16[R_IO_H]) +#define RSCAN0RFCC6HL (RSCAN0.RFCC6.UINT8[R_IO_HL]) +#define RSCAN0RFCC6HH (RSCAN0.RFCC6.UINT8[R_IO_HH]) +#define RSCAN0RFCC7 (RSCAN0.RFCC7.UINT32) +#define RSCAN0RFCC7L (RSCAN0.RFCC7.UINT16[R_IO_L]) +#define RSCAN0RFCC7LL (RSCAN0.RFCC7.UINT8[R_IO_LL]) +#define RSCAN0RFCC7LH (RSCAN0.RFCC7.UINT8[R_IO_LH]) +#define RSCAN0RFCC7H (RSCAN0.RFCC7.UINT16[R_IO_H]) +#define RSCAN0RFCC7HL (RSCAN0.RFCC7.UINT8[R_IO_HL]) +#define RSCAN0RFCC7HH (RSCAN0.RFCC7.UINT8[R_IO_HH]) +#define RSCAN0RFSTS0 (RSCAN0.RFSTS0.UINT32) +#define RSCAN0RFSTS0L (RSCAN0.RFSTS0.UINT16[R_IO_L]) +#define RSCAN0RFSTS0LL (RSCAN0.RFSTS0.UINT8[R_IO_LL]) +#define RSCAN0RFSTS0LH (RSCAN0.RFSTS0.UINT8[R_IO_LH]) +#define RSCAN0RFSTS0H (RSCAN0.RFSTS0.UINT16[R_IO_H]) +#define RSCAN0RFSTS0HL (RSCAN0.RFSTS0.UINT8[R_IO_HL]) +#define RSCAN0RFSTS0HH (RSCAN0.RFSTS0.UINT8[R_IO_HH]) +#define RSCAN0RFSTS1 (RSCAN0.RFSTS1.UINT32) +#define RSCAN0RFSTS1L (RSCAN0.RFSTS1.UINT16[R_IO_L]) +#define RSCAN0RFSTS1LL (RSCAN0.RFSTS1.UINT8[R_IO_LL]) +#define RSCAN0RFSTS1LH (RSCAN0.RFSTS1.UINT8[R_IO_LH]) +#define RSCAN0RFSTS1H (RSCAN0.RFSTS1.UINT16[R_IO_H]) +#define RSCAN0RFSTS1HL (RSCAN0.RFSTS1.UINT8[R_IO_HL]) +#define RSCAN0RFSTS1HH (RSCAN0.RFSTS1.UINT8[R_IO_HH]) +#define RSCAN0RFSTS2 (RSCAN0.RFSTS2.UINT32) +#define RSCAN0RFSTS2L (RSCAN0.RFSTS2.UINT16[R_IO_L]) +#define RSCAN0RFSTS2LL (RSCAN0.RFSTS2.UINT8[R_IO_LL]) +#define RSCAN0RFSTS2LH (RSCAN0.RFSTS2.UINT8[R_IO_LH]) +#define RSCAN0RFSTS2H (RSCAN0.RFSTS2.UINT16[R_IO_H]) +#define RSCAN0RFSTS2HL (RSCAN0.RFSTS2.UINT8[R_IO_HL]) +#define RSCAN0RFSTS2HH (RSCAN0.RFSTS2.UINT8[R_IO_HH]) +#define RSCAN0RFSTS3 (RSCAN0.RFSTS3.UINT32) +#define RSCAN0RFSTS3L (RSCAN0.RFSTS3.UINT16[R_IO_L]) +#define RSCAN0RFSTS3LL (RSCAN0.RFSTS3.UINT8[R_IO_LL]) +#define RSCAN0RFSTS3LH (RSCAN0.RFSTS3.UINT8[R_IO_LH]) +#define RSCAN0RFSTS3H (RSCAN0.RFSTS3.UINT16[R_IO_H]) +#define RSCAN0RFSTS3HL (RSCAN0.RFSTS3.UINT8[R_IO_HL]) +#define RSCAN0RFSTS3HH (RSCAN0.RFSTS3.UINT8[R_IO_HH]) +#define RSCAN0RFSTS4 (RSCAN0.RFSTS4.UINT32) +#define RSCAN0RFSTS4L (RSCAN0.RFSTS4.UINT16[R_IO_L]) +#define RSCAN0RFSTS4LL (RSCAN0.RFSTS4.UINT8[R_IO_LL]) +#define RSCAN0RFSTS4LH (RSCAN0.RFSTS4.UINT8[R_IO_LH]) +#define RSCAN0RFSTS4H (RSCAN0.RFSTS4.UINT16[R_IO_H]) +#define RSCAN0RFSTS4HL (RSCAN0.RFSTS4.UINT8[R_IO_HL]) +#define RSCAN0RFSTS4HH (RSCAN0.RFSTS4.UINT8[R_IO_HH]) +#define RSCAN0RFSTS5 (RSCAN0.RFSTS5.UINT32) +#define RSCAN0RFSTS5L (RSCAN0.RFSTS5.UINT16[R_IO_L]) +#define RSCAN0RFSTS5LL (RSCAN0.RFSTS5.UINT8[R_IO_LL]) +#define RSCAN0RFSTS5LH (RSCAN0.RFSTS5.UINT8[R_IO_LH]) +#define RSCAN0RFSTS5H (RSCAN0.RFSTS5.UINT16[R_IO_H]) +#define RSCAN0RFSTS5HL (RSCAN0.RFSTS5.UINT8[R_IO_HL]) +#define RSCAN0RFSTS5HH (RSCAN0.RFSTS5.UINT8[R_IO_HH]) +#define RSCAN0RFSTS6 (RSCAN0.RFSTS6.UINT32) +#define RSCAN0RFSTS6L (RSCAN0.RFSTS6.UINT16[R_IO_L]) +#define RSCAN0RFSTS6LL (RSCAN0.RFSTS6.UINT8[R_IO_LL]) +#define RSCAN0RFSTS6LH (RSCAN0.RFSTS6.UINT8[R_IO_LH]) +#define RSCAN0RFSTS6H (RSCAN0.RFSTS6.UINT16[R_IO_H]) +#define RSCAN0RFSTS6HL (RSCAN0.RFSTS6.UINT8[R_IO_HL]) +#define RSCAN0RFSTS6HH (RSCAN0.RFSTS6.UINT8[R_IO_HH]) +#define RSCAN0RFSTS7 (RSCAN0.RFSTS7.UINT32) +#define RSCAN0RFSTS7L (RSCAN0.RFSTS7.UINT16[R_IO_L]) +#define RSCAN0RFSTS7LL (RSCAN0.RFSTS7.UINT8[R_IO_LL]) +#define RSCAN0RFSTS7LH (RSCAN0.RFSTS7.UINT8[R_IO_LH]) +#define RSCAN0RFSTS7H (RSCAN0.RFSTS7.UINT16[R_IO_H]) +#define RSCAN0RFSTS7HL (RSCAN0.RFSTS7.UINT8[R_IO_HL]) +#define RSCAN0RFSTS7HH (RSCAN0.RFSTS7.UINT8[R_IO_HH]) +#define RSCAN0RFPCTR0 (RSCAN0.RFPCTR0.UINT32) +#define RSCAN0RFPCTR0L (RSCAN0.RFPCTR0.UINT16[R_IO_L]) +#define RSCAN0RFPCTR0LL (RSCAN0.RFPCTR0.UINT8[R_IO_LL]) +#define RSCAN0RFPCTR0LH (RSCAN0.RFPCTR0.UINT8[R_IO_LH]) +#define RSCAN0RFPCTR0H (RSCAN0.RFPCTR0.UINT16[R_IO_H]) +#define RSCAN0RFPCTR0HL (RSCAN0.RFPCTR0.UINT8[R_IO_HL]) +#define RSCAN0RFPCTR0HH (RSCAN0.RFPCTR0.UINT8[R_IO_HH]) +#define RSCAN0RFPCTR1 (RSCAN0.RFPCTR1.UINT32) +#define RSCAN0RFPCTR1L (RSCAN0.RFPCTR1.UINT16[R_IO_L]) +#define RSCAN0RFPCTR1LL (RSCAN0.RFPCTR1.UINT8[R_IO_LL]) +#define RSCAN0RFPCTR1LH (RSCAN0.RFPCTR1.UINT8[R_IO_LH]) +#define RSCAN0RFPCTR1H (RSCAN0.RFPCTR1.UINT16[R_IO_H]) +#define RSCAN0RFPCTR1HL (RSCAN0.RFPCTR1.UINT8[R_IO_HL]) +#define RSCAN0RFPCTR1HH (RSCAN0.RFPCTR1.UINT8[R_IO_HH]) +#define RSCAN0RFPCTR2 (RSCAN0.RFPCTR2.UINT32) +#define RSCAN0RFPCTR2L (RSCAN0.RFPCTR2.UINT16[R_IO_L]) +#define RSCAN0RFPCTR2LL (RSCAN0.RFPCTR2.UINT8[R_IO_LL]) +#define RSCAN0RFPCTR2LH (RSCAN0.RFPCTR2.UINT8[R_IO_LH]) +#define RSCAN0RFPCTR2H (RSCAN0.RFPCTR2.UINT16[R_IO_H]) +#define RSCAN0RFPCTR2HL (RSCAN0.RFPCTR2.UINT8[R_IO_HL]) +#define RSCAN0RFPCTR2HH (RSCAN0.RFPCTR2.UINT8[R_IO_HH]) +#define RSCAN0RFPCTR3 (RSCAN0.RFPCTR3.UINT32) +#define RSCAN0RFPCTR3L (RSCAN0.RFPCTR3.UINT16[R_IO_L]) +#define RSCAN0RFPCTR3LL (RSCAN0.RFPCTR3.UINT8[R_IO_LL]) +#define RSCAN0RFPCTR3LH (RSCAN0.RFPCTR3.UINT8[R_IO_LH]) +#define RSCAN0RFPCTR3H (RSCAN0.RFPCTR3.UINT16[R_IO_H]) +#define RSCAN0RFPCTR3HL (RSCAN0.RFPCTR3.UINT8[R_IO_HL]) +#define RSCAN0RFPCTR3HH (RSCAN0.RFPCTR3.UINT8[R_IO_HH]) +#define RSCAN0RFPCTR4 (RSCAN0.RFPCTR4.UINT32) +#define RSCAN0RFPCTR4L (RSCAN0.RFPCTR4.UINT16[R_IO_L]) +#define RSCAN0RFPCTR4LL (RSCAN0.RFPCTR4.UINT8[R_IO_LL]) +#define RSCAN0RFPCTR4LH (RSCAN0.RFPCTR4.UINT8[R_IO_LH]) +#define RSCAN0RFPCTR4H (RSCAN0.RFPCTR4.UINT16[R_IO_H]) +#define RSCAN0RFPCTR4HL (RSCAN0.RFPCTR4.UINT8[R_IO_HL]) +#define RSCAN0RFPCTR4HH (RSCAN0.RFPCTR4.UINT8[R_IO_HH]) +#define RSCAN0RFPCTR5 (RSCAN0.RFPCTR5.UINT32) +#define RSCAN0RFPCTR5L (RSCAN0.RFPCTR5.UINT16[R_IO_L]) +#define RSCAN0RFPCTR5LL (RSCAN0.RFPCTR5.UINT8[R_IO_LL]) +#define RSCAN0RFPCTR5LH (RSCAN0.RFPCTR5.UINT8[R_IO_LH]) +#define RSCAN0RFPCTR5H (RSCAN0.RFPCTR5.UINT16[R_IO_H]) +#define RSCAN0RFPCTR5HL (RSCAN0.RFPCTR5.UINT8[R_IO_HL]) +#define RSCAN0RFPCTR5HH (RSCAN0.RFPCTR5.UINT8[R_IO_HH]) +#define RSCAN0RFPCTR6 (RSCAN0.RFPCTR6.UINT32) +#define RSCAN0RFPCTR6L (RSCAN0.RFPCTR6.UINT16[R_IO_L]) +#define RSCAN0RFPCTR6LL (RSCAN0.RFPCTR6.UINT8[R_IO_LL]) +#define RSCAN0RFPCTR6LH (RSCAN0.RFPCTR6.UINT8[R_IO_LH]) +#define RSCAN0RFPCTR6H (RSCAN0.RFPCTR6.UINT16[R_IO_H]) +#define RSCAN0RFPCTR6HL (RSCAN0.RFPCTR6.UINT8[R_IO_HL]) +#define RSCAN0RFPCTR6HH (RSCAN0.RFPCTR6.UINT8[R_IO_HH]) +#define RSCAN0RFPCTR7 (RSCAN0.RFPCTR7.UINT32) +#define RSCAN0RFPCTR7L (RSCAN0.RFPCTR7.UINT16[R_IO_L]) +#define RSCAN0RFPCTR7LL (RSCAN0.RFPCTR7.UINT8[R_IO_LL]) +#define RSCAN0RFPCTR7LH (RSCAN0.RFPCTR7.UINT8[R_IO_LH]) +#define RSCAN0RFPCTR7H (RSCAN0.RFPCTR7.UINT16[R_IO_H]) +#define RSCAN0RFPCTR7HL (RSCAN0.RFPCTR7.UINT8[R_IO_HL]) +#define RSCAN0RFPCTR7HH (RSCAN0.RFPCTR7.UINT8[R_IO_HH]) +#define RSCAN0CFCC0 (RSCAN0.CFCC0.UINT32) +#define RSCAN0CFCC0L (RSCAN0.CFCC0.UINT16[R_IO_L]) +#define RSCAN0CFCC0LL (RSCAN0.CFCC0.UINT8[R_IO_LL]) +#define RSCAN0CFCC0LH (RSCAN0.CFCC0.UINT8[R_IO_LH]) +#define RSCAN0CFCC0H (RSCAN0.CFCC0.UINT16[R_IO_H]) +#define RSCAN0CFCC0HL (RSCAN0.CFCC0.UINT8[R_IO_HL]) +#define RSCAN0CFCC0HH (RSCAN0.CFCC0.UINT8[R_IO_HH]) +#define RSCAN0CFCC1 (RSCAN0.CFCC1.UINT32) +#define RSCAN0CFCC1L (RSCAN0.CFCC1.UINT16[R_IO_L]) +#define RSCAN0CFCC1LL (RSCAN0.CFCC1.UINT8[R_IO_LL]) +#define RSCAN0CFCC1LH (RSCAN0.CFCC1.UINT8[R_IO_LH]) +#define RSCAN0CFCC1H (RSCAN0.CFCC1.UINT16[R_IO_H]) +#define RSCAN0CFCC1HL (RSCAN0.CFCC1.UINT8[R_IO_HL]) +#define RSCAN0CFCC1HH (RSCAN0.CFCC1.UINT8[R_IO_HH]) +#define RSCAN0CFCC2 (RSCAN0.CFCC2.UINT32) +#define RSCAN0CFCC2L (RSCAN0.CFCC2.UINT16[R_IO_L]) +#define RSCAN0CFCC2LL (RSCAN0.CFCC2.UINT8[R_IO_LL]) +#define RSCAN0CFCC2LH (RSCAN0.CFCC2.UINT8[R_IO_LH]) +#define RSCAN0CFCC2H (RSCAN0.CFCC2.UINT16[R_IO_H]) +#define RSCAN0CFCC2HL (RSCAN0.CFCC2.UINT8[R_IO_HL]) +#define RSCAN0CFCC2HH (RSCAN0.CFCC2.UINT8[R_IO_HH]) +#define RSCAN0CFCC3 (RSCAN0.CFCC3.UINT32) +#define RSCAN0CFCC3L (RSCAN0.CFCC3.UINT16[R_IO_L]) +#define RSCAN0CFCC3LL (RSCAN0.CFCC3.UINT8[R_IO_LL]) +#define RSCAN0CFCC3LH (RSCAN0.CFCC3.UINT8[R_IO_LH]) +#define RSCAN0CFCC3H (RSCAN0.CFCC3.UINT16[R_IO_H]) +#define RSCAN0CFCC3HL (RSCAN0.CFCC3.UINT8[R_IO_HL]) +#define RSCAN0CFCC3HH (RSCAN0.CFCC3.UINT8[R_IO_HH]) +#define RSCAN0CFCC4 (RSCAN0.CFCC4.UINT32) +#define RSCAN0CFCC4L (RSCAN0.CFCC4.UINT16[R_IO_L]) +#define RSCAN0CFCC4LL (RSCAN0.CFCC4.UINT8[R_IO_LL]) +#define RSCAN0CFCC4LH (RSCAN0.CFCC4.UINT8[R_IO_LH]) +#define RSCAN0CFCC4H (RSCAN0.CFCC4.UINT16[R_IO_H]) +#define RSCAN0CFCC4HL (RSCAN0.CFCC4.UINT8[R_IO_HL]) +#define RSCAN0CFCC4HH (RSCAN0.CFCC4.UINT8[R_IO_HH]) +#define RSCAN0CFCC5 (RSCAN0.CFCC5.UINT32) +#define RSCAN0CFCC5L (RSCAN0.CFCC5.UINT16[R_IO_L]) +#define RSCAN0CFCC5LL (RSCAN0.CFCC5.UINT8[R_IO_LL]) +#define RSCAN0CFCC5LH (RSCAN0.CFCC5.UINT8[R_IO_LH]) +#define RSCAN0CFCC5H (RSCAN0.CFCC5.UINT16[R_IO_H]) +#define RSCAN0CFCC5HL (RSCAN0.CFCC5.UINT8[R_IO_HL]) +#define RSCAN0CFCC5HH (RSCAN0.CFCC5.UINT8[R_IO_HH]) +#define RSCAN0CFSTS0 (RSCAN0.CFSTS0.UINT32) +#define RSCAN0CFSTS0L (RSCAN0.CFSTS0.UINT16[R_IO_L]) +#define RSCAN0CFSTS0LL (RSCAN0.CFSTS0.UINT8[R_IO_LL]) +#define RSCAN0CFSTS0LH (RSCAN0.CFSTS0.UINT8[R_IO_LH]) +#define RSCAN0CFSTS0H (RSCAN0.CFSTS0.UINT16[R_IO_H]) +#define RSCAN0CFSTS0HL (RSCAN0.CFSTS0.UINT8[R_IO_HL]) +#define RSCAN0CFSTS0HH (RSCAN0.CFSTS0.UINT8[R_IO_HH]) +#define RSCAN0CFSTS1 (RSCAN0.CFSTS1.UINT32) +#define RSCAN0CFSTS1L (RSCAN0.CFSTS1.UINT16[R_IO_L]) +#define RSCAN0CFSTS1LL (RSCAN0.CFSTS1.UINT8[R_IO_LL]) +#define RSCAN0CFSTS1LH (RSCAN0.CFSTS1.UINT8[R_IO_LH]) +#define RSCAN0CFSTS1H (RSCAN0.CFSTS1.UINT16[R_IO_H]) +#define RSCAN0CFSTS1HL (RSCAN0.CFSTS1.UINT8[R_IO_HL]) +#define RSCAN0CFSTS1HH (RSCAN0.CFSTS1.UINT8[R_IO_HH]) +#define RSCAN0CFSTS2 (RSCAN0.CFSTS2.UINT32) +#define RSCAN0CFSTS2L (RSCAN0.CFSTS2.UINT16[R_IO_L]) +#define RSCAN0CFSTS2LL (RSCAN0.CFSTS2.UINT8[R_IO_LL]) +#define RSCAN0CFSTS2LH (RSCAN0.CFSTS2.UINT8[R_IO_LH]) +#define RSCAN0CFSTS2H (RSCAN0.CFSTS2.UINT16[R_IO_H]) +#define RSCAN0CFSTS2HL (RSCAN0.CFSTS2.UINT8[R_IO_HL]) +#define RSCAN0CFSTS2HH (RSCAN0.CFSTS2.UINT8[R_IO_HH]) +#define RSCAN0CFSTS3 (RSCAN0.CFSTS3.UINT32) +#define RSCAN0CFSTS3L (RSCAN0.CFSTS3.UINT16[R_IO_L]) +#define RSCAN0CFSTS3LL (RSCAN0.CFSTS3.UINT8[R_IO_LL]) +#define RSCAN0CFSTS3LH (RSCAN0.CFSTS3.UINT8[R_IO_LH]) +#define RSCAN0CFSTS3H (RSCAN0.CFSTS3.UINT16[R_IO_H]) +#define RSCAN0CFSTS3HL (RSCAN0.CFSTS3.UINT8[R_IO_HL]) +#define RSCAN0CFSTS3HH (RSCAN0.CFSTS3.UINT8[R_IO_HH]) +#define RSCAN0CFSTS4 (RSCAN0.CFSTS4.UINT32) +#define RSCAN0CFSTS4L (RSCAN0.CFSTS4.UINT16[R_IO_L]) +#define RSCAN0CFSTS4LL (RSCAN0.CFSTS4.UINT8[R_IO_LL]) +#define RSCAN0CFSTS4LH (RSCAN0.CFSTS4.UINT8[R_IO_LH]) +#define RSCAN0CFSTS4H (RSCAN0.CFSTS4.UINT16[R_IO_H]) +#define RSCAN0CFSTS4HL (RSCAN0.CFSTS4.UINT8[R_IO_HL]) +#define RSCAN0CFSTS4HH (RSCAN0.CFSTS4.UINT8[R_IO_HH]) +#define RSCAN0CFSTS5 (RSCAN0.CFSTS5.UINT32) +#define RSCAN0CFSTS5L (RSCAN0.CFSTS5.UINT16[R_IO_L]) +#define RSCAN0CFSTS5LL (RSCAN0.CFSTS5.UINT8[R_IO_LL]) +#define RSCAN0CFSTS5LH (RSCAN0.CFSTS5.UINT8[R_IO_LH]) +#define RSCAN0CFSTS5H (RSCAN0.CFSTS5.UINT16[R_IO_H]) +#define RSCAN0CFSTS5HL (RSCAN0.CFSTS5.UINT8[R_IO_HL]) +#define RSCAN0CFSTS5HH (RSCAN0.CFSTS5.UINT8[R_IO_HH]) +#define RSCAN0CFPCTR0 (RSCAN0.CFPCTR0.UINT32) +#define RSCAN0CFPCTR0L (RSCAN0.CFPCTR0.UINT16[R_IO_L]) +#define RSCAN0CFPCTR0LL (RSCAN0.CFPCTR0.UINT8[R_IO_LL]) +#define RSCAN0CFPCTR0LH (RSCAN0.CFPCTR0.UINT8[R_IO_LH]) +#define RSCAN0CFPCTR0H (RSCAN0.CFPCTR0.UINT16[R_IO_H]) +#define RSCAN0CFPCTR0HL (RSCAN0.CFPCTR0.UINT8[R_IO_HL]) +#define RSCAN0CFPCTR0HH (RSCAN0.CFPCTR0.UINT8[R_IO_HH]) +#define RSCAN0CFPCTR1 (RSCAN0.CFPCTR1.UINT32) +#define RSCAN0CFPCTR1L (RSCAN0.CFPCTR1.UINT16[R_IO_L]) +#define RSCAN0CFPCTR1LL (RSCAN0.CFPCTR1.UINT8[R_IO_LL]) +#define RSCAN0CFPCTR1LH (RSCAN0.CFPCTR1.UINT8[R_IO_LH]) +#define RSCAN0CFPCTR1H (RSCAN0.CFPCTR1.UINT16[R_IO_H]) +#define RSCAN0CFPCTR1HL (RSCAN0.CFPCTR1.UINT8[R_IO_HL]) +#define RSCAN0CFPCTR1HH (RSCAN0.CFPCTR1.UINT8[R_IO_HH]) +#define RSCAN0CFPCTR2 (RSCAN0.CFPCTR2.UINT32) +#define RSCAN0CFPCTR2L (RSCAN0.CFPCTR2.UINT16[R_IO_L]) +#define RSCAN0CFPCTR2LL (RSCAN0.CFPCTR2.UINT8[R_IO_LL]) +#define RSCAN0CFPCTR2LH (RSCAN0.CFPCTR2.UINT8[R_IO_LH]) +#define RSCAN0CFPCTR2H (RSCAN0.CFPCTR2.UINT16[R_IO_H]) +#define RSCAN0CFPCTR2HL (RSCAN0.CFPCTR2.UINT8[R_IO_HL]) +#define RSCAN0CFPCTR2HH (RSCAN0.CFPCTR2.UINT8[R_IO_HH]) +#define RSCAN0CFPCTR3 (RSCAN0.CFPCTR3.UINT32) +#define RSCAN0CFPCTR3L (RSCAN0.CFPCTR3.UINT16[R_IO_L]) +#define RSCAN0CFPCTR3LL (RSCAN0.CFPCTR3.UINT8[R_IO_LL]) +#define RSCAN0CFPCTR3LH (RSCAN0.CFPCTR3.UINT8[R_IO_LH]) +#define RSCAN0CFPCTR3H (RSCAN0.CFPCTR3.UINT16[R_IO_H]) +#define RSCAN0CFPCTR3HL (RSCAN0.CFPCTR3.UINT8[R_IO_HL]) +#define RSCAN0CFPCTR3HH (RSCAN0.CFPCTR3.UINT8[R_IO_HH]) +#define RSCAN0CFPCTR4 (RSCAN0.CFPCTR4.UINT32) +#define RSCAN0CFPCTR4L (RSCAN0.CFPCTR4.UINT16[R_IO_L]) +#define RSCAN0CFPCTR4LL (RSCAN0.CFPCTR4.UINT8[R_IO_LL]) +#define RSCAN0CFPCTR4LH (RSCAN0.CFPCTR4.UINT8[R_IO_LH]) +#define RSCAN0CFPCTR4H (RSCAN0.CFPCTR4.UINT16[R_IO_H]) +#define RSCAN0CFPCTR4HL (RSCAN0.CFPCTR4.UINT8[R_IO_HL]) +#define RSCAN0CFPCTR4HH (RSCAN0.CFPCTR4.UINT8[R_IO_HH]) +#define RSCAN0CFPCTR5 (RSCAN0.CFPCTR5.UINT32) +#define RSCAN0CFPCTR5L (RSCAN0.CFPCTR5.UINT16[R_IO_L]) +#define RSCAN0CFPCTR5LL (RSCAN0.CFPCTR5.UINT8[R_IO_LL]) +#define RSCAN0CFPCTR5LH (RSCAN0.CFPCTR5.UINT8[R_IO_LH]) +#define RSCAN0CFPCTR5H (RSCAN0.CFPCTR5.UINT16[R_IO_H]) +#define RSCAN0CFPCTR5HL (RSCAN0.CFPCTR5.UINT8[R_IO_HL]) +#define RSCAN0CFPCTR5HH (RSCAN0.CFPCTR5.UINT8[R_IO_HH]) +#define RSCAN0FESTS (RSCAN0.FESTS.UINT32) +#define RSCAN0FESTSL (RSCAN0.FESTS.UINT16[R_IO_L]) +#define RSCAN0FESTSLL (RSCAN0.FESTS.UINT8[R_IO_LL]) +#define RSCAN0FESTSLH (RSCAN0.FESTS.UINT8[R_IO_LH]) +#define RSCAN0FESTSH (RSCAN0.FESTS.UINT16[R_IO_H]) +#define RSCAN0FESTSHL (RSCAN0.FESTS.UINT8[R_IO_HL]) +#define RSCAN0FESTSHH (RSCAN0.FESTS.UINT8[R_IO_HH]) +#define RSCAN0FFSTS (RSCAN0.FFSTS.UINT32) +#define RSCAN0FFSTSL (RSCAN0.FFSTS.UINT16[R_IO_L]) +#define RSCAN0FFSTSLL (RSCAN0.FFSTS.UINT8[R_IO_LL]) +#define RSCAN0FFSTSLH (RSCAN0.FFSTS.UINT8[R_IO_LH]) +#define RSCAN0FFSTSH (RSCAN0.FFSTS.UINT16[R_IO_H]) +#define RSCAN0FFSTSHL (RSCAN0.FFSTS.UINT8[R_IO_HL]) +#define RSCAN0FFSTSHH (RSCAN0.FFSTS.UINT8[R_IO_HH]) +#define RSCAN0FMSTS (RSCAN0.FMSTS.UINT32) +#define RSCAN0FMSTSL (RSCAN0.FMSTS.UINT16[R_IO_L]) +#define RSCAN0FMSTSLL (RSCAN0.FMSTS.UINT8[R_IO_LL]) +#define RSCAN0FMSTSLH (RSCAN0.FMSTS.UINT8[R_IO_LH]) +#define RSCAN0FMSTSH (RSCAN0.FMSTS.UINT16[R_IO_H]) +#define RSCAN0FMSTSHL (RSCAN0.FMSTS.UINT8[R_IO_HL]) +#define RSCAN0FMSTSHH (RSCAN0.FMSTS.UINT8[R_IO_HH]) +#define RSCAN0RFISTS (RSCAN0.RFISTS.UINT32) +#define RSCAN0RFISTSL (RSCAN0.RFISTS.UINT16[R_IO_L]) +#define RSCAN0RFISTSLL (RSCAN0.RFISTS.UINT8[R_IO_LL]) +#define RSCAN0RFISTSLH (RSCAN0.RFISTS.UINT8[R_IO_LH]) +#define RSCAN0RFISTSH (RSCAN0.RFISTS.UINT16[R_IO_H]) +#define RSCAN0RFISTSHL (RSCAN0.RFISTS.UINT8[R_IO_HL]) +#define RSCAN0RFISTSHH (RSCAN0.RFISTS.UINT8[R_IO_HH]) +#define RSCAN0CFRISTS (RSCAN0.CFRISTS.UINT32) +#define RSCAN0CFRISTSL (RSCAN0.CFRISTS.UINT16[R_IO_L]) +#define RSCAN0CFRISTSLL (RSCAN0.CFRISTS.UINT8[R_IO_LL]) +#define RSCAN0CFRISTSLH (RSCAN0.CFRISTS.UINT8[R_IO_LH]) +#define RSCAN0CFRISTSH (RSCAN0.CFRISTS.UINT16[R_IO_H]) +#define RSCAN0CFRISTSHL (RSCAN0.CFRISTS.UINT8[R_IO_HL]) +#define RSCAN0CFRISTSHH (RSCAN0.CFRISTS.UINT8[R_IO_HH]) +#define RSCAN0CFTISTS (RSCAN0.CFTISTS.UINT32) +#define RSCAN0CFTISTSL (RSCAN0.CFTISTS.UINT16[R_IO_L]) +#define RSCAN0CFTISTSLL (RSCAN0.CFTISTS.UINT8[R_IO_LL]) +#define RSCAN0CFTISTSLH (RSCAN0.CFTISTS.UINT8[R_IO_LH]) +#define RSCAN0CFTISTSH (RSCAN0.CFTISTS.UINT16[R_IO_H]) +#define RSCAN0CFTISTSHL (RSCAN0.CFTISTS.UINT8[R_IO_HL]) +#define RSCAN0CFTISTSHH (RSCAN0.CFTISTS.UINT8[R_IO_HH]) +#define RSCAN0TMC0 (RSCAN0.TMC0) +#define RSCAN0TMC1 (RSCAN0.TMC1) +#define RSCAN0TMC2 (RSCAN0.TMC2) +#define RSCAN0TMC3 (RSCAN0.TMC3) +#define RSCAN0TMC4 (RSCAN0.TMC4) +#define RSCAN0TMC5 (RSCAN0.TMC5) +#define RSCAN0TMC6 (RSCAN0.TMC6) +#define RSCAN0TMC7 (RSCAN0.TMC7) +#define RSCAN0TMC8 (RSCAN0.TMC8) +#define RSCAN0TMC9 (RSCAN0.TMC9) +#define RSCAN0TMC10 (RSCAN0.TMC10) +#define RSCAN0TMC11 (RSCAN0.TMC11) +#define RSCAN0TMC12 (RSCAN0.TMC12) +#define RSCAN0TMC13 (RSCAN0.TMC13) +#define RSCAN0TMC14 (RSCAN0.TMC14) +#define RSCAN0TMC15 (RSCAN0.TMC15) +#define RSCAN0TMC16 (RSCAN0.TMC16) +#define RSCAN0TMC17 (RSCAN0.TMC17) +#define RSCAN0TMC18 (RSCAN0.TMC18) +#define RSCAN0TMC19 (RSCAN0.TMC19) +#define RSCAN0TMC20 (RSCAN0.TMC20) +#define RSCAN0TMC21 (RSCAN0.TMC21) +#define RSCAN0TMC22 (RSCAN0.TMC22) +#define RSCAN0TMC23 (RSCAN0.TMC23) +#define RSCAN0TMC24 (RSCAN0.TMC24) +#define RSCAN0TMC25 (RSCAN0.TMC25) +#define RSCAN0TMC26 (RSCAN0.TMC26) +#define RSCAN0TMC27 (RSCAN0.TMC27) +#define RSCAN0TMC28 (RSCAN0.TMC28) +#define RSCAN0TMC29 (RSCAN0.TMC29) +#define RSCAN0TMC30 (RSCAN0.TMC30) +#define RSCAN0TMC31 (RSCAN0.TMC31) +#define RSCAN0TMSTS0 (RSCAN0.TMSTS0) +#define RSCAN0TMSTS1 (RSCAN0.TMSTS1) +#define RSCAN0TMSTS2 (RSCAN0.TMSTS2) +#define RSCAN0TMSTS3 (RSCAN0.TMSTS3) +#define RSCAN0TMSTS4 (RSCAN0.TMSTS4) +#define RSCAN0TMSTS5 (RSCAN0.TMSTS5) +#define RSCAN0TMSTS6 (RSCAN0.TMSTS6) +#define RSCAN0TMSTS7 (RSCAN0.TMSTS7) +#define RSCAN0TMSTS8 (RSCAN0.TMSTS8) +#define RSCAN0TMSTS9 (RSCAN0.TMSTS9) +#define RSCAN0TMSTS10 (RSCAN0.TMSTS10) +#define RSCAN0TMSTS11 (RSCAN0.TMSTS11) +#define RSCAN0TMSTS12 (RSCAN0.TMSTS12) +#define RSCAN0TMSTS13 (RSCAN0.TMSTS13) +#define RSCAN0TMSTS14 (RSCAN0.TMSTS14) +#define RSCAN0TMSTS15 (RSCAN0.TMSTS15) +#define RSCAN0TMSTS16 (RSCAN0.TMSTS16) +#define RSCAN0TMSTS17 (RSCAN0.TMSTS17) +#define RSCAN0TMSTS18 (RSCAN0.TMSTS18) +#define RSCAN0TMSTS19 (RSCAN0.TMSTS19) +#define RSCAN0TMSTS20 (RSCAN0.TMSTS20) +#define RSCAN0TMSTS21 (RSCAN0.TMSTS21) +#define RSCAN0TMSTS22 (RSCAN0.TMSTS22) +#define RSCAN0TMSTS23 (RSCAN0.TMSTS23) +#define RSCAN0TMSTS24 (RSCAN0.TMSTS24) +#define RSCAN0TMSTS25 (RSCAN0.TMSTS25) +#define RSCAN0TMSTS26 (RSCAN0.TMSTS26) +#define RSCAN0TMSTS27 (RSCAN0.TMSTS27) +#define RSCAN0TMSTS28 (RSCAN0.TMSTS28) +#define RSCAN0TMSTS29 (RSCAN0.TMSTS29) +#define RSCAN0TMSTS30 (RSCAN0.TMSTS30) +#define RSCAN0TMSTS31 (RSCAN0.TMSTS31) +#define RSCAN0TMTRSTS0 (RSCAN0.TMTRSTS0.UINT32) +#define RSCAN0TMTRSTS0L (RSCAN0.TMTRSTS0.UINT16[R_IO_L]) +#define RSCAN0TMTRSTS0LL (RSCAN0.TMTRSTS0.UINT8[R_IO_LL]) +#define RSCAN0TMTRSTS0LH (RSCAN0.TMTRSTS0.UINT8[R_IO_LH]) +#define RSCAN0TMTRSTS0H (RSCAN0.TMTRSTS0.UINT16[R_IO_H]) +#define RSCAN0TMTRSTS0HL (RSCAN0.TMTRSTS0.UINT8[R_IO_HL]) +#define RSCAN0TMTRSTS0HH (RSCAN0.TMTRSTS0.UINT8[R_IO_HH]) +#define RSCAN0TMTARSTS0 (RSCAN0.TMTARSTS0.UINT32) +#define RSCAN0TMTARSTS0L (RSCAN0.TMTARSTS0.UINT16[R_IO_L]) +#define RSCAN0TMTARSTS0LL (RSCAN0.TMTARSTS0.UINT8[R_IO_LL]) +#define RSCAN0TMTARSTS0LH (RSCAN0.TMTARSTS0.UINT8[R_IO_LH]) +#define RSCAN0TMTARSTS0H (RSCAN0.TMTARSTS0.UINT16[R_IO_H]) +#define RSCAN0TMTARSTS0HL (RSCAN0.TMTARSTS0.UINT8[R_IO_HL]) +#define RSCAN0TMTARSTS0HH (RSCAN0.TMTARSTS0.UINT8[R_IO_HH]) +#define RSCAN0TMTCSTS0 (RSCAN0.TMTCSTS0.UINT32) +#define RSCAN0TMTCSTS0L (RSCAN0.TMTCSTS0.UINT16[R_IO_L]) +#define RSCAN0TMTCSTS0LL (RSCAN0.TMTCSTS0.UINT8[R_IO_LL]) +#define RSCAN0TMTCSTS0LH (RSCAN0.TMTCSTS0.UINT8[R_IO_LH]) +#define RSCAN0TMTCSTS0H (RSCAN0.TMTCSTS0.UINT16[R_IO_H]) +#define RSCAN0TMTCSTS0HL (RSCAN0.TMTCSTS0.UINT8[R_IO_HL]) +#define RSCAN0TMTCSTS0HH (RSCAN0.TMTCSTS0.UINT8[R_IO_HH]) +#define RSCAN0TMTASTS0 (RSCAN0.TMTASTS0.UINT32) +#define RSCAN0TMTASTS0L (RSCAN0.TMTASTS0.UINT16[R_IO_L]) +#define RSCAN0TMTASTS0LL (RSCAN0.TMTASTS0.UINT8[R_IO_LL]) +#define RSCAN0TMTASTS0LH (RSCAN0.TMTASTS0.UINT8[R_IO_LH]) +#define RSCAN0TMTASTS0H (RSCAN0.TMTASTS0.UINT16[R_IO_H]) +#define RSCAN0TMTASTS0HL (RSCAN0.TMTASTS0.UINT8[R_IO_HL]) +#define RSCAN0TMTASTS0HH (RSCAN0.TMTASTS0.UINT8[R_IO_HH]) +#define RSCAN0TMIEC0 (RSCAN0.TMIEC0.UINT32) +#define RSCAN0TMIEC0L (RSCAN0.TMIEC0.UINT16[R_IO_L]) +#define RSCAN0TMIEC0LL (RSCAN0.TMIEC0.UINT8[R_IO_LL]) +#define RSCAN0TMIEC0LH (RSCAN0.TMIEC0.UINT8[R_IO_LH]) +#define RSCAN0TMIEC0H (RSCAN0.TMIEC0.UINT16[R_IO_H]) +#define RSCAN0TMIEC0HL (RSCAN0.TMIEC0.UINT8[R_IO_HL]) +#define RSCAN0TMIEC0HH (RSCAN0.TMIEC0.UINT8[R_IO_HH]) +#define RSCAN0TXQCC0 (RSCAN0.TXQCC0.UINT32) +#define RSCAN0TXQCC0L (RSCAN0.TXQCC0.UINT16[R_IO_L]) +#define RSCAN0TXQCC0LL (RSCAN0.TXQCC0.UINT8[R_IO_LL]) +#define RSCAN0TXQCC0LH (RSCAN0.TXQCC0.UINT8[R_IO_LH]) +#define RSCAN0TXQCC0H (RSCAN0.TXQCC0.UINT16[R_IO_H]) +#define RSCAN0TXQCC0HL (RSCAN0.TXQCC0.UINT8[R_IO_HL]) +#define RSCAN0TXQCC0HH (RSCAN0.TXQCC0.UINT8[R_IO_HH]) +#define RSCAN0TXQCC1 (RSCAN0.TXQCC1.UINT32) +#define RSCAN0TXQCC1L (RSCAN0.TXQCC1.UINT16[R_IO_L]) +#define RSCAN0TXQCC1LL (RSCAN0.TXQCC1.UINT8[R_IO_LL]) +#define RSCAN0TXQCC1LH (RSCAN0.TXQCC1.UINT8[R_IO_LH]) +#define RSCAN0TXQCC1H (RSCAN0.TXQCC1.UINT16[R_IO_H]) +#define RSCAN0TXQCC1HL (RSCAN0.TXQCC1.UINT8[R_IO_HL]) +#define RSCAN0TXQCC1HH (RSCAN0.TXQCC1.UINT8[R_IO_HH]) +#define RSCAN0TXQSTS0 (RSCAN0.TXQSTS0.UINT32) +#define RSCAN0TXQSTS0L (RSCAN0.TXQSTS0.UINT16[R_IO_L]) +#define RSCAN0TXQSTS0LL (RSCAN0.TXQSTS0.UINT8[R_IO_LL]) +#define RSCAN0TXQSTS0LH (RSCAN0.TXQSTS0.UINT8[R_IO_LH]) +#define RSCAN0TXQSTS0H (RSCAN0.TXQSTS0.UINT16[R_IO_H]) +#define RSCAN0TXQSTS0HL (RSCAN0.TXQSTS0.UINT8[R_IO_HL]) +#define RSCAN0TXQSTS0HH (RSCAN0.TXQSTS0.UINT8[R_IO_HH]) +#define RSCAN0TXQSTS1 (RSCAN0.TXQSTS1.UINT32) +#define RSCAN0TXQSTS1L (RSCAN0.TXQSTS1.UINT16[R_IO_L]) +#define RSCAN0TXQSTS1LL (RSCAN0.TXQSTS1.UINT8[R_IO_LL]) +#define RSCAN0TXQSTS1LH (RSCAN0.TXQSTS1.UINT8[R_IO_LH]) +#define RSCAN0TXQSTS1H (RSCAN0.TXQSTS1.UINT16[R_IO_H]) +#define RSCAN0TXQSTS1HL (RSCAN0.TXQSTS1.UINT8[R_IO_HL]) +#define RSCAN0TXQSTS1HH (RSCAN0.TXQSTS1.UINT8[R_IO_HH]) +#define RSCAN0TXQPCTR0 (RSCAN0.TXQPCTR0.UINT32) +#define RSCAN0TXQPCTR0L (RSCAN0.TXQPCTR0.UINT16[R_IO_L]) +#define RSCAN0TXQPCTR0LL (RSCAN0.TXQPCTR0.UINT8[R_IO_LL]) +#define RSCAN0TXQPCTR0LH (RSCAN0.TXQPCTR0.UINT8[R_IO_LH]) +#define RSCAN0TXQPCTR0H (RSCAN0.TXQPCTR0.UINT16[R_IO_H]) +#define RSCAN0TXQPCTR0HL (RSCAN0.TXQPCTR0.UINT8[R_IO_HL]) +#define RSCAN0TXQPCTR0HH (RSCAN0.TXQPCTR0.UINT8[R_IO_HH]) +#define RSCAN0TXQPCTR1 (RSCAN0.TXQPCTR1.UINT32) +#define RSCAN0TXQPCTR1L (RSCAN0.TXQPCTR1.UINT16[R_IO_L]) +#define RSCAN0TXQPCTR1LL (RSCAN0.TXQPCTR1.UINT8[R_IO_LL]) +#define RSCAN0TXQPCTR1LH (RSCAN0.TXQPCTR1.UINT8[R_IO_LH]) +#define RSCAN0TXQPCTR1H (RSCAN0.TXQPCTR1.UINT16[R_IO_H]) +#define RSCAN0TXQPCTR1HL (RSCAN0.TXQPCTR1.UINT8[R_IO_HL]) +#define RSCAN0TXQPCTR1HH (RSCAN0.TXQPCTR1.UINT8[R_IO_HH]) +#define RSCAN0THLCC0 (RSCAN0.THLCC0.UINT32) +#define RSCAN0THLCC0L (RSCAN0.THLCC0.UINT16[R_IO_L]) +#define RSCAN0THLCC0LL (RSCAN0.THLCC0.UINT8[R_IO_LL]) +#define RSCAN0THLCC0LH (RSCAN0.THLCC0.UINT8[R_IO_LH]) +#define RSCAN0THLCC0H (RSCAN0.THLCC0.UINT16[R_IO_H]) +#define RSCAN0THLCC0HL (RSCAN0.THLCC0.UINT8[R_IO_HL]) +#define RSCAN0THLCC0HH (RSCAN0.THLCC0.UINT8[R_IO_HH]) +#define RSCAN0THLCC1 (RSCAN0.THLCC1.UINT32) +#define RSCAN0THLCC1L (RSCAN0.THLCC1.UINT16[R_IO_L]) +#define RSCAN0THLCC1LL (RSCAN0.THLCC1.UINT8[R_IO_LL]) +#define RSCAN0THLCC1LH (RSCAN0.THLCC1.UINT8[R_IO_LH]) +#define RSCAN0THLCC1H (RSCAN0.THLCC1.UINT16[R_IO_H]) +#define RSCAN0THLCC1HL (RSCAN0.THLCC1.UINT8[R_IO_HL]) +#define RSCAN0THLCC1HH (RSCAN0.THLCC1.UINT8[R_IO_HH]) +#define RSCAN0THLSTS0 (RSCAN0.THLSTS0.UINT32) +#define RSCAN0THLSTS0L (RSCAN0.THLSTS0.UINT16[R_IO_L]) +#define RSCAN0THLSTS0LL (RSCAN0.THLSTS0.UINT8[R_IO_LL]) +#define RSCAN0THLSTS0LH (RSCAN0.THLSTS0.UINT8[R_IO_LH]) +#define RSCAN0THLSTS0H (RSCAN0.THLSTS0.UINT16[R_IO_H]) +#define RSCAN0THLSTS0HL (RSCAN0.THLSTS0.UINT8[R_IO_HL]) +#define RSCAN0THLSTS0HH (RSCAN0.THLSTS0.UINT8[R_IO_HH]) +#define RSCAN0THLSTS1 (RSCAN0.THLSTS1.UINT32) +#define RSCAN0THLSTS1L (RSCAN0.THLSTS1.UINT16[R_IO_L]) +#define RSCAN0THLSTS1LL (RSCAN0.THLSTS1.UINT8[R_IO_LL]) +#define RSCAN0THLSTS1LH (RSCAN0.THLSTS1.UINT8[R_IO_LH]) +#define RSCAN0THLSTS1H (RSCAN0.THLSTS1.UINT16[R_IO_H]) +#define RSCAN0THLSTS1HL (RSCAN0.THLSTS1.UINT8[R_IO_HL]) +#define RSCAN0THLSTS1HH (RSCAN0.THLSTS1.UINT8[R_IO_HH]) +#define RSCAN0THLPCTR0 (RSCAN0.THLPCTR0.UINT32) +#define RSCAN0THLPCTR0L (RSCAN0.THLPCTR0.UINT16[R_IO_L]) +#define RSCAN0THLPCTR0LL (RSCAN0.THLPCTR0.UINT8[R_IO_LL]) +#define RSCAN0THLPCTR0LH (RSCAN0.THLPCTR0.UINT8[R_IO_LH]) +#define RSCAN0THLPCTR0H (RSCAN0.THLPCTR0.UINT16[R_IO_H]) +#define RSCAN0THLPCTR0HL (RSCAN0.THLPCTR0.UINT8[R_IO_HL]) +#define RSCAN0THLPCTR0HH (RSCAN0.THLPCTR0.UINT8[R_IO_HH]) +#define RSCAN0THLPCTR1 (RSCAN0.THLPCTR1.UINT32) +#define RSCAN0THLPCTR1L (RSCAN0.THLPCTR1.UINT16[R_IO_L]) +#define RSCAN0THLPCTR1LL (RSCAN0.THLPCTR1.UINT8[R_IO_LL]) +#define RSCAN0THLPCTR1LH (RSCAN0.THLPCTR1.UINT8[R_IO_LH]) +#define RSCAN0THLPCTR1H (RSCAN0.THLPCTR1.UINT16[R_IO_H]) +#define RSCAN0THLPCTR1HL (RSCAN0.THLPCTR1.UINT8[R_IO_HL]) +#define RSCAN0THLPCTR1HH (RSCAN0.THLPCTR1.UINT8[R_IO_HH]) +#define RSCAN0GTINTSTS0 (RSCAN0.GTINTSTS0.UINT32) +#define RSCAN0GTINTSTS0L (RSCAN0.GTINTSTS0.UINT16[R_IO_L]) +#define RSCAN0GTINTSTS0LL (RSCAN0.GTINTSTS0.UINT8[R_IO_LL]) +#define RSCAN0GTINTSTS0LH (RSCAN0.GTINTSTS0.UINT8[R_IO_LH]) +#define RSCAN0GTINTSTS0H (RSCAN0.GTINTSTS0.UINT16[R_IO_H]) +#define RSCAN0GTINTSTS0HL (RSCAN0.GTINTSTS0.UINT8[R_IO_HL]) +#define RSCAN0GTINTSTS0HH (RSCAN0.GTINTSTS0.UINT8[R_IO_HH]) +#define RSCAN0GTSTCFG (RSCAN0.GTSTCFG.UINT32) +#define RSCAN0GTSTCFGL (RSCAN0.GTSTCFG.UINT16[R_IO_L]) +#define RSCAN0GTSTCFGLL (RSCAN0.GTSTCFG.UINT8[R_IO_LL]) +#define RSCAN0GTSTCFGLH (RSCAN0.GTSTCFG.UINT8[R_IO_LH]) +#define RSCAN0GTSTCFGH (RSCAN0.GTSTCFG.UINT16[R_IO_H]) +#define RSCAN0GTSTCFGHL (RSCAN0.GTSTCFG.UINT8[R_IO_HL]) +#define RSCAN0GTSTCFGHH (RSCAN0.GTSTCFG.UINT8[R_IO_HH]) +#define RSCAN0GTSTCTR (RSCAN0.GTSTCTR.UINT32) +#define RSCAN0GTSTCTRL (RSCAN0.GTSTCTR.UINT16[R_IO_L]) +#define RSCAN0GTSTCTRLL (RSCAN0.GTSTCTR.UINT8[R_IO_LL]) +#define RSCAN0GTSTCTRLH (RSCAN0.GTSTCTR.UINT8[R_IO_LH]) +#define RSCAN0GTSTCTRH (RSCAN0.GTSTCTR.UINT16[R_IO_H]) +#define RSCAN0GTSTCTRHL (RSCAN0.GTSTCTR.UINT8[R_IO_HL]) +#define RSCAN0GTSTCTRHH (RSCAN0.GTSTCTR.UINT8[R_IO_HH]) +#define RSCAN0GLOCKK (RSCAN0.GLOCKK.UINT32) +#define RSCAN0GLOCKKL (RSCAN0.GLOCKK.UINT16[R_IO_L]) +#define RSCAN0GLOCKKH (RSCAN0.GLOCKK.UINT16[R_IO_H]) +#define RSCAN0GAFLID0 (RSCAN0.GAFLID0.UINT32) +#define RSCAN0GAFLID0L (RSCAN0.GAFLID0.UINT16[R_IO_L]) +#define RSCAN0GAFLID0LL (RSCAN0.GAFLID0.UINT8[R_IO_LL]) +#define RSCAN0GAFLID0LH (RSCAN0.GAFLID0.UINT8[R_IO_LH]) +#define RSCAN0GAFLID0H (RSCAN0.GAFLID0.UINT16[R_IO_H]) +#define RSCAN0GAFLID0HL (RSCAN0.GAFLID0.UINT8[R_IO_HL]) +#define RSCAN0GAFLID0HH (RSCAN0.GAFLID0.UINT8[R_IO_HH]) +#define RSCAN0GAFLM0 (RSCAN0.GAFLM0.UINT32) +#define RSCAN0GAFLM0L (RSCAN0.GAFLM0.UINT16[R_IO_L]) +#define RSCAN0GAFLM0LL (RSCAN0.GAFLM0.UINT8[R_IO_LL]) +#define RSCAN0GAFLM0LH (RSCAN0.GAFLM0.UINT8[R_IO_LH]) +#define RSCAN0GAFLM0H (RSCAN0.GAFLM0.UINT16[R_IO_H]) +#define RSCAN0GAFLM0HL (RSCAN0.GAFLM0.UINT8[R_IO_HL]) +#define RSCAN0GAFLM0HH (RSCAN0.GAFLM0.UINT8[R_IO_HH]) +#define RSCAN0GAFLP00 (RSCAN0.GAFLP00.UINT32) +#define RSCAN0GAFLP00L (RSCAN0.GAFLP00.UINT16[R_IO_L]) +#define RSCAN0GAFLP00LL (RSCAN0.GAFLP00.UINT8[R_IO_LL]) +#define RSCAN0GAFLP00LH (RSCAN0.GAFLP00.UINT8[R_IO_LH]) +#define RSCAN0GAFLP00H (RSCAN0.GAFLP00.UINT16[R_IO_H]) +#define RSCAN0GAFLP00HL (RSCAN0.GAFLP00.UINT8[R_IO_HL]) +#define RSCAN0GAFLP00HH (RSCAN0.GAFLP00.UINT8[R_IO_HH]) +#define RSCAN0GAFLP10 (RSCAN0.GAFLP10.UINT32) +#define RSCAN0GAFLP10L (RSCAN0.GAFLP10.UINT16[R_IO_L]) +#define RSCAN0GAFLP10LL (RSCAN0.GAFLP10.UINT8[R_IO_LL]) +#define RSCAN0GAFLP10LH (RSCAN0.GAFLP10.UINT8[R_IO_LH]) +#define RSCAN0GAFLP10H (RSCAN0.GAFLP10.UINT16[R_IO_H]) +#define RSCAN0GAFLP10HL (RSCAN0.GAFLP10.UINT8[R_IO_HL]) +#define RSCAN0GAFLP10HH (RSCAN0.GAFLP10.UINT8[R_IO_HH]) +#define RSCAN0GAFLID1 (RSCAN0.GAFLID1.UINT32) +#define RSCAN0GAFLID1L (RSCAN0.GAFLID1.UINT16[R_IO_L]) +#define RSCAN0GAFLID1LL (RSCAN0.GAFLID1.UINT8[R_IO_LL]) +#define RSCAN0GAFLID1LH (RSCAN0.GAFLID1.UINT8[R_IO_LH]) +#define RSCAN0GAFLID1H (RSCAN0.GAFLID1.UINT16[R_IO_H]) +#define RSCAN0GAFLID1HL (RSCAN0.GAFLID1.UINT8[R_IO_HL]) +#define RSCAN0GAFLID1HH (RSCAN0.GAFLID1.UINT8[R_IO_HH]) +#define RSCAN0GAFLM1 (RSCAN0.GAFLM1.UINT32) +#define RSCAN0GAFLM1L (RSCAN0.GAFLM1.UINT16[R_IO_L]) +#define RSCAN0GAFLM1LL (RSCAN0.GAFLM1.UINT8[R_IO_LL]) +#define RSCAN0GAFLM1LH (RSCAN0.GAFLM1.UINT8[R_IO_LH]) +#define RSCAN0GAFLM1H (RSCAN0.GAFLM1.UINT16[R_IO_H]) +#define RSCAN0GAFLM1HL (RSCAN0.GAFLM1.UINT8[R_IO_HL]) +#define RSCAN0GAFLM1HH (RSCAN0.GAFLM1.UINT8[R_IO_HH]) +#define RSCAN0GAFLP01 (RSCAN0.GAFLP01.UINT32) +#define RSCAN0GAFLP01L (RSCAN0.GAFLP01.UINT16[R_IO_L]) +#define RSCAN0GAFLP01LL (RSCAN0.GAFLP01.UINT8[R_IO_LL]) +#define RSCAN0GAFLP01LH (RSCAN0.GAFLP01.UINT8[R_IO_LH]) +#define RSCAN0GAFLP01H (RSCAN0.GAFLP01.UINT16[R_IO_H]) +#define RSCAN0GAFLP01HL (RSCAN0.GAFLP01.UINT8[R_IO_HL]) +#define RSCAN0GAFLP01HH (RSCAN0.GAFLP01.UINT8[R_IO_HH]) +#define RSCAN0GAFLP11 (RSCAN0.GAFLP11.UINT32) +#define RSCAN0GAFLP11L (RSCAN0.GAFLP11.UINT16[R_IO_L]) +#define RSCAN0GAFLP11LL (RSCAN0.GAFLP11.UINT8[R_IO_LL]) +#define RSCAN0GAFLP11LH (RSCAN0.GAFLP11.UINT8[R_IO_LH]) +#define RSCAN0GAFLP11H (RSCAN0.GAFLP11.UINT16[R_IO_H]) +#define RSCAN0GAFLP11HL (RSCAN0.GAFLP11.UINT8[R_IO_HL]) +#define RSCAN0GAFLP11HH (RSCAN0.GAFLP11.UINT8[R_IO_HH]) +#define RSCAN0GAFLID2 (RSCAN0.GAFLID2.UINT32) +#define RSCAN0GAFLID2L (RSCAN0.GAFLID2.UINT16[R_IO_L]) +#define RSCAN0GAFLID2LL (RSCAN0.GAFLID2.UINT8[R_IO_LL]) +#define RSCAN0GAFLID2LH (RSCAN0.GAFLID2.UINT8[R_IO_LH]) +#define RSCAN0GAFLID2H (RSCAN0.GAFLID2.UINT16[R_IO_H]) +#define RSCAN0GAFLID2HL (RSCAN0.GAFLID2.UINT8[R_IO_HL]) +#define RSCAN0GAFLID2HH (RSCAN0.GAFLID2.UINT8[R_IO_HH]) +#define RSCAN0GAFLM2 (RSCAN0.GAFLM2.UINT32) +#define RSCAN0GAFLM2L (RSCAN0.GAFLM2.UINT16[R_IO_L]) +#define RSCAN0GAFLM2LL (RSCAN0.GAFLM2.UINT8[R_IO_LL]) +#define RSCAN0GAFLM2LH (RSCAN0.GAFLM2.UINT8[R_IO_LH]) +#define RSCAN0GAFLM2H (RSCAN0.GAFLM2.UINT16[R_IO_H]) +#define RSCAN0GAFLM2HL (RSCAN0.GAFLM2.UINT8[R_IO_HL]) +#define RSCAN0GAFLM2HH (RSCAN0.GAFLM2.UINT8[R_IO_HH]) +#define RSCAN0GAFLP02 (RSCAN0.GAFLP02.UINT32) +#define RSCAN0GAFLP02L (RSCAN0.GAFLP02.UINT16[R_IO_L]) +#define RSCAN0GAFLP02LL (RSCAN0.GAFLP02.UINT8[R_IO_LL]) +#define RSCAN0GAFLP02LH (RSCAN0.GAFLP02.UINT8[R_IO_LH]) +#define RSCAN0GAFLP02H (RSCAN0.GAFLP02.UINT16[R_IO_H]) +#define RSCAN0GAFLP02HL (RSCAN0.GAFLP02.UINT8[R_IO_HL]) +#define RSCAN0GAFLP02HH (RSCAN0.GAFLP02.UINT8[R_IO_HH]) +#define RSCAN0GAFLP12 (RSCAN0.GAFLP12.UINT32) +#define RSCAN0GAFLP12L (RSCAN0.GAFLP12.UINT16[R_IO_L]) +#define RSCAN0GAFLP12LL (RSCAN0.GAFLP12.UINT8[R_IO_LL]) +#define RSCAN0GAFLP12LH (RSCAN0.GAFLP12.UINT8[R_IO_LH]) +#define RSCAN0GAFLP12H (RSCAN0.GAFLP12.UINT16[R_IO_H]) +#define RSCAN0GAFLP12HL (RSCAN0.GAFLP12.UINT8[R_IO_HL]) +#define RSCAN0GAFLP12HH (RSCAN0.GAFLP12.UINT8[R_IO_HH]) +#define RSCAN0GAFLID3 (RSCAN0.GAFLID3.UINT32) +#define RSCAN0GAFLID3L (RSCAN0.GAFLID3.UINT16[R_IO_L]) +#define RSCAN0GAFLID3LL (RSCAN0.GAFLID3.UINT8[R_IO_LL]) +#define RSCAN0GAFLID3LH (RSCAN0.GAFLID3.UINT8[R_IO_LH]) +#define RSCAN0GAFLID3H (RSCAN0.GAFLID3.UINT16[R_IO_H]) +#define RSCAN0GAFLID3HL (RSCAN0.GAFLID3.UINT8[R_IO_HL]) +#define RSCAN0GAFLID3HH (RSCAN0.GAFLID3.UINT8[R_IO_HH]) +#define RSCAN0GAFLM3 (RSCAN0.GAFLM3.UINT32) +#define RSCAN0GAFLM3L (RSCAN0.GAFLM3.UINT16[R_IO_L]) +#define RSCAN0GAFLM3LL (RSCAN0.GAFLM3.UINT8[R_IO_LL]) +#define RSCAN0GAFLM3LH (RSCAN0.GAFLM3.UINT8[R_IO_LH]) +#define RSCAN0GAFLM3H (RSCAN0.GAFLM3.UINT16[R_IO_H]) +#define RSCAN0GAFLM3HL (RSCAN0.GAFLM3.UINT8[R_IO_HL]) +#define RSCAN0GAFLM3HH (RSCAN0.GAFLM3.UINT8[R_IO_HH]) +#define RSCAN0GAFLP03 (RSCAN0.GAFLP03.UINT32) +#define RSCAN0GAFLP03L (RSCAN0.GAFLP03.UINT16[R_IO_L]) +#define RSCAN0GAFLP03LL (RSCAN0.GAFLP03.UINT8[R_IO_LL]) +#define RSCAN0GAFLP03LH (RSCAN0.GAFLP03.UINT8[R_IO_LH]) +#define RSCAN0GAFLP03H (RSCAN0.GAFLP03.UINT16[R_IO_H]) +#define RSCAN0GAFLP03HL (RSCAN0.GAFLP03.UINT8[R_IO_HL]) +#define RSCAN0GAFLP03HH (RSCAN0.GAFLP03.UINT8[R_IO_HH]) +#define RSCAN0GAFLP13 (RSCAN0.GAFLP13.UINT32) +#define RSCAN0GAFLP13L (RSCAN0.GAFLP13.UINT16[R_IO_L]) +#define RSCAN0GAFLP13LL (RSCAN0.GAFLP13.UINT8[R_IO_LL]) +#define RSCAN0GAFLP13LH (RSCAN0.GAFLP13.UINT8[R_IO_LH]) +#define RSCAN0GAFLP13H (RSCAN0.GAFLP13.UINT16[R_IO_H]) +#define RSCAN0GAFLP13HL (RSCAN0.GAFLP13.UINT8[R_IO_HL]) +#define RSCAN0GAFLP13HH (RSCAN0.GAFLP13.UINT8[R_IO_HH]) +#define RSCAN0GAFLID4 (RSCAN0.GAFLID4.UINT32) +#define RSCAN0GAFLID4L (RSCAN0.GAFLID4.UINT16[R_IO_L]) +#define RSCAN0GAFLID4LL (RSCAN0.GAFLID4.UINT8[R_IO_LL]) +#define RSCAN0GAFLID4LH (RSCAN0.GAFLID4.UINT8[R_IO_LH]) +#define RSCAN0GAFLID4H (RSCAN0.GAFLID4.UINT16[R_IO_H]) +#define RSCAN0GAFLID4HL (RSCAN0.GAFLID4.UINT8[R_IO_HL]) +#define RSCAN0GAFLID4HH (RSCAN0.GAFLID4.UINT8[R_IO_HH]) +#define RSCAN0GAFLM4 (RSCAN0.GAFLM4.UINT32) +#define RSCAN0GAFLM4L (RSCAN0.GAFLM4.UINT16[R_IO_L]) +#define RSCAN0GAFLM4LL (RSCAN0.GAFLM4.UINT8[R_IO_LL]) +#define RSCAN0GAFLM4LH (RSCAN0.GAFLM4.UINT8[R_IO_LH]) +#define RSCAN0GAFLM4H (RSCAN0.GAFLM4.UINT16[R_IO_H]) +#define RSCAN0GAFLM4HL (RSCAN0.GAFLM4.UINT8[R_IO_HL]) +#define RSCAN0GAFLM4HH (RSCAN0.GAFLM4.UINT8[R_IO_HH]) +#define RSCAN0GAFLP04 (RSCAN0.GAFLP04.UINT32) +#define RSCAN0GAFLP04L (RSCAN0.GAFLP04.UINT16[R_IO_L]) +#define RSCAN0GAFLP04LL (RSCAN0.GAFLP04.UINT8[R_IO_LL]) +#define RSCAN0GAFLP04LH (RSCAN0.GAFLP04.UINT8[R_IO_LH]) +#define RSCAN0GAFLP04H (RSCAN0.GAFLP04.UINT16[R_IO_H]) +#define RSCAN0GAFLP04HL (RSCAN0.GAFLP04.UINT8[R_IO_HL]) +#define RSCAN0GAFLP04HH (RSCAN0.GAFLP04.UINT8[R_IO_HH]) +#define RSCAN0GAFLP14 (RSCAN0.GAFLP14.UINT32) +#define RSCAN0GAFLP14L (RSCAN0.GAFLP14.UINT16[R_IO_L]) +#define RSCAN0GAFLP14LL (RSCAN0.GAFLP14.UINT8[R_IO_LL]) +#define RSCAN0GAFLP14LH (RSCAN0.GAFLP14.UINT8[R_IO_LH]) +#define RSCAN0GAFLP14H (RSCAN0.GAFLP14.UINT16[R_IO_H]) +#define RSCAN0GAFLP14HL (RSCAN0.GAFLP14.UINT8[R_IO_HL]) +#define RSCAN0GAFLP14HH (RSCAN0.GAFLP14.UINT8[R_IO_HH]) +#define RSCAN0GAFLID5 (RSCAN0.GAFLID5.UINT32) +#define RSCAN0GAFLID5L (RSCAN0.GAFLID5.UINT16[R_IO_L]) +#define RSCAN0GAFLID5LL (RSCAN0.GAFLID5.UINT8[R_IO_LL]) +#define RSCAN0GAFLID5LH (RSCAN0.GAFLID5.UINT8[R_IO_LH]) +#define RSCAN0GAFLID5H (RSCAN0.GAFLID5.UINT16[R_IO_H]) +#define RSCAN0GAFLID5HL (RSCAN0.GAFLID5.UINT8[R_IO_HL]) +#define RSCAN0GAFLID5HH (RSCAN0.GAFLID5.UINT8[R_IO_HH]) +#define RSCAN0GAFLM5 (RSCAN0.GAFLM5.UINT32) +#define RSCAN0GAFLM5L (RSCAN0.GAFLM5.UINT16[R_IO_L]) +#define RSCAN0GAFLM5LL (RSCAN0.GAFLM5.UINT8[R_IO_LL]) +#define RSCAN0GAFLM5LH (RSCAN0.GAFLM5.UINT8[R_IO_LH]) +#define RSCAN0GAFLM5H (RSCAN0.GAFLM5.UINT16[R_IO_H]) +#define RSCAN0GAFLM5HL (RSCAN0.GAFLM5.UINT8[R_IO_HL]) +#define RSCAN0GAFLM5HH (RSCAN0.GAFLM5.UINT8[R_IO_HH]) +#define RSCAN0GAFLP05 (RSCAN0.GAFLP05.UINT32) +#define RSCAN0GAFLP05L (RSCAN0.GAFLP05.UINT16[R_IO_L]) +#define RSCAN0GAFLP05LL (RSCAN0.GAFLP05.UINT8[R_IO_LL]) +#define RSCAN0GAFLP05LH (RSCAN0.GAFLP05.UINT8[R_IO_LH]) +#define RSCAN0GAFLP05H (RSCAN0.GAFLP05.UINT16[R_IO_H]) +#define RSCAN0GAFLP05HL (RSCAN0.GAFLP05.UINT8[R_IO_HL]) +#define RSCAN0GAFLP05HH (RSCAN0.GAFLP05.UINT8[R_IO_HH]) +#define RSCAN0GAFLP15 (RSCAN0.GAFLP15.UINT32) +#define RSCAN0GAFLP15L (RSCAN0.GAFLP15.UINT16[R_IO_L]) +#define RSCAN0GAFLP15LL (RSCAN0.GAFLP15.UINT8[R_IO_LL]) +#define RSCAN0GAFLP15LH (RSCAN0.GAFLP15.UINT8[R_IO_LH]) +#define RSCAN0GAFLP15H (RSCAN0.GAFLP15.UINT16[R_IO_H]) +#define RSCAN0GAFLP15HL (RSCAN0.GAFLP15.UINT8[R_IO_HL]) +#define RSCAN0GAFLP15HH (RSCAN0.GAFLP15.UINT8[R_IO_HH]) +#define RSCAN0GAFLID6 (RSCAN0.GAFLID6.UINT32) +#define RSCAN0GAFLID6L (RSCAN0.GAFLID6.UINT16[R_IO_L]) +#define RSCAN0GAFLID6LL (RSCAN0.GAFLID6.UINT8[R_IO_LL]) +#define RSCAN0GAFLID6LH (RSCAN0.GAFLID6.UINT8[R_IO_LH]) +#define RSCAN0GAFLID6H (RSCAN0.GAFLID6.UINT16[R_IO_H]) +#define RSCAN0GAFLID6HL (RSCAN0.GAFLID6.UINT8[R_IO_HL]) +#define RSCAN0GAFLID6HH (RSCAN0.GAFLID6.UINT8[R_IO_HH]) +#define RSCAN0GAFLM6 (RSCAN0.GAFLM6.UINT32) +#define RSCAN0GAFLM6L (RSCAN0.GAFLM6.UINT16[R_IO_L]) +#define RSCAN0GAFLM6LL (RSCAN0.GAFLM6.UINT8[R_IO_LL]) +#define RSCAN0GAFLM6LH (RSCAN0.GAFLM6.UINT8[R_IO_LH]) +#define RSCAN0GAFLM6H (RSCAN0.GAFLM6.UINT16[R_IO_H]) +#define RSCAN0GAFLM6HL (RSCAN0.GAFLM6.UINT8[R_IO_HL]) +#define RSCAN0GAFLM6HH (RSCAN0.GAFLM6.UINT8[R_IO_HH]) +#define RSCAN0GAFLP06 (RSCAN0.GAFLP06.UINT32) +#define RSCAN0GAFLP06L (RSCAN0.GAFLP06.UINT16[R_IO_L]) +#define RSCAN0GAFLP06LL (RSCAN0.GAFLP06.UINT8[R_IO_LL]) +#define RSCAN0GAFLP06LH (RSCAN0.GAFLP06.UINT8[R_IO_LH]) +#define RSCAN0GAFLP06H (RSCAN0.GAFLP06.UINT16[R_IO_H]) +#define RSCAN0GAFLP06HL (RSCAN0.GAFLP06.UINT8[R_IO_HL]) +#define RSCAN0GAFLP06HH (RSCAN0.GAFLP06.UINT8[R_IO_HH]) +#define RSCAN0GAFLP16 (RSCAN0.GAFLP16.UINT32) +#define RSCAN0GAFLP16L (RSCAN0.GAFLP16.UINT16[R_IO_L]) +#define RSCAN0GAFLP16LL (RSCAN0.GAFLP16.UINT8[R_IO_LL]) +#define RSCAN0GAFLP16LH (RSCAN0.GAFLP16.UINT8[R_IO_LH]) +#define RSCAN0GAFLP16H (RSCAN0.GAFLP16.UINT16[R_IO_H]) +#define RSCAN0GAFLP16HL (RSCAN0.GAFLP16.UINT8[R_IO_HL]) +#define RSCAN0GAFLP16HH (RSCAN0.GAFLP16.UINT8[R_IO_HH]) +#define RSCAN0GAFLID7 (RSCAN0.GAFLID7.UINT32) +#define RSCAN0GAFLID7L (RSCAN0.GAFLID7.UINT16[R_IO_L]) +#define RSCAN0GAFLID7LL (RSCAN0.GAFLID7.UINT8[R_IO_LL]) +#define RSCAN0GAFLID7LH (RSCAN0.GAFLID7.UINT8[R_IO_LH]) +#define RSCAN0GAFLID7H (RSCAN0.GAFLID7.UINT16[R_IO_H]) +#define RSCAN0GAFLID7HL (RSCAN0.GAFLID7.UINT8[R_IO_HL]) +#define RSCAN0GAFLID7HH (RSCAN0.GAFLID7.UINT8[R_IO_HH]) +#define RSCAN0GAFLM7 (RSCAN0.GAFLM7.UINT32) +#define RSCAN0GAFLM7L (RSCAN0.GAFLM7.UINT16[R_IO_L]) +#define RSCAN0GAFLM7LL (RSCAN0.GAFLM7.UINT8[R_IO_LL]) +#define RSCAN0GAFLM7LH (RSCAN0.GAFLM7.UINT8[R_IO_LH]) +#define RSCAN0GAFLM7H (RSCAN0.GAFLM7.UINT16[R_IO_H]) +#define RSCAN0GAFLM7HL (RSCAN0.GAFLM7.UINT8[R_IO_HL]) +#define RSCAN0GAFLM7HH (RSCAN0.GAFLM7.UINT8[R_IO_HH]) +#define RSCAN0GAFLP07 (RSCAN0.GAFLP07.UINT32) +#define RSCAN0GAFLP07L (RSCAN0.GAFLP07.UINT16[R_IO_L]) +#define RSCAN0GAFLP07LL (RSCAN0.GAFLP07.UINT8[R_IO_LL]) +#define RSCAN0GAFLP07LH (RSCAN0.GAFLP07.UINT8[R_IO_LH]) +#define RSCAN0GAFLP07H (RSCAN0.GAFLP07.UINT16[R_IO_H]) +#define RSCAN0GAFLP07HL (RSCAN0.GAFLP07.UINT8[R_IO_HL]) +#define RSCAN0GAFLP07HH (RSCAN0.GAFLP07.UINT8[R_IO_HH]) +#define RSCAN0GAFLP17 (RSCAN0.GAFLP17.UINT32) +#define RSCAN0GAFLP17L (RSCAN0.GAFLP17.UINT16[R_IO_L]) +#define RSCAN0GAFLP17LL (RSCAN0.GAFLP17.UINT8[R_IO_LL]) +#define RSCAN0GAFLP17LH (RSCAN0.GAFLP17.UINT8[R_IO_LH]) +#define RSCAN0GAFLP17H (RSCAN0.GAFLP17.UINT16[R_IO_H]) +#define RSCAN0GAFLP17HL (RSCAN0.GAFLP17.UINT8[R_IO_HL]) +#define RSCAN0GAFLP17HH (RSCAN0.GAFLP17.UINT8[R_IO_HH]) +#define RSCAN0GAFLID8 (RSCAN0.GAFLID8.UINT32) +#define RSCAN0GAFLID8L (RSCAN0.GAFLID8.UINT16[R_IO_L]) +#define RSCAN0GAFLID8LL (RSCAN0.GAFLID8.UINT8[R_IO_LL]) +#define RSCAN0GAFLID8LH (RSCAN0.GAFLID8.UINT8[R_IO_LH]) +#define RSCAN0GAFLID8H (RSCAN0.GAFLID8.UINT16[R_IO_H]) +#define RSCAN0GAFLID8HL (RSCAN0.GAFLID8.UINT8[R_IO_HL]) +#define RSCAN0GAFLID8HH (RSCAN0.GAFLID8.UINT8[R_IO_HH]) +#define RSCAN0GAFLM8 (RSCAN0.GAFLM8.UINT32) +#define RSCAN0GAFLM8L (RSCAN0.GAFLM8.UINT16[R_IO_L]) +#define RSCAN0GAFLM8LL (RSCAN0.GAFLM8.UINT8[R_IO_LL]) +#define RSCAN0GAFLM8LH (RSCAN0.GAFLM8.UINT8[R_IO_LH]) +#define RSCAN0GAFLM8H (RSCAN0.GAFLM8.UINT16[R_IO_H]) +#define RSCAN0GAFLM8HL (RSCAN0.GAFLM8.UINT8[R_IO_HL]) +#define RSCAN0GAFLM8HH (RSCAN0.GAFLM8.UINT8[R_IO_HH]) +#define RSCAN0GAFLP08 (RSCAN0.GAFLP08.UINT32) +#define RSCAN0GAFLP08L (RSCAN0.GAFLP08.UINT16[R_IO_L]) +#define RSCAN0GAFLP08LL (RSCAN0.GAFLP08.UINT8[R_IO_LL]) +#define RSCAN0GAFLP08LH (RSCAN0.GAFLP08.UINT8[R_IO_LH]) +#define RSCAN0GAFLP08H (RSCAN0.GAFLP08.UINT16[R_IO_H]) +#define RSCAN0GAFLP08HL (RSCAN0.GAFLP08.UINT8[R_IO_HL]) +#define RSCAN0GAFLP08HH (RSCAN0.GAFLP08.UINT8[R_IO_HH]) +#define RSCAN0GAFLP18 (RSCAN0.GAFLP18.UINT32) +#define RSCAN0GAFLP18L (RSCAN0.GAFLP18.UINT16[R_IO_L]) +#define RSCAN0GAFLP18LL (RSCAN0.GAFLP18.UINT8[R_IO_LL]) +#define RSCAN0GAFLP18LH (RSCAN0.GAFLP18.UINT8[R_IO_LH]) +#define RSCAN0GAFLP18H (RSCAN0.GAFLP18.UINT16[R_IO_H]) +#define RSCAN0GAFLP18HL (RSCAN0.GAFLP18.UINT8[R_IO_HL]) +#define RSCAN0GAFLP18HH (RSCAN0.GAFLP18.UINT8[R_IO_HH]) +#define RSCAN0GAFLID9 (RSCAN0.GAFLID9.UINT32) +#define RSCAN0GAFLID9L (RSCAN0.GAFLID9.UINT16[R_IO_L]) +#define RSCAN0GAFLID9LL (RSCAN0.GAFLID9.UINT8[R_IO_LL]) +#define RSCAN0GAFLID9LH (RSCAN0.GAFLID9.UINT8[R_IO_LH]) +#define RSCAN0GAFLID9H (RSCAN0.GAFLID9.UINT16[R_IO_H]) +#define RSCAN0GAFLID9HL (RSCAN0.GAFLID9.UINT8[R_IO_HL]) +#define RSCAN0GAFLID9HH (RSCAN0.GAFLID9.UINT8[R_IO_HH]) +#define RSCAN0GAFLM9 (RSCAN0.GAFLM9.UINT32) +#define RSCAN0GAFLM9L (RSCAN0.GAFLM9.UINT16[R_IO_L]) +#define RSCAN0GAFLM9LL (RSCAN0.GAFLM9.UINT8[R_IO_LL]) +#define RSCAN0GAFLM9LH (RSCAN0.GAFLM9.UINT8[R_IO_LH]) +#define RSCAN0GAFLM9H (RSCAN0.GAFLM9.UINT16[R_IO_H]) +#define RSCAN0GAFLM9HL (RSCAN0.GAFLM9.UINT8[R_IO_HL]) +#define RSCAN0GAFLM9HH (RSCAN0.GAFLM9.UINT8[R_IO_HH]) +#define RSCAN0GAFLP09 (RSCAN0.GAFLP09.UINT32) +#define RSCAN0GAFLP09L (RSCAN0.GAFLP09.UINT16[R_IO_L]) +#define RSCAN0GAFLP09LL (RSCAN0.GAFLP09.UINT8[R_IO_LL]) +#define RSCAN0GAFLP09LH (RSCAN0.GAFLP09.UINT8[R_IO_LH]) +#define RSCAN0GAFLP09H (RSCAN0.GAFLP09.UINT16[R_IO_H]) +#define RSCAN0GAFLP09HL (RSCAN0.GAFLP09.UINT8[R_IO_HL]) +#define RSCAN0GAFLP09HH (RSCAN0.GAFLP09.UINT8[R_IO_HH]) +#define RSCAN0GAFLP19 (RSCAN0.GAFLP19.UINT32) +#define RSCAN0GAFLP19L (RSCAN0.GAFLP19.UINT16[R_IO_L]) +#define RSCAN0GAFLP19LL (RSCAN0.GAFLP19.UINT8[R_IO_LL]) +#define RSCAN0GAFLP19LH (RSCAN0.GAFLP19.UINT8[R_IO_LH]) +#define RSCAN0GAFLP19H (RSCAN0.GAFLP19.UINT16[R_IO_H]) +#define RSCAN0GAFLP19HL (RSCAN0.GAFLP19.UINT8[R_IO_HL]) +#define RSCAN0GAFLP19HH (RSCAN0.GAFLP19.UINT8[R_IO_HH]) +#define RSCAN0GAFLID10 (RSCAN0.GAFLID10.UINT32) +#define RSCAN0GAFLID10L (RSCAN0.GAFLID10.UINT16[R_IO_L]) +#define RSCAN0GAFLID10LL (RSCAN0.GAFLID10.UINT8[R_IO_LL]) +#define RSCAN0GAFLID10LH (RSCAN0.GAFLID10.UINT8[R_IO_LH]) +#define RSCAN0GAFLID10H (RSCAN0.GAFLID10.UINT16[R_IO_H]) +#define RSCAN0GAFLID10HL (RSCAN0.GAFLID10.UINT8[R_IO_HL]) +#define RSCAN0GAFLID10HH (RSCAN0.GAFLID10.UINT8[R_IO_HH]) +#define RSCAN0GAFLM10 (RSCAN0.GAFLM10.UINT32) +#define RSCAN0GAFLM10L (RSCAN0.GAFLM10.UINT16[R_IO_L]) +#define RSCAN0GAFLM10LL (RSCAN0.GAFLM10.UINT8[R_IO_LL]) +#define RSCAN0GAFLM10LH (RSCAN0.GAFLM10.UINT8[R_IO_LH]) +#define RSCAN0GAFLM10H (RSCAN0.GAFLM10.UINT16[R_IO_H]) +#define RSCAN0GAFLM10HL (RSCAN0.GAFLM10.UINT8[R_IO_HL]) +#define RSCAN0GAFLM10HH (RSCAN0.GAFLM10.UINT8[R_IO_HH]) +#define RSCAN0GAFLP010 (RSCAN0.GAFLP010.UINT32) +#define RSCAN0GAFLP010L (RSCAN0.GAFLP010.UINT16[R_IO_L]) +#define RSCAN0GAFLP010LL (RSCAN0.GAFLP010.UINT8[R_IO_LL]) +#define RSCAN0GAFLP010LH (RSCAN0.GAFLP010.UINT8[R_IO_LH]) +#define RSCAN0GAFLP010H (RSCAN0.GAFLP010.UINT16[R_IO_H]) +#define RSCAN0GAFLP010HL (RSCAN0.GAFLP010.UINT8[R_IO_HL]) +#define RSCAN0GAFLP010HH (RSCAN0.GAFLP010.UINT8[R_IO_HH]) +#define RSCAN0GAFLP110 (RSCAN0.GAFLP110.UINT32) +#define RSCAN0GAFLP110L (RSCAN0.GAFLP110.UINT16[R_IO_L]) +#define RSCAN0GAFLP110LL (RSCAN0.GAFLP110.UINT8[R_IO_LL]) +#define RSCAN0GAFLP110LH (RSCAN0.GAFLP110.UINT8[R_IO_LH]) +#define RSCAN0GAFLP110H (RSCAN0.GAFLP110.UINT16[R_IO_H]) +#define RSCAN0GAFLP110HL (RSCAN0.GAFLP110.UINT8[R_IO_HL]) +#define RSCAN0GAFLP110HH (RSCAN0.GAFLP110.UINT8[R_IO_HH]) +#define RSCAN0GAFLID11 (RSCAN0.GAFLID11.UINT32) +#define RSCAN0GAFLID11L (RSCAN0.GAFLID11.UINT16[R_IO_L]) +#define RSCAN0GAFLID11LL (RSCAN0.GAFLID11.UINT8[R_IO_LL]) +#define RSCAN0GAFLID11LH (RSCAN0.GAFLID11.UINT8[R_IO_LH]) +#define RSCAN0GAFLID11H (RSCAN0.GAFLID11.UINT16[R_IO_H]) +#define RSCAN0GAFLID11HL (RSCAN0.GAFLID11.UINT8[R_IO_HL]) +#define RSCAN0GAFLID11HH (RSCAN0.GAFLID11.UINT8[R_IO_HH]) +#define RSCAN0GAFLM11 (RSCAN0.GAFLM11.UINT32) +#define RSCAN0GAFLM11L (RSCAN0.GAFLM11.UINT16[R_IO_L]) +#define RSCAN0GAFLM11LL (RSCAN0.GAFLM11.UINT8[R_IO_LL]) +#define RSCAN0GAFLM11LH (RSCAN0.GAFLM11.UINT8[R_IO_LH]) +#define RSCAN0GAFLM11H (RSCAN0.GAFLM11.UINT16[R_IO_H]) +#define RSCAN0GAFLM11HL (RSCAN0.GAFLM11.UINT8[R_IO_HL]) +#define RSCAN0GAFLM11HH (RSCAN0.GAFLM11.UINT8[R_IO_HH]) +#define RSCAN0GAFLP011 (RSCAN0.GAFLP011.UINT32) +#define RSCAN0GAFLP011L (RSCAN0.GAFLP011.UINT16[R_IO_L]) +#define RSCAN0GAFLP011LL (RSCAN0.GAFLP011.UINT8[R_IO_LL]) +#define RSCAN0GAFLP011LH (RSCAN0.GAFLP011.UINT8[R_IO_LH]) +#define RSCAN0GAFLP011H (RSCAN0.GAFLP011.UINT16[R_IO_H]) +#define RSCAN0GAFLP011HL (RSCAN0.GAFLP011.UINT8[R_IO_HL]) +#define RSCAN0GAFLP011HH (RSCAN0.GAFLP011.UINT8[R_IO_HH]) +#define RSCAN0GAFLP111 (RSCAN0.GAFLP111.UINT32) +#define RSCAN0GAFLP111L (RSCAN0.GAFLP111.UINT16[R_IO_L]) +#define RSCAN0GAFLP111LL (RSCAN0.GAFLP111.UINT8[R_IO_LL]) +#define RSCAN0GAFLP111LH (RSCAN0.GAFLP111.UINT8[R_IO_LH]) +#define RSCAN0GAFLP111H (RSCAN0.GAFLP111.UINT16[R_IO_H]) +#define RSCAN0GAFLP111HL (RSCAN0.GAFLP111.UINT8[R_IO_HL]) +#define RSCAN0GAFLP111HH (RSCAN0.GAFLP111.UINT8[R_IO_HH]) +#define RSCAN0GAFLID12 (RSCAN0.GAFLID12.UINT32) +#define RSCAN0GAFLID12L (RSCAN0.GAFLID12.UINT16[R_IO_L]) +#define RSCAN0GAFLID12LL (RSCAN0.GAFLID12.UINT8[R_IO_LL]) +#define RSCAN0GAFLID12LH (RSCAN0.GAFLID12.UINT8[R_IO_LH]) +#define RSCAN0GAFLID12H (RSCAN0.GAFLID12.UINT16[R_IO_H]) +#define RSCAN0GAFLID12HL (RSCAN0.GAFLID12.UINT8[R_IO_HL]) +#define RSCAN0GAFLID12HH (RSCAN0.GAFLID12.UINT8[R_IO_HH]) +#define RSCAN0GAFLM12 (RSCAN0.GAFLM12.UINT32) +#define RSCAN0GAFLM12L (RSCAN0.GAFLM12.UINT16[R_IO_L]) +#define RSCAN0GAFLM12LL (RSCAN0.GAFLM12.UINT8[R_IO_LL]) +#define RSCAN0GAFLM12LH (RSCAN0.GAFLM12.UINT8[R_IO_LH]) +#define RSCAN0GAFLM12H (RSCAN0.GAFLM12.UINT16[R_IO_H]) +#define RSCAN0GAFLM12HL (RSCAN0.GAFLM12.UINT8[R_IO_HL]) +#define RSCAN0GAFLM12HH (RSCAN0.GAFLM12.UINT8[R_IO_HH]) +#define RSCAN0GAFLP012 (RSCAN0.GAFLP012.UINT32) +#define RSCAN0GAFLP012L (RSCAN0.GAFLP012.UINT16[R_IO_L]) +#define RSCAN0GAFLP012LL (RSCAN0.GAFLP012.UINT8[R_IO_LL]) +#define RSCAN0GAFLP012LH (RSCAN0.GAFLP012.UINT8[R_IO_LH]) +#define RSCAN0GAFLP012H (RSCAN0.GAFLP012.UINT16[R_IO_H]) +#define RSCAN0GAFLP012HL (RSCAN0.GAFLP012.UINT8[R_IO_HL]) +#define RSCAN0GAFLP012HH (RSCAN0.GAFLP012.UINT8[R_IO_HH]) +#define RSCAN0GAFLP112 (RSCAN0.GAFLP112.UINT32) +#define RSCAN0GAFLP112L (RSCAN0.GAFLP112.UINT16[R_IO_L]) +#define RSCAN0GAFLP112LL (RSCAN0.GAFLP112.UINT8[R_IO_LL]) +#define RSCAN0GAFLP112LH (RSCAN0.GAFLP112.UINT8[R_IO_LH]) +#define RSCAN0GAFLP112H (RSCAN0.GAFLP112.UINT16[R_IO_H]) +#define RSCAN0GAFLP112HL (RSCAN0.GAFLP112.UINT8[R_IO_HL]) +#define RSCAN0GAFLP112HH (RSCAN0.GAFLP112.UINT8[R_IO_HH]) +#define RSCAN0GAFLID13 (RSCAN0.GAFLID13.UINT32) +#define RSCAN0GAFLID13L (RSCAN0.GAFLID13.UINT16[R_IO_L]) +#define RSCAN0GAFLID13LL (RSCAN0.GAFLID13.UINT8[R_IO_LL]) +#define RSCAN0GAFLID13LH (RSCAN0.GAFLID13.UINT8[R_IO_LH]) +#define RSCAN0GAFLID13H (RSCAN0.GAFLID13.UINT16[R_IO_H]) +#define RSCAN0GAFLID13HL (RSCAN0.GAFLID13.UINT8[R_IO_HL]) +#define RSCAN0GAFLID13HH (RSCAN0.GAFLID13.UINT8[R_IO_HH]) +#define RSCAN0GAFLM13 (RSCAN0.GAFLM13.UINT32) +#define RSCAN0GAFLM13L (RSCAN0.GAFLM13.UINT16[R_IO_L]) +#define RSCAN0GAFLM13LL (RSCAN0.GAFLM13.UINT8[R_IO_LL]) +#define RSCAN0GAFLM13LH (RSCAN0.GAFLM13.UINT8[R_IO_LH]) +#define RSCAN0GAFLM13H (RSCAN0.GAFLM13.UINT16[R_IO_H]) +#define RSCAN0GAFLM13HL (RSCAN0.GAFLM13.UINT8[R_IO_HL]) +#define RSCAN0GAFLM13HH (RSCAN0.GAFLM13.UINT8[R_IO_HH]) +#define RSCAN0GAFLP013 (RSCAN0.GAFLP013.UINT32) +#define RSCAN0GAFLP013L (RSCAN0.GAFLP013.UINT16[R_IO_L]) +#define RSCAN0GAFLP013LL (RSCAN0.GAFLP013.UINT8[R_IO_LL]) +#define RSCAN0GAFLP013LH (RSCAN0.GAFLP013.UINT8[R_IO_LH]) +#define RSCAN0GAFLP013H (RSCAN0.GAFLP013.UINT16[R_IO_H]) +#define RSCAN0GAFLP013HL (RSCAN0.GAFLP013.UINT8[R_IO_HL]) +#define RSCAN0GAFLP013HH (RSCAN0.GAFLP013.UINT8[R_IO_HH]) +#define RSCAN0GAFLP113 (RSCAN0.GAFLP113.UINT32) +#define RSCAN0GAFLP113L (RSCAN0.GAFLP113.UINT16[R_IO_L]) +#define RSCAN0GAFLP113LL (RSCAN0.GAFLP113.UINT8[R_IO_LL]) +#define RSCAN0GAFLP113LH (RSCAN0.GAFLP113.UINT8[R_IO_LH]) +#define RSCAN0GAFLP113H (RSCAN0.GAFLP113.UINT16[R_IO_H]) +#define RSCAN0GAFLP113HL (RSCAN0.GAFLP113.UINT8[R_IO_HL]) +#define RSCAN0GAFLP113HH (RSCAN0.GAFLP113.UINT8[R_IO_HH]) +#define RSCAN0GAFLID14 (RSCAN0.GAFLID14.UINT32) +#define RSCAN0GAFLID14L (RSCAN0.GAFLID14.UINT16[R_IO_L]) +#define RSCAN0GAFLID14LL (RSCAN0.GAFLID14.UINT8[R_IO_LL]) +#define RSCAN0GAFLID14LH (RSCAN0.GAFLID14.UINT8[R_IO_LH]) +#define RSCAN0GAFLID14H (RSCAN0.GAFLID14.UINT16[R_IO_H]) +#define RSCAN0GAFLID14HL (RSCAN0.GAFLID14.UINT8[R_IO_HL]) +#define RSCAN0GAFLID14HH (RSCAN0.GAFLID14.UINT8[R_IO_HH]) +#define RSCAN0GAFLM14 (RSCAN0.GAFLM14.UINT32) +#define RSCAN0GAFLM14L (RSCAN0.GAFLM14.UINT16[R_IO_L]) +#define RSCAN0GAFLM14LL (RSCAN0.GAFLM14.UINT8[R_IO_LL]) +#define RSCAN0GAFLM14LH (RSCAN0.GAFLM14.UINT8[R_IO_LH]) +#define RSCAN0GAFLM14H (RSCAN0.GAFLM14.UINT16[R_IO_H]) +#define RSCAN0GAFLM14HL (RSCAN0.GAFLM14.UINT8[R_IO_HL]) +#define RSCAN0GAFLM14HH (RSCAN0.GAFLM14.UINT8[R_IO_HH]) +#define RSCAN0GAFLP014 (RSCAN0.GAFLP014.UINT32) +#define RSCAN0GAFLP014L (RSCAN0.GAFLP014.UINT16[R_IO_L]) +#define RSCAN0GAFLP014LL (RSCAN0.GAFLP014.UINT8[R_IO_LL]) +#define RSCAN0GAFLP014LH (RSCAN0.GAFLP014.UINT8[R_IO_LH]) +#define RSCAN0GAFLP014H (RSCAN0.GAFLP014.UINT16[R_IO_H]) +#define RSCAN0GAFLP014HL (RSCAN0.GAFLP014.UINT8[R_IO_HL]) +#define RSCAN0GAFLP014HH (RSCAN0.GAFLP014.UINT8[R_IO_HH]) +#define RSCAN0GAFLP114 (RSCAN0.GAFLP114.UINT32) +#define RSCAN0GAFLP114L (RSCAN0.GAFLP114.UINT16[R_IO_L]) +#define RSCAN0GAFLP114LL (RSCAN0.GAFLP114.UINT8[R_IO_LL]) +#define RSCAN0GAFLP114LH (RSCAN0.GAFLP114.UINT8[R_IO_LH]) +#define RSCAN0GAFLP114H (RSCAN0.GAFLP114.UINT16[R_IO_H]) +#define RSCAN0GAFLP114HL (RSCAN0.GAFLP114.UINT8[R_IO_HL]) +#define RSCAN0GAFLP114HH (RSCAN0.GAFLP114.UINT8[R_IO_HH]) +#define RSCAN0GAFLID15 (RSCAN0.GAFLID15.UINT32) +#define RSCAN0GAFLID15L (RSCAN0.GAFLID15.UINT16[R_IO_L]) +#define RSCAN0GAFLID15LL (RSCAN0.GAFLID15.UINT8[R_IO_LL]) +#define RSCAN0GAFLID15LH (RSCAN0.GAFLID15.UINT8[R_IO_LH]) +#define RSCAN0GAFLID15H (RSCAN0.GAFLID15.UINT16[R_IO_H]) +#define RSCAN0GAFLID15HL (RSCAN0.GAFLID15.UINT8[R_IO_HL]) +#define RSCAN0GAFLID15HH (RSCAN0.GAFLID15.UINT8[R_IO_HH]) +#define RSCAN0GAFLM15 (RSCAN0.GAFLM15.UINT32) +#define RSCAN0GAFLM15L (RSCAN0.GAFLM15.UINT16[R_IO_L]) +#define RSCAN0GAFLM15LL (RSCAN0.GAFLM15.UINT8[R_IO_LL]) +#define RSCAN0GAFLM15LH (RSCAN0.GAFLM15.UINT8[R_IO_LH]) +#define RSCAN0GAFLM15H (RSCAN0.GAFLM15.UINT16[R_IO_H]) +#define RSCAN0GAFLM15HL (RSCAN0.GAFLM15.UINT8[R_IO_HL]) +#define RSCAN0GAFLM15HH (RSCAN0.GAFLM15.UINT8[R_IO_HH]) +#define RSCAN0GAFLP015 (RSCAN0.GAFLP015.UINT32) +#define RSCAN0GAFLP015L (RSCAN0.GAFLP015.UINT16[R_IO_L]) +#define RSCAN0GAFLP015LL (RSCAN0.GAFLP015.UINT8[R_IO_LL]) +#define RSCAN0GAFLP015LH (RSCAN0.GAFLP015.UINT8[R_IO_LH]) +#define RSCAN0GAFLP015H (RSCAN0.GAFLP015.UINT16[R_IO_H]) +#define RSCAN0GAFLP015HL (RSCAN0.GAFLP015.UINT8[R_IO_HL]) +#define RSCAN0GAFLP015HH (RSCAN0.GAFLP015.UINT8[R_IO_HH]) +#define RSCAN0GAFLP115 (RSCAN0.GAFLP115.UINT32) +#define RSCAN0GAFLP115L (RSCAN0.GAFLP115.UINT16[R_IO_L]) +#define RSCAN0GAFLP115LL (RSCAN0.GAFLP115.UINT8[R_IO_LL]) +#define RSCAN0GAFLP115LH (RSCAN0.GAFLP115.UINT8[R_IO_LH]) +#define RSCAN0GAFLP115H (RSCAN0.GAFLP115.UINT16[R_IO_H]) +#define RSCAN0GAFLP115HL (RSCAN0.GAFLP115.UINT8[R_IO_HL]) +#define RSCAN0GAFLP115HH (RSCAN0.GAFLP115.UINT8[R_IO_HH]) +#define RSCAN0RMID0 (RSCAN0.RMID0.UINT32) +#define RSCAN0RMID0L (RSCAN0.RMID0.UINT16[R_IO_L]) +#define RSCAN0RMID0LL (RSCAN0.RMID0.UINT8[R_IO_LL]) +#define RSCAN0RMID0LH (RSCAN0.RMID0.UINT8[R_IO_LH]) +#define RSCAN0RMID0H (RSCAN0.RMID0.UINT16[R_IO_H]) +#define RSCAN0RMID0HL (RSCAN0.RMID0.UINT8[R_IO_HL]) +#define RSCAN0RMID0HH (RSCAN0.RMID0.UINT8[R_IO_HH]) +#define RSCAN0RMPTR0 (RSCAN0.RMPTR0.UINT32) +#define RSCAN0RMPTR0L (RSCAN0.RMPTR0.UINT16[R_IO_L]) +#define RSCAN0RMPTR0LL (RSCAN0.RMPTR0.UINT8[R_IO_LL]) +#define RSCAN0RMPTR0LH (RSCAN0.RMPTR0.UINT8[R_IO_LH]) +#define RSCAN0RMPTR0H (RSCAN0.RMPTR0.UINT16[R_IO_H]) +#define RSCAN0RMPTR0HL (RSCAN0.RMPTR0.UINT8[R_IO_HL]) +#define RSCAN0RMPTR0HH (RSCAN0.RMPTR0.UINT8[R_IO_HH]) +#define RSCAN0RMDF00 (RSCAN0.RMDF00.UINT32) +#define RSCAN0RMDF00L (RSCAN0.RMDF00.UINT16[R_IO_L]) +#define RSCAN0RMDF00LL (RSCAN0.RMDF00.UINT8[R_IO_LL]) +#define RSCAN0RMDF00LH (RSCAN0.RMDF00.UINT8[R_IO_LH]) +#define RSCAN0RMDF00H (RSCAN0.RMDF00.UINT16[R_IO_H]) +#define RSCAN0RMDF00HL (RSCAN0.RMDF00.UINT8[R_IO_HL]) +#define RSCAN0RMDF00HH (RSCAN0.RMDF00.UINT8[R_IO_HH]) +#define RSCAN0RMDF10 (RSCAN0.RMDF10.UINT32) +#define RSCAN0RMDF10L (RSCAN0.RMDF10.UINT16[R_IO_L]) +#define RSCAN0RMDF10LL (RSCAN0.RMDF10.UINT8[R_IO_LL]) +#define RSCAN0RMDF10LH (RSCAN0.RMDF10.UINT8[R_IO_LH]) +#define RSCAN0RMDF10H (RSCAN0.RMDF10.UINT16[R_IO_H]) +#define RSCAN0RMDF10HL (RSCAN0.RMDF10.UINT8[R_IO_HL]) +#define RSCAN0RMDF10HH (RSCAN0.RMDF10.UINT8[R_IO_HH]) +#define RSCAN0RMID1 (RSCAN0.RMID1.UINT32) +#define RSCAN0RMID1L (RSCAN0.RMID1.UINT16[R_IO_L]) +#define RSCAN0RMID1LL (RSCAN0.RMID1.UINT8[R_IO_LL]) +#define RSCAN0RMID1LH (RSCAN0.RMID1.UINT8[R_IO_LH]) +#define RSCAN0RMID1H (RSCAN0.RMID1.UINT16[R_IO_H]) +#define RSCAN0RMID1HL (RSCAN0.RMID1.UINT8[R_IO_HL]) +#define RSCAN0RMID1HH (RSCAN0.RMID1.UINT8[R_IO_HH]) +#define RSCAN0RMPTR1 (RSCAN0.RMPTR1.UINT32) +#define RSCAN0RMPTR1L (RSCAN0.RMPTR1.UINT16[R_IO_L]) +#define RSCAN0RMPTR1LL (RSCAN0.RMPTR1.UINT8[R_IO_LL]) +#define RSCAN0RMPTR1LH (RSCAN0.RMPTR1.UINT8[R_IO_LH]) +#define RSCAN0RMPTR1H (RSCAN0.RMPTR1.UINT16[R_IO_H]) +#define RSCAN0RMPTR1HL (RSCAN0.RMPTR1.UINT8[R_IO_HL]) +#define RSCAN0RMPTR1HH (RSCAN0.RMPTR1.UINT8[R_IO_HH]) +#define RSCAN0RMDF01 (RSCAN0.RMDF01.UINT32) +#define RSCAN0RMDF01L (RSCAN0.RMDF01.UINT16[R_IO_L]) +#define RSCAN0RMDF01LL (RSCAN0.RMDF01.UINT8[R_IO_LL]) +#define RSCAN0RMDF01LH (RSCAN0.RMDF01.UINT8[R_IO_LH]) +#define RSCAN0RMDF01H (RSCAN0.RMDF01.UINT16[R_IO_H]) +#define RSCAN0RMDF01HL (RSCAN0.RMDF01.UINT8[R_IO_HL]) +#define RSCAN0RMDF01HH (RSCAN0.RMDF01.UINT8[R_IO_HH]) +#define RSCAN0RMDF11 (RSCAN0.RMDF11.UINT32) +#define RSCAN0RMDF11L (RSCAN0.RMDF11.UINT16[R_IO_L]) +#define RSCAN0RMDF11LL (RSCAN0.RMDF11.UINT8[R_IO_LL]) +#define RSCAN0RMDF11LH (RSCAN0.RMDF11.UINT8[R_IO_LH]) +#define RSCAN0RMDF11H (RSCAN0.RMDF11.UINT16[R_IO_H]) +#define RSCAN0RMDF11HL (RSCAN0.RMDF11.UINT8[R_IO_HL]) +#define RSCAN0RMDF11HH (RSCAN0.RMDF11.UINT8[R_IO_HH]) +#define RSCAN0RMID2 (RSCAN0.RMID2.UINT32) +#define RSCAN0RMID2L (RSCAN0.RMID2.UINT16[R_IO_L]) +#define RSCAN0RMID2LL (RSCAN0.RMID2.UINT8[R_IO_LL]) +#define RSCAN0RMID2LH (RSCAN0.RMID2.UINT8[R_IO_LH]) +#define RSCAN0RMID2H (RSCAN0.RMID2.UINT16[R_IO_H]) +#define RSCAN0RMID2HL (RSCAN0.RMID2.UINT8[R_IO_HL]) +#define RSCAN0RMID2HH (RSCAN0.RMID2.UINT8[R_IO_HH]) +#define RSCAN0RMPTR2 (RSCAN0.RMPTR2.UINT32) +#define RSCAN0RMPTR2L (RSCAN0.RMPTR2.UINT16[R_IO_L]) +#define RSCAN0RMPTR2LL (RSCAN0.RMPTR2.UINT8[R_IO_LL]) +#define RSCAN0RMPTR2LH (RSCAN0.RMPTR2.UINT8[R_IO_LH]) +#define RSCAN0RMPTR2H (RSCAN0.RMPTR2.UINT16[R_IO_H]) +#define RSCAN0RMPTR2HL (RSCAN0.RMPTR2.UINT8[R_IO_HL]) +#define RSCAN0RMPTR2HH (RSCAN0.RMPTR2.UINT8[R_IO_HH]) +#define RSCAN0RMDF02 (RSCAN0.RMDF02.UINT32) +#define RSCAN0RMDF02L (RSCAN0.RMDF02.UINT16[R_IO_L]) +#define RSCAN0RMDF02LL (RSCAN0.RMDF02.UINT8[R_IO_LL]) +#define RSCAN0RMDF02LH (RSCAN0.RMDF02.UINT8[R_IO_LH]) +#define RSCAN0RMDF02H (RSCAN0.RMDF02.UINT16[R_IO_H]) +#define RSCAN0RMDF02HL (RSCAN0.RMDF02.UINT8[R_IO_HL]) +#define RSCAN0RMDF02HH (RSCAN0.RMDF02.UINT8[R_IO_HH]) +#define RSCAN0RMDF12 (RSCAN0.RMDF12.UINT32) +#define RSCAN0RMDF12L (RSCAN0.RMDF12.UINT16[R_IO_L]) +#define RSCAN0RMDF12LL (RSCAN0.RMDF12.UINT8[R_IO_LL]) +#define RSCAN0RMDF12LH (RSCAN0.RMDF12.UINT8[R_IO_LH]) +#define RSCAN0RMDF12H (RSCAN0.RMDF12.UINT16[R_IO_H]) +#define RSCAN0RMDF12HL (RSCAN0.RMDF12.UINT8[R_IO_HL]) +#define RSCAN0RMDF12HH (RSCAN0.RMDF12.UINT8[R_IO_HH]) +#define RSCAN0RMID3 (RSCAN0.RMID3.UINT32) +#define RSCAN0RMID3L (RSCAN0.RMID3.UINT16[R_IO_L]) +#define RSCAN0RMID3LL (RSCAN0.RMID3.UINT8[R_IO_LL]) +#define RSCAN0RMID3LH (RSCAN0.RMID3.UINT8[R_IO_LH]) +#define RSCAN0RMID3H (RSCAN0.RMID3.UINT16[R_IO_H]) +#define RSCAN0RMID3HL (RSCAN0.RMID3.UINT8[R_IO_HL]) +#define RSCAN0RMID3HH (RSCAN0.RMID3.UINT8[R_IO_HH]) +#define RSCAN0RMPTR3 (RSCAN0.RMPTR3.UINT32) +#define RSCAN0RMPTR3L (RSCAN0.RMPTR3.UINT16[R_IO_L]) +#define RSCAN0RMPTR3LL (RSCAN0.RMPTR3.UINT8[R_IO_LL]) +#define RSCAN0RMPTR3LH (RSCAN0.RMPTR3.UINT8[R_IO_LH]) +#define RSCAN0RMPTR3H (RSCAN0.RMPTR3.UINT16[R_IO_H]) +#define RSCAN0RMPTR3HL (RSCAN0.RMPTR3.UINT8[R_IO_HL]) +#define RSCAN0RMPTR3HH (RSCAN0.RMPTR3.UINT8[R_IO_HH]) +#define RSCAN0RMDF03 (RSCAN0.RMDF03.UINT32) +#define RSCAN0RMDF03L (RSCAN0.RMDF03.UINT16[R_IO_L]) +#define RSCAN0RMDF03LL (RSCAN0.RMDF03.UINT8[R_IO_LL]) +#define RSCAN0RMDF03LH (RSCAN0.RMDF03.UINT8[R_IO_LH]) +#define RSCAN0RMDF03H (RSCAN0.RMDF03.UINT16[R_IO_H]) +#define RSCAN0RMDF03HL (RSCAN0.RMDF03.UINT8[R_IO_HL]) +#define RSCAN0RMDF03HH (RSCAN0.RMDF03.UINT8[R_IO_HH]) +#define RSCAN0RMDF13 (RSCAN0.RMDF13.UINT32) +#define RSCAN0RMDF13L (RSCAN0.RMDF13.UINT16[R_IO_L]) +#define RSCAN0RMDF13LL (RSCAN0.RMDF13.UINT8[R_IO_LL]) +#define RSCAN0RMDF13LH (RSCAN0.RMDF13.UINT8[R_IO_LH]) +#define RSCAN0RMDF13H (RSCAN0.RMDF13.UINT16[R_IO_H]) +#define RSCAN0RMDF13HL (RSCAN0.RMDF13.UINT8[R_IO_HL]) +#define RSCAN0RMDF13HH (RSCAN0.RMDF13.UINT8[R_IO_HH]) +#define RSCAN0RMID4 (RSCAN0.RMID4.UINT32) +#define RSCAN0RMID4L (RSCAN0.RMID4.UINT16[R_IO_L]) +#define RSCAN0RMID4LL (RSCAN0.RMID4.UINT8[R_IO_LL]) +#define RSCAN0RMID4LH (RSCAN0.RMID4.UINT8[R_IO_LH]) +#define RSCAN0RMID4H (RSCAN0.RMID4.UINT16[R_IO_H]) +#define RSCAN0RMID4HL (RSCAN0.RMID4.UINT8[R_IO_HL]) +#define RSCAN0RMID4HH (RSCAN0.RMID4.UINT8[R_IO_HH]) +#define RSCAN0RMPTR4 (RSCAN0.RMPTR4.UINT32) +#define RSCAN0RMPTR4L (RSCAN0.RMPTR4.UINT16[R_IO_L]) +#define RSCAN0RMPTR4LL (RSCAN0.RMPTR4.UINT8[R_IO_LL]) +#define RSCAN0RMPTR4LH (RSCAN0.RMPTR4.UINT8[R_IO_LH]) +#define RSCAN0RMPTR4H (RSCAN0.RMPTR4.UINT16[R_IO_H]) +#define RSCAN0RMPTR4HL (RSCAN0.RMPTR4.UINT8[R_IO_HL]) +#define RSCAN0RMPTR4HH (RSCAN0.RMPTR4.UINT8[R_IO_HH]) +#define RSCAN0RMDF04 (RSCAN0.RMDF04.UINT32) +#define RSCAN0RMDF04L (RSCAN0.RMDF04.UINT16[R_IO_L]) +#define RSCAN0RMDF04LL (RSCAN0.RMDF04.UINT8[R_IO_LL]) +#define RSCAN0RMDF04LH (RSCAN0.RMDF04.UINT8[R_IO_LH]) +#define RSCAN0RMDF04H (RSCAN0.RMDF04.UINT16[R_IO_H]) +#define RSCAN0RMDF04HL (RSCAN0.RMDF04.UINT8[R_IO_HL]) +#define RSCAN0RMDF04HH (RSCAN0.RMDF04.UINT8[R_IO_HH]) +#define RSCAN0RMDF14 (RSCAN0.RMDF14.UINT32) +#define RSCAN0RMDF14L (RSCAN0.RMDF14.UINT16[R_IO_L]) +#define RSCAN0RMDF14LL (RSCAN0.RMDF14.UINT8[R_IO_LL]) +#define RSCAN0RMDF14LH (RSCAN0.RMDF14.UINT8[R_IO_LH]) +#define RSCAN0RMDF14H (RSCAN0.RMDF14.UINT16[R_IO_H]) +#define RSCAN0RMDF14HL (RSCAN0.RMDF14.UINT8[R_IO_HL]) +#define RSCAN0RMDF14HH (RSCAN0.RMDF14.UINT8[R_IO_HH]) +#define RSCAN0RMID5 (RSCAN0.RMID5.UINT32) +#define RSCAN0RMID5L (RSCAN0.RMID5.UINT16[R_IO_L]) +#define RSCAN0RMID5LL (RSCAN0.RMID5.UINT8[R_IO_LL]) +#define RSCAN0RMID5LH (RSCAN0.RMID5.UINT8[R_IO_LH]) +#define RSCAN0RMID5H (RSCAN0.RMID5.UINT16[R_IO_H]) +#define RSCAN0RMID5HL (RSCAN0.RMID5.UINT8[R_IO_HL]) +#define RSCAN0RMID5HH (RSCAN0.RMID5.UINT8[R_IO_HH]) +#define RSCAN0RMPTR5 (RSCAN0.RMPTR5.UINT32) +#define RSCAN0RMPTR5L (RSCAN0.RMPTR5.UINT16[R_IO_L]) +#define RSCAN0RMPTR5LL (RSCAN0.RMPTR5.UINT8[R_IO_LL]) +#define RSCAN0RMPTR5LH (RSCAN0.RMPTR5.UINT8[R_IO_LH]) +#define RSCAN0RMPTR5H (RSCAN0.RMPTR5.UINT16[R_IO_H]) +#define RSCAN0RMPTR5HL (RSCAN0.RMPTR5.UINT8[R_IO_HL]) +#define RSCAN0RMPTR5HH (RSCAN0.RMPTR5.UINT8[R_IO_HH]) +#define RSCAN0RMDF05 (RSCAN0.RMDF05.UINT32) +#define RSCAN0RMDF05L (RSCAN0.RMDF05.UINT16[R_IO_L]) +#define RSCAN0RMDF05LL (RSCAN0.RMDF05.UINT8[R_IO_LL]) +#define RSCAN0RMDF05LH (RSCAN0.RMDF05.UINT8[R_IO_LH]) +#define RSCAN0RMDF05H (RSCAN0.RMDF05.UINT16[R_IO_H]) +#define RSCAN0RMDF05HL (RSCAN0.RMDF05.UINT8[R_IO_HL]) +#define RSCAN0RMDF05HH (RSCAN0.RMDF05.UINT8[R_IO_HH]) +#define RSCAN0RMDF15 (RSCAN0.RMDF15.UINT32) +#define RSCAN0RMDF15L (RSCAN0.RMDF15.UINT16[R_IO_L]) +#define RSCAN0RMDF15LL (RSCAN0.RMDF15.UINT8[R_IO_LL]) +#define RSCAN0RMDF15LH (RSCAN0.RMDF15.UINT8[R_IO_LH]) +#define RSCAN0RMDF15H (RSCAN0.RMDF15.UINT16[R_IO_H]) +#define RSCAN0RMDF15HL (RSCAN0.RMDF15.UINT8[R_IO_HL]) +#define RSCAN0RMDF15HH (RSCAN0.RMDF15.UINT8[R_IO_HH]) +#define RSCAN0RMID6 (RSCAN0.RMID6.UINT32) +#define RSCAN0RMID6L (RSCAN0.RMID6.UINT16[R_IO_L]) +#define RSCAN0RMID6LL (RSCAN0.RMID6.UINT8[R_IO_LL]) +#define RSCAN0RMID6LH (RSCAN0.RMID6.UINT8[R_IO_LH]) +#define RSCAN0RMID6H (RSCAN0.RMID6.UINT16[R_IO_H]) +#define RSCAN0RMID6HL (RSCAN0.RMID6.UINT8[R_IO_HL]) +#define RSCAN0RMID6HH (RSCAN0.RMID6.UINT8[R_IO_HH]) +#define RSCAN0RMPTR6 (RSCAN0.RMPTR6.UINT32) +#define RSCAN0RMPTR6L (RSCAN0.RMPTR6.UINT16[R_IO_L]) +#define RSCAN0RMPTR6LL (RSCAN0.RMPTR6.UINT8[R_IO_LL]) +#define RSCAN0RMPTR6LH (RSCAN0.RMPTR6.UINT8[R_IO_LH]) +#define RSCAN0RMPTR6H (RSCAN0.RMPTR6.UINT16[R_IO_H]) +#define RSCAN0RMPTR6HL (RSCAN0.RMPTR6.UINT8[R_IO_HL]) +#define RSCAN0RMPTR6HH (RSCAN0.RMPTR6.UINT8[R_IO_HH]) +#define RSCAN0RMDF06 (RSCAN0.RMDF06.UINT32) +#define RSCAN0RMDF06L (RSCAN0.RMDF06.UINT16[R_IO_L]) +#define RSCAN0RMDF06LL (RSCAN0.RMDF06.UINT8[R_IO_LL]) +#define RSCAN0RMDF06LH (RSCAN0.RMDF06.UINT8[R_IO_LH]) +#define RSCAN0RMDF06H (RSCAN0.RMDF06.UINT16[R_IO_H]) +#define RSCAN0RMDF06HL (RSCAN0.RMDF06.UINT8[R_IO_HL]) +#define RSCAN0RMDF06HH (RSCAN0.RMDF06.UINT8[R_IO_HH]) +#define RSCAN0RMDF16 (RSCAN0.RMDF16.UINT32) +#define RSCAN0RMDF16L (RSCAN0.RMDF16.UINT16[R_IO_L]) +#define RSCAN0RMDF16LL (RSCAN0.RMDF16.UINT8[R_IO_LL]) +#define RSCAN0RMDF16LH (RSCAN0.RMDF16.UINT8[R_IO_LH]) +#define RSCAN0RMDF16H (RSCAN0.RMDF16.UINT16[R_IO_H]) +#define RSCAN0RMDF16HL (RSCAN0.RMDF16.UINT8[R_IO_HL]) +#define RSCAN0RMDF16HH (RSCAN0.RMDF16.UINT8[R_IO_HH]) +#define RSCAN0RMID7 (RSCAN0.RMID7.UINT32) +#define RSCAN0RMID7L (RSCAN0.RMID7.UINT16[R_IO_L]) +#define RSCAN0RMID7LL (RSCAN0.RMID7.UINT8[R_IO_LL]) +#define RSCAN0RMID7LH (RSCAN0.RMID7.UINT8[R_IO_LH]) +#define RSCAN0RMID7H (RSCAN0.RMID7.UINT16[R_IO_H]) +#define RSCAN0RMID7HL (RSCAN0.RMID7.UINT8[R_IO_HL]) +#define RSCAN0RMID7HH (RSCAN0.RMID7.UINT8[R_IO_HH]) +#define RSCAN0RMPTR7 (RSCAN0.RMPTR7.UINT32) +#define RSCAN0RMPTR7L (RSCAN0.RMPTR7.UINT16[R_IO_L]) +#define RSCAN0RMPTR7LL (RSCAN0.RMPTR7.UINT8[R_IO_LL]) +#define RSCAN0RMPTR7LH (RSCAN0.RMPTR7.UINT8[R_IO_LH]) +#define RSCAN0RMPTR7H (RSCAN0.RMPTR7.UINT16[R_IO_H]) +#define RSCAN0RMPTR7HL (RSCAN0.RMPTR7.UINT8[R_IO_HL]) +#define RSCAN0RMPTR7HH (RSCAN0.RMPTR7.UINT8[R_IO_HH]) +#define RSCAN0RMDF07 (RSCAN0.RMDF07.UINT32) +#define RSCAN0RMDF07L (RSCAN0.RMDF07.UINT16[R_IO_L]) +#define RSCAN0RMDF07LL (RSCAN0.RMDF07.UINT8[R_IO_LL]) +#define RSCAN0RMDF07LH (RSCAN0.RMDF07.UINT8[R_IO_LH]) +#define RSCAN0RMDF07H (RSCAN0.RMDF07.UINT16[R_IO_H]) +#define RSCAN0RMDF07HL (RSCAN0.RMDF07.UINT8[R_IO_HL]) +#define RSCAN0RMDF07HH (RSCAN0.RMDF07.UINT8[R_IO_HH]) +#define RSCAN0RMDF17 (RSCAN0.RMDF17.UINT32) +#define RSCAN0RMDF17L (RSCAN0.RMDF17.UINT16[R_IO_L]) +#define RSCAN0RMDF17LL (RSCAN0.RMDF17.UINT8[R_IO_LL]) +#define RSCAN0RMDF17LH (RSCAN0.RMDF17.UINT8[R_IO_LH]) +#define RSCAN0RMDF17H (RSCAN0.RMDF17.UINT16[R_IO_H]) +#define RSCAN0RMDF17HL (RSCAN0.RMDF17.UINT8[R_IO_HL]) +#define RSCAN0RMDF17HH (RSCAN0.RMDF17.UINT8[R_IO_HH]) +#define RSCAN0RMID8 (RSCAN0.RMID8.UINT32) +#define RSCAN0RMID8L (RSCAN0.RMID8.UINT16[R_IO_L]) +#define RSCAN0RMID8LL (RSCAN0.RMID8.UINT8[R_IO_LL]) +#define RSCAN0RMID8LH (RSCAN0.RMID8.UINT8[R_IO_LH]) +#define RSCAN0RMID8H (RSCAN0.RMID8.UINT16[R_IO_H]) +#define RSCAN0RMID8HL (RSCAN0.RMID8.UINT8[R_IO_HL]) +#define RSCAN0RMID8HH (RSCAN0.RMID8.UINT8[R_IO_HH]) +#define RSCAN0RMPTR8 (RSCAN0.RMPTR8.UINT32) +#define RSCAN0RMPTR8L (RSCAN0.RMPTR8.UINT16[R_IO_L]) +#define RSCAN0RMPTR8LL (RSCAN0.RMPTR8.UINT8[R_IO_LL]) +#define RSCAN0RMPTR8LH (RSCAN0.RMPTR8.UINT8[R_IO_LH]) +#define RSCAN0RMPTR8H (RSCAN0.RMPTR8.UINT16[R_IO_H]) +#define RSCAN0RMPTR8HL (RSCAN0.RMPTR8.UINT8[R_IO_HL]) +#define RSCAN0RMPTR8HH (RSCAN0.RMPTR8.UINT8[R_IO_HH]) +#define RSCAN0RMDF08 (RSCAN0.RMDF08.UINT32) +#define RSCAN0RMDF08L (RSCAN0.RMDF08.UINT16[R_IO_L]) +#define RSCAN0RMDF08LL (RSCAN0.RMDF08.UINT8[R_IO_LL]) +#define RSCAN0RMDF08LH (RSCAN0.RMDF08.UINT8[R_IO_LH]) +#define RSCAN0RMDF08H (RSCAN0.RMDF08.UINT16[R_IO_H]) +#define RSCAN0RMDF08HL (RSCAN0.RMDF08.UINT8[R_IO_HL]) +#define RSCAN0RMDF08HH (RSCAN0.RMDF08.UINT8[R_IO_HH]) +#define RSCAN0RMDF18 (RSCAN0.RMDF18.UINT32) +#define RSCAN0RMDF18L (RSCAN0.RMDF18.UINT16[R_IO_L]) +#define RSCAN0RMDF18LL (RSCAN0.RMDF18.UINT8[R_IO_LL]) +#define RSCAN0RMDF18LH (RSCAN0.RMDF18.UINT8[R_IO_LH]) +#define RSCAN0RMDF18H (RSCAN0.RMDF18.UINT16[R_IO_H]) +#define RSCAN0RMDF18HL (RSCAN0.RMDF18.UINT8[R_IO_HL]) +#define RSCAN0RMDF18HH (RSCAN0.RMDF18.UINT8[R_IO_HH]) +#define RSCAN0RMID9 (RSCAN0.RMID9.UINT32) +#define RSCAN0RMID9L (RSCAN0.RMID9.UINT16[R_IO_L]) +#define RSCAN0RMID9LL (RSCAN0.RMID9.UINT8[R_IO_LL]) +#define RSCAN0RMID9LH (RSCAN0.RMID9.UINT8[R_IO_LH]) +#define RSCAN0RMID9H (RSCAN0.RMID9.UINT16[R_IO_H]) +#define RSCAN0RMID9HL (RSCAN0.RMID9.UINT8[R_IO_HL]) +#define RSCAN0RMID9HH (RSCAN0.RMID9.UINT8[R_IO_HH]) +#define RSCAN0RMPTR9 (RSCAN0.RMPTR9.UINT32) +#define RSCAN0RMPTR9L (RSCAN0.RMPTR9.UINT16[R_IO_L]) +#define RSCAN0RMPTR9LL (RSCAN0.RMPTR9.UINT8[R_IO_LL]) +#define RSCAN0RMPTR9LH (RSCAN0.RMPTR9.UINT8[R_IO_LH]) +#define RSCAN0RMPTR9H (RSCAN0.RMPTR9.UINT16[R_IO_H]) +#define RSCAN0RMPTR9HL (RSCAN0.RMPTR9.UINT8[R_IO_HL]) +#define RSCAN0RMPTR9HH (RSCAN0.RMPTR9.UINT8[R_IO_HH]) +#define RSCAN0RMDF09 (RSCAN0.RMDF09.UINT32) +#define RSCAN0RMDF09L (RSCAN0.RMDF09.UINT16[R_IO_L]) +#define RSCAN0RMDF09LL (RSCAN0.RMDF09.UINT8[R_IO_LL]) +#define RSCAN0RMDF09LH (RSCAN0.RMDF09.UINT8[R_IO_LH]) +#define RSCAN0RMDF09H (RSCAN0.RMDF09.UINT16[R_IO_H]) +#define RSCAN0RMDF09HL (RSCAN0.RMDF09.UINT8[R_IO_HL]) +#define RSCAN0RMDF09HH (RSCAN0.RMDF09.UINT8[R_IO_HH]) +#define RSCAN0RMDF19 (RSCAN0.RMDF19.UINT32) +#define RSCAN0RMDF19L (RSCAN0.RMDF19.UINT16[R_IO_L]) +#define RSCAN0RMDF19LL (RSCAN0.RMDF19.UINT8[R_IO_LL]) +#define RSCAN0RMDF19LH (RSCAN0.RMDF19.UINT8[R_IO_LH]) +#define RSCAN0RMDF19H (RSCAN0.RMDF19.UINT16[R_IO_H]) +#define RSCAN0RMDF19HL (RSCAN0.RMDF19.UINT8[R_IO_HL]) +#define RSCAN0RMDF19HH (RSCAN0.RMDF19.UINT8[R_IO_HH]) +#define RSCAN0RMID10 (RSCAN0.RMID10.UINT32) +#define RSCAN0RMID10L (RSCAN0.RMID10.UINT16[R_IO_L]) +#define RSCAN0RMID10LL (RSCAN0.RMID10.UINT8[R_IO_LL]) +#define RSCAN0RMID10LH (RSCAN0.RMID10.UINT8[R_IO_LH]) +#define RSCAN0RMID10H (RSCAN0.RMID10.UINT16[R_IO_H]) +#define RSCAN0RMID10HL (RSCAN0.RMID10.UINT8[R_IO_HL]) +#define RSCAN0RMID10HH (RSCAN0.RMID10.UINT8[R_IO_HH]) +#define RSCAN0RMPTR10 (RSCAN0.RMPTR10.UINT32) +#define RSCAN0RMPTR10L (RSCAN0.RMPTR10.UINT16[R_IO_L]) +#define RSCAN0RMPTR10LL (RSCAN0.RMPTR10.UINT8[R_IO_LL]) +#define RSCAN0RMPTR10LH (RSCAN0.RMPTR10.UINT8[R_IO_LH]) +#define RSCAN0RMPTR10H (RSCAN0.RMPTR10.UINT16[R_IO_H]) +#define RSCAN0RMPTR10HL (RSCAN0.RMPTR10.UINT8[R_IO_HL]) +#define RSCAN0RMPTR10HH (RSCAN0.RMPTR10.UINT8[R_IO_HH]) +#define RSCAN0RMDF010 (RSCAN0.RMDF010.UINT32) +#define RSCAN0RMDF010L (RSCAN0.RMDF010.UINT16[R_IO_L]) +#define RSCAN0RMDF010LL (RSCAN0.RMDF010.UINT8[R_IO_LL]) +#define RSCAN0RMDF010LH (RSCAN0.RMDF010.UINT8[R_IO_LH]) +#define RSCAN0RMDF010H (RSCAN0.RMDF010.UINT16[R_IO_H]) +#define RSCAN0RMDF010HL (RSCAN0.RMDF010.UINT8[R_IO_HL]) +#define RSCAN0RMDF010HH (RSCAN0.RMDF010.UINT8[R_IO_HH]) +#define RSCAN0RMDF110 (RSCAN0.RMDF110.UINT32) +#define RSCAN0RMDF110L (RSCAN0.RMDF110.UINT16[R_IO_L]) +#define RSCAN0RMDF110LL (RSCAN0.RMDF110.UINT8[R_IO_LL]) +#define RSCAN0RMDF110LH (RSCAN0.RMDF110.UINT8[R_IO_LH]) +#define RSCAN0RMDF110H (RSCAN0.RMDF110.UINT16[R_IO_H]) +#define RSCAN0RMDF110HL (RSCAN0.RMDF110.UINT8[R_IO_HL]) +#define RSCAN0RMDF110HH (RSCAN0.RMDF110.UINT8[R_IO_HH]) +#define RSCAN0RMID11 (RSCAN0.RMID11.UINT32) +#define RSCAN0RMID11L (RSCAN0.RMID11.UINT16[R_IO_L]) +#define RSCAN0RMID11LL (RSCAN0.RMID11.UINT8[R_IO_LL]) +#define RSCAN0RMID11LH (RSCAN0.RMID11.UINT8[R_IO_LH]) +#define RSCAN0RMID11H (RSCAN0.RMID11.UINT16[R_IO_H]) +#define RSCAN0RMID11HL (RSCAN0.RMID11.UINT8[R_IO_HL]) +#define RSCAN0RMID11HH (RSCAN0.RMID11.UINT8[R_IO_HH]) +#define RSCAN0RMPTR11 (RSCAN0.RMPTR11.UINT32) +#define RSCAN0RMPTR11L (RSCAN0.RMPTR11.UINT16[R_IO_L]) +#define RSCAN0RMPTR11LL (RSCAN0.RMPTR11.UINT8[R_IO_LL]) +#define RSCAN0RMPTR11LH (RSCAN0.RMPTR11.UINT8[R_IO_LH]) +#define RSCAN0RMPTR11H (RSCAN0.RMPTR11.UINT16[R_IO_H]) +#define RSCAN0RMPTR11HL (RSCAN0.RMPTR11.UINT8[R_IO_HL]) +#define RSCAN0RMPTR11HH (RSCAN0.RMPTR11.UINT8[R_IO_HH]) +#define RSCAN0RMDF011 (RSCAN0.RMDF011.UINT32) +#define RSCAN0RMDF011L (RSCAN0.RMDF011.UINT16[R_IO_L]) +#define RSCAN0RMDF011LL (RSCAN0.RMDF011.UINT8[R_IO_LL]) +#define RSCAN0RMDF011LH (RSCAN0.RMDF011.UINT8[R_IO_LH]) +#define RSCAN0RMDF011H (RSCAN0.RMDF011.UINT16[R_IO_H]) +#define RSCAN0RMDF011HL (RSCAN0.RMDF011.UINT8[R_IO_HL]) +#define RSCAN0RMDF011HH (RSCAN0.RMDF011.UINT8[R_IO_HH]) +#define RSCAN0RMDF111 (RSCAN0.RMDF111.UINT32) +#define RSCAN0RMDF111L (RSCAN0.RMDF111.UINT16[R_IO_L]) +#define RSCAN0RMDF111LL (RSCAN0.RMDF111.UINT8[R_IO_LL]) +#define RSCAN0RMDF111LH (RSCAN0.RMDF111.UINT8[R_IO_LH]) +#define RSCAN0RMDF111H (RSCAN0.RMDF111.UINT16[R_IO_H]) +#define RSCAN0RMDF111HL (RSCAN0.RMDF111.UINT8[R_IO_HL]) +#define RSCAN0RMDF111HH (RSCAN0.RMDF111.UINT8[R_IO_HH]) +#define RSCAN0RMID12 (RSCAN0.RMID12.UINT32) +#define RSCAN0RMID12L (RSCAN0.RMID12.UINT16[R_IO_L]) +#define RSCAN0RMID12LL (RSCAN0.RMID12.UINT8[R_IO_LL]) +#define RSCAN0RMID12LH (RSCAN0.RMID12.UINT8[R_IO_LH]) +#define RSCAN0RMID12H (RSCAN0.RMID12.UINT16[R_IO_H]) +#define RSCAN0RMID12HL (RSCAN0.RMID12.UINT8[R_IO_HL]) +#define RSCAN0RMID12HH (RSCAN0.RMID12.UINT8[R_IO_HH]) +#define RSCAN0RMPTR12 (RSCAN0.RMPTR12.UINT32) +#define RSCAN0RMPTR12L (RSCAN0.RMPTR12.UINT16[R_IO_L]) +#define RSCAN0RMPTR12LL (RSCAN0.RMPTR12.UINT8[R_IO_LL]) +#define RSCAN0RMPTR12LH (RSCAN0.RMPTR12.UINT8[R_IO_LH]) +#define RSCAN0RMPTR12H (RSCAN0.RMPTR12.UINT16[R_IO_H]) +#define RSCAN0RMPTR12HL (RSCAN0.RMPTR12.UINT8[R_IO_HL]) +#define RSCAN0RMPTR12HH (RSCAN0.RMPTR12.UINT8[R_IO_HH]) +#define RSCAN0RMDF012 (RSCAN0.RMDF012.UINT32) +#define RSCAN0RMDF012L (RSCAN0.RMDF012.UINT16[R_IO_L]) +#define RSCAN0RMDF012LL (RSCAN0.RMDF012.UINT8[R_IO_LL]) +#define RSCAN0RMDF012LH (RSCAN0.RMDF012.UINT8[R_IO_LH]) +#define RSCAN0RMDF012H (RSCAN0.RMDF012.UINT16[R_IO_H]) +#define RSCAN0RMDF012HL (RSCAN0.RMDF012.UINT8[R_IO_HL]) +#define RSCAN0RMDF012HH (RSCAN0.RMDF012.UINT8[R_IO_HH]) +#define RSCAN0RMDF112 (RSCAN0.RMDF112.UINT32) +#define RSCAN0RMDF112L (RSCAN0.RMDF112.UINT16[R_IO_L]) +#define RSCAN0RMDF112LL (RSCAN0.RMDF112.UINT8[R_IO_LL]) +#define RSCAN0RMDF112LH (RSCAN0.RMDF112.UINT8[R_IO_LH]) +#define RSCAN0RMDF112H (RSCAN0.RMDF112.UINT16[R_IO_H]) +#define RSCAN0RMDF112HL (RSCAN0.RMDF112.UINT8[R_IO_HL]) +#define RSCAN0RMDF112HH (RSCAN0.RMDF112.UINT8[R_IO_HH]) +#define RSCAN0RMID13 (RSCAN0.RMID13.UINT32) +#define RSCAN0RMID13L (RSCAN0.RMID13.UINT16[R_IO_L]) +#define RSCAN0RMID13LL (RSCAN0.RMID13.UINT8[R_IO_LL]) +#define RSCAN0RMID13LH (RSCAN0.RMID13.UINT8[R_IO_LH]) +#define RSCAN0RMID13H (RSCAN0.RMID13.UINT16[R_IO_H]) +#define RSCAN0RMID13HL (RSCAN0.RMID13.UINT8[R_IO_HL]) +#define RSCAN0RMID13HH (RSCAN0.RMID13.UINT8[R_IO_HH]) +#define RSCAN0RMPTR13 (RSCAN0.RMPTR13.UINT32) +#define RSCAN0RMPTR13L (RSCAN0.RMPTR13.UINT16[R_IO_L]) +#define RSCAN0RMPTR13LL (RSCAN0.RMPTR13.UINT8[R_IO_LL]) +#define RSCAN0RMPTR13LH (RSCAN0.RMPTR13.UINT8[R_IO_LH]) +#define RSCAN0RMPTR13H (RSCAN0.RMPTR13.UINT16[R_IO_H]) +#define RSCAN0RMPTR13HL (RSCAN0.RMPTR13.UINT8[R_IO_HL]) +#define RSCAN0RMPTR13HH (RSCAN0.RMPTR13.UINT8[R_IO_HH]) +#define RSCAN0RMDF013 (RSCAN0.RMDF013.UINT32) +#define RSCAN0RMDF013L (RSCAN0.RMDF013.UINT16[R_IO_L]) +#define RSCAN0RMDF013LL (RSCAN0.RMDF013.UINT8[R_IO_LL]) +#define RSCAN0RMDF013LH (RSCAN0.RMDF013.UINT8[R_IO_LH]) +#define RSCAN0RMDF013H (RSCAN0.RMDF013.UINT16[R_IO_H]) +#define RSCAN0RMDF013HL (RSCAN0.RMDF013.UINT8[R_IO_HL]) +#define RSCAN0RMDF013HH (RSCAN0.RMDF013.UINT8[R_IO_HH]) +#define RSCAN0RMDF113 (RSCAN0.RMDF113.UINT32) +#define RSCAN0RMDF113L (RSCAN0.RMDF113.UINT16[R_IO_L]) +#define RSCAN0RMDF113LL (RSCAN0.RMDF113.UINT8[R_IO_LL]) +#define RSCAN0RMDF113LH (RSCAN0.RMDF113.UINT8[R_IO_LH]) +#define RSCAN0RMDF113H (RSCAN0.RMDF113.UINT16[R_IO_H]) +#define RSCAN0RMDF113HL (RSCAN0.RMDF113.UINT8[R_IO_HL]) +#define RSCAN0RMDF113HH (RSCAN0.RMDF113.UINT8[R_IO_HH]) +#define RSCAN0RMID14 (RSCAN0.RMID14.UINT32) +#define RSCAN0RMID14L (RSCAN0.RMID14.UINT16[R_IO_L]) +#define RSCAN0RMID14LL (RSCAN0.RMID14.UINT8[R_IO_LL]) +#define RSCAN0RMID14LH (RSCAN0.RMID14.UINT8[R_IO_LH]) +#define RSCAN0RMID14H (RSCAN0.RMID14.UINT16[R_IO_H]) +#define RSCAN0RMID14HL (RSCAN0.RMID14.UINT8[R_IO_HL]) +#define RSCAN0RMID14HH (RSCAN0.RMID14.UINT8[R_IO_HH]) +#define RSCAN0RMPTR14 (RSCAN0.RMPTR14.UINT32) +#define RSCAN0RMPTR14L (RSCAN0.RMPTR14.UINT16[R_IO_L]) +#define RSCAN0RMPTR14LL (RSCAN0.RMPTR14.UINT8[R_IO_LL]) +#define RSCAN0RMPTR14LH (RSCAN0.RMPTR14.UINT8[R_IO_LH]) +#define RSCAN0RMPTR14H (RSCAN0.RMPTR14.UINT16[R_IO_H]) +#define RSCAN0RMPTR14HL (RSCAN0.RMPTR14.UINT8[R_IO_HL]) +#define RSCAN0RMPTR14HH (RSCAN0.RMPTR14.UINT8[R_IO_HH]) +#define RSCAN0RMDF014 (RSCAN0.RMDF014.UINT32) +#define RSCAN0RMDF014L (RSCAN0.RMDF014.UINT16[R_IO_L]) +#define RSCAN0RMDF014LL (RSCAN0.RMDF014.UINT8[R_IO_LL]) +#define RSCAN0RMDF014LH (RSCAN0.RMDF014.UINT8[R_IO_LH]) +#define RSCAN0RMDF014H (RSCAN0.RMDF014.UINT16[R_IO_H]) +#define RSCAN0RMDF014HL (RSCAN0.RMDF014.UINT8[R_IO_HL]) +#define RSCAN0RMDF014HH (RSCAN0.RMDF014.UINT8[R_IO_HH]) +#define RSCAN0RMDF114 (RSCAN0.RMDF114.UINT32) +#define RSCAN0RMDF114L (RSCAN0.RMDF114.UINT16[R_IO_L]) +#define RSCAN0RMDF114LL (RSCAN0.RMDF114.UINT8[R_IO_LL]) +#define RSCAN0RMDF114LH (RSCAN0.RMDF114.UINT8[R_IO_LH]) +#define RSCAN0RMDF114H (RSCAN0.RMDF114.UINT16[R_IO_H]) +#define RSCAN0RMDF114HL (RSCAN0.RMDF114.UINT8[R_IO_HL]) +#define RSCAN0RMDF114HH (RSCAN0.RMDF114.UINT8[R_IO_HH]) +#define RSCAN0RMID15 (RSCAN0.RMID15.UINT32) +#define RSCAN0RMID15L (RSCAN0.RMID15.UINT16[R_IO_L]) +#define RSCAN0RMID15LL (RSCAN0.RMID15.UINT8[R_IO_LL]) +#define RSCAN0RMID15LH (RSCAN0.RMID15.UINT8[R_IO_LH]) +#define RSCAN0RMID15H (RSCAN0.RMID15.UINT16[R_IO_H]) +#define RSCAN0RMID15HL (RSCAN0.RMID15.UINT8[R_IO_HL]) +#define RSCAN0RMID15HH (RSCAN0.RMID15.UINT8[R_IO_HH]) +#define RSCAN0RMPTR15 (RSCAN0.RMPTR15.UINT32) +#define RSCAN0RMPTR15L (RSCAN0.RMPTR15.UINT16[R_IO_L]) +#define RSCAN0RMPTR15LL (RSCAN0.RMPTR15.UINT8[R_IO_LL]) +#define RSCAN0RMPTR15LH (RSCAN0.RMPTR15.UINT8[R_IO_LH]) +#define RSCAN0RMPTR15H (RSCAN0.RMPTR15.UINT16[R_IO_H]) +#define RSCAN0RMPTR15HL (RSCAN0.RMPTR15.UINT8[R_IO_HL]) +#define RSCAN0RMPTR15HH (RSCAN0.RMPTR15.UINT8[R_IO_HH]) +#define RSCAN0RMDF015 (RSCAN0.RMDF015.UINT32) +#define RSCAN0RMDF015L (RSCAN0.RMDF015.UINT16[R_IO_L]) +#define RSCAN0RMDF015LL (RSCAN0.RMDF015.UINT8[R_IO_LL]) +#define RSCAN0RMDF015LH (RSCAN0.RMDF015.UINT8[R_IO_LH]) +#define RSCAN0RMDF015H (RSCAN0.RMDF015.UINT16[R_IO_H]) +#define RSCAN0RMDF015HL (RSCAN0.RMDF015.UINT8[R_IO_HL]) +#define RSCAN0RMDF015HH (RSCAN0.RMDF015.UINT8[R_IO_HH]) +#define RSCAN0RMDF115 (RSCAN0.RMDF115.UINT32) +#define RSCAN0RMDF115L (RSCAN0.RMDF115.UINT16[R_IO_L]) +#define RSCAN0RMDF115LL (RSCAN0.RMDF115.UINT8[R_IO_LL]) +#define RSCAN0RMDF115LH (RSCAN0.RMDF115.UINT8[R_IO_LH]) +#define RSCAN0RMDF115H (RSCAN0.RMDF115.UINT16[R_IO_H]) +#define RSCAN0RMDF115HL (RSCAN0.RMDF115.UINT8[R_IO_HL]) +#define RSCAN0RMDF115HH (RSCAN0.RMDF115.UINT8[R_IO_HH]) +#define RSCAN0RMID16 (RSCAN0.RMID16.UINT32) +#define RSCAN0RMID16L (RSCAN0.RMID16.UINT16[R_IO_L]) +#define RSCAN0RMID16LL (RSCAN0.RMID16.UINT8[R_IO_LL]) +#define RSCAN0RMID16LH (RSCAN0.RMID16.UINT8[R_IO_LH]) +#define RSCAN0RMID16H (RSCAN0.RMID16.UINT16[R_IO_H]) +#define RSCAN0RMID16HL (RSCAN0.RMID16.UINT8[R_IO_HL]) +#define RSCAN0RMID16HH (RSCAN0.RMID16.UINT8[R_IO_HH]) +#define RSCAN0RMPTR16 (RSCAN0.RMPTR16.UINT32) +#define RSCAN0RMPTR16L (RSCAN0.RMPTR16.UINT16[R_IO_L]) +#define RSCAN0RMPTR16LL (RSCAN0.RMPTR16.UINT8[R_IO_LL]) +#define RSCAN0RMPTR16LH (RSCAN0.RMPTR16.UINT8[R_IO_LH]) +#define RSCAN0RMPTR16H (RSCAN0.RMPTR16.UINT16[R_IO_H]) +#define RSCAN0RMPTR16HL (RSCAN0.RMPTR16.UINT8[R_IO_HL]) +#define RSCAN0RMPTR16HH (RSCAN0.RMPTR16.UINT8[R_IO_HH]) +#define RSCAN0RMDF016 (RSCAN0.RMDF016.UINT32) +#define RSCAN0RMDF016L (RSCAN0.RMDF016.UINT16[R_IO_L]) +#define RSCAN0RMDF016LL (RSCAN0.RMDF016.UINT8[R_IO_LL]) +#define RSCAN0RMDF016LH (RSCAN0.RMDF016.UINT8[R_IO_LH]) +#define RSCAN0RMDF016H (RSCAN0.RMDF016.UINT16[R_IO_H]) +#define RSCAN0RMDF016HL (RSCAN0.RMDF016.UINT8[R_IO_HL]) +#define RSCAN0RMDF016HH (RSCAN0.RMDF016.UINT8[R_IO_HH]) +#define RSCAN0RMDF116 (RSCAN0.RMDF116.UINT32) +#define RSCAN0RMDF116L (RSCAN0.RMDF116.UINT16[R_IO_L]) +#define RSCAN0RMDF116LL (RSCAN0.RMDF116.UINT8[R_IO_LL]) +#define RSCAN0RMDF116LH (RSCAN0.RMDF116.UINT8[R_IO_LH]) +#define RSCAN0RMDF116H (RSCAN0.RMDF116.UINT16[R_IO_H]) +#define RSCAN0RMDF116HL (RSCAN0.RMDF116.UINT8[R_IO_HL]) +#define RSCAN0RMDF116HH (RSCAN0.RMDF116.UINT8[R_IO_HH]) +#define RSCAN0RMID17 (RSCAN0.RMID17.UINT32) +#define RSCAN0RMID17L (RSCAN0.RMID17.UINT16[R_IO_L]) +#define RSCAN0RMID17LL (RSCAN0.RMID17.UINT8[R_IO_LL]) +#define RSCAN0RMID17LH (RSCAN0.RMID17.UINT8[R_IO_LH]) +#define RSCAN0RMID17H (RSCAN0.RMID17.UINT16[R_IO_H]) +#define RSCAN0RMID17HL (RSCAN0.RMID17.UINT8[R_IO_HL]) +#define RSCAN0RMID17HH (RSCAN0.RMID17.UINT8[R_IO_HH]) +#define RSCAN0RMPTR17 (RSCAN0.RMPTR17.UINT32) +#define RSCAN0RMPTR17L (RSCAN0.RMPTR17.UINT16[R_IO_L]) +#define RSCAN0RMPTR17LL (RSCAN0.RMPTR17.UINT8[R_IO_LL]) +#define RSCAN0RMPTR17LH (RSCAN0.RMPTR17.UINT8[R_IO_LH]) +#define RSCAN0RMPTR17H (RSCAN0.RMPTR17.UINT16[R_IO_H]) +#define RSCAN0RMPTR17HL (RSCAN0.RMPTR17.UINT8[R_IO_HL]) +#define RSCAN0RMPTR17HH (RSCAN0.RMPTR17.UINT8[R_IO_HH]) +#define RSCAN0RMDF017 (RSCAN0.RMDF017.UINT32) +#define RSCAN0RMDF017L (RSCAN0.RMDF017.UINT16[R_IO_L]) +#define RSCAN0RMDF017LL (RSCAN0.RMDF017.UINT8[R_IO_LL]) +#define RSCAN0RMDF017LH (RSCAN0.RMDF017.UINT8[R_IO_LH]) +#define RSCAN0RMDF017H (RSCAN0.RMDF017.UINT16[R_IO_H]) +#define RSCAN0RMDF017HL (RSCAN0.RMDF017.UINT8[R_IO_HL]) +#define RSCAN0RMDF017HH (RSCAN0.RMDF017.UINT8[R_IO_HH]) +#define RSCAN0RMDF117 (RSCAN0.RMDF117.UINT32) +#define RSCAN0RMDF117L (RSCAN0.RMDF117.UINT16[R_IO_L]) +#define RSCAN0RMDF117LL (RSCAN0.RMDF117.UINT8[R_IO_LL]) +#define RSCAN0RMDF117LH (RSCAN0.RMDF117.UINT8[R_IO_LH]) +#define RSCAN0RMDF117H (RSCAN0.RMDF117.UINT16[R_IO_H]) +#define RSCAN0RMDF117HL (RSCAN0.RMDF117.UINT8[R_IO_HL]) +#define RSCAN0RMDF117HH (RSCAN0.RMDF117.UINT8[R_IO_HH]) +#define RSCAN0RMID18 (RSCAN0.RMID18.UINT32) +#define RSCAN0RMID18L (RSCAN0.RMID18.UINT16[R_IO_L]) +#define RSCAN0RMID18LL (RSCAN0.RMID18.UINT8[R_IO_LL]) +#define RSCAN0RMID18LH (RSCAN0.RMID18.UINT8[R_IO_LH]) +#define RSCAN0RMID18H (RSCAN0.RMID18.UINT16[R_IO_H]) +#define RSCAN0RMID18HL (RSCAN0.RMID18.UINT8[R_IO_HL]) +#define RSCAN0RMID18HH (RSCAN0.RMID18.UINT8[R_IO_HH]) +#define RSCAN0RMPTR18 (RSCAN0.RMPTR18.UINT32) +#define RSCAN0RMPTR18L (RSCAN0.RMPTR18.UINT16[R_IO_L]) +#define RSCAN0RMPTR18LL (RSCAN0.RMPTR18.UINT8[R_IO_LL]) +#define RSCAN0RMPTR18LH (RSCAN0.RMPTR18.UINT8[R_IO_LH]) +#define RSCAN0RMPTR18H (RSCAN0.RMPTR18.UINT16[R_IO_H]) +#define RSCAN0RMPTR18HL (RSCAN0.RMPTR18.UINT8[R_IO_HL]) +#define RSCAN0RMPTR18HH (RSCAN0.RMPTR18.UINT8[R_IO_HH]) +#define RSCAN0RMDF018 (RSCAN0.RMDF018.UINT32) +#define RSCAN0RMDF018L (RSCAN0.RMDF018.UINT16[R_IO_L]) +#define RSCAN0RMDF018LL (RSCAN0.RMDF018.UINT8[R_IO_LL]) +#define RSCAN0RMDF018LH (RSCAN0.RMDF018.UINT8[R_IO_LH]) +#define RSCAN0RMDF018H (RSCAN0.RMDF018.UINT16[R_IO_H]) +#define RSCAN0RMDF018HL (RSCAN0.RMDF018.UINT8[R_IO_HL]) +#define RSCAN0RMDF018HH (RSCAN0.RMDF018.UINT8[R_IO_HH]) +#define RSCAN0RMDF118 (RSCAN0.RMDF118.UINT32) +#define RSCAN0RMDF118L (RSCAN0.RMDF118.UINT16[R_IO_L]) +#define RSCAN0RMDF118LL (RSCAN0.RMDF118.UINT8[R_IO_LL]) +#define RSCAN0RMDF118LH (RSCAN0.RMDF118.UINT8[R_IO_LH]) +#define RSCAN0RMDF118H (RSCAN0.RMDF118.UINT16[R_IO_H]) +#define RSCAN0RMDF118HL (RSCAN0.RMDF118.UINT8[R_IO_HL]) +#define RSCAN0RMDF118HH (RSCAN0.RMDF118.UINT8[R_IO_HH]) +#define RSCAN0RMID19 (RSCAN0.RMID19.UINT32) +#define RSCAN0RMID19L (RSCAN0.RMID19.UINT16[R_IO_L]) +#define RSCAN0RMID19LL (RSCAN0.RMID19.UINT8[R_IO_LL]) +#define RSCAN0RMID19LH (RSCAN0.RMID19.UINT8[R_IO_LH]) +#define RSCAN0RMID19H (RSCAN0.RMID19.UINT16[R_IO_H]) +#define RSCAN0RMID19HL (RSCAN0.RMID19.UINT8[R_IO_HL]) +#define RSCAN0RMID19HH (RSCAN0.RMID19.UINT8[R_IO_HH]) +#define RSCAN0RMPTR19 (RSCAN0.RMPTR19.UINT32) +#define RSCAN0RMPTR19L (RSCAN0.RMPTR19.UINT16[R_IO_L]) +#define RSCAN0RMPTR19LL (RSCAN0.RMPTR19.UINT8[R_IO_LL]) +#define RSCAN0RMPTR19LH (RSCAN0.RMPTR19.UINT8[R_IO_LH]) +#define RSCAN0RMPTR19H (RSCAN0.RMPTR19.UINT16[R_IO_H]) +#define RSCAN0RMPTR19HL (RSCAN0.RMPTR19.UINT8[R_IO_HL]) +#define RSCAN0RMPTR19HH (RSCAN0.RMPTR19.UINT8[R_IO_HH]) +#define RSCAN0RMDF019 (RSCAN0.RMDF019.UINT32) +#define RSCAN0RMDF019L (RSCAN0.RMDF019.UINT16[R_IO_L]) +#define RSCAN0RMDF019LL (RSCAN0.RMDF019.UINT8[R_IO_LL]) +#define RSCAN0RMDF019LH (RSCAN0.RMDF019.UINT8[R_IO_LH]) +#define RSCAN0RMDF019H (RSCAN0.RMDF019.UINT16[R_IO_H]) +#define RSCAN0RMDF019HL (RSCAN0.RMDF019.UINT8[R_IO_HL]) +#define RSCAN0RMDF019HH (RSCAN0.RMDF019.UINT8[R_IO_HH]) +#define RSCAN0RMDF119 (RSCAN0.RMDF119.UINT32) +#define RSCAN0RMDF119L (RSCAN0.RMDF119.UINT16[R_IO_L]) +#define RSCAN0RMDF119LL (RSCAN0.RMDF119.UINT8[R_IO_LL]) +#define RSCAN0RMDF119LH (RSCAN0.RMDF119.UINT8[R_IO_LH]) +#define RSCAN0RMDF119H (RSCAN0.RMDF119.UINT16[R_IO_H]) +#define RSCAN0RMDF119HL (RSCAN0.RMDF119.UINT8[R_IO_HL]) +#define RSCAN0RMDF119HH (RSCAN0.RMDF119.UINT8[R_IO_HH]) +#define RSCAN0RMID20 (RSCAN0.RMID20.UINT32) +#define RSCAN0RMID20L (RSCAN0.RMID20.UINT16[R_IO_L]) +#define RSCAN0RMID20LL (RSCAN0.RMID20.UINT8[R_IO_LL]) +#define RSCAN0RMID20LH (RSCAN0.RMID20.UINT8[R_IO_LH]) +#define RSCAN0RMID20H (RSCAN0.RMID20.UINT16[R_IO_H]) +#define RSCAN0RMID20HL (RSCAN0.RMID20.UINT8[R_IO_HL]) +#define RSCAN0RMID20HH (RSCAN0.RMID20.UINT8[R_IO_HH]) +#define RSCAN0RMPTR20 (RSCAN0.RMPTR20.UINT32) +#define RSCAN0RMPTR20L (RSCAN0.RMPTR20.UINT16[R_IO_L]) +#define RSCAN0RMPTR20LL (RSCAN0.RMPTR20.UINT8[R_IO_LL]) +#define RSCAN0RMPTR20LH (RSCAN0.RMPTR20.UINT8[R_IO_LH]) +#define RSCAN0RMPTR20H (RSCAN0.RMPTR20.UINT16[R_IO_H]) +#define RSCAN0RMPTR20HL (RSCAN0.RMPTR20.UINT8[R_IO_HL]) +#define RSCAN0RMPTR20HH (RSCAN0.RMPTR20.UINT8[R_IO_HH]) +#define RSCAN0RMDF020 (RSCAN0.RMDF020.UINT32) +#define RSCAN0RMDF020L (RSCAN0.RMDF020.UINT16[R_IO_L]) +#define RSCAN0RMDF020LL (RSCAN0.RMDF020.UINT8[R_IO_LL]) +#define RSCAN0RMDF020LH (RSCAN0.RMDF020.UINT8[R_IO_LH]) +#define RSCAN0RMDF020H (RSCAN0.RMDF020.UINT16[R_IO_H]) +#define RSCAN0RMDF020HL (RSCAN0.RMDF020.UINT8[R_IO_HL]) +#define RSCAN0RMDF020HH (RSCAN0.RMDF020.UINT8[R_IO_HH]) +#define RSCAN0RMDF120 (RSCAN0.RMDF120.UINT32) +#define RSCAN0RMDF120L (RSCAN0.RMDF120.UINT16[R_IO_L]) +#define RSCAN0RMDF120LL (RSCAN0.RMDF120.UINT8[R_IO_LL]) +#define RSCAN0RMDF120LH (RSCAN0.RMDF120.UINT8[R_IO_LH]) +#define RSCAN0RMDF120H (RSCAN0.RMDF120.UINT16[R_IO_H]) +#define RSCAN0RMDF120HL (RSCAN0.RMDF120.UINT8[R_IO_HL]) +#define RSCAN0RMDF120HH (RSCAN0.RMDF120.UINT8[R_IO_HH]) +#define RSCAN0RMID21 (RSCAN0.RMID21.UINT32) +#define RSCAN0RMID21L (RSCAN0.RMID21.UINT16[R_IO_L]) +#define RSCAN0RMID21LL (RSCAN0.RMID21.UINT8[R_IO_LL]) +#define RSCAN0RMID21LH (RSCAN0.RMID21.UINT8[R_IO_LH]) +#define RSCAN0RMID21H (RSCAN0.RMID21.UINT16[R_IO_H]) +#define RSCAN0RMID21HL (RSCAN0.RMID21.UINT8[R_IO_HL]) +#define RSCAN0RMID21HH (RSCAN0.RMID21.UINT8[R_IO_HH]) +#define RSCAN0RMPTR21 (RSCAN0.RMPTR21.UINT32) +#define RSCAN0RMPTR21L (RSCAN0.RMPTR21.UINT16[R_IO_L]) +#define RSCAN0RMPTR21LL (RSCAN0.RMPTR21.UINT8[R_IO_LL]) +#define RSCAN0RMPTR21LH (RSCAN0.RMPTR21.UINT8[R_IO_LH]) +#define RSCAN0RMPTR21H (RSCAN0.RMPTR21.UINT16[R_IO_H]) +#define RSCAN0RMPTR21HL (RSCAN0.RMPTR21.UINT8[R_IO_HL]) +#define RSCAN0RMPTR21HH (RSCAN0.RMPTR21.UINT8[R_IO_HH]) +#define RSCAN0RMDF021 (RSCAN0.RMDF021.UINT32) +#define RSCAN0RMDF021L (RSCAN0.RMDF021.UINT16[R_IO_L]) +#define RSCAN0RMDF021LL (RSCAN0.RMDF021.UINT8[R_IO_LL]) +#define RSCAN0RMDF021LH (RSCAN0.RMDF021.UINT8[R_IO_LH]) +#define RSCAN0RMDF021H (RSCAN0.RMDF021.UINT16[R_IO_H]) +#define RSCAN0RMDF021HL (RSCAN0.RMDF021.UINT8[R_IO_HL]) +#define RSCAN0RMDF021HH (RSCAN0.RMDF021.UINT8[R_IO_HH]) +#define RSCAN0RMDF121 (RSCAN0.RMDF121.UINT32) +#define RSCAN0RMDF121L (RSCAN0.RMDF121.UINT16[R_IO_L]) +#define RSCAN0RMDF121LL (RSCAN0.RMDF121.UINT8[R_IO_LL]) +#define RSCAN0RMDF121LH (RSCAN0.RMDF121.UINT8[R_IO_LH]) +#define RSCAN0RMDF121H (RSCAN0.RMDF121.UINT16[R_IO_H]) +#define RSCAN0RMDF121HL (RSCAN0.RMDF121.UINT8[R_IO_HL]) +#define RSCAN0RMDF121HH (RSCAN0.RMDF121.UINT8[R_IO_HH]) +#define RSCAN0RMID22 (RSCAN0.RMID22.UINT32) +#define RSCAN0RMID22L (RSCAN0.RMID22.UINT16[R_IO_L]) +#define RSCAN0RMID22LL (RSCAN0.RMID22.UINT8[R_IO_LL]) +#define RSCAN0RMID22LH (RSCAN0.RMID22.UINT8[R_IO_LH]) +#define RSCAN0RMID22H (RSCAN0.RMID22.UINT16[R_IO_H]) +#define RSCAN0RMID22HL (RSCAN0.RMID22.UINT8[R_IO_HL]) +#define RSCAN0RMID22HH (RSCAN0.RMID22.UINT8[R_IO_HH]) +#define RSCAN0RMPTR22 (RSCAN0.RMPTR22.UINT32) +#define RSCAN0RMPTR22L (RSCAN0.RMPTR22.UINT16[R_IO_L]) +#define RSCAN0RMPTR22LL (RSCAN0.RMPTR22.UINT8[R_IO_LL]) +#define RSCAN0RMPTR22LH (RSCAN0.RMPTR22.UINT8[R_IO_LH]) +#define RSCAN0RMPTR22H (RSCAN0.RMPTR22.UINT16[R_IO_H]) +#define RSCAN0RMPTR22HL (RSCAN0.RMPTR22.UINT8[R_IO_HL]) +#define RSCAN0RMPTR22HH (RSCAN0.RMPTR22.UINT8[R_IO_HH]) +#define RSCAN0RMDF022 (RSCAN0.RMDF022.UINT32) +#define RSCAN0RMDF022L (RSCAN0.RMDF022.UINT16[R_IO_L]) +#define RSCAN0RMDF022LL (RSCAN0.RMDF022.UINT8[R_IO_LL]) +#define RSCAN0RMDF022LH (RSCAN0.RMDF022.UINT8[R_IO_LH]) +#define RSCAN0RMDF022H (RSCAN0.RMDF022.UINT16[R_IO_H]) +#define RSCAN0RMDF022HL (RSCAN0.RMDF022.UINT8[R_IO_HL]) +#define RSCAN0RMDF022HH (RSCAN0.RMDF022.UINT8[R_IO_HH]) +#define RSCAN0RMDF122 (RSCAN0.RMDF122.UINT32) +#define RSCAN0RMDF122L (RSCAN0.RMDF122.UINT16[R_IO_L]) +#define RSCAN0RMDF122LL (RSCAN0.RMDF122.UINT8[R_IO_LL]) +#define RSCAN0RMDF122LH (RSCAN0.RMDF122.UINT8[R_IO_LH]) +#define RSCAN0RMDF122H (RSCAN0.RMDF122.UINT16[R_IO_H]) +#define RSCAN0RMDF122HL (RSCAN0.RMDF122.UINT8[R_IO_HL]) +#define RSCAN0RMDF122HH (RSCAN0.RMDF122.UINT8[R_IO_HH]) +#define RSCAN0RMID23 (RSCAN0.RMID23.UINT32) +#define RSCAN0RMID23L (RSCAN0.RMID23.UINT16[R_IO_L]) +#define RSCAN0RMID23LL (RSCAN0.RMID23.UINT8[R_IO_LL]) +#define RSCAN0RMID23LH (RSCAN0.RMID23.UINT8[R_IO_LH]) +#define RSCAN0RMID23H (RSCAN0.RMID23.UINT16[R_IO_H]) +#define RSCAN0RMID23HL (RSCAN0.RMID23.UINT8[R_IO_HL]) +#define RSCAN0RMID23HH (RSCAN0.RMID23.UINT8[R_IO_HH]) +#define RSCAN0RMPTR23 (RSCAN0.RMPTR23.UINT32) +#define RSCAN0RMPTR23L (RSCAN0.RMPTR23.UINT16[R_IO_L]) +#define RSCAN0RMPTR23LL (RSCAN0.RMPTR23.UINT8[R_IO_LL]) +#define RSCAN0RMPTR23LH (RSCAN0.RMPTR23.UINT8[R_IO_LH]) +#define RSCAN0RMPTR23H (RSCAN0.RMPTR23.UINT16[R_IO_H]) +#define RSCAN0RMPTR23HL (RSCAN0.RMPTR23.UINT8[R_IO_HL]) +#define RSCAN0RMPTR23HH (RSCAN0.RMPTR23.UINT8[R_IO_HH]) +#define RSCAN0RMDF023 (RSCAN0.RMDF023.UINT32) +#define RSCAN0RMDF023L (RSCAN0.RMDF023.UINT16[R_IO_L]) +#define RSCAN0RMDF023LL (RSCAN0.RMDF023.UINT8[R_IO_LL]) +#define RSCAN0RMDF023LH (RSCAN0.RMDF023.UINT8[R_IO_LH]) +#define RSCAN0RMDF023H (RSCAN0.RMDF023.UINT16[R_IO_H]) +#define RSCAN0RMDF023HL (RSCAN0.RMDF023.UINT8[R_IO_HL]) +#define RSCAN0RMDF023HH (RSCAN0.RMDF023.UINT8[R_IO_HH]) +#define RSCAN0RMDF123 (RSCAN0.RMDF123.UINT32) +#define RSCAN0RMDF123L (RSCAN0.RMDF123.UINT16[R_IO_L]) +#define RSCAN0RMDF123LL (RSCAN0.RMDF123.UINT8[R_IO_LL]) +#define RSCAN0RMDF123LH (RSCAN0.RMDF123.UINT8[R_IO_LH]) +#define RSCAN0RMDF123H (RSCAN0.RMDF123.UINT16[R_IO_H]) +#define RSCAN0RMDF123HL (RSCAN0.RMDF123.UINT8[R_IO_HL]) +#define RSCAN0RMDF123HH (RSCAN0.RMDF123.UINT8[R_IO_HH]) +#define RSCAN0RMID24 (RSCAN0.RMID24.UINT32) +#define RSCAN0RMID24L (RSCAN0.RMID24.UINT16[R_IO_L]) +#define RSCAN0RMID24LL (RSCAN0.RMID24.UINT8[R_IO_LL]) +#define RSCAN0RMID24LH (RSCAN0.RMID24.UINT8[R_IO_LH]) +#define RSCAN0RMID24H (RSCAN0.RMID24.UINT16[R_IO_H]) +#define RSCAN0RMID24HL (RSCAN0.RMID24.UINT8[R_IO_HL]) +#define RSCAN0RMID24HH (RSCAN0.RMID24.UINT8[R_IO_HH]) +#define RSCAN0RMPTR24 (RSCAN0.RMPTR24.UINT32) +#define RSCAN0RMPTR24L (RSCAN0.RMPTR24.UINT16[R_IO_L]) +#define RSCAN0RMPTR24LL (RSCAN0.RMPTR24.UINT8[R_IO_LL]) +#define RSCAN0RMPTR24LH (RSCAN0.RMPTR24.UINT8[R_IO_LH]) +#define RSCAN0RMPTR24H (RSCAN0.RMPTR24.UINT16[R_IO_H]) +#define RSCAN0RMPTR24HL (RSCAN0.RMPTR24.UINT8[R_IO_HL]) +#define RSCAN0RMPTR24HH (RSCAN0.RMPTR24.UINT8[R_IO_HH]) +#define RSCAN0RMDF024 (RSCAN0.RMDF024.UINT32) +#define RSCAN0RMDF024L (RSCAN0.RMDF024.UINT16[R_IO_L]) +#define RSCAN0RMDF024LL (RSCAN0.RMDF024.UINT8[R_IO_LL]) +#define RSCAN0RMDF024LH (RSCAN0.RMDF024.UINT8[R_IO_LH]) +#define RSCAN0RMDF024H (RSCAN0.RMDF024.UINT16[R_IO_H]) +#define RSCAN0RMDF024HL (RSCAN0.RMDF024.UINT8[R_IO_HL]) +#define RSCAN0RMDF024HH (RSCAN0.RMDF024.UINT8[R_IO_HH]) +#define RSCAN0RMDF124 (RSCAN0.RMDF124.UINT32) +#define RSCAN0RMDF124L (RSCAN0.RMDF124.UINT16[R_IO_L]) +#define RSCAN0RMDF124LL (RSCAN0.RMDF124.UINT8[R_IO_LL]) +#define RSCAN0RMDF124LH (RSCAN0.RMDF124.UINT8[R_IO_LH]) +#define RSCAN0RMDF124H (RSCAN0.RMDF124.UINT16[R_IO_H]) +#define RSCAN0RMDF124HL (RSCAN0.RMDF124.UINT8[R_IO_HL]) +#define RSCAN0RMDF124HH (RSCAN0.RMDF124.UINT8[R_IO_HH]) +#define RSCAN0RMID25 (RSCAN0.RMID25.UINT32) +#define RSCAN0RMID25L (RSCAN0.RMID25.UINT16[R_IO_L]) +#define RSCAN0RMID25LL (RSCAN0.RMID25.UINT8[R_IO_LL]) +#define RSCAN0RMID25LH (RSCAN0.RMID25.UINT8[R_IO_LH]) +#define RSCAN0RMID25H (RSCAN0.RMID25.UINT16[R_IO_H]) +#define RSCAN0RMID25HL (RSCAN0.RMID25.UINT8[R_IO_HL]) +#define RSCAN0RMID25HH (RSCAN0.RMID25.UINT8[R_IO_HH]) +#define RSCAN0RMPTR25 (RSCAN0.RMPTR25.UINT32) +#define RSCAN0RMPTR25L (RSCAN0.RMPTR25.UINT16[R_IO_L]) +#define RSCAN0RMPTR25LL (RSCAN0.RMPTR25.UINT8[R_IO_LL]) +#define RSCAN0RMPTR25LH (RSCAN0.RMPTR25.UINT8[R_IO_LH]) +#define RSCAN0RMPTR25H (RSCAN0.RMPTR25.UINT16[R_IO_H]) +#define RSCAN0RMPTR25HL (RSCAN0.RMPTR25.UINT8[R_IO_HL]) +#define RSCAN0RMPTR25HH (RSCAN0.RMPTR25.UINT8[R_IO_HH]) +#define RSCAN0RMDF025 (RSCAN0.RMDF025.UINT32) +#define RSCAN0RMDF025L (RSCAN0.RMDF025.UINT16[R_IO_L]) +#define RSCAN0RMDF025LL (RSCAN0.RMDF025.UINT8[R_IO_LL]) +#define RSCAN0RMDF025LH (RSCAN0.RMDF025.UINT8[R_IO_LH]) +#define RSCAN0RMDF025H (RSCAN0.RMDF025.UINT16[R_IO_H]) +#define RSCAN0RMDF025HL (RSCAN0.RMDF025.UINT8[R_IO_HL]) +#define RSCAN0RMDF025HH (RSCAN0.RMDF025.UINT8[R_IO_HH]) +#define RSCAN0RMDF125 (RSCAN0.RMDF125.UINT32) +#define RSCAN0RMDF125L (RSCAN0.RMDF125.UINT16[R_IO_L]) +#define RSCAN0RMDF125LL (RSCAN0.RMDF125.UINT8[R_IO_LL]) +#define RSCAN0RMDF125LH (RSCAN0.RMDF125.UINT8[R_IO_LH]) +#define RSCAN0RMDF125H (RSCAN0.RMDF125.UINT16[R_IO_H]) +#define RSCAN0RMDF125HL (RSCAN0.RMDF125.UINT8[R_IO_HL]) +#define RSCAN0RMDF125HH (RSCAN0.RMDF125.UINT8[R_IO_HH]) +#define RSCAN0RMID26 (RSCAN0.RMID26.UINT32) +#define RSCAN0RMID26L (RSCAN0.RMID26.UINT16[R_IO_L]) +#define RSCAN0RMID26LL (RSCAN0.RMID26.UINT8[R_IO_LL]) +#define RSCAN0RMID26LH (RSCAN0.RMID26.UINT8[R_IO_LH]) +#define RSCAN0RMID26H (RSCAN0.RMID26.UINT16[R_IO_H]) +#define RSCAN0RMID26HL (RSCAN0.RMID26.UINT8[R_IO_HL]) +#define RSCAN0RMID26HH (RSCAN0.RMID26.UINT8[R_IO_HH]) +#define RSCAN0RMPTR26 (RSCAN0.RMPTR26.UINT32) +#define RSCAN0RMPTR26L (RSCAN0.RMPTR26.UINT16[R_IO_L]) +#define RSCAN0RMPTR26LL (RSCAN0.RMPTR26.UINT8[R_IO_LL]) +#define RSCAN0RMPTR26LH (RSCAN0.RMPTR26.UINT8[R_IO_LH]) +#define RSCAN0RMPTR26H (RSCAN0.RMPTR26.UINT16[R_IO_H]) +#define RSCAN0RMPTR26HL (RSCAN0.RMPTR26.UINT8[R_IO_HL]) +#define RSCAN0RMPTR26HH (RSCAN0.RMPTR26.UINT8[R_IO_HH]) +#define RSCAN0RMDF026 (RSCAN0.RMDF026.UINT32) +#define RSCAN0RMDF026L (RSCAN0.RMDF026.UINT16[R_IO_L]) +#define RSCAN0RMDF026LL (RSCAN0.RMDF026.UINT8[R_IO_LL]) +#define RSCAN0RMDF026LH (RSCAN0.RMDF026.UINT8[R_IO_LH]) +#define RSCAN0RMDF026H (RSCAN0.RMDF026.UINT16[R_IO_H]) +#define RSCAN0RMDF026HL (RSCAN0.RMDF026.UINT8[R_IO_HL]) +#define RSCAN0RMDF026HH (RSCAN0.RMDF026.UINT8[R_IO_HH]) +#define RSCAN0RMDF126 (RSCAN0.RMDF126.UINT32) +#define RSCAN0RMDF126L (RSCAN0.RMDF126.UINT16[R_IO_L]) +#define RSCAN0RMDF126LL (RSCAN0.RMDF126.UINT8[R_IO_LL]) +#define RSCAN0RMDF126LH (RSCAN0.RMDF126.UINT8[R_IO_LH]) +#define RSCAN0RMDF126H (RSCAN0.RMDF126.UINT16[R_IO_H]) +#define RSCAN0RMDF126HL (RSCAN0.RMDF126.UINT8[R_IO_HL]) +#define RSCAN0RMDF126HH (RSCAN0.RMDF126.UINT8[R_IO_HH]) +#define RSCAN0RMID27 (RSCAN0.RMID27.UINT32) +#define RSCAN0RMID27L (RSCAN0.RMID27.UINT16[R_IO_L]) +#define RSCAN0RMID27LL (RSCAN0.RMID27.UINT8[R_IO_LL]) +#define RSCAN0RMID27LH (RSCAN0.RMID27.UINT8[R_IO_LH]) +#define RSCAN0RMID27H (RSCAN0.RMID27.UINT16[R_IO_H]) +#define RSCAN0RMID27HL (RSCAN0.RMID27.UINT8[R_IO_HL]) +#define RSCAN0RMID27HH (RSCAN0.RMID27.UINT8[R_IO_HH]) +#define RSCAN0RMPTR27 (RSCAN0.RMPTR27.UINT32) +#define RSCAN0RMPTR27L (RSCAN0.RMPTR27.UINT16[R_IO_L]) +#define RSCAN0RMPTR27LL (RSCAN0.RMPTR27.UINT8[R_IO_LL]) +#define RSCAN0RMPTR27LH (RSCAN0.RMPTR27.UINT8[R_IO_LH]) +#define RSCAN0RMPTR27H (RSCAN0.RMPTR27.UINT16[R_IO_H]) +#define RSCAN0RMPTR27HL (RSCAN0.RMPTR27.UINT8[R_IO_HL]) +#define RSCAN0RMPTR27HH (RSCAN0.RMPTR27.UINT8[R_IO_HH]) +#define RSCAN0RMDF027 (RSCAN0.RMDF027.UINT32) +#define RSCAN0RMDF027L (RSCAN0.RMDF027.UINT16[R_IO_L]) +#define RSCAN0RMDF027LL (RSCAN0.RMDF027.UINT8[R_IO_LL]) +#define RSCAN0RMDF027LH (RSCAN0.RMDF027.UINT8[R_IO_LH]) +#define RSCAN0RMDF027H (RSCAN0.RMDF027.UINT16[R_IO_H]) +#define RSCAN0RMDF027HL (RSCAN0.RMDF027.UINT8[R_IO_HL]) +#define RSCAN0RMDF027HH (RSCAN0.RMDF027.UINT8[R_IO_HH]) +#define RSCAN0RMDF127 (RSCAN0.RMDF127.UINT32) +#define RSCAN0RMDF127L (RSCAN0.RMDF127.UINT16[R_IO_L]) +#define RSCAN0RMDF127LL (RSCAN0.RMDF127.UINT8[R_IO_LL]) +#define RSCAN0RMDF127LH (RSCAN0.RMDF127.UINT8[R_IO_LH]) +#define RSCAN0RMDF127H (RSCAN0.RMDF127.UINT16[R_IO_H]) +#define RSCAN0RMDF127HL (RSCAN0.RMDF127.UINT8[R_IO_HL]) +#define RSCAN0RMDF127HH (RSCAN0.RMDF127.UINT8[R_IO_HH]) +#define RSCAN0RMID28 (RSCAN0.RMID28.UINT32) +#define RSCAN0RMID28L (RSCAN0.RMID28.UINT16[R_IO_L]) +#define RSCAN0RMID28LL (RSCAN0.RMID28.UINT8[R_IO_LL]) +#define RSCAN0RMID28LH (RSCAN0.RMID28.UINT8[R_IO_LH]) +#define RSCAN0RMID28H (RSCAN0.RMID28.UINT16[R_IO_H]) +#define RSCAN0RMID28HL (RSCAN0.RMID28.UINT8[R_IO_HL]) +#define RSCAN0RMID28HH (RSCAN0.RMID28.UINT8[R_IO_HH]) +#define RSCAN0RMPTR28 (RSCAN0.RMPTR28.UINT32) +#define RSCAN0RMPTR28L (RSCAN0.RMPTR28.UINT16[R_IO_L]) +#define RSCAN0RMPTR28LL (RSCAN0.RMPTR28.UINT8[R_IO_LL]) +#define RSCAN0RMPTR28LH (RSCAN0.RMPTR28.UINT8[R_IO_LH]) +#define RSCAN0RMPTR28H (RSCAN0.RMPTR28.UINT16[R_IO_H]) +#define RSCAN0RMPTR28HL (RSCAN0.RMPTR28.UINT8[R_IO_HL]) +#define RSCAN0RMPTR28HH (RSCAN0.RMPTR28.UINT8[R_IO_HH]) +#define RSCAN0RMDF028 (RSCAN0.RMDF028.UINT32) +#define RSCAN0RMDF028L (RSCAN0.RMDF028.UINT16[R_IO_L]) +#define RSCAN0RMDF028LL (RSCAN0.RMDF028.UINT8[R_IO_LL]) +#define RSCAN0RMDF028LH (RSCAN0.RMDF028.UINT8[R_IO_LH]) +#define RSCAN0RMDF028H (RSCAN0.RMDF028.UINT16[R_IO_H]) +#define RSCAN0RMDF028HL (RSCAN0.RMDF028.UINT8[R_IO_HL]) +#define RSCAN0RMDF028HH (RSCAN0.RMDF028.UINT8[R_IO_HH]) +#define RSCAN0RMDF128 (RSCAN0.RMDF128.UINT32) +#define RSCAN0RMDF128L (RSCAN0.RMDF128.UINT16[R_IO_L]) +#define RSCAN0RMDF128LL (RSCAN0.RMDF128.UINT8[R_IO_LL]) +#define RSCAN0RMDF128LH (RSCAN0.RMDF128.UINT8[R_IO_LH]) +#define RSCAN0RMDF128H (RSCAN0.RMDF128.UINT16[R_IO_H]) +#define RSCAN0RMDF128HL (RSCAN0.RMDF128.UINT8[R_IO_HL]) +#define RSCAN0RMDF128HH (RSCAN0.RMDF128.UINT8[R_IO_HH]) +#define RSCAN0RMID29 (RSCAN0.RMID29.UINT32) +#define RSCAN0RMID29L (RSCAN0.RMID29.UINT16[R_IO_L]) +#define RSCAN0RMID29LL (RSCAN0.RMID29.UINT8[R_IO_LL]) +#define RSCAN0RMID29LH (RSCAN0.RMID29.UINT8[R_IO_LH]) +#define RSCAN0RMID29H (RSCAN0.RMID29.UINT16[R_IO_H]) +#define RSCAN0RMID29HL (RSCAN0.RMID29.UINT8[R_IO_HL]) +#define RSCAN0RMID29HH (RSCAN0.RMID29.UINT8[R_IO_HH]) +#define RSCAN0RMPTR29 (RSCAN0.RMPTR29.UINT32) +#define RSCAN0RMPTR29L (RSCAN0.RMPTR29.UINT16[R_IO_L]) +#define RSCAN0RMPTR29LL (RSCAN0.RMPTR29.UINT8[R_IO_LL]) +#define RSCAN0RMPTR29LH (RSCAN0.RMPTR29.UINT8[R_IO_LH]) +#define RSCAN0RMPTR29H (RSCAN0.RMPTR29.UINT16[R_IO_H]) +#define RSCAN0RMPTR29HL (RSCAN0.RMPTR29.UINT8[R_IO_HL]) +#define RSCAN0RMPTR29HH (RSCAN0.RMPTR29.UINT8[R_IO_HH]) +#define RSCAN0RMDF029 (RSCAN0.RMDF029.UINT32) +#define RSCAN0RMDF029L (RSCAN0.RMDF029.UINT16[R_IO_L]) +#define RSCAN0RMDF029LL (RSCAN0.RMDF029.UINT8[R_IO_LL]) +#define RSCAN0RMDF029LH (RSCAN0.RMDF029.UINT8[R_IO_LH]) +#define RSCAN0RMDF029H (RSCAN0.RMDF029.UINT16[R_IO_H]) +#define RSCAN0RMDF029HL (RSCAN0.RMDF029.UINT8[R_IO_HL]) +#define RSCAN0RMDF029HH (RSCAN0.RMDF029.UINT8[R_IO_HH]) +#define RSCAN0RMDF129 (RSCAN0.RMDF129.UINT32) +#define RSCAN0RMDF129L (RSCAN0.RMDF129.UINT16[R_IO_L]) +#define RSCAN0RMDF129LL (RSCAN0.RMDF129.UINT8[R_IO_LL]) +#define RSCAN0RMDF129LH (RSCAN0.RMDF129.UINT8[R_IO_LH]) +#define RSCAN0RMDF129H (RSCAN0.RMDF129.UINT16[R_IO_H]) +#define RSCAN0RMDF129HL (RSCAN0.RMDF129.UINT8[R_IO_HL]) +#define RSCAN0RMDF129HH (RSCAN0.RMDF129.UINT8[R_IO_HH]) +#define RSCAN0RMID30 (RSCAN0.RMID30.UINT32) +#define RSCAN0RMID30L (RSCAN0.RMID30.UINT16[R_IO_L]) +#define RSCAN0RMID30LL (RSCAN0.RMID30.UINT8[R_IO_LL]) +#define RSCAN0RMID30LH (RSCAN0.RMID30.UINT8[R_IO_LH]) +#define RSCAN0RMID30H (RSCAN0.RMID30.UINT16[R_IO_H]) +#define RSCAN0RMID30HL (RSCAN0.RMID30.UINT8[R_IO_HL]) +#define RSCAN0RMID30HH (RSCAN0.RMID30.UINT8[R_IO_HH]) +#define RSCAN0RMPTR30 (RSCAN0.RMPTR30.UINT32) +#define RSCAN0RMPTR30L (RSCAN0.RMPTR30.UINT16[R_IO_L]) +#define RSCAN0RMPTR30LL (RSCAN0.RMPTR30.UINT8[R_IO_LL]) +#define RSCAN0RMPTR30LH (RSCAN0.RMPTR30.UINT8[R_IO_LH]) +#define RSCAN0RMPTR30H (RSCAN0.RMPTR30.UINT16[R_IO_H]) +#define RSCAN0RMPTR30HL (RSCAN0.RMPTR30.UINT8[R_IO_HL]) +#define RSCAN0RMPTR30HH (RSCAN0.RMPTR30.UINT8[R_IO_HH]) +#define RSCAN0RMDF030 (RSCAN0.RMDF030.UINT32) +#define RSCAN0RMDF030L (RSCAN0.RMDF030.UINT16[R_IO_L]) +#define RSCAN0RMDF030LL (RSCAN0.RMDF030.UINT8[R_IO_LL]) +#define RSCAN0RMDF030LH (RSCAN0.RMDF030.UINT8[R_IO_LH]) +#define RSCAN0RMDF030H (RSCAN0.RMDF030.UINT16[R_IO_H]) +#define RSCAN0RMDF030HL (RSCAN0.RMDF030.UINT8[R_IO_HL]) +#define RSCAN0RMDF030HH (RSCAN0.RMDF030.UINT8[R_IO_HH]) +#define RSCAN0RMDF130 (RSCAN0.RMDF130.UINT32) +#define RSCAN0RMDF130L (RSCAN0.RMDF130.UINT16[R_IO_L]) +#define RSCAN0RMDF130LL (RSCAN0.RMDF130.UINT8[R_IO_LL]) +#define RSCAN0RMDF130LH (RSCAN0.RMDF130.UINT8[R_IO_LH]) +#define RSCAN0RMDF130H (RSCAN0.RMDF130.UINT16[R_IO_H]) +#define RSCAN0RMDF130HL (RSCAN0.RMDF130.UINT8[R_IO_HL]) +#define RSCAN0RMDF130HH (RSCAN0.RMDF130.UINT8[R_IO_HH]) +#define RSCAN0RMID31 (RSCAN0.RMID31.UINT32) +#define RSCAN0RMID31L (RSCAN0.RMID31.UINT16[R_IO_L]) +#define RSCAN0RMID31LL (RSCAN0.RMID31.UINT8[R_IO_LL]) +#define RSCAN0RMID31LH (RSCAN0.RMID31.UINT8[R_IO_LH]) +#define RSCAN0RMID31H (RSCAN0.RMID31.UINT16[R_IO_H]) +#define RSCAN0RMID31HL (RSCAN0.RMID31.UINT8[R_IO_HL]) +#define RSCAN0RMID31HH (RSCAN0.RMID31.UINT8[R_IO_HH]) +#define RSCAN0RMPTR31 (RSCAN0.RMPTR31.UINT32) +#define RSCAN0RMPTR31L (RSCAN0.RMPTR31.UINT16[R_IO_L]) +#define RSCAN0RMPTR31LL (RSCAN0.RMPTR31.UINT8[R_IO_LL]) +#define RSCAN0RMPTR31LH (RSCAN0.RMPTR31.UINT8[R_IO_LH]) +#define RSCAN0RMPTR31H (RSCAN0.RMPTR31.UINT16[R_IO_H]) +#define RSCAN0RMPTR31HL (RSCAN0.RMPTR31.UINT8[R_IO_HL]) +#define RSCAN0RMPTR31HH (RSCAN0.RMPTR31.UINT8[R_IO_HH]) +#define RSCAN0RMDF031 (RSCAN0.RMDF031.UINT32) +#define RSCAN0RMDF031L (RSCAN0.RMDF031.UINT16[R_IO_L]) +#define RSCAN0RMDF031LL (RSCAN0.RMDF031.UINT8[R_IO_LL]) +#define RSCAN0RMDF031LH (RSCAN0.RMDF031.UINT8[R_IO_LH]) +#define RSCAN0RMDF031H (RSCAN0.RMDF031.UINT16[R_IO_H]) +#define RSCAN0RMDF031HL (RSCAN0.RMDF031.UINT8[R_IO_HL]) +#define RSCAN0RMDF031HH (RSCAN0.RMDF031.UINT8[R_IO_HH]) +#define RSCAN0RMDF131 (RSCAN0.RMDF131.UINT32) +#define RSCAN0RMDF131L (RSCAN0.RMDF131.UINT16[R_IO_L]) +#define RSCAN0RMDF131LL (RSCAN0.RMDF131.UINT8[R_IO_LL]) +#define RSCAN0RMDF131LH (RSCAN0.RMDF131.UINT8[R_IO_LH]) +#define RSCAN0RMDF131H (RSCAN0.RMDF131.UINT16[R_IO_H]) +#define RSCAN0RMDF131HL (RSCAN0.RMDF131.UINT8[R_IO_HL]) +#define RSCAN0RMDF131HH (RSCAN0.RMDF131.UINT8[R_IO_HH]) +#define RSCAN0RFID0 (RSCAN0.RFID0.UINT32) +#define RSCAN0RFID0L (RSCAN0.RFID0.UINT16[R_IO_L]) +#define RSCAN0RFID0LL (RSCAN0.RFID0.UINT8[R_IO_LL]) +#define RSCAN0RFID0LH (RSCAN0.RFID0.UINT8[R_IO_LH]) +#define RSCAN0RFID0H (RSCAN0.RFID0.UINT16[R_IO_H]) +#define RSCAN0RFID0HL (RSCAN0.RFID0.UINT8[R_IO_HL]) +#define RSCAN0RFID0HH (RSCAN0.RFID0.UINT8[R_IO_HH]) +#define RSCAN0RFPTR0 (RSCAN0.RFPTR0.UINT32) +#define RSCAN0RFPTR0L (RSCAN0.RFPTR0.UINT16[R_IO_L]) +#define RSCAN0RFPTR0LL (RSCAN0.RFPTR0.UINT8[R_IO_LL]) +#define RSCAN0RFPTR0LH (RSCAN0.RFPTR0.UINT8[R_IO_LH]) +#define RSCAN0RFPTR0H (RSCAN0.RFPTR0.UINT16[R_IO_H]) +#define RSCAN0RFPTR0HL (RSCAN0.RFPTR0.UINT8[R_IO_HL]) +#define RSCAN0RFPTR0HH (RSCAN0.RFPTR0.UINT8[R_IO_HH]) +#define RSCAN0RFDF00 (RSCAN0.RFDF00.UINT32) +#define RSCAN0RFDF00L (RSCAN0.RFDF00.UINT16[R_IO_L]) +#define RSCAN0RFDF00LL (RSCAN0.RFDF00.UINT8[R_IO_LL]) +#define RSCAN0RFDF00LH (RSCAN0.RFDF00.UINT8[R_IO_LH]) +#define RSCAN0RFDF00H (RSCAN0.RFDF00.UINT16[R_IO_H]) +#define RSCAN0RFDF00HL (RSCAN0.RFDF00.UINT8[R_IO_HL]) +#define RSCAN0RFDF00HH (RSCAN0.RFDF00.UINT8[R_IO_HH]) +#define RSCAN0RFDF10 (RSCAN0.RFDF10.UINT32) +#define RSCAN0RFDF10L (RSCAN0.RFDF10.UINT16[R_IO_L]) +#define RSCAN0RFDF10LL (RSCAN0.RFDF10.UINT8[R_IO_LL]) +#define RSCAN0RFDF10LH (RSCAN0.RFDF10.UINT8[R_IO_LH]) +#define RSCAN0RFDF10H (RSCAN0.RFDF10.UINT16[R_IO_H]) +#define RSCAN0RFDF10HL (RSCAN0.RFDF10.UINT8[R_IO_HL]) +#define RSCAN0RFDF10HH (RSCAN0.RFDF10.UINT8[R_IO_HH]) +#define RSCAN0RFID1 (RSCAN0.RFID1.UINT32) +#define RSCAN0RFID1L (RSCAN0.RFID1.UINT16[R_IO_L]) +#define RSCAN0RFID1LL (RSCAN0.RFID1.UINT8[R_IO_LL]) +#define RSCAN0RFID1LH (RSCAN0.RFID1.UINT8[R_IO_LH]) +#define RSCAN0RFID1H (RSCAN0.RFID1.UINT16[R_IO_H]) +#define RSCAN0RFID1HL (RSCAN0.RFID1.UINT8[R_IO_HL]) +#define RSCAN0RFID1HH (RSCAN0.RFID1.UINT8[R_IO_HH]) +#define RSCAN0RFPTR1 (RSCAN0.RFPTR1.UINT32) +#define RSCAN0RFPTR1L (RSCAN0.RFPTR1.UINT16[R_IO_L]) +#define RSCAN0RFPTR1LL (RSCAN0.RFPTR1.UINT8[R_IO_LL]) +#define RSCAN0RFPTR1LH (RSCAN0.RFPTR1.UINT8[R_IO_LH]) +#define RSCAN0RFPTR1H (RSCAN0.RFPTR1.UINT16[R_IO_H]) +#define RSCAN0RFPTR1HL (RSCAN0.RFPTR1.UINT8[R_IO_HL]) +#define RSCAN0RFPTR1HH (RSCAN0.RFPTR1.UINT8[R_IO_HH]) +#define RSCAN0RFDF01 (RSCAN0.RFDF01.UINT32) +#define RSCAN0RFDF01L (RSCAN0.RFDF01.UINT16[R_IO_L]) +#define RSCAN0RFDF01LL (RSCAN0.RFDF01.UINT8[R_IO_LL]) +#define RSCAN0RFDF01LH (RSCAN0.RFDF01.UINT8[R_IO_LH]) +#define RSCAN0RFDF01H (RSCAN0.RFDF01.UINT16[R_IO_H]) +#define RSCAN0RFDF01HL (RSCAN0.RFDF01.UINT8[R_IO_HL]) +#define RSCAN0RFDF01HH (RSCAN0.RFDF01.UINT8[R_IO_HH]) +#define RSCAN0RFDF11 (RSCAN0.RFDF11.UINT32) +#define RSCAN0RFDF11L (RSCAN0.RFDF11.UINT16[R_IO_L]) +#define RSCAN0RFDF11LL (RSCAN0.RFDF11.UINT8[R_IO_LL]) +#define RSCAN0RFDF11LH (RSCAN0.RFDF11.UINT8[R_IO_LH]) +#define RSCAN0RFDF11H (RSCAN0.RFDF11.UINT16[R_IO_H]) +#define RSCAN0RFDF11HL (RSCAN0.RFDF11.UINT8[R_IO_HL]) +#define RSCAN0RFDF11HH (RSCAN0.RFDF11.UINT8[R_IO_HH]) +#define RSCAN0RFID2 (RSCAN0.RFID2.UINT32) +#define RSCAN0RFID2L (RSCAN0.RFID2.UINT16[R_IO_L]) +#define RSCAN0RFID2LL (RSCAN0.RFID2.UINT8[R_IO_LL]) +#define RSCAN0RFID2LH (RSCAN0.RFID2.UINT8[R_IO_LH]) +#define RSCAN0RFID2H (RSCAN0.RFID2.UINT16[R_IO_H]) +#define RSCAN0RFID2HL (RSCAN0.RFID2.UINT8[R_IO_HL]) +#define RSCAN0RFID2HH (RSCAN0.RFID2.UINT8[R_IO_HH]) +#define RSCAN0RFPTR2 (RSCAN0.RFPTR2.UINT32) +#define RSCAN0RFPTR2L (RSCAN0.RFPTR2.UINT16[R_IO_L]) +#define RSCAN0RFPTR2LL (RSCAN0.RFPTR2.UINT8[R_IO_LL]) +#define RSCAN0RFPTR2LH (RSCAN0.RFPTR2.UINT8[R_IO_LH]) +#define RSCAN0RFPTR2H (RSCAN0.RFPTR2.UINT16[R_IO_H]) +#define RSCAN0RFPTR2HL (RSCAN0.RFPTR2.UINT8[R_IO_HL]) +#define RSCAN0RFPTR2HH (RSCAN0.RFPTR2.UINT8[R_IO_HH]) +#define RSCAN0RFDF02 (RSCAN0.RFDF02.UINT32) +#define RSCAN0RFDF02L (RSCAN0.RFDF02.UINT16[R_IO_L]) +#define RSCAN0RFDF02LL (RSCAN0.RFDF02.UINT8[R_IO_LL]) +#define RSCAN0RFDF02LH (RSCAN0.RFDF02.UINT8[R_IO_LH]) +#define RSCAN0RFDF02H (RSCAN0.RFDF02.UINT16[R_IO_H]) +#define RSCAN0RFDF02HL (RSCAN0.RFDF02.UINT8[R_IO_HL]) +#define RSCAN0RFDF02HH (RSCAN0.RFDF02.UINT8[R_IO_HH]) +#define RSCAN0RFDF12 (RSCAN0.RFDF12.UINT32) +#define RSCAN0RFDF12L (RSCAN0.RFDF12.UINT16[R_IO_L]) +#define RSCAN0RFDF12LL (RSCAN0.RFDF12.UINT8[R_IO_LL]) +#define RSCAN0RFDF12LH (RSCAN0.RFDF12.UINT8[R_IO_LH]) +#define RSCAN0RFDF12H (RSCAN0.RFDF12.UINT16[R_IO_H]) +#define RSCAN0RFDF12HL (RSCAN0.RFDF12.UINT8[R_IO_HL]) +#define RSCAN0RFDF12HH (RSCAN0.RFDF12.UINT8[R_IO_HH]) +#define RSCAN0RFID3 (RSCAN0.RFID3.UINT32) +#define RSCAN0RFID3L (RSCAN0.RFID3.UINT16[R_IO_L]) +#define RSCAN0RFID3LL (RSCAN0.RFID3.UINT8[R_IO_LL]) +#define RSCAN0RFID3LH (RSCAN0.RFID3.UINT8[R_IO_LH]) +#define RSCAN0RFID3H (RSCAN0.RFID3.UINT16[R_IO_H]) +#define RSCAN0RFID3HL (RSCAN0.RFID3.UINT8[R_IO_HL]) +#define RSCAN0RFID3HH (RSCAN0.RFID3.UINT8[R_IO_HH]) +#define RSCAN0RFPTR3 (RSCAN0.RFPTR3.UINT32) +#define RSCAN0RFPTR3L (RSCAN0.RFPTR3.UINT16[R_IO_L]) +#define RSCAN0RFPTR3LL (RSCAN0.RFPTR3.UINT8[R_IO_LL]) +#define RSCAN0RFPTR3LH (RSCAN0.RFPTR3.UINT8[R_IO_LH]) +#define RSCAN0RFPTR3H (RSCAN0.RFPTR3.UINT16[R_IO_H]) +#define RSCAN0RFPTR3HL (RSCAN0.RFPTR3.UINT8[R_IO_HL]) +#define RSCAN0RFPTR3HH (RSCAN0.RFPTR3.UINT8[R_IO_HH]) +#define RSCAN0RFDF03 (RSCAN0.RFDF03.UINT32) +#define RSCAN0RFDF03L (RSCAN0.RFDF03.UINT16[R_IO_L]) +#define RSCAN0RFDF03LL (RSCAN0.RFDF03.UINT8[R_IO_LL]) +#define RSCAN0RFDF03LH (RSCAN0.RFDF03.UINT8[R_IO_LH]) +#define RSCAN0RFDF03H (RSCAN0.RFDF03.UINT16[R_IO_H]) +#define RSCAN0RFDF03HL (RSCAN0.RFDF03.UINT8[R_IO_HL]) +#define RSCAN0RFDF03HH (RSCAN0.RFDF03.UINT8[R_IO_HH]) +#define RSCAN0RFDF13 (RSCAN0.RFDF13.UINT32) +#define RSCAN0RFDF13L (RSCAN0.RFDF13.UINT16[R_IO_L]) +#define RSCAN0RFDF13LL (RSCAN0.RFDF13.UINT8[R_IO_LL]) +#define RSCAN0RFDF13LH (RSCAN0.RFDF13.UINT8[R_IO_LH]) +#define RSCAN0RFDF13H (RSCAN0.RFDF13.UINT16[R_IO_H]) +#define RSCAN0RFDF13HL (RSCAN0.RFDF13.UINT8[R_IO_HL]) +#define RSCAN0RFDF13HH (RSCAN0.RFDF13.UINT8[R_IO_HH]) +#define RSCAN0RFID4 (RSCAN0.RFID4.UINT32) +#define RSCAN0RFID4L (RSCAN0.RFID4.UINT16[R_IO_L]) +#define RSCAN0RFID4LL (RSCAN0.RFID4.UINT8[R_IO_LL]) +#define RSCAN0RFID4LH (RSCAN0.RFID4.UINT8[R_IO_LH]) +#define RSCAN0RFID4H (RSCAN0.RFID4.UINT16[R_IO_H]) +#define RSCAN0RFID4HL (RSCAN0.RFID4.UINT8[R_IO_HL]) +#define RSCAN0RFID4HH (RSCAN0.RFID4.UINT8[R_IO_HH]) +#define RSCAN0RFPTR4 (RSCAN0.RFPTR4.UINT32) +#define RSCAN0RFPTR4L (RSCAN0.RFPTR4.UINT16[R_IO_L]) +#define RSCAN0RFPTR4LL (RSCAN0.RFPTR4.UINT8[R_IO_LL]) +#define RSCAN0RFPTR4LH (RSCAN0.RFPTR4.UINT8[R_IO_LH]) +#define RSCAN0RFPTR4H (RSCAN0.RFPTR4.UINT16[R_IO_H]) +#define RSCAN0RFPTR4HL (RSCAN0.RFPTR4.UINT8[R_IO_HL]) +#define RSCAN0RFPTR4HH (RSCAN0.RFPTR4.UINT8[R_IO_HH]) +#define RSCAN0RFDF04 (RSCAN0.RFDF04.UINT32) +#define RSCAN0RFDF04L (RSCAN0.RFDF04.UINT16[R_IO_L]) +#define RSCAN0RFDF04LL (RSCAN0.RFDF04.UINT8[R_IO_LL]) +#define RSCAN0RFDF04LH (RSCAN0.RFDF04.UINT8[R_IO_LH]) +#define RSCAN0RFDF04H (RSCAN0.RFDF04.UINT16[R_IO_H]) +#define RSCAN0RFDF04HL (RSCAN0.RFDF04.UINT8[R_IO_HL]) +#define RSCAN0RFDF04HH (RSCAN0.RFDF04.UINT8[R_IO_HH]) +#define RSCAN0RFDF14 (RSCAN0.RFDF14.UINT32) +#define RSCAN0RFDF14L (RSCAN0.RFDF14.UINT16[R_IO_L]) +#define RSCAN0RFDF14LL (RSCAN0.RFDF14.UINT8[R_IO_LL]) +#define RSCAN0RFDF14LH (RSCAN0.RFDF14.UINT8[R_IO_LH]) +#define RSCAN0RFDF14H (RSCAN0.RFDF14.UINT16[R_IO_H]) +#define RSCAN0RFDF14HL (RSCAN0.RFDF14.UINT8[R_IO_HL]) +#define RSCAN0RFDF14HH (RSCAN0.RFDF14.UINT8[R_IO_HH]) +#define RSCAN0RFID5 (RSCAN0.RFID5.UINT32) +#define RSCAN0RFID5L (RSCAN0.RFID5.UINT16[R_IO_L]) +#define RSCAN0RFID5LL (RSCAN0.RFID5.UINT8[R_IO_LL]) +#define RSCAN0RFID5LH (RSCAN0.RFID5.UINT8[R_IO_LH]) +#define RSCAN0RFID5H (RSCAN0.RFID5.UINT16[R_IO_H]) +#define RSCAN0RFID5HL (RSCAN0.RFID5.UINT8[R_IO_HL]) +#define RSCAN0RFID5HH (RSCAN0.RFID5.UINT8[R_IO_HH]) +#define RSCAN0RFPTR5 (RSCAN0.RFPTR5.UINT32) +#define RSCAN0RFPTR5L (RSCAN0.RFPTR5.UINT16[R_IO_L]) +#define RSCAN0RFPTR5LL (RSCAN0.RFPTR5.UINT8[R_IO_LL]) +#define RSCAN0RFPTR5LH (RSCAN0.RFPTR5.UINT8[R_IO_LH]) +#define RSCAN0RFPTR5H (RSCAN0.RFPTR5.UINT16[R_IO_H]) +#define RSCAN0RFPTR5HL (RSCAN0.RFPTR5.UINT8[R_IO_HL]) +#define RSCAN0RFPTR5HH (RSCAN0.RFPTR5.UINT8[R_IO_HH]) +#define RSCAN0RFDF05 (RSCAN0.RFDF05.UINT32) +#define RSCAN0RFDF05L (RSCAN0.RFDF05.UINT16[R_IO_L]) +#define RSCAN0RFDF05LL (RSCAN0.RFDF05.UINT8[R_IO_LL]) +#define RSCAN0RFDF05LH (RSCAN0.RFDF05.UINT8[R_IO_LH]) +#define RSCAN0RFDF05H (RSCAN0.RFDF05.UINT16[R_IO_H]) +#define RSCAN0RFDF05HL (RSCAN0.RFDF05.UINT8[R_IO_HL]) +#define RSCAN0RFDF05HH (RSCAN0.RFDF05.UINT8[R_IO_HH]) +#define RSCAN0RFDF15 (RSCAN0.RFDF15.UINT32) +#define RSCAN0RFDF15L (RSCAN0.RFDF15.UINT16[R_IO_L]) +#define RSCAN0RFDF15LL (RSCAN0.RFDF15.UINT8[R_IO_LL]) +#define RSCAN0RFDF15LH (RSCAN0.RFDF15.UINT8[R_IO_LH]) +#define RSCAN0RFDF15H (RSCAN0.RFDF15.UINT16[R_IO_H]) +#define RSCAN0RFDF15HL (RSCAN0.RFDF15.UINT8[R_IO_HL]) +#define RSCAN0RFDF15HH (RSCAN0.RFDF15.UINT8[R_IO_HH]) +#define RSCAN0RFID6 (RSCAN0.RFID6.UINT32) +#define RSCAN0RFID6L (RSCAN0.RFID6.UINT16[R_IO_L]) +#define RSCAN0RFID6LL (RSCAN0.RFID6.UINT8[R_IO_LL]) +#define RSCAN0RFID6LH (RSCAN0.RFID6.UINT8[R_IO_LH]) +#define RSCAN0RFID6H (RSCAN0.RFID6.UINT16[R_IO_H]) +#define RSCAN0RFID6HL (RSCAN0.RFID6.UINT8[R_IO_HL]) +#define RSCAN0RFID6HH (RSCAN0.RFID6.UINT8[R_IO_HH]) +#define RSCAN0RFPTR6 (RSCAN0.RFPTR6.UINT32) +#define RSCAN0RFPTR6L (RSCAN0.RFPTR6.UINT16[R_IO_L]) +#define RSCAN0RFPTR6LL (RSCAN0.RFPTR6.UINT8[R_IO_LL]) +#define RSCAN0RFPTR6LH (RSCAN0.RFPTR6.UINT8[R_IO_LH]) +#define RSCAN0RFPTR6H (RSCAN0.RFPTR6.UINT16[R_IO_H]) +#define RSCAN0RFPTR6HL (RSCAN0.RFPTR6.UINT8[R_IO_HL]) +#define RSCAN0RFPTR6HH (RSCAN0.RFPTR6.UINT8[R_IO_HH]) +#define RSCAN0RFDF06 (RSCAN0.RFDF06.UINT32) +#define RSCAN0RFDF06L (RSCAN0.RFDF06.UINT16[R_IO_L]) +#define RSCAN0RFDF06LL (RSCAN0.RFDF06.UINT8[R_IO_LL]) +#define RSCAN0RFDF06LH (RSCAN0.RFDF06.UINT8[R_IO_LH]) +#define RSCAN0RFDF06H (RSCAN0.RFDF06.UINT16[R_IO_H]) +#define RSCAN0RFDF06HL (RSCAN0.RFDF06.UINT8[R_IO_HL]) +#define RSCAN0RFDF06HH (RSCAN0.RFDF06.UINT8[R_IO_HH]) +#define RSCAN0RFDF16 (RSCAN0.RFDF16.UINT32) +#define RSCAN0RFDF16L (RSCAN0.RFDF16.UINT16[R_IO_L]) +#define RSCAN0RFDF16LL (RSCAN0.RFDF16.UINT8[R_IO_LL]) +#define RSCAN0RFDF16LH (RSCAN0.RFDF16.UINT8[R_IO_LH]) +#define RSCAN0RFDF16H (RSCAN0.RFDF16.UINT16[R_IO_H]) +#define RSCAN0RFDF16HL (RSCAN0.RFDF16.UINT8[R_IO_HL]) +#define RSCAN0RFDF16HH (RSCAN0.RFDF16.UINT8[R_IO_HH]) +#define RSCAN0RFID7 (RSCAN0.RFID7.UINT32) +#define RSCAN0RFID7L (RSCAN0.RFID7.UINT16[R_IO_L]) +#define RSCAN0RFID7LL (RSCAN0.RFID7.UINT8[R_IO_LL]) +#define RSCAN0RFID7LH (RSCAN0.RFID7.UINT8[R_IO_LH]) +#define RSCAN0RFID7H (RSCAN0.RFID7.UINT16[R_IO_H]) +#define RSCAN0RFID7HL (RSCAN0.RFID7.UINT8[R_IO_HL]) +#define RSCAN0RFID7HH (RSCAN0.RFID7.UINT8[R_IO_HH]) +#define RSCAN0RFPTR7 (RSCAN0.RFPTR7.UINT32) +#define RSCAN0RFPTR7L (RSCAN0.RFPTR7.UINT16[R_IO_L]) +#define RSCAN0RFPTR7LL (RSCAN0.RFPTR7.UINT8[R_IO_LL]) +#define RSCAN0RFPTR7LH (RSCAN0.RFPTR7.UINT8[R_IO_LH]) +#define RSCAN0RFPTR7H (RSCAN0.RFPTR7.UINT16[R_IO_H]) +#define RSCAN0RFPTR7HL (RSCAN0.RFPTR7.UINT8[R_IO_HL]) +#define RSCAN0RFPTR7HH (RSCAN0.RFPTR7.UINT8[R_IO_HH]) +#define RSCAN0RFDF07 (RSCAN0.RFDF07.UINT32) +#define RSCAN0RFDF07L (RSCAN0.RFDF07.UINT16[R_IO_L]) +#define RSCAN0RFDF07LL (RSCAN0.RFDF07.UINT8[R_IO_LL]) +#define RSCAN0RFDF07LH (RSCAN0.RFDF07.UINT8[R_IO_LH]) +#define RSCAN0RFDF07H (RSCAN0.RFDF07.UINT16[R_IO_H]) +#define RSCAN0RFDF07HL (RSCAN0.RFDF07.UINT8[R_IO_HL]) +#define RSCAN0RFDF07HH (RSCAN0.RFDF07.UINT8[R_IO_HH]) +#define RSCAN0RFDF17 (RSCAN0.RFDF17.UINT32) +#define RSCAN0RFDF17L (RSCAN0.RFDF17.UINT16[R_IO_L]) +#define RSCAN0RFDF17LL (RSCAN0.RFDF17.UINT8[R_IO_LL]) +#define RSCAN0RFDF17LH (RSCAN0.RFDF17.UINT8[R_IO_LH]) +#define RSCAN0RFDF17H (RSCAN0.RFDF17.UINT16[R_IO_H]) +#define RSCAN0RFDF17HL (RSCAN0.RFDF17.UINT8[R_IO_HL]) +#define RSCAN0RFDF17HH (RSCAN0.RFDF17.UINT8[R_IO_HH]) +#define RSCAN0CFID0 (RSCAN0.CFID0.UINT32) +#define RSCAN0CFID0L (RSCAN0.CFID0.UINT16[R_IO_L]) +#define RSCAN0CFID0LL (RSCAN0.CFID0.UINT8[R_IO_LL]) +#define RSCAN0CFID0LH (RSCAN0.CFID0.UINT8[R_IO_LH]) +#define RSCAN0CFID0H (RSCAN0.CFID0.UINT16[R_IO_H]) +#define RSCAN0CFID0HL (RSCAN0.CFID0.UINT8[R_IO_HL]) +#define RSCAN0CFID0HH (RSCAN0.CFID0.UINT8[R_IO_HH]) +#define RSCAN0CFPTR0 (RSCAN0.CFPTR0.UINT32) +#define RSCAN0CFPTR0L (RSCAN0.CFPTR0.UINT16[R_IO_L]) +#define RSCAN0CFPTR0LL (RSCAN0.CFPTR0.UINT8[R_IO_LL]) +#define RSCAN0CFPTR0LH (RSCAN0.CFPTR0.UINT8[R_IO_LH]) +#define RSCAN0CFPTR0H (RSCAN0.CFPTR0.UINT16[R_IO_H]) +#define RSCAN0CFPTR0HL (RSCAN0.CFPTR0.UINT8[R_IO_HL]) +#define RSCAN0CFPTR0HH (RSCAN0.CFPTR0.UINT8[R_IO_HH]) +#define RSCAN0CFDF00 (RSCAN0.CFDF00.UINT32) +#define RSCAN0CFDF00L (RSCAN0.CFDF00.UINT16[R_IO_L]) +#define RSCAN0CFDF00LL (RSCAN0.CFDF00.UINT8[R_IO_LL]) +#define RSCAN0CFDF00LH (RSCAN0.CFDF00.UINT8[R_IO_LH]) +#define RSCAN0CFDF00H (RSCAN0.CFDF00.UINT16[R_IO_H]) +#define RSCAN0CFDF00HL (RSCAN0.CFDF00.UINT8[R_IO_HL]) +#define RSCAN0CFDF00HH (RSCAN0.CFDF00.UINT8[R_IO_HH]) +#define RSCAN0CFDF10 (RSCAN0.CFDF10.UINT32) +#define RSCAN0CFDF10L (RSCAN0.CFDF10.UINT16[R_IO_L]) +#define RSCAN0CFDF10LL (RSCAN0.CFDF10.UINT8[R_IO_LL]) +#define RSCAN0CFDF10LH (RSCAN0.CFDF10.UINT8[R_IO_LH]) +#define RSCAN0CFDF10H (RSCAN0.CFDF10.UINT16[R_IO_H]) +#define RSCAN0CFDF10HL (RSCAN0.CFDF10.UINT8[R_IO_HL]) +#define RSCAN0CFDF10HH (RSCAN0.CFDF10.UINT8[R_IO_HH]) +#define RSCAN0CFID1 (RSCAN0.CFID1.UINT32) +#define RSCAN0CFID1L (RSCAN0.CFID1.UINT16[R_IO_L]) +#define RSCAN0CFID1LL (RSCAN0.CFID1.UINT8[R_IO_LL]) +#define RSCAN0CFID1LH (RSCAN0.CFID1.UINT8[R_IO_LH]) +#define RSCAN0CFID1H (RSCAN0.CFID1.UINT16[R_IO_H]) +#define RSCAN0CFID1HL (RSCAN0.CFID1.UINT8[R_IO_HL]) +#define RSCAN0CFID1HH (RSCAN0.CFID1.UINT8[R_IO_HH]) +#define RSCAN0CFPTR1 (RSCAN0.CFPTR1.UINT32) +#define RSCAN0CFPTR1L (RSCAN0.CFPTR1.UINT16[R_IO_L]) +#define RSCAN0CFPTR1LL (RSCAN0.CFPTR1.UINT8[R_IO_LL]) +#define RSCAN0CFPTR1LH (RSCAN0.CFPTR1.UINT8[R_IO_LH]) +#define RSCAN0CFPTR1H (RSCAN0.CFPTR1.UINT16[R_IO_H]) +#define RSCAN0CFPTR1HL (RSCAN0.CFPTR1.UINT8[R_IO_HL]) +#define RSCAN0CFPTR1HH (RSCAN0.CFPTR1.UINT8[R_IO_HH]) +#define RSCAN0CFDF01 (RSCAN0.CFDF01.UINT32) +#define RSCAN0CFDF01L (RSCAN0.CFDF01.UINT16[R_IO_L]) +#define RSCAN0CFDF01LL (RSCAN0.CFDF01.UINT8[R_IO_LL]) +#define RSCAN0CFDF01LH (RSCAN0.CFDF01.UINT8[R_IO_LH]) +#define RSCAN0CFDF01H (RSCAN0.CFDF01.UINT16[R_IO_H]) +#define RSCAN0CFDF01HL (RSCAN0.CFDF01.UINT8[R_IO_HL]) +#define RSCAN0CFDF01HH (RSCAN0.CFDF01.UINT8[R_IO_HH]) +#define RSCAN0CFDF11 (RSCAN0.CFDF11.UINT32) +#define RSCAN0CFDF11L (RSCAN0.CFDF11.UINT16[R_IO_L]) +#define RSCAN0CFDF11LL (RSCAN0.CFDF11.UINT8[R_IO_LL]) +#define RSCAN0CFDF11LH (RSCAN0.CFDF11.UINT8[R_IO_LH]) +#define RSCAN0CFDF11H (RSCAN0.CFDF11.UINT16[R_IO_H]) +#define RSCAN0CFDF11HL (RSCAN0.CFDF11.UINT8[R_IO_HL]) +#define RSCAN0CFDF11HH (RSCAN0.CFDF11.UINT8[R_IO_HH]) +#define RSCAN0CFID2 (RSCAN0.CFID2.UINT32) +#define RSCAN0CFID2L (RSCAN0.CFID2.UINT16[R_IO_L]) +#define RSCAN0CFID2LL (RSCAN0.CFID2.UINT8[R_IO_LL]) +#define RSCAN0CFID2LH (RSCAN0.CFID2.UINT8[R_IO_LH]) +#define RSCAN0CFID2H (RSCAN0.CFID2.UINT16[R_IO_H]) +#define RSCAN0CFID2HL (RSCAN0.CFID2.UINT8[R_IO_HL]) +#define RSCAN0CFID2HH (RSCAN0.CFID2.UINT8[R_IO_HH]) +#define RSCAN0CFPTR2 (RSCAN0.CFPTR2.UINT32) +#define RSCAN0CFPTR2L (RSCAN0.CFPTR2.UINT16[R_IO_L]) +#define RSCAN0CFPTR2LL (RSCAN0.CFPTR2.UINT8[R_IO_LL]) +#define RSCAN0CFPTR2LH (RSCAN0.CFPTR2.UINT8[R_IO_LH]) +#define RSCAN0CFPTR2H (RSCAN0.CFPTR2.UINT16[R_IO_H]) +#define RSCAN0CFPTR2HL (RSCAN0.CFPTR2.UINT8[R_IO_HL]) +#define RSCAN0CFPTR2HH (RSCAN0.CFPTR2.UINT8[R_IO_HH]) +#define RSCAN0CFDF02 (RSCAN0.CFDF02.UINT32) +#define RSCAN0CFDF02L (RSCAN0.CFDF02.UINT16[R_IO_L]) +#define RSCAN0CFDF02LL (RSCAN0.CFDF02.UINT8[R_IO_LL]) +#define RSCAN0CFDF02LH (RSCAN0.CFDF02.UINT8[R_IO_LH]) +#define RSCAN0CFDF02H (RSCAN0.CFDF02.UINT16[R_IO_H]) +#define RSCAN0CFDF02HL (RSCAN0.CFDF02.UINT8[R_IO_HL]) +#define RSCAN0CFDF02HH (RSCAN0.CFDF02.UINT8[R_IO_HH]) +#define RSCAN0CFDF12 (RSCAN0.CFDF12.UINT32) +#define RSCAN0CFDF12L (RSCAN0.CFDF12.UINT16[R_IO_L]) +#define RSCAN0CFDF12LL (RSCAN0.CFDF12.UINT8[R_IO_LL]) +#define RSCAN0CFDF12LH (RSCAN0.CFDF12.UINT8[R_IO_LH]) +#define RSCAN0CFDF12H (RSCAN0.CFDF12.UINT16[R_IO_H]) +#define RSCAN0CFDF12HL (RSCAN0.CFDF12.UINT8[R_IO_HL]) +#define RSCAN0CFDF12HH (RSCAN0.CFDF12.UINT8[R_IO_HH]) +#define RSCAN0CFID3 (RSCAN0.CFID3.UINT32) +#define RSCAN0CFID3L (RSCAN0.CFID3.UINT16[R_IO_L]) +#define RSCAN0CFID3LL (RSCAN0.CFID3.UINT8[R_IO_LL]) +#define RSCAN0CFID3LH (RSCAN0.CFID3.UINT8[R_IO_LH]) +#define RSCAN0CFID3H (RSCAN0.CFID3.UINT16[R_IO_H]) +#define RSCAN0CFID3HL (RSCAN0.CFID3.UINT8[R_IO_HL]) +#define RSCAN0CFID3HH (RSCAN0.CFID3.UINT8[R_IO_HH]) +#define RSCAN0CFPTR3 (RSCAN0.CFPTR3.UINT32) +#define RSCAN0CFPTR3L (RSCAN0.CFPTR3.UINT16[R_IO_L]) +#define RSCAN0CFPTR3LL (RSCAN0.CFPTR3.UINT8[R_IO_LL]) +#define RSCAN0CFPTR3LH (RSCAN0.CFPTR3.UINT8[R_IO_LH]) +#define RSCAN0CFPTR3H (RSCAN0.CFPTR3.UINT16[R_IO_H]) +#define RSCAN0CFPTR3HL (RSCAN0.CFPTR3.UINT8[R_IO_HL]) +#define RSCAN0CFPTR3HH (RSCAN0.CFPTR3.UINT8[R_IO_HH]) +#define RSCAN0CFDF03 (RSCAN0.CFDF03.UINT32) +#define RSCAN0CFDF03L (RSCAN0.CFDF03.UINT16[R_IO_L]) +#define RSCAN0CFDF03LL (RSCAN0.CFDF03.UINT8[R_IO_LL]) +#define RSCAN0CFDF03LH (RSCAN0.CFDF03.UINT8[R_IO_LH]) +#define RSCAN0CFDF03H (RSCAN0.CFDF03.UINT16[R_IO_H]) +#define RSCAN0CFDF03HL (RSCAN0.CFDF03.UINT8[R_IO_HL]) +#define RSCAN0CFDF03HH (RSCAN0.CFDF03.UINT8[R_IO_HH]) +#define RSCAN0CFDF13 (RSCAN0.CFDF13.UINT32) +#define RSCAN0CFDF13L (RSCAN0.CFDF13.UINT16[R_IO_L]) +#define RSCAN0CFDF13LL (RSCAN0.CFDF13.UINT8[R_IO_LL]) +#define RSCAN0CFDF13LH (RSCAN0.CFDF13.UINT8[R_IO_LH]) +#define RSCAN0CFDF13H (RSCAN0.CFDF13.UINT16[R_IO_H]) +#define RSCAN0CFDF13HL (RSCAN0.CFDF13.UINT8[R_IO_HL]) +#define RSCAN0CFDF13HH (RSCAN0.CFDF13.UINT8[R_IO_HH]) +#define RSCAN0CFID4 (RSCAN0.CFID4.UINT32) +#define RSCAN0CFID4L (RSCAN0.CFID4.UINT16[R_IO_L]) +#define RSCAN0CFID4LL (RSCAN0.CFID4.UINT8[R_IO_LL]) +#define RSCAN0CFID4LH (RSCAN0.CFID4.UINT8[R_IO_LH]) +#define RSCAN0CFID4H (RSCAN0.CFID4.UINT16[R_IO_H]) +#define RSCAN0CFID4HL (RSCAN0.CFID4.UINT8[R_IO_HL]) +#define RSCAN0CFID4HH (RSCAN0.CFID4.UINT8[R_IO_HH]) +#define RSCAN0CFPTR4 (RSCAN0.CFPTR4.UINT32) +#define RSCAN0CFPTR4L (RSCAN0.CFPTR4.UINT16[R_IO_L]) +#define RSCAN0CFPTR4LL (RSCAN0.CFPTR4.UINT8[R_IO_LL]) +#define RSCAN0CFPTR4LH (RSCAN0.CFPTR4.UINT8[R_IO_LH]) +#define RSCAN0CFPTR4H (RSCAN0.CFPTR4.UINT16[R_IO_H]) +#define RSCAN0CFPTR4HL (RSCAN0.CFPTR4.UINT8[R_IO_HL]) +#define RSCAN0CFPTR4HH (RSCAN0.CFPTR4.UINT8[R_IO_HH]) +#define RSCAN0CFDF04 (RSCAN0.CFDF04.UINT32) +#define RSCAN0CFDF04L (RSCAN0.CFDF04.UINT16[R_IO_L]) +#define RSCAN0CFDF04LL (RSCAN0.CFDF04.UINT8[R_IO_LL]) +#define RSCAN0CFDF04LH (RSCAN0.CFDF04.UINT8[R_IO_LH]) +#define RSCAN0CFDF04H (RSCAN0.CFDF04.UINT16[R_IO_H]) +#define RSCAN0CFDF04HL (RSCAN0.CFDF04.UINT8[R_IO_HL]) +#define RSCAN0CFDF04HH (RSCAN0.CFDF04.UINT8[R_IO_HH]) +#define RSCAN0CFDF14 (RSCAN0.CFDF14.UINT32) +#define RSCAN0CFDF14L (RSCAN0.CFDF14.UINT16[R_IO_L]) +#define RSCAN0CFDF14LL (RSCAN0.CFDF14.UINT8[R_IO_LL]) +#define RSCAN0CFDF14LH (RSCAN0.CFDF14.UINT8[R_IO_LH]) +#define RSCAN0CFDF14H (RSCAN0.CFDF14.UINT16[R_IO_H]) +#define RSCAN0CFDF14HL (RSCAN0.CFDF14.UINT8[R_IO_HL]) +#define RSCAN0CFDF14HH (RSCAN0.CFDF14.UINT8[R_IO_HH]) +#define RSCAN0CFID5 (RSCAN0.CFID5.UINT32) +#define RSCAN0CFID5L (RSCAN0.CFID5.UINT16[R_IO_L]) +#define RSCAN0CFID5LL (RSCAN0.CFID5.UINT8[R_IO_LL]) +#define RSCAN0CFID5LH (RSCAN0.CFID5.UINT8[R_IO_LH]) +#define RSCAN0CFID5H (RSCAN0.CFID5.UINT16[R_IO_H]) +#define RSCAN0CFID5HL (RSCAN0.CFID5.UINT8[R_IO_HL]) +#define RSCAN0CFID5HH (RSCAN0.CFID5.UINT8[R_IO_HH]) +#define RSCAN0CFPTR5 (RSCAN0.CFPTR5.UINT32) +#define RSCAN0CFPTR5L (RSCAN0.CFPTR5.UINT16[R_IO_L]) +#define RSCAN0CFPTR5LL (RSCAN0.CFPTR5.UINT8[R_IO_LL]) +#define RSCAN0CFPTR5LH (RSCAN0.CFPTR5.UINT8[R_IO_LH]) +#define RSCAN0CFPTR5H (RSCAN0.CFPTR5.UINT16[R_IO_H]) +#define RSCAN0CFPTR5HL (RSCAN0.CFPTR5.UINT8[R_IO_HL]) +#define RSCAN0CFPTR5HH (RSCAN0.CFPTR5.UINT8[R_IO_HH]) +#define RSCAN0CFDF05 (RSCAN0.CFDF05.UINT32) +#define RSCAN0CFDF05L (RSCAN0.CFDF05.UINT16[R_IO_L]) +#define RSCAN0CFDF05LL (RSCAN0.CFDF05.UINT8[R_IO_LL]) +#define RSCAN0CFDF05LH (RSCAN0.CFDF05.UINT8[R_IO_LH]) +#define RSCAN0CFDF05H (RSCAN0.CFDF05.UINT16[R_IO_H]) +#define RSCAN0CFDF05HL (RSCAN0.CFDF05.UINT8[R_IO_HL]) +#define RSCAN0CFDF05HH (RSCAN0.CFDF05.UINT8[R_IO_HH]) +#define RSCAN0CFDF15 (RSCAN0.CFDF15.UINT32) +#define RSCAN0CFDF15L (RSCAN0.CFDF15.UINT16[R_IO_L]) +#define RSCAN0CFDF15LL (RSCAN0.CFDF15.UINT8[R_IO_LL]) +#define RSCAN0CFDF15LH (RSCAN0.CFDF15.UINT8[R_IO_LH]) +#define RSCAN0CFDF15H (RSCAN0.CFDF15.UINT16[R_IO_H]) +#define RSCAN0CFDF15HL (RSCAN0.CFDF15.UINT8[R_IO_HL]) +#define RSCAN0CFDF15HH (RSCAN0.CFDF15.UINT8[R_IO_HH]) +#define RSCAN0TMID0 (RSCAN0.TMID0.UINT32) +#define RSCAN0TMID0L (RSCAN0.TMID0.UINT16[R_IO_L]) +#define RSCAN0TMID0LL (RSCAN0.TMID0.UINT8[R_IO_LL]) +#define RSCAN0TMID0LH (RSCAN0.TMID0.UINT8[R_IO_LH]) +#define RSCAN0TMID0H (RSCAN0.TMID0.UINT16[R_IO_H]) +#define RSCAN0TMID0HL (RSCAN0.TMID0.UINT8[R_IO_HL]) +#define RSCAN0TMID0HH (RSCAN0.TMID0.UINT8[R_IO_HH]) +#define RSCAN0TMPTR0 (RSCAN0.TMPTR0.UINT32) +#define RSCAN0TMPTR0L (RSCAN0.TMPTR0.UINT16[R_IO_L]) +#define RSCAN0TMPTR0LL (RSCAN0.TMPTR0.UINT8[R_IO_LL]) +#define RSCAN0TMPTR0LH (RSCAN0.TMPTR0.UINT8[R_IO_LH]) +#define RSCAN0TMPTR0H (RSCAN0.TMPTR0.UINT16[R_IO_H]) +#define RSCAN0TMPTR0HL (RSCAN0.TMPTR0.UINT8[R_IO_HL]) +#define RSCAN0TMPTR0HH (RSCAN0.TMPTR0.UINT8[R_IO_HH]) +#define RSCAN0TMDF00 (RSCAN0.TMDF00.UINT32) +#define RSCAN0TMDF00L (RSCAN0.TMDF00.UINT16[R_IO_L]) +#define RSCAN0TMDF00LL (RSCAN0.TMDF00.UINT8[R_IO_LL]) +#define RSCAN0TMDF00LH (RSCAN0.TMDF00.UINT8[R_IO_LH]) +#define RSCAN0TMDF00H (RSCAN0.TMDF00.UINT16[R_IO_H]) +#define RSCAN0TMDF00HL (RSCAN0.TMDF00.UINT8[R_IO_HL]) +#define RSCAN0TMDF00HH (RSCAN0.TMDF00.UINT8[R_IO_HH]) +#define RSCAN0TMDF10 (RSCAN0.TMDF10.UINT32) +#define RSCAN0TMDF10L (RSCAN0.TMDF10.UINT16[R_IO_L]) +#define RSCAN0TMDF10LL (RSCAN0.TMDF10.UINT8[R_IO_LL]) +#define RSCAN0TMDF10LH (RSCAN0.TMDF10.UINT8[R_IO_LH]) +#define RSCAN0TMDF10H (RSCAN0.TMDF10.UINT16[R_IO_H]) +#define RSCAN0TMDF10HL (RSCAN0.TMDF10.UINT8[R_IO_HL]) +#define RSCAN0TMDF10HH (RSCAN0.TMDF10.UINT8[R_IO_HH]) +#define RSCAN0TMID1 (RSCAN0.TMID1.UINT32) +#define RSCAN0TMID1L (RSCAN0.TMID1.UINT16[R_IO_L]) +#define RSCAN0TMID1LL (RSCAN0.TMID1.UINT8[R_IO_LL]) +#define RSCAN0TMID1LH (RSCAN0.TMID1.UINT8[R_IO_LH]) +#define RSCAN0TMID1H (RSCAN0.TMID1.UINT16[R_IO_H]) +#define RSCAN0TMID1HL (RSCAN0.TMID1.UINT8[R_IO_HL]) +#define RSCAN0TMID1HH (RSCAN0.TMID1.UINT8[R_IO_HH]) +#define RSCAN0TMPTR1 (RSCAN0.TMPTR1.UINT32) +#define RSCAN0TMPTR1L (RSCAN0.TMPTR1.UINT16[R_IO_L]) +#define RSCAN0TMPTR1LL (RSCAN0.TMPTR1.UINT8[R_IO_LL]) +#define RSCAN0TMPTR1LH (RSCAN0.TMPTR1.UINT8[R_IO_LH]) +#define RSCAN0TMPTR1H (RSCAN0.TMPTR1.UINT16[R_IO_H]) +#define RSCAN0TMPTR1HL (RSCAN0.TMPTR1.UINT8[R_IO_HL]) +#define RSCAN0TMPTR1HH (RSCAN0.TMPTR1.UINT8[R_IO_HH]) +#define RSCAN0TMDF01 (RSCAN0.TMDF01.UINT32) +#define RSCAN0TMDF01L (RSCAN0.TMDF01.UINT16[R_IO_L]) +#define RSCAN0TMDF01LL (RSCAN0.TMDF01.UINT8[R_IO_LL]) +#define RSCAN0TMDF01LH (RSCAN0.TMDF01.UINT8[R_IO_LH]) +#define RSCAN0TMDF01H (RSCAN0.TMDF01.UINT16[R_IO_H]) +#define RSCAN0TMDF01HL (RSCAN0.TMDF01.UINT8[R_IO_HL]) +#define RSCAN0TMDF01HH (RSCAN0.TMDF01.UINT8[R_IO_HH]) +#define RSCAN0TMDF11 (RSCAN0.TMDF11.UINT32) +#define RSCAN0TMDF11L (RSCAN0.TMDF11.UINT16[R_IO_L]) +#define RSCAN0TMDF11LL (RSCAN0.TMDF11.UINT8[R_IO_LL]) +#define RSCAN0TMDF11LH (RSCAN0.TMDF11.UINT8[R_IO_LH]) +#define RSCAN0TMDF11H (RSCAN0.TMDF11.UINT16[R_IO_H]) +#define RSCAN0TMDF11HL (RSCAN0.TMDF11.UINT8[R_IO_HL]) +#define RSCAN0TMDF11HH (RSCAN0.TMDF11.UINT8[R_IO_HH]) +#define RSCAN0TMID2 (RSCAN0.TMID2.UINT32) +#define RSCAN0TMID2L (RSCAN0.TMID2.UINT16[R_IO_L]) +#define RSCAN0TMID2LL (RSCAN0.TMID2.UINT8[R_IO_LL]) +#define RSCAN0TMID2LH (RSCAN0.TMID2.UINT8[R_IO_LH]) +#define RSCAN0TMID2H (RSCAN0.TMID2.UINT16[R_IO_H]) +#define RSCAN0TMID2HL (RSCAN0.TMID2.UINT8[R_IO_HL]) +#define RSCAN0TMID2HH (RSCAN0.TMID2.UINT8[R_IO_HH]) +#define RSCAN0TMPTR2 (RSCAN0.TMPTR2.UINT32) +#define RSCAN0TMPTR2L (RSCAN0.TMPTR2.UINT16[R_IO_L]) +#define RSCAN0TMPTR2LL (RSCAN0.TMPTR2.UINT8[R_IO_LL]) +#define RSCAN0TMPTR2LH (RSCAN0.TMPTR2.UINT8[R_IO_LH]) +#define RSCAN0TMPTR2H (RSCAN0.TMPTR2.UINT16[R_IO_H]) +#define RSCAN0TMPTR2HL (RSCAN0.TMPTR2.UINT8[R_IO_HL]) +#define RSCAN0TMPTR2HH (RSCAN0.TMPTR2.UINT8[R_IO_HH]) +#define RSCAN0TMDF02 (RSCAN0.TMDF02.UINT32) +#define RSCAN0TMDF02L (RSCAN0.TMDF02.UINT16[R_IO_L]) +#define RSCAN0TMDF02LL (RSCAN0.TMDF02.UINT8[R_IO_LL]) +#define RSCAN0TMDF02LH (RSCAN0.TMDF02.UINT8[R_IO_LH]) +#define RSCAN0TMDF02H (RSCAN0.TMDF02.UINT16[R_IO_H]) +#define RSCAN0TMDF02HL (RSCAN0.TMDF02.UINT8[R_IO_HL]) +#define RSCAN0TMDF02HH (RSCAN0.TMDF02.UINT8[R_IO_HH]) +#define RSCAN0TMDF12 (RSCAN0.TMDF12.UINT32) +#define RSCAN0TMDF12L (RSCAN0.TMDF12.UINT16[R_IO_L]) +#define RSCAN0TMDF12LL (RSCAN0.TMDF12.UINT8[R_IO_LL]) +#define RSCAN0TMDF12LH (RSCAN0.TMDF12.UINT8[R_IO_LH]) +#define RSCAN0TMDF12H (RSCAN0.TMDF12.UINT16[R_IO_H]) +#define RSCAN0TMDF12HL (RSCAN0.TMDF12.UINT8[R_IO_HL]) +#define RSCAN0TMDF12HH (RSCAN0.TMDF12.UINT8[R_IO_HH]) +#define RSCAN0TMID3 (RSCAN0.TMID3.UINT32) +#define RSCAN0TMID3L (RSCAN0.TMID3.UINT16[R_IO_L]) +#define RSCAN0TMID3LL (RSCAN0.TMID3.UINT8[R_IO_LL]) +#define RSCAN0TMID3LH (RSCAN0.TMID3.UINT8[R_IO_LH]) +#define RSCAN0TMID3H (RSCAN0.TMID3.UINT16[R_IO_H]) +#define RSCAN0TMID3HL (RSCAN0.TMID3.UINT8[R_IO_HL]) +#define RSCAN0TMID3HH (RSCAN0.TMID3.UINT8[R_IO_HH]) +#define RSCAN0TMPTR3 (RSCAN0.TMPTR3.UINT32) +#define RSCAN0TMPTR3L (RSCAN0.TMPTR3.UINT16[R_IO_L]) +#define RSCAN0TMPTR3LL (RSCAN0.TMPTR3.UINT8[R_IO_LL]) +#define RSCAN0TMPTR3LH (RSCAN0.TMPTR3.UINT8[R_IO_LH]) +#define RSCAN0TMPTR3H (RSCAN0.TMPTR3.UINT16[R_IO_H]) +#define RSCAN0TMPTR3HL (RSCAN0.TMPTR3.UINT8[R_IO_HL]) +#define RSCAN0TMPTR3HH (RSCAN0.TMPTR3.UINT8[R_IO_HH]) +#define RSCAN0TMDF03 (RSCAN0.TMDF03.UINT32) +#define RSCAN0TMDF03L (RSCAN0.TMDF03.UINT16[R_IO_L]) +#define RSCAN0TMDF03LL (RSCAN0.TMDF03.UINT8[R_IO_LL]) +#define RSCAN0TMDF03LH (RSCAN0.TMDF03.UINT8[R_IO_LH]) +#define RSCAN0TMDF03H (RSCAN0.TMDF03.UINT16[R_IO_H]) +#define RSCAN0TMDF03HL (RSCAN0.TMDF03.UINT8[R_IO_HL]) +#define RSCAN0TMDF03HH (RSCAN0.TMDF03.UINT8[R_IO_HH]) +#define RSCAN0TMDF13 (RSCAN0.TMDF13.UINT32) +#define RSCAN0TMDF13L (RSCAN0.TMDF13.UINT16[R_IO_L]) +#define RSCAN0TMDF13LL (RSCAN0.TMDF13.UINT8[R_IO_LL]) +#define RSCAN0TMDF13LH (RSCAN0.TMDF13.UINT8[R_IO_LH]) +#define RSCAN0TMDF13H (RSCAN0.TMDF13.UINT16[R_IO_H]) +#define RSCAN0TMDF13HL (RSCAN0.TMDF13.UINT8[R_IO_HL]) +#define RSCAN0TMDF13HH (RSCAN0.TMDF13.UINT8[R_IO_HH]) +#define RSCAN0TMID4 (RSCAN0.TMID4.UINT32) +#define RSCAN0TMID4L (RSCAN0.TMID4.UINT16[R_IO_L]) +#define RSCAN0TMID4LL (RSCAN0.TMID4.UINT8[R_IO_LL]) +#define RSCAN0TMID4LH (RSCAN0.TMID4.UINT8[R_IO_LH]) +#define RSCAN0TMID4H (RSCAN0.TMID4.UINT16[R_IO_H]) +#define RSCAN0TMID4HL (RSCAN0.TMID4.UINT8[R_IO_HL]) +#define RSCAN0TMID4HH (RSCAN0.TMID4.UINT8[R_IO_HH]) +#define RSCAN0TMPTR4 (RSCAN0.TMPTR4.UINT32) +#define RSCAN0TMPTR4L (RSCAN0.TMPTR4.UINT16[R_IO_L]) +#define RSCAN0TMPTR4LL (RSCAN0.TMPTR4.UINT8[R_IO_LL]) +#define RSCAN0TMPTR4LH (RSCAN0.TMPTR4.UINT8[R_IO_LH]) +#define RSCAN0TMPTR4H (RSCAN0.TMPTR4.UINT16[R_IO_H]) +#define RSCAN0TMPTR4HL (RSCAN0.TMPTR4.UINT8[R_IO_HL]) +#define RSCAN0TMPTR4HH (RSCAN0.TMPTR4.UINT8[R_IO_HH]) +#define RSCAN0TMDF04 (RSCAN0.TMDF04.UINT32) +#define RSCAN0TMDF04L (RSCAN0.TMDF04.UINT16[R_IO_L]) +#define RSCAN0TMDF04LL (RSCAN0.TMDF04.UINT8[R_IO_LL]) +#define RSCAN0TMDF04LH (RSCAN0.TMDF04.UINT8[R_IO_LH]) +#define RSCAN0TMDF04H (RSCAN0.TMDF04.UINT16[R_IO_H]) +#define RSCAN0TMDF04HL (RSCAN0.TMDF04.UINT8[R_IO_HL]) +#define RSCAN0TMDF04HH (RSCAN0.TMDF04.UINT8[R_IO_HH]) +#define RSCAN0TMDF14 (RSCAN0.TMDF14.UINT32) +#define RSCAN0TMDF14L (RSCAN0.TMDF14.UINT16[R_IO_L]) +#define RSCAN0TMDF14LL (RSCAN0.TMDF14.UINT8[R_IO_LL]) +#define RSCAN0TMDF14LH (RSCAN0.TMDF14.UINT8[R_IO_LH]) +#define RSCAN0TMDF14H (RSCAN0.TMDF14.UINT16[R_IO_H]) +#define RSCAN0TMDF14HL (RSCAN0.TMDF14.UINT8[R_IO_HL]) +#define RSCAN0TMDF14HH (RSCAN0.TMDF14.UINT8[R_IO_HH]) +#define RSCAN0TMID5 (RSCAN0.TMID5.UINT32) +#define RSCAN0TMID5L (RSCAN0.TMID5.UINT16[R_IO_L]) +#define RSCAN0TMID5LL (RSCAN0.TMID5.UINT8[R_IO_LL]) +#define RSCAN0TMID5LH (RSCAN0.TMID5.UINT8[R_IO_LH]) +#define RSCAN0TMID5H (RSCAN0.TMID5.UINT16[R_IO_H]) +#define RSCAN0TMID5HL (RSCAN0.TMID5.UINT8[R_IO_HL]) +#define RSCAN0TMID5HH (RSCAN0.TMID5.UINT8[R_IO_HH]) +#define RSCAN0TMPTR5 (RSCAN0.TMPTR5.UINT32) +#define RSCAN0TMPTR5L (RSCAN0.TMPTR5.UINT16[R_IO_L]) +#define RSCAN0TMPTR5LL (RSCAN0.TMPTR5.UINT8[R_IO_LL]) +#define RSCAN0TMPTR5LH (RSCAN0.TMPTR5.UINT8[R_IO_LH]) +#define RSCAN0TMPTR5H (RSCAN0.TMPTR5.UINT16[R_IO_H]) +#define RSCAN0TMPTR5HL (RSCAN0.TMPTR5.UINT8[R_IO_HL]) +#define RSCAN0TMPTR5HH (RSCAN0.TMPTR5.UINT8[R_IO_HH]) +#define RSCAN0TMDF05 (RSCAN0.TMDF05.UINT32) +#define RSCAN0TMDF05L (RSCAN0.TMDF05.UINT16[R_IO_L]) +#define RSCAN0TMDF05LL (RSCAN0.TMDF05.UINT8[R_IO_LL]) +#define RSCAN0TMDF05LH (RSCAN0.TMDF05.UINT8[R_IO_LH]) +#define RSCAN0TMDF05H (RSCAN0.TMDF05.UINT16[R_IO_H]) +#define RSCAN0TMDF05HL (RSCAN0.TMDF05.UINT8[R_IO_HL]) +#define RSCAN0TMDF05HH (RSCAN0.TMDF05.UINT8[R_IO_HH]) +#define RSCAN0TMDF15 (RSCAN0.TMDF15.UINT32) +#define RSCAN0TMDF15L (RSCAN0.TMDF15.UINT16[R_IO_L]) +#define RSCAN0TMDF15LL (RSCAN0.TMDF15.UINT8[R_IO_LL]) +#define RSCAN0TMDF15LH (RSCAN0.TMDF15.UINT8[R_IO_LH]) +#define RSCAN0TMDF15H (RSCAN0.TMDF15.UINT16[R_IO_H]) +#define RSCAN0TMDF15HL (RSCAN0.TMDF15.UINT8[R_IO_HL]) +#define RSCAN0TMDF15HH (RSCAN0.TMDF15.UINT8[R_IO_HH]) +#define RSCAN0TMID6 (RSCAN0.TMID6.UINT32) +#define RSCAN0TMID6L (RSCAN0.TMID6.UINT16[R_IO_L]) +#define RSCAN0TMID6LL (RSCAN0.TMID6.UINT8[R_IO_LL]) +#define RSCAN0TMID6LH (RSCAN0.TMID6.UINT8[R_IO_LH]) +#define RSCAN0TMID6H (RSCAN0.TMID6.UINT16[R_IO_H]) +#define RSCAN0TMID6HL (RSCAN0.TMID6.UINT8[R_IO_HL]) +#define RSCAN0TMID6HH (RSCAN0.TMID6.UINT8[R_IO_HH]) +#define RSCAN0TMPTR6 (RSCAN0.TMPTR6.UINT32) +#define RSCAN0TMPTR6L (RSCAN0.TMPTR6.UINT16[R_IO_L]) +#define RSCAN0TMPTR6LL (RSCAN0.TMPTR6.UINT8[R_IO_LL]) +#define RSCAN0TMPTR6LH (RSCAN0.TMPTR6.UINT8[R_IO_LH]) +#define RSCAN0TMPTR6H (RSCAN0.TMPTR6.UINT16[R_IO_H]) +#define RSCAN0TMPTR6HL (RSCAN0.TMPTR6.UINT8[R_IO_HL]) +#define RSCAN0TMPTR6HH (RSCAN0.TMPTR6.UINT8[R_IO_HH]) +#define RSCAN0TMDF06 (RSCAN0.TMDF06.UINT32) +#define RSCAN0TMDF06L (RSCAN0.TMDF06.UINT16[R_IO_L]) +#define RSCAN0TMDF06LL (RSCAN0.TMDF06.UINT8[R_IO_LL]) +#define RSCAN0TMDF06LH (RSCAN0.TMDF06.UINT8[R_IO_LH]) +#define RSCAN0TMDF06H (RSCAN0.TMDF06.UINT16[R_IO_H]) +#define RSCAN0TMDF06HL (RSCAN0.TMDF06.UINT8[R_IO_HL]) +#define RSCAN0TMDF06HH (RSCAN0.TMDF06.UINT8[R_IO_HH]) +#define RSCAN0TMDF16 (RSCAN0.TMDF16.UINT32) +#define RSCAN0TMDF16L (RSCAN0.TMDF16.UINT16[R_IO_L]) +#define RSCAN0TMDF16LL (RSCAN0.TMDF16.UINT8[R_IO_LL]) +#define RSCAN0TMDF16LH (RSCAN0.TMDF16.UINT8[R_IO_LH]) +#define RSCAN0TMDF16H (RSCAN0.TMDF16.UINT16[R_IO_H]) +#define RSCAN0TMDF16HL (RSCAN0.TMDF16.UINT8[R_IO_HL]) +#define RSCAN0TMDF16HH (RSCAN0.TMDF16.UINT8[R_IO_HH]) +#define RSCAN0TMID7 (RSCAN0.TMID7.UINT32) +#define RSCAN0TMID7L (RSCAN0.TMID7.UINT16[R_IO_L]) +#define RSCAN0TMID7LL (RSCAN0.TMID7.UINT8[R_IO_LL]) +#define RSCAN0TMID7LH (RSCAN0.TMID7.UINT8[R_IO_LH]) +#define RSCAN0TMID7H (RSCAN0.TMID7.UINT16[R_IO_H]) +#define RSCAN0TMID7HL (RSCAN0.TMID7.UINT8[R_IO_HL]) +#define RSCAN0TMID7HH (RSCAN0.TMID7.UINT8[R_IO_HH]) +#define RSCAN0TMPTR7 (RSCAN0.TMPTR7.UINT32) +#define RSCAN0TMPTR7L (RSCAN0.TMPTR7.UINT16[R_IO_L]) +#define RSCAN0TMPTR7LL (RSCAN0.TMPTR7.UINT8[R_IO_LL]) +#define RSCAN0TMPTR7LH (RSCAN0.TMPTR7.UINT8[R_IO_LH]) +#define RSCAN0TMPTR7H (RSCAN0.TMPTR7.UINT16[R_IO_H]) +#define RSCAN0TMPTR7HL (RSCAN0.TMPTR7.UINT8[R_IO_HL]) +#define RSCAN0TMPTR7HH (RSCAN0.TMPTR7.UINT8[R_IO_HH]) +#define RSCAN0TMDF07 (RSCAN0.TMDF07.UINT32) +#define RSCAN0TMDF07L (RSCAN0.TMDF07.UINT16[R_IO_L]) +#define RSCAN0TMDF07LL (RSCAN0.TMDF07.UINT8[R_IO_LL]) +#define RSCAN0TMDF07LH (RSCAN0.TMDF07.UINT8[R_IO_LH]) +#define RSCAN0TMDF07H (RSCAN0.TMDF07.UINT16[R_IO_H]) +#define RSCAN0TMDF07HL (RSCAN0.TMDF07.UINT8[R_IO_HL]) +#define RSCAN0TMDF07HH (RSCAN0.TMDF07.UINT8[R_IO_HH]) +#define RSCAN0TMDF17 (RSCAN0.TMDF17.UINT32) +#define RSCAN0TMDF17L (RSCAN0.TMDF17.UINT16[R_IO_L]) +#define RSCAN0TMDF17LL (RSCAN0.TMDF17.UINT8[R_IO_LL]) +#define RSCAN0TMDF17LH (RSCAN0.TMDF17.UINT8[R_IO_LH]) +#define RSCAN0TMDF17H (RSCAN0.TMDF17.UINT16[R_IO_H]) +#define RSCAN0TMDF17HL (RSCAN0.TMDF17.UINT8[R_IO_HL]) +#define RSCAN0TMDF17HH (RSCAN0.TMDF17.UINT8[R_IO_HH]) +#define RSCAN0TMID8 (RSCAN0.TMID8.UINT32) +#define RSCAN0TMID8L (RSCAN0.TMID8.UINT16[R_IO_L]) +#define RSCAN0TMID8LL (RSCAN0.TMID8.UINT8[R_IO_LL]) +#define RSCAN0TMID8LH (RSCAN0.TMID8.UINT8[R_IO_LH]) +#define RSCAN0TMID8H (RSCAN0.TMID8.UINT16[R_IO_H]) +#define RSCAN0TMID8HL (RSCAN0.TMID8.UINT8[R_IO_HL]) +#define RSCAN0TMID8HH (RSCAN0.TMID8.UINT8[R_IO_HH]) +#define RSCAN0TMPTR8 (RSCAN0.TMPTR8.UINT32) +#define RSCAN0TMPTR8L (RSCAN0.TMPTR8.UINT16[R_IO_L]) +#define RSCAN0TMPTR8LL (RSCAN0.TMPTR8.UINT8[R_IO_LL]) +#define RSCAN0TMPTR8LH (RSCAN0.TMPTR8.UINT8[R_IO_LH]) +#define RSCAN0TMPTR8H (RSCAN0.TMPTR8.UINT16[R_IO_H]) +#define RSCAN0TMPTR8HL (RSCAN0.TMPTR8.UINT8[R_IO_HL]) +#define RSCAN0TMPTR8HH (RSCAN0.TMPTR8.UINT8[R_IO_HH]) +#define RSCAN0TMDF08 (RSCAN0.TMDF08.UINT32) +#define RSCAN0TMDF08L (RSCAN0.TMDF08.UINT16[R_IO_L]) +#define RSCAN0TMDF08LL (RSCAN0.TMDF08.UINT8[R_IO_LL]) +#define RSCAN0TMDF08LH (RSCAN0.TMDF08.UINT8[R_IO_LH]) +#define RSCAN0TMDF08H (RSCAN0.TMDF08.UINT16[R_IO_H]) +#define RSCAN0TMDF08HL (RSCAN0.TMDF08.UINT8[R_IO_HL]) +#define RSCAN0TMDF08HH (RSCAN0.TMDF08.UINT8[R_IO_HH]) +#define RSCAN0TMDF18 (RSCAN0.TMDF18.UINT32) +#define RSCAN0TMDF18L (RSCAN0.TMDF18.UINT16[R_IO_L]) +#define RSCAN0TMDF18LL (RSCAN0.TMDF18.UINT8[R_IO_LL]) +#define RSCAN0TMDF18LH (RSCAN0.TMDF18.UINT8[R_IO_LH]) +#define RSCAN0TMDF18H (RSCAN0.TMDF18.UINT16[R_IO_H]) +#define RSCAN0TMDF18HL (RSCAN0.TMDF18.UINT8[R_IO_HL]) +#define RSCAN0TMDF18HH (RSCAN0.TMDF18.UINT8[R_IO_HH]) +#define RSCAN0TMID9 (RSCAN0.TMID9.UINT32) +#define RSCAN0TMID9L (RSCAN0.TMID9.UINT16[R_IO_L]) +#define RSCAN0TMID9LL (RSCAN0.TMID9.UINT8[R_IO_LL]) +#define RSCAN0TMID9LH (RSCAN0.TMID9.UINT8[R_IO_LH]) +#define RSCAN0TMID9H (RSCAN0.TMID9.UINT16[R_IO_H]) +#define RSCAN0TMID9HL (RSCAN0.TMID9.UINT8[R_IO_HL]) +#define RSCAN0TMID9HH (RSCAN0.TMID9.UINT8[R_IO_HH]) +#define RSCAN0TMPTR9 (RSCAN0.TMPTR9.UINT32) +#define RSCAN0TMPTR9L (RSCAN0.TMPTR9.UINT16[R_IO_L]) +#define RSCAN0TMPTR9LL (RSCAN0.TMPTR9.UINT8[R_IO_LL]) +#define RSCAN0TMPTR9LH (RSCAN0.TMPTR9.UINT8[R_IO_LH]) +#define RSCAN0TMPTR9H (RSCAN0.TMPTR9.UINT16[R_IO_H]) +#define RSCAN0TMPTR9HL (RSCAN0.TMPTR9.UINT8[R_IO_HL]) +#define RSCAN0TMPTR9HH (RSCAN0.TMPTR9.UINT8[R_IO_HH]) +#define RSCAN0TMDF09 (RSCAN0.TMDF09.UINT32) +#define RSCAN0TMDF09L (RSCAN0.TMDF09.UINT16[R_IO_L]) +#define RSCAN0TMDF09LL (RSCAN0.TMDF09.UINT8[R_IO_LL]) +#define RSCAN0TMDF09LH (RSCAN0.TMDF09.UINT8[R_IO_LH]) +#define RSCAN0TMDF09H (RSCAN0.TMDF09.UINT16[R_IO_H]) +#define RSCAN0TMDF09HL (RSCAN0.TMDF09.UINT8[R_IO_HL]) +#define RSCAN0TMDF09HH (RSCAN0.TMDF09.UINT8[R_IO_HH]) +#define RSCAN0TMDF19 (RSCAN0.TMDF19.UINT32) +#define RSCAN0TMDF19L (RSCAN0.TMDF19.UINT16[R_IO_L]) +#define RSCAN0TMDF19LL (RSCAN0.TMDF19.UINT8[R_IO_LL]) +#define RSCAN0TMDF19LH (RSCAN0.TMDF19.UINT8[R_IO_LH]) +#define RSCAN0TMDF19H (RSCAN0.TMDF19.UINT16[R_IO_H]) +#define RSCAN0TMDF19HL (RSCAN0.TMDF19.UINT8[R_IO_HL]) +#define RSCAN0TMDF19HH (RSCAN0.TMDF19.UINT8[R_IO_HH]) +#define RSCAN0TMID10 (RSCAN0.TMID10.UINT32) +#define RSCAN0TMID10L (RSCAN0.TMID10.UINT16[R_IO_L]) +#define RSCAN0TMID10LL (RSCAN0.TMID10.UINT8[R_IO_LL]) +#define RSCAN0TMID10LH (RSCAN0.TMID10.UINT8[R_IO_LH]) +#define RSCAN0TMID10H (RSCAN0.TMID10.UINT16[R_IO_H]) +#define RSCAN0TMID10HL (RSCAN0.TMID10.UINT8[R_IO_HL]) +#define RSCAN0TMID10HH (RSCAN0.TMID10.UINT8[R_IO_HH]) +#define RSCAN0TMPTR10 (RSCAN0.TMPTR10.UINT32) +#define RSCAN0TMPTR10L (RSCAN0.TMPTR10.UINT16[R_IO_L]) +#define RSCAN0TMPTR10LL (RSCAN0.TMPTR10.UINT8[R_IO_LL]) +#define RSCAN0TMPTR10LH (RSCAN0.TMPTR10.UINT8[R_IO_LH]) +#define RSCAN0TMPTR10H (RSCAN0.TMPTR10.UINT16[R_IO_H]) +#define RSCAN0TMPTR10HL (RSCAN0.TMPTR10.UINT8[R_IO_HL]) +#define RSCAN0TMPTR10HH (RSCAN0.TMPTR10.UINT8[R_IO_HH]) +#define RSCAN0TMDF010 (RSCAN0.TMDF010.UINT32) +#define RSCAN0TMDF010L (RSCAN0.TMDF010.UINT16[R_IO_L]) +#define RSCAN0TMDF010LL (RSCAN0.TMDF010.UINT8[R_IO_LL]) +#define RSCAN0TMDF010LH (RSCAN0.TMDF010.UINT8[R_IO_LH]) +#define RSCAN0TMDF010H (RSCAN0.TMDF010.UINT16[R_IO_H]) +#define RSCAN0TMDF010HL (RSCAN0.TMDF010.UINT8[R_IO_HL]) +#define RSCAN0TMDF010HH (RSCAN0.TMDF010.UINT8[R_IO_HH]) +#define RSCAN0TMDF110 (RSCAN0.TMDF110.UINT32) +#define RSCAN0TMDF110L (RSCAN0.TMDF110.UINT16[R_IO_L]) +#define RSCAN0TMDF110LL (RSCAN0.TMDF110.UINT8[R_IO_LL]) +#define RSCAN0TMDF110LH (RSCAN0.TMDF110.UINT8[R_IO_LH]) +#define RSCAN0TMDF110H (RSCAN0.TMDF110.UINT16[R_IO_H]) +#define RSCAN0TMDF110HL (RSCAN0.TMDF110.UINT8[R_IO_HL]) +#define RSCAN0TMDF110HH (RSCAN0.TMDF110.UINT8[R_IO_HH]) +#define RSCAN0TMID11 (RSCAN0.TMID11.UINT32) +#define RSCAN0TMID11L (RSCAN0.TMID11.UINT16[R_IO_L]) +#define RSCAN0TMID11LL (RSCAN0.TMID11.UINT8[R_IO_LL]) +#define RSCAN0TMID11LH (RSCAN0.TMID11.UINT8[R_IO_LH]) +#define RSCAN0TMID11H (RSCAN0.TMID11.UINT16[R_IO_H]) +#define RSCAN0TMID11HL (RSCAN0.TMID11.UINT8[R_IO_HL]) +#define RSCAN0TMID11HH (RSCAN0.TMID11.UINT8[R_IO_HH]) +#define RSCAN0TMPTR11 (RSCAN0.TMPTR11.UINT32) +#define RSCAN0TMPTR11L (RSCAN0.TMPTR11.UINT16[R_IO_L]) +#define RSCAN0TMPTR11LL (RSCAN0.TMPTR11.UINT8[R_IO_LL]) +#define RSCAN0TMPTR11LH (RSCAN0.TMPTR11.UINT8[R_IO_LH]) +#define RSCAN0TMPTR11H (RSCAN0.TMPTR11.UINT16[R_IO_H]) +#define RSCAN0TMPTR11HL (RSCAN0.TMPTR11.UINT8[R_IO_HL]) +#define RSCAN0TMPTR11HH (RSCAN0.TMPTR11.UINT8[R_IO_HH]) +#define RSCAN0TMDF011 (RSCAN0.TMDF011.UINT32) +#define RSCAN0TMDF011L (RSCAN0.TMDF011.UINT16[R_IO_L]) +#define RSCAN0TMDF011LL (RSCAN0.TMDF011.UINT8[R_IO_LL]) +#define RSCAN0TMDF011LH (RSCAN0.TMDF011.UINT8[R_IO_LH]) +#define RSCAN0TMDF011H (RSCAN0.TMDF011.UINT16[R_IO_H]) +#define RSCAN0TMDF011HL (RSCAN0.TMDF011.UINT8[R_IO_HL]) +#define RSCAN0TMDF011HH (RSCAN0.TMDF011.UINT8[R_IO_HH]) +#define RSCAN0TMDF111 (RSCAN0.TMDF111.UINT32) +#define RSCAN0TMDF111L (RSCAN0.TMDF111.UINT16[R_IO_L]) +#define RSCAN0TMDF111LL (RSCAN0.TMDF111.UINT8[R_IO_LL]) +#define RSCAN0TMDF111LH (RSCAN0.TMDF111.UINT8[R_IO_LH]) +#define RSCAN0TMDF111H (RSCAN0.TMDF111.UINT16[R_IO_H]) +#define RSCAN0TMDF111HL (RSCAN0.TMDF111.UINT8[R_IO_HL]) +#define RSCAN0TMDF111HH (RSCAN0.TMDF111.UINT8[R_IO_HH]) +#define RSCAN0TMID12 (RSCAN0.TMID12.UINT32) +#define RSCAN0TMID12L (RSCAN0.TMID12.UINT16[R_IO_L]) +#define RSCAN0TMID12LL (RSCAN0.TMID12.UINT8[R_IO_LL]) +#define RSCAN0TMID12LH (RSCAN0.TMID12.UINT8[R_IO_LH]) +#define RSCAN0TMID12H (RSCAN0.TMID12.UINT16[R_IO_H]) +#define RSCAN0TMID12HL (RSCAN0.TMID12.UINT8[R_IO_HL]) +#define RSCAN0TMID12HH (RSCAN0.TMID12.UINT8[R_IO_HH]) +#define RSCAN0TMPTR12 (RSCAN0.TMPTR12.UINT32) +#define RSCAN0TMPTR12L (RSCAN0.TMPTR12.UINT16[R_IO_L]) +#define RSCAN0TMPTR12LL (RSCAN0.TMPTR12.UINT8[R_IO_LL]) +#define RSCAN0TMPTR12LH (RSCAN0.TMPTR12.UINT8[R_IO_LH]) +#define RSCAN0TMPTR12H (RSCAN0.TMPTR12.UINT16[R_IO_H]) +#define RSCAN0TMPTR12HL (RSCAN0.TMPTR12.UINT8[R_IO_HL]) +#define RSCAN0TMPTR12HH (RSCAN0.TMPTR12.UINT8[R_IO_HH]) +#define RSCAN0TMDF012 (RSCAN0.TMDF012.UINT32) +#define RSCAN0TMDF012L (RSCAN0.TMDF012.UINT16[R_IO_L]) +#define RSCAN0TMDF012LL (RSCAN0.TMDF012.UINT8[R_IO_LL]) +#define RSCAN0TMDF012LH (RSCAN0.TMDF012.UINT8[R_IO_LH]) +#define RSCAN0TMDF012H (RSCAN0.TMDF012.UINT16[R_IO_H]) +#define RSCAN0TMDF012HL (RSCAN0.TMDF012.UINT8[R_IO_HL]) +#define RSCAN0TMDF012HH (RSCAN0.TMDF012.UINT8[R_IO_HH]) +#define RSCAN0TMDF112 (RSCAN0.TMDF112.UINT32) +#define RSCAN0TMDF112L (RSCAN0.TMDF112.UINT16[R_IO_L]) +#define RSCAN0TMDF112LL (RSCAN0.TMDF112.UINT8[R_IO_LL]) +#define RSCAN0TMDF112LH (RSCAN0.TMDF112.UINT8[R_IO_LH]) +#define RSCAN0TMDF112H (RSCAN0.TMDF112.UINT16[R_IO_H]) +#define RSCAN0TMDF112HL (RSCAN0.TMDF112.UINT8[R_IO_HL]) +#define RSCAN0TMDF112HH (RSCAN0.TMDF112.UINT8[R_IO_HH]) +#define RSCAN0TMID13 (RSCAN0.TMID13.UINT32) +#define RSCAN0TMID13L (RSCAN0.TMID13.UINT16[R_IO_L]) +#define RSCAN0TMID13LL (RSCAN0.TMID13.UINT8[R_IO_LL]) +#define RSCAN0TMID13LH (RSCAN0.TMID13.UINT8[R_IO_LH]) +#define RSCAN0TMID13H (RSCAN0.TMID13.UINT16[R_IO_H]) +#define RSCAN0TMID13HL (RSCAN0.TMID13.UINT8[R_IO_HL]) +#define RSCAN0TMID13HH (RSCAN0.TMID13.UINT8[R_IO_HH]) +#define RSCAN0TMPTR13 (RSCAN0.TMPTR13.UINT32) +#define RSCAN0TMPTR13L (RSCAN0.TMPTR13.UINT16[R_IO_L]) +#define RSCAN0TMPTR13LL (RSCAN0.TMPTR13.UINT8[R_IO_LL]) +#define RSCAN0TMPTR13LH (RSCAN0.TMPTR13.UINT8[R_IO_LH]) +#define RSCAN0TMPTR13H (RSCAN0.TMPTR13.UINT16[R_IO_H]) +#define RSCAN0TMPTR13HL (RSCAN0.TMPTR13.UINT8[R_IO_HL]) +#define RSCAN0TMPTR13HH (RSCAN0.TMPTR13.UINT8[R_IO_HH]) +#define RSCAN0TMDF013 (RSCAN0.TMDF013.UINT32) +#define RSCAN0TMDF013L (RSCAN0.TMDF013.UINT16[R_IO_L]) +#define RSCAN0TMDF013LL (RSCAN0.TMDF013.UINT8[R_IO_LL]) +#define RSCAN0TMDF013LH (RSCAN0.TMDF013.UINT8[R_IO_LH]) +#define RSCAN0TMDF013H (RSCAN0.TMDF013.UINT16[R_IO_H]) +#define RSCAN0TMDF013HL (RSCAN0.TMDF013.UINT8[R_IO_HL]) +#define RSCAN0TMDF013HH (RSCAN0.TMDF013.UINT8[R_IO_HH]) +#define RSCAN0TMDF113 (RSCAN0.TMDF113.UINT32) +#define RSCAN0TMDF113L (RSCAN0.TMDF113.UINT16[R_IO_L]) +#define RSCAN0TMDF113LL (RSCAN0.TMDF113.UINT8[R_IO_LL]) +#define RSCAN0TMDF113LH (RSCAN0.TMDF113.UINT8[R_IO_LH]) +#define RSCAN0TMDF113H (RSCAN0.TMDF113.UINT16[R_IO_H]) +#define RSCAN0TMDF113HL (RSCAN0.TMDF113.UINT8[R_IO_HL]) +#define RSCAN0TMDF113HH (RSCAN0.TMDF113.UINT8[R_IO_HH]) +#define RSCAN0TMID14 (RSCAN0.TMID14.UINT32) +#define RSCAN0TMID14L (RSCAN0.TMID14.UINT16[R_IO_L]) +#define RSCAN0TMID14LL (RSCAN0.TMID14.UINT8[R_IO_LL]) +#define RSCAN0TMID14LH (RSCAN0.TMID14.UINT8[R_IO_LH]) +#define RSCAN0TMID14H (RSCAN0.TMID14.UINT16[R_IO_H]) +#define RSCAN0TMID14HL (RSCAN0.TMID14.UINT8[R_IO_HL]) +#define RSCAN0TMID14HH (RSCAN0.TMID14.UINT8[R_IO_HH]) +#define RSCAN0TMPTR14 (RSCAN0.TMPTR14.UINT32) +#define RSCAN0TMPTR14L (RSCAN0.TMPTR14.UINT16[R_IO_L]) +#define RSCAN0TMPTR14LL (RSCAN0.TMPTR14.UINT8[R_IO_LL]) +#define RSCAN0TMPTR14LH (RSCAN0.TMPTR14.UINT8[R_IO_LH]) +#define RSCAN0TMPTR14H (RSCAN0.TMPTR14.UINT16[R_IO_H]) +#define RSCAN0TMPTR14HL (RSCAN0.TMPTR14.UINT8[R_IO_HL]) +#define RSCAN0TMPTR14HH (RSCAN0.TMPTR14.UINT8[R_IO_HH]) +#define RSCAN0TMDF014 (RSCAN0.TMDF014.UINT32) +#define RSCAN0TMDF014L (RSCAN0.TMDF014.UINT16[R_IO_L]) +#define RSCAN0TMDF014LL (RSCAN0.TMDF014.UINT8[R_IO_LL]) +#define RSCAN0TMDF014LH (RSCAN0.TMDF014.UINT8[R_IO_LH]) +#define RSCAN0TMDF014H (RSCAN0.TMDF014.UINT16[R_IO_H]) +#define RSCAN0TMDF014HL (RSCAN0.TMDF014.UINT8[R_IO_HL]) +#define RSCAN0TMDF014HH (RSCAN0.TMDF014.UINT8[R_IO_HH]) +#define RSCAN0TMDF114 (RSCAN0.TMDF114.UINT32) +#define RSCAN0TMDF114L (RSCAN0.TMDF114.UINT16[R_IO_L]) +#define RSCAN0TMDF114LL (RSCAN0.TMDF114.UINT8[R_IO_LL]) +#define RSCAN0TMDF114LH (RSCAN0.TMDF114.UINT8[R_IO_LH]) +#define RSCAN0TMDF114H (RSCAN0.TMDF114.UINT16[R_IO_H]) +#define RSCAN0TMDF114HL (RSCAN0.TMDF114.UINT8[R_IO_HL]) +#define RSCAN0TMDF114HH (RSCAN0.TMDF114.UINT8[R_IO_HH]) +#define RSCAN0TMID15 (RSCAN0.TMID15.UINT32) +#define RSCAN0TMID15L (RSCAN0.TMID15.UINT16[R_IO_L]) +#define RSCAN0TMID15LL (RSCAN0.TMID15.UINT8[R_IO_LL]) +#define RSCAN0TMID15LH (RSCAN0.TMID15.UINT8[R_IO_LH]) +#define RSCAN0TMID15H (RSCAN0.TMID15.UINT16[R_IO_H]) +#define RSCAN0TMID15HL (RSCAN0.TMID15.UINT8[R_IO_HL]) +#define RSCAN0TMID15HH (RSCAN0.TMID15.UINT8[R_IO_HH]) +#define RSCAN0TMPTR15 (RSCAN0.TMPTR15.UINT32) +#define RSCAN0TMPTR15L (RSCAN0.TMPTR15.UINT16[R_IO_L]) +#define RSCAN0TMPTR15LL (RSCAN0.TMPTR15.UINT8[R_IO_LL]) +#define RSCAN0TMPTR15LH (RSCAN0.TMPTR15.UINT8[R_IO_LH]) +#define RSCAN0TMPTR15H (RSCAN0.TMPTR15.UINT16[R_IO_H]) +#define RSCAN0TMPTR15HL (RSCAN0.TMPTR15.UINT8[R_IO_HL]) +#define RSCAN0TMPTR15HH (RSCAN0.TMPTR15.UINT8[R_IO_HH]) +#define RSCAN0TMDF015 (RSCAN0.TMDF015.UINT32) +#define RSCAN0TMDF015L (RSCAN0.TMDF015.UINT16[R_IO_L]) +#define RSCAN0TMDF015LL (RSCAN0.TMDF015.UINT8[R_IO_LL]) +#define RSCAN0TMDF015LH (RSCAN0.TMDF015.UINT8[R_IO_LH]) +#define RSCAN0TMDF015H (RSCAN0.TMDF015.UINT16[R_IO_H]) +#define RSCAN0TMDF015HL (RSCAN0.TMDF015.UINT8[R_IO_HL]) +#define RSCAN0TMDF015HH (RSCAN0.TMDF015.UINT8[R_IO_HH]) +#define RSCAN0TMDF115 (RSCAN0.TMDF115.UINT32) +#define RSCAN0TMDF115L (RSCAN0.TMDF115.UINT16[R_IO_L]) +#define RSCAN0TMDF115LL (RSCAN0.TMDF115.UINT8[R_IO_LL]) +#define RSCAN0TMDF115LH (RSCAN0.TMDF115.UINT8[R_IO_LH]) +#define RSCAN0TMDF115H (RSCAN0.TMDF115.UINT16[R_IO_H]) +#define RSCAN0TMDF115HL (RSCAN0.TMDF115.UINT8[R_IO_HL]) +#define RSCAN0TMDF115HH (RSCAN0.TMDF115.UINT8[R_IO_HH]) +#define RSCAN0TMID16 (RSCAN0.TMID16.UINT32) +#define RSCAN0TMID16L (RSCAN0.TMID16.UINT16[R_IO_L]) +#define RSCAN0TMID16LL (RSCAN0.TMID16.UINT8[R_IO_LL]) +#define RSCAN0TMID16LH (RSCAN0.TMID16.UINT8[R_IO_LH]) +#define RSCAN0TMID16H (RSCAN0.TMID16.UINT16[R_IO_H]) +#define RSCAN0TMID16HL (RSCAN0.TMID16.UINT8[R_IO_HL]) +#define RSCAN0TMID16HH (RSCAN0.TMID16.UINT8[R_IO_HH]) +#define RSCAN0TMPTR16 (RSCAN0.TMPTR16.UINT32) +#define RSCAN0TMPTR16L (RSCAN0.TMPTR16.UINT16[R_IO_L]) +#define RSCAN0TMPTR16LL (RSCAN0.TMPTR16.UINT8[R_IO_LL]) +#define RSCAN0TMPTR16LH (RSCAN0.TMPTR16.UINT8[R_IO_LH]) +#define RSCAN0TMPTR16H (RSCAN0.TMPTR16.UINT16[R_IO_H]) +#define RSCAN0TMPTR16HL (RSCAN0.TMPTR16.UINT8[R_IO_HL]) +#define RSCAN0TMPTR16HH (RSCAN0.TMPTR16.UINT8[R_IO_HH]) +#define RSCAN0TMDF016 (RSCAN0.TMDF016.UINT32) +#define RSCAN0TMDF016L (RSCAN0.TMDF016.UINT16[R_IO_L]) +#define RSCAN0TMDF016LL (RSCAN0.TMDF016.UINT8[R_IO_LL]) +#define RSCAN0TMDF016LH (RSCAN0.TMDF016.UINT8[R_IO_LH]) +#define RSCAN0TMDF016H (RSCAN0.TMDF016.UINT16[R_IO_H]) +#define RSCAN0TMDF016HL (RSCAN0.TMDF016.UINT8[R_IO_HL]) +#define RSCAN0TMDF016HH (RSCAN0.TMDF016.UINT8[R_IO_HH]) +#define RSCAN0TMDF116 (RSCAN0.TMDF116.UINT32) +#define RSCAN0TMDF116L (RSCAN0.TMDF116.UINT16[R_IO_L]) +#define RSCAN0TMDF116LL (RSCAN0.TMDF116.UINT8[R_IO_LL]) +#define RSCAN0TMDF116LH (RSCAN0.TMDF116.UINT8[R_IO_LH]) +#define RSCAN0TMDF116H (RSCAN0.TMDF116.UINT16[R_IO_H]) +#define RSCAN0TMDF116HL (RSCAN0.TMDF116.UINT8[R_IO_HL]) +#define RSCAN0TMDF116HH (RSCAN0.TMDF116.UINT8[R_IO_HH]) +#define RSCAN0TMID17 (RSCAN0.TMID17.UINT32) +#define RSCAN0TMID17L (RSCAN0.TMID17.UINT16[R_IO_L]) +#define RSCAN0TMID17LL (RSCAN0.TMID17.UINT8[R_IO_LL]) +#define RSCAN0TMID17LH (RSCAN0.TMID17.UINT8[R_IO_LH]) +#define RSCAN0TMID17H (RSCAN0.TMID17.UINT16[R_IO_H]) +#define RSCAN0TMID17HL (RSCAN0.TMID17.UINT8[R_IO_HL]) +#define RSCAN0TMID17HH (RSCAN0.TMID17.UINT8[R_IO_HH]) +#define RSCAN0TMPTR17 (RSCAN0.TMPTR17.UINT32) +#define RSCAN0TMPTR17L (RSCAN0.TMPTR17.UINT16[R_IO_L]) +#define RSCAN0TMPTR17LL (RSCAN0.TMPTR17.UINT8[R_IO_LL]) +#define RSCAN0TMPTR17LH (RSCAN0.TMPTR17.UINT8[R_IO_LH]) +#define RSCAN0TMPTR17H (RSCAN0.TMPTR17.UINT16[R_IO_H]) +#define RSCAN0TMPTR17HL (RSCAN0.TMPTR17.UINT8[R_IO_HL]) +#define RSCAN0TMPTR17HH (RSCAN0.TMPTR17.UINT8[R_IO_HH]) +#define RSCAN0TMDF017 (RSCAN0.TMDF017.UINT32) +#define RSCAN0TMDF017L (RSCAN0.TMDF017.UINT16[R_IO_L]) +#define RSCAN0TMDF017LL (RSCAN0.TMDF017.UINT8[R_IO_LL]) +#define RSCAN0TMDF017LH (RSCAN0.TMDF017.UINT8[R_IO_LH]) +#define RSCAN0TMDF017H (RSCAN0.TMDF017.UINT16[R_IO_H]) +#define RSCAN0TMDF017HL (RSCAN0.TMDF017.UINT8[R_IO_HL]) +#define RSCAN0TMDF017HH (RSCAN0.TMDF017.UINT8[R_IO_HH]) +#define RSCAN0TMDF117 (RSCAN0.TMDF117.UINT32) +#define RSCAN0TMDF117L (RSCAN0.TMDF117.UINT16[R_IO_L]) +#define RSCAN0TMDF117LL (RSCAN0.TMDF117.UINT8[R_IO_LL]) +#define RSCAN0TMDF117LH (RSCAN0.TMDF117.UINT8[R_IO_LH]) +#define RSCAN0TMDF117H (RSCAN0.TMDF117.UINT16[R_IO_H]) +#define RSCAN0TMDF117HL (RSCAN0.TMDF117.UINT8[R_IO_HL]) +#define RSCAN0TMDF117HH (RSCAN0.TMDF117.UINT8[R_IO_HH]) +#define RSCAN0TMID18 (RSCAN0.TMID18.UINT32) +#define RSCAN0TMID18L (RSCAN0.TMID18.UINT16[R_IO_L]) +#define RSCAN0TMID18LL (RSCAN0.TMID18.UINT8[R_IO_LL]) +#define RSCAN0TMID18LH (RSCAN0.TMID18.UINT8[R_IO_LH]) +#define RSCAN0TMID18H (RSCAN0.TMID18.UINT16[R_IO_H]) +#define RSCAN0TMID18HL (RSCAN0.TMID18.UINT8[R_IO_HL]) +#define RSCAN0TMID18HH (RSCAN0.TMID18.UINT8[R_IO_HH]) +#define RSCAN0TMPTR18 (RSCAN0.TMPTR18.UINT32) +#define RSCAN0TMPTR18L (RSCAN0.TMPTR18.UINT16[R_IO_L]) +#define RSCAN0TMPTR18LL (RSCAN0.TMPTR18.UINT8[R_IO_LL]) +#define RSCAN0TMPTR18LH (RSCAN0.TMPTR18.UINT8[R_IO_LH]) +#define RSCAN0TMPTR18H (RSCAN0.TMPTR18.UINT16[R_IO_H]) +#define RSCAN0TMPTR18HL (RSCAN0.TMPTR18.UINT8[R_IO_HL]) +#define RSCAN0TMPTR18HH (RSCAN0.TMPTR18.UINT8[R_IO_HH]) +#define RSCAN0TMDF018 (RSCAN0.TMDF018.UINT32) +#define RSCAN0TMDF018L (RSCAN0.TMDF018.UINT16[R_IO_L]) +#define RSCAN0TMDF018LL (RSCAN0.TMDF018.UINT8[R_IO_LL]) +#define RSCAN0TMDF018LH (RSCAN0.TMDF018.UINT8[R_IO_LH]) +#define RSCAN0TMDF018H (RSCAN0.TMDF018.UINT16[R_IO_H]) +#define RSCAN0TMDF018HL (RSCAN0.TMDF018.UINT8[R_IO_HL]) +#define RSCAN0TMDF018HH (RSCAN0.TMDF018.UINT8[R_IO_HH]) +#define RSCAN0TMDF118 (RSCAN0.TMDF118.UINT32) +#define RSCAN0TMDF118L (RSCAN0.TMDF118.UINT16[R_IO_L]) +#define RSCAN0TMDF118LL (RSCAN0.TMDF118.UINT8[R_IO_LL]) +#define RSCAN0TMDF118LH (RSCAN0.TMDF118.UINT8[R_IO_LH]) +#define RSCAN0TMDF118H (RSCAN0.TMDF118.UINT16[R_IO_H]) +#define RSCAN0TMDF118HL (RSCAN0.TMDF118.UINT8[R_IO_HL]) +#define RSCAN0TMDF118HH (RSCAN0.TMDF118.UINT8[R_IO_HH]) +#define RSCAN0TMID19 (RSCAN0.TMID19.UINT32) +#define RSCAN0TMID19L (RSCAN0.TMID19.UINT16[R_IO_L]) +#define RSCAN0TMID19LL (RSCAN0.TMID19.UINT8[R_IO_LL]) +#define RSCAN0TMID19LH (RSCAN0.TMID19.UINT8[R_IO_LH]) +#define RSCAN0TMID19H (RSCAN0.TMID19.UINT16[R_IO_H]) +#define RSCAN0TMID19HL (RSCAN0.TMID19.UINT8[R_IO_HL]) +#define RSCAN0TMID19HH (RSCAN0.TMID19.UINT8[R_IO_HH]) +#define RSCAN0TMPTR19 (RSCAN0.TMPTR19.UINT32) +#define RSCAN0TMPTR19L (RSCAN0.TMPTR19.UINT16[R_IO_L]) +#define RSCAN0TMPTR19LL (RSCAN0.TMPTR19.UINT8[R_IO_LL]) +#define RSCAN0TMPTR19LH (RSCAN0.TMPTR19.UINT8[R_IO_LH]) +#define RSCAN0TMPTR19H (RSCAN0.TMPTR19.UINT16[R_IO_H]) +#define RSCAN0TMPTR19HL (RSCAN0.TMPTR19.UINT8[R_IO_HL]) +#define RSCAN0TMPTR19HH (RSCAN0.TMPTR19.UINT8[R_IO_HH]) +#define RSCAN0TMDF019 (RSCAN0.TMDF019.UINT32) +#define RSCAN0TMDF019L (RSCAN0.TMDF019.UINT16[R_IO_L]) +#define RSCAN0TMDF019LL (RSCAN0.TMDF019.UINT8[R_IO_LL]) +#define RSCAN0TMDF019LH (RSCAN0.TMDF019.UINT8[R_IO_LH]) +#define RSCAN0TMDF019H (RSCAN0.TMDF019.UINT16[R_IO_H]) +#define RSCAN0TMDF019HL (RSCAN0.TMDF019.UINT8[R_IO_HL]) +#define RSCAN0TMDF019HH (RSCAN0.TMDF019.UINT8[R_IO_HH]) +#define RSCAN0TMDF119 (RSCAN0.TMDF119.UINT32) +#define RSCAN0TMDF119L (RSCAN0.TMDF119.UINT16[R_IO_L]) +#define RSCAN0TMDF119LL (RSCAN0.TMDF119.UINT8[R_IO_LL]) +#define RSCAN0TMDF119LH (RSCAN0.TMDF119.UINT8[R_IO_LH]) +#define RSCAN0TMDF119H (RSCAN0.TMDF119.UINT16[R_IO_H]) +#define RSCAN0TMDF119HL (RSCAN0.TMDF119.UINT8[R_IO_HL]) +#define RSCAN0TMDF119HH (RSCAN0.TMDF119.UINT8[R_IO_HH]) +#define RSCAN0TMID20 (RSCAN0.TMID20.UINT32) +#define RSCAN0TMID20L (RSCAN0.TMID20.UINT16[R_IO_L]) +#define RSCAN0TMID20LL (RSCAN0.TMID20.UINT8[R_IO_LL]) +#define RSCAN0TMID20LH (RSCAN0.TMID20.UINT8[R_IO_LH]) +#define RSCAN0TMID20H (RSCAN0.TMID20.UINT16[R_IO_H]) +#define RSCAN0TMID20HL (RSCAN0.TMID20.UINT8[R_IO_HL]) +#define RSCAN0TMID20HH (RSCAN0.TMID20.UINT8[R_IO_HH]) +#define RSCAN0TMPTR20 (RSCAN0.TMPTR20.UINT32) +#define RSCAN0TMPTR20L (RSCAN0.TMPTR20.UINT16[R_IO_L]) +#define RSCAN0TMPTR20LL (RSCAN0.TMPTR20.UINT8[R_IO_LL]) +#define RSCAN0TMPTR20LH (RSCAN0.TMPTR20.UINT8[R_IO_LH]) +#define RSCAN0TMPTR20H (RSCAN0.TMPTR20.UINT16[R_IO_H]) +#define RSCAN0TMPTR20HL (RSCAN0.TMPTR20.UINT8[R_IO_HL]) +#define RSCAN0TMPTR20HH (RSCAN0.TMPTR20.UINT8[R_IO_HH]) +#define RSCAN0TMDF020 (RSCAN0.TMDF020.UINT32) +#define RSCAN0TMDF020L (RSCAN0.TMDF020.UINT16[R_IO_L]) +#define RSCAN0TMDF020LL (RSCAN0.TMDF020.UINT8[R_IO_LL]) +#define RSCAN0TMDF020LH (RSCAN0.TMDF020.UINT8[R_IO_LH]) +#define RSCAN0TMDF020H (RSCAN0.TMDF020.UINT16[R_IO_H]) +#define RSCAN0TMDF020HL (RSCAN0.TMDF020.UINT8[R_IO_HL]) +#define RSCAN0TMDF020HH (RSCAN0.TMDF020.UINT8[R_IO_HH]) +#define RSCAN0TMDF120 (RSCAN0.TMDF120.UINT32) +#define RSCAN0TMDF120L (RSCAN0.TMDF120.UINT16[R_IO_L]) +#define RSCAN0TMDF120LL (RSCAN0.TMDF120.UINT8[R_IO_LL]) +#define RSCAN0TMDF120LH (RSCAN0.TMDF120.UINT8[R_IO_LH]) +#define RSCAN0TMDF120H (RSCAN0.TMDF120.UINT16[R_IO_H]) +#define RSCAN0TMDF120HL (RSCAN0.TMDF120.UINT8[R_IO_HL]) +#define RSCAN0TMDF120HH (RSCAN0.TMDF120.UINT8[R_IO_HH]) +#define RSCAN0TMID21 (RSCAN0.TMID21.UINT32) +#define RSCAN0TMID21L (RSCAN0.TMID21.UINT16[R_IO_L]) +#define RSCAN0TMID21LL (RSCAN0.TMID21.UINT8[R_IO_LL]) +#define RSCAN0TMID21LH (RSCAN0.TMID21.UINT8[R_IO_LH]) +#define RSCAN0TMID21H (RSCAN0.TMID21.UINT16[R_IO_H]) +#define RSCAN0TMID21HL (RSCAN0.TMID21.UINT8[R_IO_HL]) +#define RSCAN0TMID21HH (RSCAN0.TMID21.UINT8[R_IO_HH]) +#define RSCAN0TMPTR21 (RSCAN0.TMPTR21.UINT32) +#define RSCAN0TMPTR21L (RSCAN0.TMPTR21.UINT16[R_IO_L]) +#define RSCAN0TMPTR21LL (RSCAN0.TMPTR21.UINT8[R_IO_LL]) +#define RSCAN0TMPTR21LH (RSCAN0.TMPTR21.UINT8[R_IO_LH]) +#define RSCAN0TMPTR21H (RSCAN0.TMPTR21.UINT16[R_IO_H]) +#define RSCAN0TMPTR21HL (RSCAN0.TMPTR21.UINT8[R_IO_HL]) +#define RSCAN0TMPTR21HH (RSCAN0.TMPTR21.UINT8[R_IO_HH]) +#define RSCAN0TMDF021 (RSCAN0.TMDF021.UINT32) +#define RSCAN0TMDF021L (RSCAN0.TMDF021.UINT16[R_IO_L]) +#define RSCAN0TMDF021LL (RSCAN0.TMDF021.UINT8[R_IO_LL]) +#define RSCAN0TMDF021LH (RSCAN0.TMDF021.UINT8[R_IO_LH]) +#define RSCAN0TMDF021H (RSCAN0.TMDF021.UINT16[R_IO_H]) +#define RSCAN0TMDF021HL (RSCAN0.TMDF021.UINT8[R_IO_HL]) +#define RSCAN0TMDF021HH (RSCAN0.TMDF021.UINT8[R_IO_HH]) +#define RSCAN0TMDF121 (RSCAN0.TMDF121.UINT32) +#define RSCAN0TMDF121L (RSCAN0.TMDF121.UINT16[R_IO_L]) +#define RSCAN0TMDF121LL (RSCAN0.TMDF121.UINT8[R_IO_LL]) +#define RSCAN0TMDF121LH (RSCAN0.TMDF121.UINT8[R_IO_LH]) +#define RSCAN0TMDF121H (RSCAN0.TMDF121.UINT16[R_IO_H]) +#define RSCAN0TMDF121HL (RSCAN0.TMDF121.UINT8[R_IO_HL]) +#define RSCAN0TMDF121HH (RSCAN0.TMDF121.UINT8[R_IO_HH]) +#define RSCAN0TMID22 (RSCAN0.TMID22.UINT32) +#define RSCAN0TMID22L (RSCAN0.TMID22.UINT16[R_IO_L]) +#define RSCAN0TMID22LL (RSCAN0.TMID22.UINT8[R_IO_LL]) +#define RSCAN0TMID22LH (RSCAN0.TMID22.UINT8[R_IO_LH]) +#define RSCAN0TMID22H (RSCAN0.TMID22.UINT16[R_IO_H]) +#define RSCAN0TMID22HL (RSCAN0.TMID22.UINT8[R_IO_HL]) +#define RSCAN0TMID22HH (RSCAN0.TMID22.UINT8[R_IO_HH]) +#define RSCAN0TMPTR22 (RSCAN0.TMPTR22.UINT32) +#define RSCAN0TMPTR22L (RSCAN0.TMPTR22.UINT16[R_IO_L]) +#define RSCAN0TMPTR22LL (RSCAN0.TMPTR22.UINT8[R_IO_LL]) +#define RSCAN0TMPTR22LH (RSCAN0.TMPTR22.UINT8[R_IO_LH]) +#define RSCAN0TMPTR22H (RSCAN0.TMPTR22.UINT16[R_IO_H]) +#define RSCAN0TMPTR22HL (RSCAN0.TMPTR22.UINT8[R_IO_HL]) +#define RSCAN0TMPTR22HH (RSCAN0.TMPTR22.UINT8[R_IO_HH]) +#define RSCAN0TMDF022 (RSCAN0.TMDF022.UINT32) +#define RSCAN0TMDF022L (RSCAN0.TMDF022.UINT16[R_IO_L]) +#define RSCAN0TMDF022LL (RSCAN0.TMDF022.UINT8[R_IO_LL]) +#define RSCAN0TMDF022LH (RSCAN0.TMDF022.UINT8[R_IO_LH]) +#define RSCAN0TMDF022H (RSCAN0.TMDF022.UINT16[R_IO_H]) +#define RSCAN0TMDF022HL (RSCAN0.TMDF022.UINT8[R_IO_HL]) +#define RSCAN0TMDF022HH (RSCAN0.TMDF022.UINT8[R_IO_HH]) +#define RSCAN0TMDF122 (RSCAN0.TMDF122.UINT32) +#define RSCAN0TMDF122L (RSCAN0.TMDF122.UINT16[R_IO_L]) +#define RSCAN0TMDF122LL (RSCAN0.TMDF122.UINT8[R_IO_LL]) +#define RSCAN0TMDF122LH (RSCAN0.TMDF122.UINT8[R_IO_LH]) +#define RSCAN0TMDF122H (RSCAN0.TMDF122.UINT16[R_IO_H]) +#define RSCAN0TMDF122HL (RSCAN0.TMDF122.UINT8[R_IO_HL]) +#define RSCAN0TMDF122HH (RSCAN0.TMDF122.UINT8[R_IO_HH]) +#define RSCAN0TMID23 (RSCAN0.TMID23.UINT32) +#define RSCAN0TMID23L (RSCAN0.TMID23.UINT16[R_IO_L]) +#define RSCAN0TMID23LL (RSCAN0.TMID23.UINT8[R_IO_LL]) +#define RSCAN0TMID23LH (RSCAN0.TMID23.UINT8[R_IO_LH]) +#define RSCAN0TMID23H (RSCAN0.TMID23.UINT16[R_IO_H]) +#define RSCAN0TMID23HL (RSCAN0.TMID23.UINT8[R_IO_HL]) +#define RSCAN0TMID23HH (RSCAN0.TMID23.UINT8[R_IO_HH]) +#define RSCAN0TMPTR23 (RSCAN0.TMPTR23.UINT32) +#define RSCAN0TMPTR23L (RSCAN0.TMPTR23.UINT16[R_IO_L]) +#define RSCAN0TMPTR23LL (RSCAN0.TMPTR23.UINT8[R_IO_LL]) +#define RSCAN0TMPTR23LH (RSCAN0.TMPTR23.UINT8[R_IO_LH]) +#define RSCAN0TMPTR23H (RSCAN0.TMPTR23.UINT16[R_IO_H]) +#define RSCAN0TMPTR23HL (RSCAN0.TMPTR23.UINT8[R_IO_HL]) +#define RSCAN0TMPTR23HH (RSCAN0.TMPTR23.UINT8[R_IO_HH]) +#define RSCAN0TMDF023 (RSCAN0.TMDF023.UINT32) +#define RSCAN0TMDF023L (RSCAN0.TMDF023.UINT16[R_IO_L]) +#define RSCAN0TMDF023LL (RSCAN0.TMDF023.UINT8[R_IO_LL]) +#define RSCAN0TMDF023LH (RSCAN0.TMDF023.UINT8[R_IO_LH]) +#define RSCAN0TMDF023H (RSCAN0.TMDF023.UINT16[R_IO_H]) +#define RSCAN0TMDF023HL (RSCAN0.TMDF023.UINT8[R_IO_HL]) +#define RSCAN0TMDF023HH (RSCAN0.TMDF023.UINT8[R_IO_HH]) +#define RSCAN0TMDF123 (RSCAN0.TMDF123.UINT32) +#define RSCAN0TMDF123L (RSCAN0.TMDF123.UINT16[R_IO_L]) +#define RSCAN0TMDF123LL (RSCAN0.TMDF123.UINT8[R_IO_LL]) +#define RSCAN0TMDF123LH (RSCAN0.TMDF123.UINT8[R_IO_LH]) +#define RSCAN0TMDF123H (RSCAN0.TMDF123.UINT16[R_IO_H]) +#define RSCAN0TMDF123HL (RSCAN0.TMDF123.UINT8[R_IO_HL]) +#define RSCAN0TMDF123HH (RSCAN0.TMDF123.UINT8[R_IO_HH]) +#define RSCAN0TMID24 (RSCAN0.TMID24.UINT32) +#define RSCAN0TMID24L (RSCAN0.TMID24.UINT16[R_IO_L]) +#define RSCAN0TMID24LL (RSCAN0.TMID24.UINT8[R_IO_LL]) +#define RSCAN0TMID24LH (RSCAN0.TMID24.UINT8[R_IO_LH]) +#define RSCAN0TMID24H (RSCAN0.TMID24.UINT16[R_IO_H]) +#define RSCAN0TMID24HL (RSCAN0.TMID24.UINT8[R_IO_HL]) +#define RSCAN0TMID24HH (RSCAN0.TMID24.UINT8[R_IO_HH]) +#define RSCAN0TMPTR24 (RSCAN0.TMPTR24.UINT32) +#define RSCAN0TMPTR24L (RSCAN0.TMPTR24.UINT16[R_IO_L]) +#define RSCAN0TMPTR24LL (RSCAN0.TMPTR24.UINT8[R_IO_LL]) +#define RSCAN0TMPTR24LH (RSCAN0.TMPTR24.UINT8[R_IO_LH]) +#define RSCAN0TMPTR24H (RSCAN0.TMPTR24.UINT16[R_IO_H]) +#define RSCAN0TMPTR24HL (RSCAN0.TMPTR24.UINT8[R_IO_HL]) +#define RSCAN0TMPTR24HH (RSCAN0.TMPTR24.UINT8[R_IO_HH]) +#define RSCAN0TMDF024 (RSCAN0.TMDF024.UINT32) +#define RSCAN0TMDF024L (RSCAN0.TMDF024.UINT16[R_IO_L]) +#define RSCAN0TMDF024LL (RSCAN0.TMDF024.UINT8[R_IO_LL]) +#define RSCAN0TMDF024LH (RSCAN0.TMDF024.UINT8[R_IO_LH]) +#define RSCAN0TMDF024H (RSCAN0.TMDF024.UINT16[R_IO_H]) +#define RSCAN0TMDF024HL (RSCAN0.TMDF024.UINT8[R_IO_HL]) +#define RSCAN0TMDF024HH (RSCAN0.TMDF024.UINT8[R_IO_HH]) +#define RSCAN0TMDF124 (RSCAN0.TMDF124.UINT32) +#define RSCAN0TMDF124L (RSCAN0.TMDF124.UINT16[R_IO_L]) +#define RSCAN0TMDF124LL (RSCAN0.TMDF124.UINT8[R_IO_LL]) +#define RSCAN0TMDF124LH (RSCAN0.TMDF124.UINT8[R_IO_LH]) +#define RSCAN0TMDF124H (RSCAN0.TMDF124.UINT16[R_IO_H]) +#define RSCAN0TMDF124HL (RSCAN0.TMDF124.UINT8[R_IO_HL]) +#define RSCAN0TMDF124HH (RSCAN0.TMDF124.UINT8[R_IO_HH]) +#define RSCAN0TMID25 (RSCAN0.TMID25.UINT32) +#define RSCAN0TMID25L (RSCAN0.TMID25.UINT16[R_IO_L]) +#define RSCAN0TMID25LL (RSCAN0.TMID25.UINT8[R_IO_LL]) +#define RSCAN0TMID25LH (RSCAN0.TMID25.UINT8[R_IO_LH]) +#define RSCAN0TMID25H (RSCAN0.TMID25.UINT16[R_IO_H]) +#define RSCAN0TMID25HL (RSCAN0.TMID25.UINT8[R_IO_HL]) +#define RSCAN0TMID25HH (RSCAN0.TMID25.UINT8[R_IO_HH]) +#define RSCAN0TMPTR25 (RSCAN0.TMPTR25.UINT32) +#define RSCAN0TMPTR25L (RSCAN0.TMPTR25.UINT16[R_IO_L]) +#define RSCAN0TMPTR25LL (RSCAN0.TMPTR25.UINT8[R_IO_LL]) +#define RSCAN0TMPTR25LH (RSCAN0.TMPTR25.UINT8[R_IO_LH]) +#define RSCAN0TMPTR25H (RSCAN0.TMPTR25.UINT16[R_IO_H]) +#define RSCAN0TMPTR25HL (RSCAN0.TMPTR25.UINT8[R_IO_HL]) +#define RSCAN0TMPTR25HH (RSCAN0.TMPTR25.UINT8[R_IO_HH]) +#define RSCAN0TMDF025 (RSCAN0.TMDF025.UINT32) +#define RSCAN0TMDF025L (RSCAN0.TMDF025.UINT16[R_IO_L]) +#define RSCAN0TMDF025LL (RSCAN0.TMDF025.UINT8[R_IO_LL]) +#define RSCAN0TMDF025LH (RSCAN0.TMDF025.UINT8[R_IO_LH]) +#define RSCAN0TMDF025H (RSCAN0.TMDF025.UINT16[R_IO_H]) +#define RSCAN0TMDF025HL (RSCAN0.TMDF025.UINT8[R_IO_HL]) +#define RSCAN0TMDF025HH (RSCAN0.TMDF025.UINT8[R_IO_HH]) +#define RSCAN0TMDF125 (RSCAN0.TMDF125.UINT32) +#define RSCAN0TMDF125L (RSCAN0.TMDF125.UINT16[R_IO_L]) +#define RSCAN0TMDF125LL (RSCAN0.TMDF125.UINT8[R_IO_LL]) +#define RSCAN0TMDF125LH (RSCAN0.TMDF125.UINT8[R_IO_LH]) +#define RSCAN0TMDF125H (RSCAN0.TMDF125.UINT16[R_IO_H]) +#define RSCAN0TMDF125HL (RSCAN0.TMDF125.UINT8[R_IO_HL]) +#define RSCAN0TMDF125HH (RSCAN0.TMDF125.UINT8[R_IO_HH]) +#define RSCAN0TMID26 (RSCAN0.TMID26.UINT32) +#define RSCAN0TMID26L (RSCAN0.TMID26.UINT16[R_IO_L]) +#define RSCAN0TMID26LL (RSCAN0.TMID26.UINT8[R_IO_LL]) +#define RSCAN0TMID26LH (RSCAN0.TMID26.UINT8[R_IO_LH]) +#define RSCAN0TMID26H (RSCAN0.TMID26.UINT16[R_IO_H]) +#define RSCAN0TMID26HL (RSCAN0.TMID26.UINT8[R_IO_HL]) +#define RSCAN0TMID26HH (RSCAN0.TMID26.UINT8[R_IO_HH]) +#define RSCAN0TMPTR26 (RSCAN0.TMPTR26.UINT32) +#define RSCAN0TMPTR26L (RSCAN0.TMPTR26.UINT16[R_IO_L]) +#define RSCAN0TMPTR26LL (RSCAN0.TMPTR26.UINT8[R_IO_LL]) +#define RSCAN0TMPTR26LH (RSCAN0.TMPTR26.UINT8[R_IO_LH]) +#define RSCAN0TMPTR26H (RSCAN0.TMPTR26.UINT16[R_IO_H]) +#define RSCAN0TMPTR26HL (RSCAN0.TMPTR26.UINT8[R_IO_HL]) +#define RSCAN0TMPTR26HH (RSCAN0.TMPTR26.UINT8[R_IO_HH]) +#define RSCAN0TMDF026 (RSCAN0.TMDF026.UINT32) +#define RSCAN0TMDF026L (RSCAN0.TMDF026.UINT16[R_IO_L]) +#define RSCAN0TMDF026LL (RSCAN0.TMDF026.UINT8[R_IO_LL]) +#define RSCAN0TMDF026LH (RSCAN0.TMDF026.UINT8[R_IO_LH]) +#define RSCAN0TMDF026H (RSCAN0.TMDF026.UINT16[R_IO_H]) +#define RSCAN0TMDF026HL (RSCAN0.TMDF026.UINT8[R_IO_HL]) +#define RSCAN0TMDF026HH (RSCAN0.TMDF026.UINT8[R_IO_HH]) +#define RSCAN0TMDF126 (RSCAN0.TMDF126.UINT32) +#define RSCAN0TMDF126L (RSCAN0.TMDF126.UINT16[R_IO_L]) +#define RSCAN0TMDF126LL (RSCAN0.TMDF126.UINT8[R_IO_LL]) +#define RSCAN0TMDF126LH (RSCAN0.TMDF126.UINT8[R_IO_LH]) +#define RSCAN0TMDF126H (RSCAN0.TMDF126.UINT16[R_IO_H]) +#define RSCAN0TMDF126HL (RSCAN0.TMDF126.UINT8[R_IO_HL]) +#define RSCAN0TMDF126HH (RSCAN0.TMDF126.UINT8[R_IO_HH]) +#define RSCAN0TMID27 (RSCAN0.TMID27.UINT32) +#define RSCAN0TMID27L (RSCAN0.TMID27.UINT16[R_IO_L]) +#define RSCAN0TMID27LL (RSCAN0.TMID27.UINT8[R_IO_LL]) +#define RSCAN0TMID27LH (RSCAN0.TMID27.UINT8[R_IO_LH]) +#define RSCAN0TMID27H (RSCAN0.TMID27.UINT16[R_IO_H]) +#define RSCAN0TMID27HL (RSCAN0.TMID27.UINT8[R_IO_HL]) +#define RSCAN0TMID27HH (RSCAN0.TMID27.UINT8[R_IO_HH]) +#define RSCAN0TMPTR27 (RSCAN0.TMPTR27.UINT32) +#define RSCAN0TMPTR27L (RSCAN0.TMPTR27.UINT16[R_IO_L]) +#define RSCAN0TMPTR27LL (RSCAN0.TMPTR27.UINT8[R_IO_LL]) +#define RSCAN0TMPTR27LH (RSCAN0.TMPTR27.UINT8[R_IO_LH]) +#define RSCAN0TMPTR27H (RSCAN0.TMPTR27.UINT16[R_IO_H]) +#define RSCAN0TMPTR27HL (RSCAN0.TMPTR27.UINT8[R_IO_HL]) +#define RSCAN0TMPTR27HH (RSCAN0.TMPTR27.UINT8[R_IO_HH]) +#define RSCAN0TMDF027 (RSCAN0.TMDF027.UINT32) +#define RSCAN0TMDF027L (RSCAN0.TMDF027.UINT16[R_IO_L]) +#define RSCAN0TMDF027LL (RSCAN0.TMDF027.UINT8[R_IO_LL]) +#define RSCAN0TMDF027LH (RSCAN0.TMDF027.UINT8[R_IO_LH]) +#define RSCAN0TMDF027H (RSCAN0.TMDF027.UINT16[R_IO_H]) +#define RSCAN0TMDF027HL (RSCAN0.TMDF027.UINT8[R_IO_HL]) +#define RSCAN0TMDF027HH (RSCAN0.TMDF027.UINT8[R_IO_HH]) +#define RSCAN0TMDF127 (RSCAN0.TMDF127.UINT32) +#define RSCAN0TMDF127L (RSCAN0.TMDF127.UINT16[R_IO_L]) +#define RSCAN0TMDF127LL (RSCAN0.TMDF127.UINT8[R_IO_LL]) +#define RSCAN0TMDF127LH (RSCAN0.TMDF127.UINT8[R_IO_LH]) +#define RSCAN0TMDF127H (RSCAN0.TMDF127.UINT16[R_IO_H]) +#define RSCAN0TMDF127HL (RSCAN0.TMDF127.UINT8[R_IO_HL]) +#define RSCAN0TMDF127HH (RSCAN0.TMDF127.UINT8[R_IO_HH]) +#define RSCAN0TMID28 (RSCAN0.TMID28.UINT32) +#define RSCAN0TMID28L (RSCAN0.TMID28.UINT16[R_IO_L]) +#define RSCAN0TMID28LL (RSCAN0.TMID28.UINT8[R_IO_LL]) +#define RSCAN0TMID28LH (RSCAN0.TMID28.UINT8[R_IO_LH]) +#define RSCAN0TMID28H (RSCAN0.TMID28.UINT16[R_IO_H]) +#define RSCAN0TMID28HL (RSCAN0.TMID28.UINT8[R_IO_HL]) +#define RSCAN0TMID28HH (RSCAN0.TMID28.UINT8[R_IO_HH]) +#define RSCAN0TMPTR28 (RSCAN0.TMPTR28.UINT32) +#define RSCAN0TMPTR28L (RSCAN0.TMPTR28.UINT16[R_IO_L]) +#define RSCAN0TMPTR28LL (RSCAN0.TMPTR28.UINT8[R_IO_LL]) +#define RSCAN0TMPTR28LH (RSCAN0.TMPTR28.UINT8[R_IO_LH]) +#define RSCAN0TMPTR28H (RSCAN0.TMPTR28.UINT16[R_IO_H]) +#define RSCAN0TMPTR28HL (RSCAN0.TMPTR28.UINT8[R_IO_HL]) +#define RSCAN0TMPTR28HH (RSCAN0.TMPTR28.UINT8[R_IO_HH]) +#define RSCAN0TMDF028 (RSCAN0.TMDF028.UINT32) +#define RSCAN0TMDF028L (RSCAN0.TMDF028.UINT16[R_IO_L]) +#define RSCAN0TMDF028LL (RSCAN0.TMDF028.UINT8[R_IO_LL]) +#define RSCAN0TMDF028LH (RSCAN0.TMDF028.UINT8[R_IO_LH]) +#define RSCAN0TMDF028H (RSCAN0.TMDF028.UINT16[R_IO_H]) +#define RSCAN0TMDF028HL (RSCAN0.TMDF028.UINT8[R_IO_HL]) +#define RSCAN0TMDF028HH (RSCAN0.TMDF028.UINT8[R_IO_HH]) +#define RSCAN0TMDF128 (RSCAN0.TMDF128.UINT32) +#define RSCAN0TMDF128L (RSCAN0.TMDF128.UINT16[R_IO_L]) +#define RSCAN0TMDF128LL (RSCAN0.TMDF128.UINT8[R_IO_LL]) +#define RSCAN0TMDF128LH (RSCAN0.TMDF128.UINT8[R_IO_LH]) +#define RSCAN0TMDF128H (RSCAN0.TMDF128.UINT16[R_IO_H]) +#define RSCAN0TMDF128HL (RSCAN0.TMDF128.UINT8[R_IO_HL]) +#define RSCAN0TMDF128HH (RSCAN0.TMDF128.UINT8[R_IO_HH]) +#define RSCAN0TMID29 (RSCAN0.TMID29.UINT32) +#define RSCAN0TMID29L (RSCAN0.TMID29.UINT16[R_IO_L]) +#define RSCAN0TMID29LL (RSCAN0.TMID29.UINT8[R_IO_LL]) +#define RSCAN0TMID29LH (RSCAN0.TMID29.UINT8[R_IO_LH]) +#define RSCAN0TMID29H (RSCAN0.TMID29.UINT16[R_IO_H]) +#define RSCAN0TMID29HL (RSCAN0.TMID29.UINT8[R_IO_HL]) +#define RSCAN0TMID29HH (RSCAN0.TMID29.UINT8[R_IO_HH]) +#define RSCAN0TMPTR29 (RSCAN0.TMPTR29.UINT32) +#define RSCAN0TMPTR29L (RSCAN0.TMPTR29.UINT16[R_IO_L]) +#define RSCAN0TMPTR29LL (RSCAN0.TMPTR29.UINT8[R_IO_LL]) +#define RSCAN0TMPTR29LH (RSCAN0.TMPTR29.UINT8[R_IO_LH]) +#define RSCAN0TMPTR29H (RSCAN0.TMPTR29.UINT16[R_IO_H]) +#define RSCAN0TMPTR29HL (RSCAN0.TMPTR29.UINT8[R_IO_HL]) +#define RSCAN0TMPTR29HH (RSCAN0.TMPTR29.UINT8[R_IO_HH]) +#define RSCAN0TMDF029 (RSCAN0.TMDF029.UINT32) +#define RSCAN0TMDF029L (RSCAN0.TMDF029.UINT16[R_IO_L]) +#define RSCAN0TMDF029LL (RSCAN0.TMDF029.UINT8[R_IO_LL]) +#define RSCAN0TMDF029LH (RSCAN0.TMDF029.UINT8[R_IO_LH]) +#define RSCAN0TMDF029H (RSCAN0.TMDF029.UINT16[R_IO_H]) +#define RSCAN0TMDF029HL (RSCAN0.TMDF029.UINT8[R_IO_HL]) +#define RSCAN0TMDF029HH (RSCAN0.TMDF029.UINT8[R_IO_HH]) +#define RSCAN0TMDF129 (RSCAN0.TMDF129.UINT32) +#define RSCAN0TMDF129L (RSCAN0.TMDF129.UINT16[R_IO_L]) +#define RSCAN0TMDF129LL (RSCAN0.TMDF129.UINT8[R_IO_LL]) +#define RSCAN0TMDF129LH (RSCAN0.TMDF129.UINT8[R_IO_LH]) +#define RSCAN0TMDF129H (RSCAN0.TMDF129.UINT16[R_IO_H]) +#define RSCAN0TMDF129HL (RSCAN0.TMDF129.UINT8[R_IO_HL]) +#define RSCAN0TMDF129HH (RSCAN0.TMDF129.UINT8[R_IO_HH]) +#define RSCAN0TMID30 (RSCAN0.TMID30.UINT32) +#define RSCAN0TMID30L (RSCAN0.TMID30.UINT16[R_IO_L]) +#define RSCAN0TMID30LL (RSCAN0.TMID30.UINT8[R_IO_LL]) +#define RSCAN0TMID30LH (RSCAN0.TMID30.UINT8[R_IO_LH]) +#define RSCAN0TMID30H (RSCAN0.TMID30.UINT16[R_IO_H]) +#define RSCAN0TMID30HL (RSCAN0.TMID30.UINT8[R_IO_HL]) +#define RSCAN0TMID30HH (RSCAN0.TMID30.UINT8[R_IO_HH]) +#define RSCAN0TMPTR30 (RSCAN0.TMPTR30.UINT32) +#define RSCAN0TMPTR30L (RSCAN0.TMPTR30.UINT16[R_IO_L]) +#define RSCAN0TMPTR30LL (RSCAN0.TMPTR30.UINT8[R_IO_LL]) +#define RSCAN0TMPTR30LH (RSCAN0.TMPTR30.UINT8[R_IO_LH]) +#define RSCAN0TMPTR30H (RSCAN0.TMPTR30.UINT16[R_IO_H]) +#define RSCAN0TMPTR30HL (RSCAN0.TMPTR30.UINT8[R_IO_HL]) +#define RSCAN0TMPTR30HH (RSCAN0.TMPTR30.UINT8[R_IO_HH]) +#define RSCAN0TMDF030 (RSCAN0.TMDF030.UINT32) +#define RSCAN0TMDF030L (RSCAN0.TMDF030.UINT16[R_IO_L]) +#define RSCAN0TMDF030LL (RSCAN0.TMDF030.UINT8[R_IO_LL]) +#define RSCAN0TMDF030LH (RSCAN0.TMDF030.UINT8[R_IO_LH]) +#define RSCAN0TMDF030H (RSCAN0.TMDF030.UINT16[R_IO_H]) +#define RSCAN0TMDF030HL (RSCAN0.TMDF030.UINT8[R_IO_HL]) +#define RSCAN0TMDF030HH (RSCAN0.TMDF030.UINT8[R_IO_HH]) +#define RSCAN0TMDF130 (RSCAN0.TMDF130.UINT32) +#define RSCAN0TMDF130L (RSCAN0.TMDF130.UINT16[R_IO_L]) +#define RSCAN0TMDF130LL (RSCAN0.TMDF130.UINT8[R_IO_LL]) +#define RSCAN0TMDF130LH (RSCAN0.TMDF130.UINT8[R_IO_LH]) +#define RSCAN0TMDF130H (RSCAN0.TMDF130.UINT16[R_IO_H]) +#define RSCAN0TMDF130HL (RSCAN0.TMDF130.UINT8[R_IO_HL]) +#define RSCAN0TMDF130HH (RSCAN0.TMDF130.UINT8[R_IO_HH]) +#define RSCAN0TMID31 (RSCAN0.TMID31.UINT32) +#define RSCAN0TMID31L (RSCAN0.TMID31.UINT16[R_IO_L]) +#define RSCAN0TMID31LL (RSCAN0.TMID31.UINT8[R_IO_LL]) +#define RSCAN0TMID31LH (RSCAN0.TMID31.UINT8[R_IO_LH]) +#define RSCAN0TMID31H (RSCAN0.TMID31.UINT16[R_IO_H]) +#define RSCAN0TMID31HL (RSCAN0.TMID31.UINT8[R_IO_HL]) +#define RSCAN0TMID31HH (RSCAN0.TMID31.UINT8[R_IO_HH]) +#define RSCAN0TMPTR31 (RSCAN0.TMPTR31.UINT32) +#define RSCAN0TMPTR31L (RSCAN0.TMPTR31.UINT16[R_IO_L]) +#define RSCAN0TMPTR31LL (RSCAN0.TMPTR31.UINT8[R_IO_LL]) +#define RSCAN0TMPTR31LH (RSCAN0.TMPTR31.UINT8[R_IO_LH]) +#define RSCAN0TMPTR31H (RSCAN0.TMPTR31.UINT16[R_IO_H]) +#define RSCAN0TMPTR31HL (RSCAN0.TMPTR31.UINT8[R_IO_HL]) +#define RSCAN0TMPTR31HH (RSCAN0.TMPTR31.UINT8[R_IO_HH]) +#define RSCAN0TMDF031 (RSCAN0.TMDF031.UINT32) +#define RSCAN0TMDF031L (RSCAN0.TMDF031.UINT16[R_IO_L]) +#define RSCAN0TMDF031LL (RSCAN0.TMDF031.UINT8[R_IO_LL]) +#define RSCAN0TMDF031LH (RSCAN0.TMDF031.UINT8[R_IO_LH]) +#define RSCAN0TMDF031H (RSCAN0.TMDF031.UINT16[R_IO_H]) +#define RSCAN0TMDF031HL (RSCAN0.TMDF031.UINT8[R_IO_HL]) +#define RSCAN0TMDF031HH (RSCAN0.TMDF031.UINT8[R_IO_HH]) +#define RSCAN0TMDF131 (RSCAN0.TMDF131.UINT32) +#define RSCAN0TMDF131L (RSCAN0.TMDF131.UINT16[R_IO_L]) +#define RSCAN0TMDF131LL (RSCAN0.TMDF131.UINT8[R_IO_LL]) +#define RSCAN0TMDF131LH (RSCAN0.TMDF131.UINT8[R_IO_LH]) +#define RSCAN0TMDF131H (RSCAN0.TMDF131.UINT16[R_IO_H]) +#define RSCAN0TMDF131HL (RSCAN0.TMDF131.UINT8[R_IO_HL]) +#define RSCAN0TMDF131HH (RSCAN0.TMDF131.UINT8[R_IO_HH]) +#define RSCAN0THLACC0 (RSCAN0.THLACC0.UINT32) +#define RSCAN0THLACC0L (RSCAN0.THLACC0.UINT16[R_IO_L]) +#define RSCAN0THLACC0LL (RSCAN0.THLACC0.UINT8[R_IO_LL]) +#define RSCAN0THLACC0LH (RSCAN0.THLACC0.UINT8[R_IO_LH]) +#define RSCAN0THLACC0H (RSCAN0.THLACC0.UINT16[R_IO_H]) +#define RSCAN0THLACC0HL (RSCAN0.THLACC0.UINT8[R_IO_HL]) +#define RSCAN0THLACC0HH (RSCAN0.THLACC0.UINT8[R_IO_HH]) +#define RSCAN0THLACC1 (RSCAN0.THLACC1.UINT32) +#define RSCAN0THLACC1L (RSCAN0.THLACC1.UINT16[R_IO_L]) +#define RSCAN0THLACC1LL (RSCAN0.THLACC1.UINT8[R_IO_LL]) +#define RSCAN0THLACC1LH (RSCAN0.THLACC1.UINT8[R_IO_LH]) +#define RSCAN0THLACC1H (RSCAN0.THLACC1.UINT16[R_IO_H]) +#define RSCAN0THLACC1HL (RSCAN0.THLACC1.UINT8[R_IO_HL]) +#define RSCAN0THLACC1HH (RSCAN0.THLACC1.UINT8[R_IO_HH]) + +#define RSCAN0_GAFLCFG0_COUNT (1) +#define RSCAN0_RMND0_COUNT (1) +#define RSCAN0_RFCC0_COUNT (8) +#define RSCAN0_RFSTS0_COUNT (8) +#define RSCAN0_RFPCTR0_COUNT (8) +#define RSCAN0_CFCC0_COUNT (6) +#define RSCAN0_CFSTS0_COUNT (6) +#define RSCAN0_CFPCTR0_COUNT (6) +#define RSCAN0_TMC0_COUNT (32) +#define RSCAN0_TMSTS0_COUNT (32) +#define RSCAN0_TMTRSTS0_COUNT (1) +#define RSCAN0_TMTARSTS0_COUNT (1) +#define RSCAN0_TMTCSTS0_COUNT (1) +#define RSCAN0_TMTASTS0_COUNT (1) +#define RSCAN0_TMIEC0_COUNT (1) +#define RSCAN0_TXQCC0_COUNT (2) +#define RSCAN0_TXQSTS0_COUNT (2) +#define RSCAN0_TXQPCTR0_COUNT (2) +#define RSCAN0_THLCC0_COUNT (2) +#define RSCAN0_THLSTS0_COUNT (2) +#define RSCAN0_THLPCTR0_COUNT (2) +#define RSCAN0_GTINTSTS0_COUNT (1) +#define RSCAN0_THLACC0_COUNT (2) + + +typedef struct st_rscan0 +{ + /* RSCAN0 */ + +/* start of struct st_rscan_from_rscan0cncfg */ + union iodefine_reg32_t C0CFG; /* C0CFG */ + union iodefine_reg32_t C0CTR; /* C0CTR */ + union iodefine_reg32_t C0STS; /* C0STS */ + union iodefine_reg32_t C0ERFL; /* C0ERFL */ + +/* end of struct st_rscan_from_rscan0cncfg */ + +/* start of struct st_rscan_from_rscan0cncfg */ + union iodefine_reg32_t C1CFG; /* C1CFG */ + union iodefine_reg32_t C1CTR; /* C1CTR */ + union iodefine_reg32_t C1STS; /* C1STS */ + union iodefine_reg32_t C1ERFL; /* C1ERFL */ + +/* end of struct st_rscan_from_rscan0cncfg */ + + volatile uint8_t dummy159[100]; /* */ + union iodefine_reg32_t GCFG; /* GCFG */ + union iodefine_reg32_t GCTR; /* GCTR */ + union iodefine_reg32_t GSTS; /* GSTS */ + union iodefine_reg32_t GERFL; /* GERFL */ + union iodefine_reg32_16_t GTSC; /* GTSC */ + union iodefine_reg32_t GAFLECTR; /* GAFLECTR */ + +/* #define RSCAN0_GAFLCFG0_COUNT (1) */ + union iodefine_reg32_t GAFLCFG0; /* GAFLCFG0 */ + + volatile uint8_t dummy160[4]; /* */ + union iodefine_reg32_t RMNB; /* RMNB */ + +/* #define RSCAN0_RMND0_COUNT (1) */ + union iodefine_reg32_t RMND0; /* RMND0 */ + + volatile uint8_t dummy161[12]; /* */ + +/* #define RSCAN0_RFCC0_COUNT (8) */ + union iodefine_reg32_t RFCC0; /* RFCC0 */ + union iodefine_reg32_t RFCC1; /* RFCC1 */ + union iodefine_reg32_t RFCC2; /* RFCC2 */ + union iodefine_reg32_t RFCC3; /* RFCC3 */ + union iodefine_reg32_t RFCC4; /* RFCC4 */ + union iodefine_reg32_t RFCC5; /* RFCC5 */ + union iodefine_reg32_t RFCC6; /* RFCC6 */ + union iodefine_reg32_t RFCC7; /* RFCC7 */ + +/* #define RSCAN0_RFSTS0_COUNT (8) */ + union iodefine_reg32_t RFSTS0; /* RFSTS0 */ + union iodefine_reg32_t RFSTS1; /* RFSTS1 */ + union iodefine_reg32_t RFSTS2; /* RFSTS2 */ + union iodefine_reg32_t RFSTS3; /* RFSTS3 */ + union iodefine_reg32_t RFSTS4; /* RFSTS4 */ + union iodefine_reg32_t RFSTS5; /* RFSTS5 */ + union iodefine_reg32_t RFSTS6; /* RFSTS6 */ + union iodefine_reg32_t RFSTS7; /* RFSTS7 */ + +/* #define RSCAN0_RFPCTR0_COUNT (8) */ + union iodefine_reg32_t RFPCTR0; /* RFPCTR0 */ + union iodefine_reg32_t RFPCTR1; /* RFPCTR1 */ + union iodefine_reg32_t RFPCTR2; /* RFPCTR2 */ + union iodefine_reg32_t RFPCTR3; /* RFPCTR3 */ + union iodefine_reg32_t RFPCTR4; /* RFPCTR4 */ + union iodefine_reg32_t RFPCTR5; /* RFPCTR5 */ + union iodefine_reg32_t RFPCTR6; /* RFPCTR6 */ + union iodefine_reg32_t RFPCTR7; /* RFPCTR7 */ + +/* #define RSCAN0_CFCC0_COUNT (6) */ + union iodefine_reg32_t CFCC0; /* CFCC0 */ + union iodefine_reg32_t CFCC1; /* CFCC1 */ + union iodefine_reg32_t CFCC2; /* CFCC2 */ + union iodefine_reg32_t CFCC3; /* CFCC3 */ + union iodefine_reg32_t CFCC4; /* CFCC4 */ + union iodefine_reg32_t CFCC5; /* CFCC5 */ + + volatile uint8_t dummy162[72]; /* */ + +/* #define RSCAN0_CFSTS0_COUNT (6) */ + union iodefine_reg32_t CFSTS0; /* CFSTS0 */ + union iodefine_reg32_t CFSTS1; /* CFSTS1 */ + union iodefine_reg32_t CFSTS2; /* CFSTS2 */ + union iodefine_reg32_t CFSTS3; /* CFSTS3 */ + union iodefine_reg32_t CFSTS4; /* CFSTS4 */ + union iodefine_reg32_t CFSTS5; /* CFSTS5 */ + + volatile uint8_t dummy163[72]; /* */ + +/* #define RSCAN0_CFPCTR0_COUNT (6) */ + union iodefine_reg32_t CFPCTR0; /* CFPCTR0 */ + union iodefine_reg32_t CFPCTR1; /* CFPCTR1 */ + union iodefine_reg32_t CFPCTR2; /* CFPCTR2 */ + union iodefine_reg32_t CFPCTR3; /* CFPCTR3 */ + union iodefine_reg32_t CFPCTR4; /* CFPCTR4 */ + union iodefine_reg32_t CFPCTR5; /* CFPCTR5 */ + + volatile uint8_t dummy164[72]; /* */ + union iodefine_reg32_t FESTS; /* FESTS */ + union iodefine_reg32_t FFSTS; /* FFSTS */ + union iodefine_reg32_t FMSTS; /* FMSTS */ + union iodefine_reg32_t RFISTS; /* RFISTS */ + union iodefine_reg32_t CFRISTS; /* CFRISTS */ + union iodefine_reg32_t CFTISTS; /* CFTISTS */ + + +/* #define RSCAN0_TMC0_COUNT (32) */ + volatile uint8_t TMC0; /* TMC0 */ + volatile uint8_t TMC1; /* TMC1 */ + volatile uint8_t TMC2; /* TMC2 */ + volatile uint8_t TMC3; /* TMC3 */ + volatile uint8_t TMC4; /* TMC4 */ + volatile uint8_t TMC5; /* TMC5 */ + volatile uint8_t TMC6; /* TMC6 */ + volatile uint8_t TMC7; /* TMC7 */ + volatile uint8_t TMC8; /* TMC8 */ + volatile uint8_t TMC9; /* TMC9 */ + volatile uint8_t TMC10; /* TMC10 */ + volatile uint8_t TMC11; /* TMC11 */ + volatile uint8_t TMC12; /* TMC12 */ + volatile uint8_t TMC13; /* TMC13 */ + volatile uint8_t TMC14; /* TMC14 */ + volatile uint8_t TMC15; /* TMC15 */ + volatile uint8_t TMC16; /* TMC16 */ + volatile uint8_t TMC17; /* TMC17 */ + volatile uint8_t TMC18; /* TMC18 */ + volatile uint8_t TMC19; /* TMC19 */ + volatile uint8_t TMC20; /* TMC20 */ + volatile uint8_t TMC21; /* TMC21 */ + volatile uint8_t TMC22; /* TMC22 */ + volatile uint8_t TMC23; /* TMC23 */ + volatile uint8_t TMC24; /* TMC24 */ + volatile uint8_t TMC25; /* TMC25 */ + volatile uint8_t TMC26; /* TMC26 */ + volatile uint8_t TMC27; /* TMC27 */ + volatile uint8_t TMC28; /* TMC28 */ + volatile uint8_t TMC29; /* TMC29 */ + volatile uint8_t TMC30; /* TMC30 */ + volatile uint8_t TMC31; /* TMC31 */ + volatile uint8_t dummy165[96]; /* */ + +/* #define RSCAN0_TMSTS0_COUNT (32) */ + volatile uint8_t TMSTS0; /* TMSTS0 */ + volatile uint8_t TMSTS1; /* TMSTS1 */ + volatile uint8_t TMSTS2; /* TMSTS2 */ + volatile uint8_t TMSTS3; /* TMSTS3 */ + volatile uint8_t TMSTS4; /* TMSTS4 */ + volatile uint8_t TMSTS5; /* TMSTS5 */ + volatile uint8_t TMSTS6; /* TMSTS6 */ + volatile uint8_t TMSTS7; /* TMSTS7 */ + volatile uint8_t TMSTS8; /* TMSTS8 */ + volatile uint8_t TMSTS9; /* TMSTS9 */ + volatile uint8_t TMSTS10; /* TMSTS10 */ + volatile uint8_t TMSTS11; /* TMSTS11 */ + volatile uint8_t TMSTS12; /* TMSTS12 */ + volatile uint8_t TMSTS13; /* TMSTS13 */ + volatile uint8_t TMSTS14; /* TMSTS14 */ + volatile uint8_t TMSTS15; /* TMSTS15 */ + volatile uint8_t TMSTS16; /* TMSTS16 */ + volatile uint8_t TMSTS17; /* TMSTS17 */ + volatile uint8_t TMSTS18; /* TMSTS18 */ + volatile uint8_t TMSTS19; /* TMSTS19 */ + volatile uint8_t TMSTS20; /* TMSTS20 */ + volatile uint8_t TMSTS21; /* TMSTS21 */ + volatile uint8_t TMSTS22; /* TMSTS22 */ + volatile uint8_t TMSTS23; /* TMSTS23 */ + volatile uint8_t TMSTS24; /* TMSTS24 */ + volatile uint8_t TMSTS25; /* TMSTS25 */ + volatile uint8_t TMSTS26; /* TMSTS26 */ + volatile uint8_t TMSTS27; /* TMSTS27 */ + volatile uint8_t TMSTS28; /* TMSTS28 */ + volatile uint8_t TMSTS29; /* TMSTS29 */ + volatile uint8_t TMSTS30; /* TMSTS30 */ + volatile uint8_t TMSTS31; /* TMSTS31 */ + volatile uint8_t dummy166[96]; /* */ + +/* #define RSCAN0_TMTRSTS0_COUNT (1) */ + union iodefine_reg32_t TMTRSTS0; /* TMTRSTS0 */ + + volatile uint8_t dummy167[12]; /* */ + +/* #define RSCAN0_TMTARSTS0_COUNT (1) */ + union iodefine_reg32_t TMTARSTS0; /* TMTARSTS0 */ + + volatile uint8_t dummy168[12]; /* */ + +/* #define RSCAN0_TMTCSTS0_COUNT (1) */ + union iodefine_reg32_t TMTCSTS0; /* TMTCSTS0 */ + + volatile uint8_t dummy169[12]; /* */ + +/* #define RSCAN0_TMTASTS0_COUNT (1) */ + union iodefine_reg32_t TMTASTS0; /* TMTASTS0 */ + + volatile uint8_t dummy170[12]; /* */ + +/* #define RSCAN0_TMIEC0_COUNT (1) */ + union iodefine_reg32_t TMIEC0; /* TMIEC0 */ + + volatile uint8_t dummy171[12]; /* */ + +/* #define RSCAN0_TXQCC0_COUNT (2) */ + union iodefine_reg32_t TXQCC0; /* TXQCC0 */ + union iodefine_reg32_t TXQCC1; /* TXQCC1 */ + + volatile uint8_t dummy172[24]; /* */ + +/* #define RSCAN0_TXQSTS0_COUNT (2) */ + union iodefine_reg32_t TXQSTS0; /* TXQSTS0 */ + union iodefine_reg32_t TXQSTS1; /* TXQSTS1 */ + + volatile uint8_t dummy173[24]; /* */ + +/* #define RSCAN0_TXQPCTR0_COUNT (2) */ + union iodefine_reg32_t TXQPCTR0; /* TXQPCTR0 */ + union iodefine_reg32_t TXQPCTR1; /* TXQPCTR1 */ + + volatile uint8_t dummy174[24]; /* */ + +/* #define RSCAN0_THLCC0_COUNT (2) */ + union iodefine_reg32_t THLCC0; /* THLCC0 */ + union iodefine_reg32_t THLCC1; /* THLCC1 */ + + volatile uint8_t dummy175[24]; /* */ + +/* #define RSCAN0_THLSTS0_COUNT (2) */ + union iodefine_reg32_t THLSTS0; /* THLSTS0 */ + union iodefine_reg32_t THLSTS1; /* THLSTS1 */ + + volatile uint8_t dummy176[24]; /* */ + +/* #define RSCAN0_THLPCTR0_COUNT (2) */ + union iodefine_reg32_t THLPCTR0; /* THLPCTR0 */ + union iodefine_reg32_t THLPCTR1; /* THLPCTR1 */ + + volatile uint8_t dummy177[24]; /* */ + +/* #define RSCAN0_GTINTSTS0_COUNT (1) */ + union iodefine_reg32_t GTINTSTS0; /* GTINTSTS0 */ + + volatile uint8_t dummy178[4]; /* */ + union iodefine_reg32_t GTSTCFG; /* GTSTCFG */ + union iodefine_reg32_t GTSTCTR; /* GTSTCTR */ + + volatile uint8_t dummy179[12]; /* */ + union iodefine_reg32_16_t GLOCKK; /* GLOCKK */ + + volatile uint8_t dummy180[128]; /* */ + +/* start of struct st_rscan_from_rscan0gaflidj */ + union iodefine_reg32_t GAFLID0; /* GAFLID0 */ + union iodefine_reg32_t GAFLM0; /* GAFLM0 */ + union iodefine_reg32_t GAFLP00; /* GAFLP00 */ + union iodefine_reg32_t GAFLP10; /* GAFLP10 */ + +/* end of struct st_rscan_from_rscan0gaflidj */ + +/* start of struct st_rscan_from_rscan0gaflidj */ + union iodefine_reg32_t GAFLID1; /* GAFLID1 */ + union iodefine_reg32_t GAFLM1; /* GAFLM1 */ + union iodefine_reg32_t GAFLP01; /* GAFLP01 */ + union iodefine_reg32_t GAFLP11; /* GAFLP11 */ + +/* end of struct st_rscan_from_rscan0gaflidj */ + +/* start of struct st_rscan_from_rscan0gaflidj */ + union iodefine_reg32_t GAFLID2; /* GAFLID2 */ + union iodefine_reg32_t GAFLM2; /* GAFLM2 */ + union iodefine_reg32_t GAFLP02; /* GAFLP02 */ + union iodefine_reg32_t GAFLP12; /* GAFLP12 */ + +/* end of struct st_rscan_from_rscan0gaflidj */ + +/* start of struct st_rscan_from_rscan0gaflidj */ + union iodefine_reg32_t GAFLID3; /* GAFLID3 */ + union iodefine_reg32_t GAFLM3; /* GAFLM3 */ + union iodefine_reg32_t GAFLP03; /* GAFLP03 */ + union iodefine_reg32_t GAFLP13; /* GAFLP13 */ + +/* end of struct st_rscan_from_rscan0gaflidj */ + +/* start of struct st_rscan_from_rscan0gaflidj */ + union iodefine_reg32_t GAFLID4; /* GAFLID4 */ + union iodefine_reg32_t GAFLM4; /* GAFLM4 */ + union iodefine_reg32_t GAFLP04; /* GAFLP04 */ + union iodefine_reg32_t GAFLP14; /* GAFLP14 */ + +/* end of struct st_rscan_from_rscan0gaflidj */ + +/* start of struct st_rscan_from_rscan0gaflidj */ + union iodefine_reg32_t GAFLID5; /* GAFLID5 */ + union iodefine_reg32_t GAFLM5; /* GAFLM5 */ + union iodefine_reg32_t GAFLP05; /* GAFLP05 */ + union iodefine_reg32_t GAFLP15; /* GAFLP15 */ + +/* end of struct st_rscan_from_rscan0gaflidj */ + +/* start of struct st_rscan_from_rscan0gaflidj */ + union iodefine_reg32_t GAFLID6; /* GAFLID6 */ + union iodefine_reg32_t GAFLM6; /* GAFLM6 */ + union iodefine_reg32_t GAFLP06; /* GAFLP06 */ + union iodefine_reg32_t GAFLP16; /* GAFLP16 */ + +/* end of struct st_rscan_from_rscan0gaflidj */ + +/* start of struct st_rscan_from_rscan0gaflidj */ + union iodefine_reg32_t GAFLID7; /* GAFLID7 */ + union iodefine_reg32_t GAFLM7; /* GAFLM7 */ + union iodefine_reg32_t GAFLP07; /* GAFLP07 */ + union iodefine_reg32_t GAFLP17; /* GAFLP17 */ + +/* end of struct st_rscan_from_rscan0gaflidj */ + +/* start of struct st_rscan_from_rscan0gaflidj */ + union iodefine_reg32_t GAFLID8; /* GAFLID8 */ + union iodefine_reg32_t GAFLM8; /* GAFLM8 */ + union iodefine_reg32_t GAFLP08; /* GAFLP08 */ + union iodefine_reg32_t GAFLP18; /* GAFLP18 */ + +/* end of struct st_rscan_from_rscan0gaflidj */ + +/* start of struct st_rscan_from_rscan0gaflidj */ + union iodefine_reg32_t GAFLID9; /* GAFLID9 */ + union iodefine_reg32_t GAFLM9; /* GAFLM9 */ + union iodefine_reg32_t GAFLP09; /* GAFLP09 */ + union iodefine_reg32_t GAFLP19; /* GAFLP19 */ + +/* end of struct st_rscan_from_rscan0gaflidj */ + +/* start of struct st_rscan_from_rscan0gaflidj */ + union iodefine_reg32_t GAFLID10; /* GAFLID10 */ + union iodefine_reg32_t GAFLM10; /* GAFLM10 */ + union iodefine_reg32_t GAFLP010; /* GAFLP010 */ + union iodefine_reg32_t GAFLP110; /* GAFLP110 */ + +/* end of struct st_rscan_from_rscan0gaflidj */ + +/* start of struct st_rscan_from_rscan0gaflidj */ + union iodefine_reg32_t GAFLID11; /* GAFLID11 */ + union iodefine_reg32_t GAFLM11; /* GAFLM11 */ + union iodefine_reg32_t GAFLP011; /* GAFLP011 */ + union iodefine_reg32_t GAFLP111; /* GAFLP111 */ + +/* end of struct st_rscan_from_rscan0gaflidj */ + +/* start of struct st_rscan_from_rscan0gaflidj */ + union iodefine_reg32_t GAFLID12; /* GAFLID12 */ + union iodefine_reg32_t GAFLM12; /* GAFLM12 */ + union iodefine_reg32_t GAFLP012; /* GAFLP012 */ + union iodefine_reg32_t GAFLP112; /* GAFLP112 */ + +/* end of struct st_rscan_from_rscan0gaflidj */ + +/* start of struct st_rscan_from_rscan0gaflidj */ + union iodefine_reg32_t GAFLID13; /* GAFLID13 */ + union iodefine_reg32_t GAFLM13; /* GAFLM13 */ + union iodefine_reg32_t GAFLP013; /* GAFLP013 */ + union iodefine_reg32_t GAFLP113; /* GAFLP113 */ + +/* end of struct st_rscan_from_rscan0gaflidj */ + +/* start of struct st_rscan_from_rscan0gaflidj */ + union iodefine_reg32_t GAFLID14; /* GAFLID14 */ + union iodefine_reg32_t GAFLM14; /* GAFLM14 */ + union iodefine_reg32_t GAFLP014; /* GAFLP014 */ + union iodefine_reg32_t GAFLP114; /* GAFLP114 */ + +/* end of struct st_rscan_from_rscan0gaflidj */ + +/* start of struct st_rscan_from_rscan0gaflidj */ + union iodefine_reg32_t GAFLID15; /* GAFLID15 */ + union iodefine_reg32_t GAFLM15; /* GAFLM15 */ + union iodefine_reg32_t GAFLP015; /* GAFLP015 */ + union iodefine_reg32_t GAFLP115; /* GAFLP115 */ + +/* end of struct st_rscan_from_rscan0gaflidj */ + +/* start of struct st_rscan_from_rscan0rmidp */ + union iodefine_reg32_t RMID0; /* RMID0 */ + union iodefine_reg32_t RMPTR0; /* RMPTR0 */ + union iodefine_reg32_t RMDF00; /* RMDF00 */ + union iodefine_reg32_t RMDF10; /* RMDF10 */ + +/* end of struct st_rscan_from_rscan0rmidp */ + +/* start of struct st_rscan_from_rscan0rmidp */ + union iodefine_reg32_t RMID1; /* RMID1 */ + union iodefine_reg32_t RMPTR1; /* RMPTR1 */ + union iodefine_reg32_t RMDF01; /* RMDF01 */ + union iodefine_reg32_t RMDF11; /* RMDF11 */ + +/* end of struct st_rscan_from_rscan0rmidp */ + +/* start of struct st_rscan_from_rscan0rmidp */ + union iodefine_reg32_t RMID2; /* RMID2 */ + union iodefine_reg32_t RMPTR2; /* RMPTR2 */ + union iodefine_reg32_t RMDF02; /* RMDF02 */ + union iodefine_reg32_t RMDF12; /* RMDF12 */ + +/* end of struct st_rscan_from_rscan0rmidp */ + +/* start of struct st_rscan_from_rscan0rmidp */ + union iodefine_reg32_t RMID3; /* RMID3 */ + union iodefine_reg32_t RMPTR3; /* RMPTR3 */ + union iodefine_reg32_t RMDF03; /* RMDF03 */ + union iodefine_reg32_t RMDF13; /* RMDF13 */ + +/* end of struct st_rscan_from_rscan0rmidp */ + +/* start of struct st_rscan_from_rscan0rmidp */ + union iodefine_reg32_t RMID4; /* RMID4 */ + union iodefine_reg32_t RMPTR4; /* RMPTR4 */ + union iodefine_reg32_t RMDF04; /* RMDF04 */ + union iodefine_reg32_t RMDF14; /* RMDF14 */ + +/* end of struct st_rscan_from_rscan0rmidp */ + +/* start of struct st_rscan_from_rscan0rmidp */ + union iodefine_reg32_t RMID5; /* RMID5 */ + union iodefine_reg32_t RMPTR5; /* RMPTR5 */ + union iodefine_reg32_t RMDF05; /* RMDF05 */ + union iodefine_reg32_t RMDF15; /* RMDF15 */ + +/* end of struct st_rscan_from_rscan0rmidp */ + +/* start of struct st_rscan_from_rscan0rmidp */ + union iodefine_reg32_t RMID6; /* RMID6 */ + union iodefine_reg32_t RMPTR6; /* RMPTR6 */ + union iodefine_reg32_t RMDF06; /* RMDF06 */ + union iodefine_reg32_t RMDF16; /* RMDF16 */ + +/* end of struct st_rscan_from_rscan0rmidp */ + +/* start of struct st_rscan_from_rscan0rmidp */ + union iodefine_reg32_t RMID7; /* RMID7 */ + union iodefine_reg32_t RMPTR7; /* RMPTR7 */ + union iodefine_reg32_t RMDF07; /* RMDF07 */ + union iodefine_reg32_t RMDF17; /* RMDF17 */ + +/* end of struct st_rscan_from_rscan0rmidp */ + +/* start of struct st_rscan_from_rscan0rmidp */ + union iodefine_reg32_t RMID8; /* RMID8 */ + union iodefine_reg32_t RMPTR8; /* RMPTR8 */ + union iodefine_reg32_t RMDF08; /* RMDF08 */ + union iodefine_reg32_t RMDF18; /* RMDF18 */ + +/* end of struct st_rscan_from_rscan0rmidp */ + +/* start of struct st_rscan_from_rscan0rmidp */ + union iodefine_reg32_t RMID9; /* RMID9 */ + union iodefine_reg32_t RMPTR9; /* RMPTR9 */ + union iodefine_reg32_t RMDF09; /* RMDF09 */ + union iodefine_reg32_t RMDF19; /* RMDF19 */ + +/* end of struct st_rscan_from_rscan0rmidp */ + +/* start of struct st_rscan_from_rscan0rmidp */ + union iodefine_reg32_t RMID10; /* RMID10 */ + union iodefine_reg32_t RMPTR10; /* RMPTR10 */ + union iodefine_reg32_t RMDF010; /* RMDF010 */ + union iodefine_reg32_t RMDF110; /* RMDF110 */ + +/* end of struct st_rscan_from_rscan0rmidp */ + +/* start of struct st_rscan_from_rscan0rmidp */ + union iodefine_reg32_t RMID11; /* RMID11 */ + union iodefine_reg32_t RMPTR11; /* RMPTR11 */ + union iodefine_reg32_t RMDF011; /* RMDF011 */ + union iodefine_reg32_t RMDF111; /* RMDF111 */ + +/* end of struct st_rscan_from_rscan0rmidp */ + +/* start of struct st_rscan_from_rscan0rmidp */ + union iodefine_reg32_t RMID12; /* RMID12 */ + union iodefine_reg32_t RMPTR12; /* RMPTR12 */ + union iodefine_reg32_t RMDF012; /* RMDF012 */ + union iodefine_reg32_t RMDF112; /* RMDF112 */ + +/* end of struct st_rscan_from_rscan0rmidp */ + +/* start of struct st_rscan_from_rscan0rmidp */ + union iodefine_reg32_t RMID13; /* RMID13 */ + union iodefine_reg32_t RMPTR13; /* RMPTR13 */ + union iodefine_reg32_t RMDF013; /* RMDF013 */ + union iodefine_reg32_t RMDF113; /* RMDF113 */ + +/* end of struct st_rscan_from_rscan0rmidp */ + +/* start of struct st_rscan_from_rscan0rmidp */ + union iodefine_reg32_t RMID14; /* RMID14 */ + union iodefine_reg32_t RMPTR14; /* RMPTR14 */ + union iodefine_reg32_t RMDF014; /* RMDF014 */ + union iodefine_reg32_t RMDF114; /* RMDF114 */ + +/* end of struct st_rscan_from_rscan0rmidp */ + +/* start of struct st_rscan_from_rscan0rmidp */ + union iodefine_reg32_t RMID15; /* RMID15 */ + union iodefine_reg32_t RMPTR15; /* RMPTR15 */ + union iodefine_reg32_t RMDF015; /* RMDF015 */ + union iodefine_reg32_t RMDF115; /* RMDF115 */ + +/* end of struct st_rscan_from_rscan0rmidp */ + +/* start of struct st_rscan_from_rscan0rmidp */ + union iodefine_reg32_t RMID16; /* RMID16 */ + union iodefine_reg32_t RMPTR16; /* RMPTR16 */ + union iodefine_reg32_t RMDF016; /* RMDF016 */ + union iodefine_reg32_t RMDF116; /* RMDF116 */ + +/* end of struct st_rscan_from_rscan0rmidp */ + +/* start of struct st_rscan_from_rscan0rmidp */ + union iodefine_reg32_t RMID17; /* RMID17 */ + union iodefine_reg32_t RMPTR17; /* RMPTR17 */ + union iodefine_reg32_t RMDF017; /* RMDF017 */ + union iodefine_reg32_t RMDF117; /* RMDF117 */ + +/* end of struct st_rscan_from_rscan0rmidp */ + +/* start of struct st_rscan_from_rscan0rmidp */ + union iodefine_reg32_t RMID18; /* RMID18 */ + union iodefine_reg32_t RMPTR18; /* RMPTR18 */ + union iodefine_reg32_t RMDF018; /* RMDF018 */ + union iodefine_reg32_t RMDF118; /* RMDF118 */ + +/* end of struct st_rscan_from_rscan0rmidp */ + +/* start of struct st_rscan_from_rscan0rmidp */ + union iodefine_reg32_t RMID19; /* RMID19 */ + union iodefine_reg32_t RMPTR19; /* RMPTR19 */ + union iodefine_reg32_t RMDF019; /* RMDF019 */ + union iodefine_reg32_t RMDF119; /* RMDF119 */ + +/* end of struct st_rscan_from_rscan0rmidp */ + +/* start of struct st_rscan_from_rscan0rmidp */ + union iodefine_reg32_t RMID20; /* RMID20 */ + union iodefine_reg32_t RMPTR20; /* RMPTR20 */ + union iodefine_reg32_t RMDF020; /* RMDF020 */ + union iodefine_reg32_t RMDF120; /* RMDF120 */ + +/* end of struct st_rscan_from_rscan0rmidp */ + +/* start of struct st_rscan_from_rscan0rmidp */ + union iodefine_reg32_t RMID21; /* RMID21 */ + union iodefine_reg32_t RMPTR21; /* RMPTR21 */ + union iodefine_reg32_t RMDF021; /* RMDF021 */ + union iodefine_reg32_t RMDF121; /* RMDF121 */ + +/* end of struct st_rscan_from_rscan0rmidp */ + +/* start of struct st_rscan_from_rscan0rmidp */ + union iodefine_reg32_t RMID22; /* RMID22 */ + union iodefine_reg32_t RMPTR22; /* RMPTR22 */ + union iodefine_reg32_t RMDF022; /* RMDF022 */ + union iodefine_reg32_t RMDF122; /* RMDF122 */ + +/* end of struct st_rscan_from_rscan0rmidp */ + +/* start of struct st_rscan_from_rscan0rmidp */ + union iodefine_reg32_t RMID23; /* RMID23 */ + union iodefine_reg32_t RMPTR23; /* RMPTR23 */ + union iodefine_reg32_t RMDF023; /* RMDF023 */ + union iodefine_reg32_t RMDF123; /* RMDF123 */ + +/* end of struct st_rscan_from_rscan0rmidp */ + +/* start of struct st_rscan_from_rscan0rmidp */ + union iodefine_reg32_t RMID24; /* RMID24 */ + union iodefine_reg32_t RMPTR24; /* RMPTR24 */ + union iodefine_reg32_t RMDF024; /* RMDF024 */ + union iodefine_reg32_t RMDF124; /* RMDF124 */ + +/* end of struct st_rscan_from_rscan0rmidp */ + +/* start of struct st_rscan_from_rscan0rmidp */ + union iodefine_reg32_t RMID25; /* RMID25 */ + union iodefine_reg32_t RMPTR25; /* RMPTR25 */ + union iodefine_reg32_t RMDF025; /* RMDF025 */ + union iodefine_reg32_t RMDF125; /* RMDF125 */ + +/* end of struct st_rscan_from_rscan0rmidp */ + +/* start of struct st_rscan_from_rscan0rmidp */ + union iodefine_reg32_t RMID26; /* RMID26 */ + union iodefine_reg32_t RMPTR26; /* RMPTR26 */ + union iodefine_reg32_t RMDF026; /* RMDF026 */ + union iodefine_reg32_t RMDF126; /* RMDF126 */ + +/* end of struct st_rscan_from_rscan0rmidp */ + +/* start of struct st_rscan_from_rscan0rmidp */ + union iodefine_reg32_t RMID27; /* RMID27 */ + union iodefine_reg32_t RMPTR27; /* RMPTR27 */ + union iodefine_reg32_t RMDF027; /* RMDF027 */ + union iodefine_reg32_t RMDF127; /* RMDF127 */ + +/* end of struct st_rscan_from_rscan0rmidp */ + +/* start of struct st_rscan_from_rscan0rmidp */ + union iodefine_reg32_t RMID28; /* RMID28 */ + union iodefine_reg32_t RMPTR28; /* RMPTR28 */ + union iodefine_reg32_t RMDF028; /* RMDF028 */ + union iodefine_reg32_t RMDF128; /* RMDF128 */ + +/* end of struct st_rscan_from_rscan0rmidp */ + +/* start of struct st_rscan_from_rscan0rmidp */ + union iodefine_reg32_t RMID29; /* RMID29 */ + union iodefine_reg32_t RMPTR29; /* RMPTR29 */ + union iodefine_reg32_t RMDF029; /* RMDF029 */ + union iodefine_reg32_t RMDF129; /* RMDF129 */ + +/* end of struct st_rscan_from_rscan0rmidp */ + +/* start of struct st_rscan_from_rscan0rmidp */ + union iodefine_reg32_t RMID30; /* RMID30 */ + union iodefine_reg32_t RMPTR30; /* RMPTR30 */ + union iodefine_reg32_t RMDF030; /* RMDF030 */ + union iodefine_reg32_t RMDF130; /* RMDF130 */ + +/* end of struct st_rscan_from_rscan0rmidp */ + +/* start of struct st_rscan_from_rscan0rmidp */ + union iodefine_reg32_t RMID31; /* RMID31 */ + union iodefine_reg32_t RMPTR31; /* RMPTR31 */ + union iodefine_reg32_t RMDF031; /* RMDF031 */ + union iodefine_reg32_t RMDF131; /* RMDF131 */ + +/* end of struct st_rscan_from_rscan0rmidp */ + + volatile uint8_t dummy181[1536]; /* */ + +/* start of struct st_rscan_from_rscan0rfidm */ + union iodefine_reg32_t RFID0; /* RFID0 */ + union iodefine_reg32_t RFPTR0; /* RFPTR0 */ + union iodefine_reg32_t RFDF00; /* RFDF00 */ + union iodefine_reg32_t RFDF10; /* RFDF10 */ + +/* end of struct st_rscan_from_rscan0rfidm */ + +/* start of struct st_rscan_from_rscan0rfidm */ + union iodefine_reg32_t RFID1; /* RFID1 */ + union iodefine_reg32_t RFPTR1; /* RFPTR1 */ + union iodefine_reg32_t RFDF01; /* RFDF01 */ + union iodefine_reg32_t RFDF11; /* RFDF11 */ + +/* end of struct st_rscan_from_rscan0rfidm */ + +/* start of struct st_rscan_from_rscan0rfidm */ + union iodefine_reg32_t RFID2; /* RFID2 */ + union iodefine_reg32_t RFPTR2; /* RFPTR2 */ + union iodefine_reg32_t RFDF02; /* RFDF02 */ + union iodefine_reg32_t RFDF12; /* RFDF12 */ + +/* end of struct st_rscan_from_rscan0rfidm */ + +/* start of struct st_rscan_from_rscan0rfidm */ + union iodefine_reg32_t RFID3; /* RFID3 */ + union iodefine_reg32_t RFPTR3; /* RFPTR3 */ + union iodefine_reg32_t RFDF03; /* RFDF03 */ + union iodefine_reg32_t RFDF13; /* RFDF13 */ + +/* end of struct st_rscan_from_rscan0rfidm */ + +/* start of struct st_rscan_from_rscan0rfidm */ + union iodefine_reg32_t RFID4; /* RFID4 */ + union iodefine_reg32_t RFPTR4; /* RFPTR4 */ + union iodefine_reg32_t RFDF04; /* RFDF04 */ + union iodefine_reg32_t RFDF14; /* RFDF14 */ + +/* end of struct st_rscan_from_rscan0rfidm */ + +/* start of struct st_rscan_from_rscan0rfidm */ + union iodefine_reg32_t RFID5; /* RFID5 */ + union iodefine_reg32_t RFPTR5; /* RFPTR5 */ + union iodefine_reg32_t RFDF05; /* RFDF05 */ + union iodefine_reg32_t RFDF15; /* RFDF15 */ + +/* end of struct st_rscan_from_rscan0rfidm */ + +/* start of struct st_rscan_from_rscan0rfidm */ + union iodefine_reg32_t RFID6; /* RFID6 */ + union iodefine_reg32_t RFPTR6; /* RFPTR6 */ + union iodefine_reg32_t RFDF06; /* RFDF06 */ + union iodefine_reg32_t RFDF16; /* RFDF16 */ + +/* end of struct st_rscan_from_rscan0rfidm */ + +/* start of struct st_rscan_from_rscan0rfidm */ + union iodefine_reg32_t RFID7; /* RFID7 */ + union iodefine_reg32_t RFPTR7; /* RFPTR7 */ + union iodefine_reg32_t RFDF07; /* RFDF07 */ + union iodefine_reg32_t RFDF17; /* RFDF17 */ + +/* end of struct st_rscan_from_rscan0rfidm */ + +/* start of struct st_rscan_from_rscan0cfidm */ + union iodefine_reg32_t CFID0; /* CFID0 */ + union iodefine_reg32_t CFPTR0; /* CFPTR0 */ + union iodefine_reg32_t CFDF00; /* CFDF00 */ + union iodefine_reg32_t CFDF10; /* CFDF10 */ + +/* end of struct st_rscan_from_rscan0cfidm */ + +/* start of struct st_rscan_from_rscan0cfidm */ + union iodefine_reg32_t CFID1; /* CFID1 */ + union iodefine_reg32_t CFPTR1; /* CFPTR1 */ + union iodefine_reg32_t CFDF01; /* CFDF01 */ + union iodefine_reg32_t CFDF11; /* CFDF11 */ + +/* end of struct st_rscan_from_rscan0cfidm */ + +/* start of struct st_rscan_from_rscan0cfidm */ + union iodefine_reg32_t CFID2; /* CFID2 */ + union iodefine_reg32_t CFPTR2; /* CFPTR2 */ + union iodefine_reg32_t CFDF02; /* CFDF02 */ + union iodefine_reg32_t CFDF12; /* CFDF12 */ + +/* end of struct st_rscan_from_rscan0cfidm */ + +/* start of struct st_rscan_from_rscan0cfidm */ + union iodefine_reg32_t CFID3; /* CFID3 */ + union iodefine_reg32_t CFPTR3; /* CFPTR3 */ + union iodefine_reg32_t CFDF03; /* CFDF03 */ + union iodefine_reg32_t CFDF13; /* CFDF13 */ + +/* end of struct st_rscan_from_rscan0cfidm */ + +/* start of struct st_rscan_from_rscan0cfidm */ + union iodefine_reg32_t CFID4; /* CFID4 */ + union iodefine_reg32_t CFPTR4; /* CFPTR4 */ + union iodefine_reg32_t CFDF04; /* CFDF04 */ + union iodefine_reg32_t CFDF14; /* CFDF14 */ + +/* end of struct st_rscan_from_rscan0cfidm */ + +/* start of struct st_rscan_from_rscan0cfidm */ + union iodefine_reg32_t CFID5; /* CFID5 */ + union iodefine_reg32_t CFPTR5; /* CFPTR5 */ + union iodefine_reg32_t CFDF05; /* CFDF05 */ + union iodefine_reg32_t CFDF15; /* CFDF15 */ + +/* end of struct st_rscan_from_rscan0cfidm */ + + volatile uint8_t dummy182[288]; /* */ + +/* start of struct st_rscan_from_rscan0tmidp */ + union iodefine_reg32_t TMID0; /* TMID0 */ + union iodefine_reg32_t TMPTR0; /* TMPTR0 */ + union iodefine_reg32_t TMDF00; /* TMDF00 */ + union iodefine_reg32_t TMDF10; /* TMDF10 */ + +/* end of struct st_rscan_from_rscan0tmidp */ + +/* start of struct st_rscan_from_rscan0tmidp */ + union iodefine_reg32_t TMID1; /* TMID1 */ + union iodefine_reg32_t TMPTR1; /* TMPTR1 */ + union iodefine_reg32_t TMDF01; /* TMDF01 */ + union iodefine_reg32_t TMDF11; /* TMDF11 */ + +/* end of struct st_rscan_from_rscan0tmidp */ + +/* start of struct st_rscan_from_rscan0tmidp */ + union iodefine_reg32_t TMID2; /* TMID2 */ + union iodefine_reg32_t TMPTR2; /* TMPTR2 */ + union iodefine_reg32_t TMDF02; /* TMDF02 */ + union iodefine_reg32_t TMDF12; /* TMDF12 */ + +/* end of struct st_rscan_from_rscan0tmidp */ + +/* start of struct st_rscan_from_rscan0tmidp */ + union iodefine_reg32_t TMID3; /* TMID3 */ + union iodefine_reg32_t TMPTR3; /* TMPTR3 */ + union iodefine_reg32_t TMDF03; /* TMDF03 */ + union iodefine_reg32_t TMDF13; /* TMDF13 */ + +/* end of struct st_rscan_from_rscan0tmidp */ + +/* start of struct st_rscan_from_rscan0tmidp */ + union iodefine_reg32_t TMID4; /* TMID4 */ + union iodefine_reg32_t TMPTR4; /* TMPTR4 */ + union iodefine_reg32_t TMDF04; /* TMDF04 */ + union iodefine_reg32_t TMDF14; /* TMDF14 */ + +/* end of struct st_rscan_from_rscan0tmidp */ + +/* start of struct st_rscan_from_rscan0tmidp */ + union iodefine_reg32_t TMID5; /* TMID5 */ + union iodefine_reg32_t TMPTR5; /* TMPTR5 */ + union iodefine_reg32_t TMDF05; /* TMDF05 */ + union iodefine_reg32_t TMDF15; /* TMDF15 */ + +/* end of struct st_rscan_from_rscan0tmidp */ + +/* start of struct st_rscan_from_rscan0tmidp */ + union iodefine_reg32_t TMID6; /* TMID6 */ + union iodefine_reg32_t TMPTR6; /* TMPTR6 */ + union iodefine_reg32_t TMDF06; /* TMDF06 */ + union iodefine_reg32_t TMDF16; /* TMDF16 */ + +/* end of struct st_rscan_from_rscan0tmidp */ + +/* start of struct st_rscan_from_rscan0tmidp */ + union iodefine_reg32_t TMID7; /* TMID7 */ + union iodefine_reg32_t TMPTR7; /* TMPTR7 */ + union iodefine_reg32_t TMDF07; /* TMDF07 */ + union iodefine_reg32_t TMDF17; /* TMDF17 */ + +/* end of struct st_rscan_from_rscan0tmidp */ + +/* start of struct st_rscan_from_rscan0tmidp */ + union iodefine_reg32_t TMID8; /* TMID8 */ + union iodefine_reg32_t TMPTR8; /* TMPTR8 */ + union iodefine_reg32_t TMDF08; /* TMDF08 */ + union iodefine_reg32_t TMDF18; /* TMDF18 */ + +/* end of struct st_rscan_from_rscan0tmidp */ + +/* start of struct st_rscan_from_rscan0tmidp */ + union iodefine_reg32_t TMID9; /* TMID9 */ + union iodefine_reg32_t TMPTR9; /* TMPTR9 */ + union iodefine_reg32_t TMDF09; /* TMDF09 */ + union iodefine_reg32_t TMDF19; /* TMDF19 */ + +/* end of struct st_rscan_from_rscan0tmidp */ + +/* start of struct st_rscan_from_rscan0tmidp */ + union iodefine_reg32_t TMID10; /* TMID10 */ + union iodefine_reg32_t TMPTR10; /* TMPTR10 */ + union iodefine_reg32_t TMDF010; /* TMDF010 */ + union iodefine_reg32_t TMDF110; /* TMDF110 */ + +/* end of struct st_rscan_from_rscan0tmidp */ + +/* start of struct st_rscan_from_rscan0tmidp */ + union iodefine_reg32_t TMID11; /* TMID11 */ + union iodefine_reg32_t TMPTR11; /* TMPTR11 */ + union iodefine_reg32_t TMDF011; /* TMDF011 */ + union iodefine_reg32_t TMDF111; /* TMDF111 */ + +/* end of struct st_rscan_from_rscan0tmidp */ + +/* start of struct st_rscan_from_rscan0tmidp */ + union iodefine_reg32_t TMID12; /* TMID12 */ + union iodefine_reg32_t TMPTR12; /* TMPTR12 */ + union iodefine_reg32_t TMDF012; /* TMDF012 */ + union iodefine_reg32_t TMDF112; /* TMDF112 */ + +/* end of struct st_rscan_from_rscan0tmidp */ + +/* start of struct st_rscan_from_rscan0tmidp */ + union iodefine_reg32_t TMID13; /* TMID13 */ + union iodefine_reg32_t TMPTR13; /* TMPTR13 */ + union iodefine_reg32_t TMDF013; /* TMDF013 */ + union iodefine_reg32_t TMDF113; /* TMDF113 */ + +/* end of struct st_rscan_from_rscan0tmidp */ + +/* start of struct st_rscan_from_rscan0tmidp */ + union iodefine_reg32_t TMID14; /* TMID14 */ + union iodefine_reg32_t TMPTR14; /* TMPTR14 */ + union iodefine_reg32_t TMDF014; /* TMDF014 */ + union iodefine_reg32_t TMDF114; /* TMDF114 */ + +/* end of struct st_rscan_from_rscan0tmidp */ + +/* start of struct st_rscan_from_rscan0tmidp */ + union iodefine_reg32_t TMID15; /* TMID15 */ + union iodefine_reg32_t TMPTR15; /* TMPTR15 */ + union iodefine_reg32_t TMDF015; /* TMDF015 */ + union iodefine_reg32_t TMDF115; /* TMDF115 */ + +/* end of struct st_rscan_from_rscan0tmidp */ + +/* start of struct st_rscan_from_rscan0tmidp */ + union iodefine_reg32_t TMID16; /* TMID16 */ + union iodefine_reg32_t TMPTR16; /* TMPTR16 */ + union iodefine_reg32_t TMDF016; /* TMDF016 */ + union iodefine_reg32_t TMDF116; /* TMDF116 */ + +/* end of struct st_rscan_from_rscan0tmidp */ + +/* start of struct st_rscan_from_rscan0tmidp */ + union iodefine_reg32_t TMID17; /* TMID17 */ + union iodefine_reg32_t TMPTR17; /* TMPTR17 */ + union iodefine_reg32_t TMDF017; /* TMDF017 */ + union iodefine_reg32_t TMDF117; /* TMDF117 */ + +/* end of struct st_rscan_from_rscan0tmidp */ + +/* start of struct st_rscan_from_rscan0tmidp */ + union iodefine_reg32_t TMID18; /* TMID18 */ + union iodefine_reg32_t TMPTR18; /* TMPTR18 */ + union iodefine_reg32_t TMDF018; /* TMDF018 */ + union iodefine_reg32_t TMDF118; /* TMDF118 */ + +/* end of struct st_rscan_from_rscan0tmidp */ + +/* start of struct st_rscan_from_rscan0tmidp */ + union iodefine_reg32_t TMID19; /* TMID19 */ + union iodefine_reg32_t TMPTR19; /* TMPTR19 */ + union iodefine_reg32_t TMDF019; /* TMDF019 */ + union iodefine_reg32_t TMDF119; /* TMDF119 */ + +/* end of struct st_rscan_from_rscan0tmidp */ + +/* start of struct st_rscan_from_rscan0tmidp */ + union iodefine_reg32_t TMID20; /* TMID20 */ + union iodefine_reg32_t TMPTR20; /* TMPTR20 */ + union iodefine_reg32_t TMDF020; /* TMDF020 */ + union iodefine_reg32_t TMDF120; /* TMDF120 */ + +/* end of struct st_rscan_from_rscan0tmidp */ + +/* start of struct st_rscan_from_rscan0tmidp */ + union iodefine_reg32_t TMID21; /* TMID21 */ + union iodefine_reg32_t TMPTR21; /* TMPTR21 */ + union iodefine_reg32_t TMDF021; /* TMDF021 */ + union iodefine_reg32_t TMDF121; /* TMDF121 */ + +/* end of struct st_rscan_from_rscan0tmidp */ + +/* start of struct st_rscan_from_rscan0tmidp */ + union iodefine_reg32_t TMID22; /* TMID22 */ + union iodefine_reg32_t TMPTR22; /* TMPTR22 */ + union iodefine_reg32_t TMDF022; /* TMDF022 */ + union iodefine_reg32_t TMDF122; /* TMDF122 */ + +/* end of struct st_rscan_from_rscan0tmidp */ + +/* start of struct st_rscan_from_rscan0tmidp */ + union iodefine_reg32_t TMID23; /* TMID23 */ + union iodefine_reg32_t TMPTR23; /* TMPTR23 */ + union iodefine_reg32_t TMDF023; /* TMDF023 */ + union iodefine_reg32_t TMDF123; /* TMDF123 */ + +/* end of struct st_rscan_from_rscan0tmidp */ + +/* start of struct st_rscan_from_rscan0tmidp */ + union iodefine_reg32_t TMID24; /* TMID24 */ + union iodefine_reg32_t TMPTR24; /* TMPTR24 */ + union iodefine_reg32_t TMDF024; /* TMDF024 */ + union iodefine_reg32_t TMDF124; /* TMDF124 */ + +/* end of struct st_rscan_from_rscan0tmidp */ + +/* start of struct st_rscan_from_rscan0tmidp */ + union iodefine_reg32_t TMID25; /* TMID25 */ + union iodefine_reg32_t TMPTR25; /* TMPTR25 */ + union iodefine_reg32_t TMDF025; /* TMDF025 */ + union iodefine_reg32_t TMDF125; /* TMDF125 */ + +/* end of struct st_rscan_from_rscan0tmidp */ + +/* start of struct st_rscan_from_rscan0tmidp */ + union iodefine_reg32_t TMID26; /* TMID26 */ + union iodefine_reg32_t TMPTR26; /* TMPTR26 */ + union iodefine_reg32_t TMDF026; /* TMDF026 */ + union iodefine_reg32_t TMDF126; /* TMDF126 */ + +/* end of struct st_rscan_from_rscan0tmidp */ + +/* start of struct st_rscan_from_rscan0tmidp */ + union iodefine_reg32_t TMID27; /* TMID27 */ + union iodefine_reg32_t TMPTR27; /* TMPTR27 */ + union iodefine_reg32_t TMDF027; /* TMDF027 */ + union iodefine_reg32_t TMDF127; /* TMDF127 */ + +/* end of struct st_rscan_from_rscan0tmidp */ + +/* start of struct st_rscan_from_rscan0tmidp */ + union iodefine_reg32_t TMID28; /* TMID28 */ + union iodefine_reg32_t TMPTR28; /* TMPTR28 */ + union iodefine_reg32_t TMDF028; /* TMDF028 */ + union iodefine_reg32_t TMDF128; /* TMDF128 */ + +/* end of struct st_rscan_from_rscan0tmidp */ + +/* start of struct st_rscan_from_rscan0tmidp */ + union iodefine_reg32_t TMID29; /* TMID29 */ + union iodefine_reg32_t TMPTR29; /* TMPTR29 */ + union iodefine_reg32_t TMDF029; /* TMDF029 */ + union iodefine_reg32_t TMDF129; /* TMDF129 */ + +/* end of struct st_rscan_from_rscan0tmidp */ + +/* start of struct st_rscan_from_rscan0tmidp */ + union iodefine_reg32_t TMID30; /* TMID30 */ + union iodefine_reg32_t TMPTR30; /* TMPTR30 */ + union iodefine_reg32_t TMDF030; /* TMDF030 */ + union iodefine_reg32_t TMDF130; /* TMDF130 */ + +/* end of struct st_rscan_from_rscan0tmidp */ + +/* start of struct st_rscan_from_rscan0tmidp */ + union iodefine_reg32_t TMID31; /* TMID31 */ + union iodefine_reg32_t TMPTR31; /* TMPTR31 */ + union iodefine_reg32_t TMDF031; /* TMDF031 */ + union iodefine_reg32_t TMDF131; /* TMDF131 */ + +/* end of struct st_rscan_from_rscan0tmidp */ + + volatile uint8_t dummy183[1536]; /* */ + +/* #define RSCAN0_THLACC0_COUNT (2) */ + union iodefine_reg32_t THLACC0; /* THLACC0 */ + union iodefine_reg32_t THLACC1; /* THLACC1 */ + +} r_io_rscan0_t; + + +typedef struct st_rscan_from_rscan0cncfg +{ + + union iodefine_reg32_t CnCFG; /* CnCFG */ + union iodefine_reg32_t CnCTR; /* CnCTR */ + union iodefine_reg32_t CnSTS; /* CnSTS */ + union iodefine_reg32_t CnERFL; /* CnERFL */ +} r_io_rscan_from_rscan0cncfg_t; + + +typedef struct st_rscan_from_rscan0gaflidj +{ + + union iodefine_reg32_t GAFLIDj; /* GAFLIDj */ + union iodefine_reg32_t GAFLMj; /* GAFLMj */ + union iodefine_reg32_t GAFLP0j; /* GAFLP0j */ + union iodefine_reg32_t GAFLP1j; /* GAFLP1j */ +} r_io_rscan_from_rscan0gaflidj_t; + + +typedef struct st_rscan_from_rscan0rmidp +{ + + union iodefine_reg32_t RMIDp; /* RMIDp */ + union iodefine_reg32_t RMPTRp; /* RMPTRp */ + union iodefine_reg32_t RMDF0p; /* RMDF0p */ + union iodefine_reg32_t RMDF1p; /* RMDF1p */ +} r_io_rscan_from_rscan0rmidp_t; + + +typedef struct st_rscan_from_rscan0rfidm +{ + + union iodefine_reg32_t RFIDm; /* RFIDm */ + union iodefine_reg32_t RFPTRm; /* RFPTRm */ + union iodefine_reg32_t RFDF0m; /* RFDF0m */ + union iodefine_reg32_t RFDF1m; /* RFDF1m */ +} r_io_rscan_from_rscan0rfidm_t; + + +typedef struct st_rscan_from_rscan0tmidp +{ + + union iodefine_reg32_t TMIDp; /* TMIDp */ + union iodefine_reg32_t TMPTRp; /* TMPTRp */ + union iodefine_reg32_t TMDF0p; /* TMDF0p */ + union iodefine_reg32_t TMDF1p; /* TMDF1p */ +} r_io_rscan_from_rscan0tmidp_t; + + +typedef struct st_rscan_from_rscan0cfidm +{ + + union iodefine_reg32_t CFIDm; /* CFIDm */ + union iodefine_reg32_t CFPTRm; /* CFPTRm */ + union iodefine_reg32_t CFDF0m; /* CFDF0m */ + union iodefine_reg32_t CFDF1m; /* CFDF1m */ +} r_io_rscan_from_rscan0cfidm_t; + + +/* Channel array defines of RSCAN0 (2)*/ +#ifdef DECLARE_RSCAN_FROM_RSCAN0_CFIDm_CHANNELS +volatile struct st_rscan_from_rscan0cfidm* RSCAN_FROM_RSCAN0_CFIDm[ RSCAN_FROM_RSCAN0_CFIDm_COUNT ] = + /* ->MISRA 11.3 */ /* ->SEC R2.7.1 */ + RSCAN_FROM_RSCAN0_CFIDm_ADDRESS_LIST; + /* <-MISRA 11.3 */ /* <-SEC R2.7.1 */ +#endif /* DECLARE_RSCAN_FROM_RSCAN0_CFIDm_CHANNELS */ + +#ifdef DECLARE_RSCAN_FROM_RSCAN0_TMIDp_CHANNELS +volatile struct st_rscan_from_rscan0tmidp* RSCAN_FROM_RSCAN0_TMIDp[ RSCAN_FROM_RSCAN0_TMIDp_COUNT ] = + /* ->MISRA 11.3 */ /* ->SEC R2.7.1 */ + RSCAN_FROM_RSCAN0_TMIDp_ADDRESS_LIST; + /* <-MISRA 11.3 */ /* <-SEC R2.7.1 */ +#endif /* DECLARE_RSCAN_FROM_RSCAN0_TMIDp_CHANNELS */ + +#ifdef DECLARE_RSCAN_FROM_RSCAN0_RFIDm_CHANNELS +volatile struct st_rscan_from_rscan0rfidm* RSCAN_FROM_RSCAN0_RFIDm[ RSCAN_FROM_RSCAN0_RFIDm_COUNT ] = + /* ->MISRA 11.3 */ /* ->SEC R2.7.1 */ + RSCAN_FROM_RSCAN0_RFIDm_ADDRESS_LIST; + /* <-MISRA 11.3 */ /* <-SEC R2.7.1 */ +#endif /* DECLARE_RSCAN_FROM_RSCAN0_RFIDm_CHANNELS */ + +#ifdef DECLARE_RSCAN_FROM_RSCAN0_RMIDp_CHANNELS +volatile struct st_rscan_from_rscan0rmidp* RSCAN_FROM_RSCAN0_RMIDp[ RSCAN_FROM_RSCAN0_RMIDp_COUNT ] = + /* ->MISRA 11.3 */ /* ->SEC R2.7.1 */ + RSCAN_FROM_RSCAN0_RMIDp_ADDRESS_LIST; + /* <-MISRA 11.3 */ /* <-SEC R2.7.1 */ +#endif /* DECLARE_RSCAN_FROM_RSCAN0_RMIDp_CHANNELS */ + +#ifdef DECLARE_RSCAN_FROM_RSCAN0_GAFLIDj_CHANNELS +volatile struct st_rscan_from_rscan0gaflidj* RSCAN_FROM_RSCAN0_GAFLIDj[ RSCAN_FROM_RSCAN0_GAFLIDj_COUNT ] = + /* ->MISRA 11.3 */ /* ->SEC R2.7.1 */ + RSCAN_FROM_RSCAN0_GAFLIDj_ADDRESS_LIST; + /* <-MISRA 11.3 */ /* <-SEC R2.7.1 */ +#endif /* DECLARE_RSCAN_FROM_RSCAN0_GAFLIDj_CHANNELS */ + +#ifdef DECLARE_RSCAN_FROM_RSCAN0_CnCFG_CHANNELS +volatile struct st_rscan_from_rscan0cncfg* RSCAN_FROM_RSCAN0_CnCFG[ RSCAN_FROM_RSCAN0_CnCFG_COUNT ] = + /* ->MISRA 11.3 */ /* ->SEC R2.7.1 */ + RSCAN_FROM_RSCAN0_CnCFG_ADDRESS_LIST; + /* <-MISRA 11.3 */ /* <-SEC R2.7.1 */ +#endif /* DECLARE_RSCAN_FROM_RSCAN0_CnCFG_CHANNELS */ +/* End of channel array defines of RSCAN0 (2)*/ + + +/* <-SEC M1.10.1 */ +/* <-MISRA 18.4 */ /* <-SEC M1.6.2 */ +/* <-QAC 0857 */ +/* <-QAC 0639 */ +#endif diff --git a/targets/TARGET_RENESAS/TARGET_RZ_A1XX/TARGET_GR_LYCHEE/device/inc/iodefines/rspi_iodefine.h b/targets/TARGET_RENESAS/TARGET_RZ_A1XX/TARGET_GR_LYCHEE/device/inc/iodefines/rspi_iodefine.h new file mode 100644 index 0000000..1599b17 --- /dev/null +++ b/targets/TARGET_RENESAS/TARGET_RZ_A1XX/TARGET_GR_LYCHEE/device/inc/iodefines/rspi_iodefine.h @@ -0,0 +1,174 @@ +/******************************************************************************* +* DISCLAIMER +* This software is supplied by Renesas Electronics Corporation and is only +* intended for use with Renesas products. No other uses are authorized. This +* software is owned by Renesas Electronics Corporation and is protected under +* all applicable laws, including copyright laws. +* THIS SOFTWARE IS PROVIDED "AS IS" AND RENESAS MAKES NO WARRANTIES REGARDING +* THIS SOFTWARE, WHETHER EXPRESS, IMPLIED OR STATUTORY, INCLUDING BUT NOT +* LIMITED TO WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE +* AND NON-INFRINGEMENT. ALL SUCH WARRANTIES ARE EXPRESSLY DISCLAIMED. +* TO THE MAXIMUM EXTENT PERMITTED NOT PROHIBITED BY LAW, NEITHER RENESAS +* ELECTRONICS CORPORATION NOR ANY OF ITS AFFILIATED COMPANIES SHALL BE LIABLE +* FOR ANY DIRECT, INDIRECT, SPECIAL, INCIDENTAL OR CONSEQUENTIAL DAMAGES FOR +* ANY REASON RELATED TO THIS SOFTWARE, EVEN IF RENESAS OR ITS AFFILIATES HAVE +* BEEN ADVISED OF THE POSSIBILITY OF SUCH DAMAGES. +* Renesas reserves the right, without notice, to make changes to this software +* and to discontinue the availability of this software. By using this software, +* you agree to the additional terms and conditions found by accessing the +* following link: +* http://www.renesas.com/disclaimer* +* Copyright (C) 2013-2016 Renesas Electronics Corporation. All rights reserved. +*******************************************************************************/ +/******************************************************************************* +* File Name : rspi_iodefine.h +* $Rev: $ +* $Date:: $ +* Description : Definition of I/O Register for RZ/A1LU (V3.00l) +******************************************************************************/ +#ifndef RSPI_IODEFINE_H +#define RSPI_IODEFINE_H +/* ->QAC 0639 : Over 127 members (C90) */ +/* ->QAC 0857 : Over 1024 #define (C90) */ +/* ->MISRA 18.4 : Pack unpack union */ /* ->SEC M1.6.2 */ +/* ->SEC M1.10.1 : Not magic number */ + +#define RSPI0 (*(struct st_rspi *)0xE800C800uL) /* RSPI0 */ +#define RSPI1 (*(struct st_rspi *)0xE800D000uL) /* RSPI1 */ +#define RSPI2 (*(struct st_rspi *)0xE800D800uL) /* RSPI2 */ + + +/* Start of channel array defines of RSPI */ + +/* Channel array defines of RSPI */ +/*(Sample) value = RSPI[ channel ]->SPCR; */ +#define RSPI_COUNT (3) +#define RSPI_ADDRESS_LIST \ +{ /* ->MISRA 11.3 */ /* ->SEC R2.7.1 */ \ + &RSPI0, &RSPI1, &RSPI2 \ +} /* <-MISRA 11.3 */ /* <-SEC R2.7.1 */ /* { } is for MISRA 19.4 */ + +/* End of channel array defines of RSPI */ + + +#define SPCR_0 (RSPI0.SPCR) +#define SSLP_0 (RSPI0.SSLP) +#define SPPCR_0 (RSPI0.SPPCR) +#define SPSR_0 (RSPI0.SPSR) +#define SPDR_0 (RSPI0.SPDR.UINT32) +#define SPDR_0L (RSPI0.SPDR.UINT16[R_IO_L]) +#define SPDR_0H (RSPI0.SPDR.UINT16[R_IO_H]) +#define SPDR_0LL (RSPI0.SPDR.UINT8[R_IO_LL]) +#define SPDR_0LH (RSPI0.SPDR.UINT8[R_IO_LH]) +#define SPDR_0HL (RSPI0.SPDR.UINT8[R_IO_HL]) +#define SPDR_0HH (RSPI0.SPDR.UINT8[R_IO_HH]) +#define SPSCR_0 (RSPI0.SPSCR) +#define SPSSR_0 (RSPI0.SPSSR) +#define SPBR_0 (RSPI0.SPBR) +#define SPDCR_0 (RSPI0.SPDCR) +#define SPCKD_0 (RSPI0.SPCKD) +#define SSLND_0 (RSPI0.SSLND) +#define SPND_0 (RSPI0.SPND) +#define SPCMD0_0 (RSPI0.SPCMD0) +#define SPCMD1_0 (RSPI0.SPCMD1) +#define SPCMD2_0 (RSPI0.SPCMD2) +#define SPCMD3_0 (RSPI0.SPCMD3) +#define SPBFCR_0 (RSPI0.SPBFCR) +#define SPBFDR_0 (RSPI0.SPBFDR) +#define SPCR_1 (RSPI1.SPCR) +#define SSLP_1 (RSPI1.SSLP) +#define SPPCR_1 (RSPI1.SPPCR) +#define SPSR_1 (RSPI1.SPSR) +#define SPDR_1 (RSPI1.SPDR.UINT32) +#define SPDR_1L (RSPI1.SPDR.UINT16[R_IO_L]) +#define SPDR_1H (RSPI1.SPDR.UINT16[R_IO_H]) +#define SPDR_1LL (RSPI1.SPDR.UINT8[R_IO_LL]) +#define SPDR_1LH (RSPI1.SPDR.UINT8[R_IO_LH]) +#define SPDR_1HL (RSPI1.SPDR.UINT8[R_IO_HL]) +#define SPDR_1HH (RSPI1.SPDR.UINT8[R_IO_HH]) +#define SPSCR_1 (RSPI1.SPSCR) +#define SPSSR_1 (RSPI1.SPSSR) +#define SPBR_1 (RSPI1.SPBR) +#define SPDCR_1 (RSPI1.SPDCR) +#define SPCKD_1 (RSPI1.SPCKD) +#define SSLND_1 (RSPI1.SSLND) +#define SPND_1 (RSPI1.SPND) +#define SPCMD0_1 (RSPI1.SPCMD0) +#define SPCMD1_1 (RSPI1.SPCMD1) +#define SPCMD2_1 (RSPI1.SPCMD2) +#define SPCMD3_1 (RSPI1.SPCMD3) +#define SPBFCR_1 (RSPI1.SPBFCR) +#define SPBFDR_1 (RSPI1.SPBFDR) +#define SPCR_2 (RSPI2.SPCR) +#define SSLP_2 (RSPI2.SSLP) +#define SPPCR_2 (RSPI2.SPPCR) +#define SPSR_2 (RSPI2.SPSR) +#define SPDR_2 (RSPI2.SPDR.UINT32) +#define SPDR_2L (RSPI2.SPDR.UINT16[R_IO_L]) +#define SPDR_2H (RSPI2.SPDR.UINT16[R_IO_H]) +#define SPDR_2LL (RSPI2.SPDR.UINT8[R_IO_LL]) +#define SPDR_2LH (RSPI2.SPDR.UINT8[R_IO_LH]) +#define SPDR_2HL (RSPI2.SPDR.UINT8[R_IO_HL]) +#define SPDR_2HH (RSPI2.SPDR.UINT8[R_IO_HH]) +#define SPSCR_2 (RSPI2.SPSCR) +#define SPSSR_2 (RSPI2.SPSSR) +#define SPBR_2 (RSPI2.SPBR) +#define SPDCR_2 (RSPI2.SPDCR) +#define SPCKD_2 (RSPI2.SPCKD) +#define SSLND_2 (RSPI2.SSLND) +#define SPND_2 (RSPI2.SPND) +#define SPCMD0_2 (RSPI2.SPCMD0) +#define SPCMD1_2 (RSPI2.SPCMD1) +#define SPCMD2_2 (RSPI2.SPCMD2) +#define SPCMD3_2 (RSPI2.SPCMD3) +#define SPBFCR_2 (RSPI2.SPBFCR) +#define SPBFDR_2 (RSPI2.SPBFDR) + +#define SPCMD_COUNT (4) + + +typedef struct st_rspi +{ + /* RSPI */ + volatile uint8_t SPCR; /* SPCR */ + volatile uint8_t SSLP; /* SSLP */ + volatile uint8_t SPPCR; /* SPPCR */ + volatile uint8_t SPSR; /* SPSR */ + union iodefine_reg32_t SPDR; /* SPDR */ + + volatile uint8_t SPSCR; /* SPSCR */ + volatile uint8_t SPSSR; /* SPSSR */ + volatile uint8_t SPBR; /* SPBR */ + volatile uint8_t SPDCR; /* SPDCR */ + volatile uint8_t SPCKD; /* SPCKD */ + volatile uint8_t SSLND; /* SSLND */ + volatile uint8_t SPND; /* SPND */ + volatile uint8_t dummy1[1]; /* */ + +/* #define SPCMD_COUNT (4) */ + volatile uint16_t SPCMD0; /* SPCMD0 */ + volatile uint16_t SPCMD1; /* SPCMD1 */ + volatile uint16_t SPCMD2; /* SPCMD2 */ + volatile uint16_t SPCMD3; /* SPCMD3 */ + volatile uint8_t dummy2[8]; /* */ + volatile uint8_t SPBFCR; /* SPBFCR */ + volatile uint8_t dummy3[1]; /* */ + volatile uint16_t SPBFDR; /* SPBFDR */ +} r_io_rspi_t; + + +/* Channel array defines of RSPI (2)*/ +#ifdef DECLARE_RSPI_CHANNELS +volatile struct st_rspi* RSPI[ RSPI_COUNT ] = + /* ->MISRA 11.3 */ /* ->SEC R2.7.1 */ + RSPI_ADDRESS_LIST; + /* <-MISRA 11.3 */ /* <-SEC R2.7.1 */ +#endif /* DECLARE_RSPI_CHANNELS */ +/* End of channel array defines of RSPI (2)*/ + + +/* <-SEC M1.10.1 */ +/* <-MISRA 18.4 */ /* <-SEC M1.6.2 */ +/* <-QAC 0857 */ +/* <-QAC 0639 */ +#endif diff --git a/targets/TARGET_RENESAS/TARGET_RZ_A1XX/TARGET_GR_LYCHEE/device/inc/iodefines/rtc_iodefine.h b/targets/TARGET_RENESAS/TARGET_RZ_A1XX/TARGET_GR_LYCHEE/device/inc/iodefines/rtc_iodefine.h new file mode 100644 index 0000000..345d749 --- /dev/null +++ b/targets/TARGET_RENESAS/TARGET_RZ_A1XX/TARGET_GR_LYCHEE/device/inc/iodefines/rtc_iodefine.h @@ -0,0 +1,111 @@ +/******************************************************************************* +* DISCLAIMER +* This software is supplied by Renesas Electronics Corporation and is only +* intended for use with Renesas products. No other uses are authorized. This +* software is owned by Renesas Electronics Corporation and is protected under +* all applicable laws, including copyright laws. +* THIS SOFTWARE IS PROVIDED "AS IS" AND RENESAS MAKES NO WARRANTIES REGARDING +* THIS SOFTWARE, WHETHER EXPRESS, IMPLIED OR STATUTORY, INCLUDING BUT NOT +* LIMITED TO WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE +* AND NON-INFRINGEMENT. ALL SUCH WARRANTIES ARE EXPRESSLY DISCLAIMED. +* TO THE MAXIMUM EXTENT PERMITTED NOT PROHIBITED BY LAW, NEITHER RENESAS +* ELECTRONICS CORPORATION NOR ANY OF ITS AFFILIATED COMPANIES SHALL BE LIABLE +* FOR ANY DIRECT, INDIRECT, SPECIAL, INCIDENTAL OR CONSEQUENTIAL DAMAGES FOR +* ANY REASON RELATED TO THIS SOFTWARE, EVEN IF RENESAS OR ITS AFFILIATES HAVE +* BEEN ADVISED OF THE POSSIBILITY OF SUCH DAMAGES. +* Renesas reserves the right, without notice, to make changes to this software +* and to discontinue the availability of this software. By using this software, +* you agree to the additional terms and conditions found by accessing the +* following link: +* http://www.renesas.com/disclaimer* +* Copyright (C) 2013-2016 Renesas Electronics Corporation. All rights reserved. +*******************************************************************************/ +/******************************************************************************* +* File Name : rtc_iodefine.h +* $Rev: $ +* $Date:: $ +* Description : Definition of I/O Register for RZ/A1LU (V3.00l) +******************************************************************************/ +#ifndef RTC_IODEFINE_H +#define RTC_IODEFINE_H +/* ->QAC 0639 : Over 127 members (C90) */ +/* ->QAC 0857 : Over 1024 #define (C90) */ +/* ->MISRA 18.4 : Pack unpack union */ /* ->SEC M1.6.2 */ +/* ->SEC M1.10.1 : Not magic number */ + +#define RTC (*(struct st_rtc *)0xFCFF1000uL) /* RTC */ + + +#define RTCR64CNT (RTC.R64CNT) +#define RTCRSECCNT (RTC.RSECCNT) +#define RTCRMINCNT (RTC.RMINCNT) +#define RTCRHRCNT (RTC.RHRCNT) +#define RTCRWKCNT (RTC.RWKCNT) +#define RTCRDAYCNT (RTC.RDAYCNT) +#define RTCRMONCNT (RTC.RMONCNT) +#define RTCRYRCNT (RTC.RYRCNT) +#define RTCRSECAR (RTC.RSECAR) +#define RTCRMINAR (RTC.RMINAR) +#define RTCRHRAR (RTC.RHRAR) +#define RTCRWKAR (RTC.RWKAR) +#define RTCRDAYAR (RTC.RDAYAR) +#define RTCRMONAR (RTC.RMONAR) +#define RTCRCR1 (RTC.RCR1) +#define RTCRCR2 (RTC.RCR2) +#define RTCRYRAR (RTC.RYRAR) +#define RTCRCR3 (RTC.RCR3) +#define RTCRCR5 (RTC.RCR5) +#define RTCRFRH (RTC.RFRH) +#define RTCRFRL (RTC.RFRL) + + +typedef struct st_rtc +{ + /* RTC */ + volatile uint8_t R64CNT; /* R64CNT */ + volatile uint8_t dummy537[1]; /* */ + volatile uint8_t RSECCNT; /* RSECCNT */ + volatile uint8_t dummy538[1]; /* */ + volatile uint8_t RMINCNT; /* RMINCNT */ + volatile uint8_t dummy539[1]; /* */ + volatile uint8_t RHRCNT; /* RHRCNT */ + volatile uint8_t dummy540[1]; /* */ + volatile uint8_t RWKCNT; /* RWKCNT */ + volatile uint8_t dummy541[1]; /* */ + volatile uint8_t RDAYCNT; /* RDAYCNT */ + volatile uint8_t dummy542[1]; /* */ + volatile uint8_t RMONCNT; /* RMONCNT */ + volatile uint8_t dummy543[1]; /* */ + volatile uint16_t RYRCNT; /* RYRCNT */ + volatile uint8_t RSECAR; /* RSECAR */ + volatile uint8_t dummy544[1]; /* */ + volatile uint8_t RMINAR; /* RMINAR */ + volatile uint8_t dummy545[1]; /* */ + volatile uint8_t RHRAR; /* RHRAR */ + volatile uint8_t dummy546[1]; /* */ + volatile uint8_t RWKAR; /* RWKAR */ + volatile uint8_t dummy547[1]; /* */ + volatile uint8_t RDAYAR; /* RDAYAR */ + volatile uint8_t dummy548[1]; /* */ + volatile uint8_t RMONAR; /* RMONAR */ + volatile uint8_t dummy549[1]; /* */ + volatile uint8_t RCR1; /* RCR1 */ + volatile uint8_t dummy550[1]; /* */ + volatile uint8_t RCR2; /* RCR2 */ + volatile uint8_t dummy551[1]; /* */ + volatile uint16_t RYRAR; /* RYRAR */ + volatile uint8_t dummy552[2]; /* */ + volatile uint8_t RCR3; /* RCR3 */ + volatile uint8_t dummy553[1]; /* */ + volatile uint8_t RCR5; /* RCR5 */ + volatile uint8_t dummy554[3]; /* */ + volatile uint16_t RFRH; /* RFRH */ + volatile uint16_t RFRL; /* RFRL */ +} r_io_rtc_t; + + +/* <-SEC M1.10.1 */ +/* <-MISRA 18.4 */ /* <-SEC M1.6.2 */ +/* <-QAC 0857 */ +/* <-QAC 0639 */ +#endif diff --git a/targets/TARGET_RENESAS/TARGET_RZ_A1XX/TARGET_GR_LYCHEE/device/inc/iodefines/scif_iodefine.h b/targets/TARGET_RENESAS/TARGET_RZ_A1XX/TARGET_GR_LYCHEE/device/inc/iodefines/scif_iodefine.h new file mode 100644 index 0000000..0d33c5e --- /dev/null +++ b/targets/TARGET_RENESAS/TARGET_RZ_A1XX/TARGET_GR_LYCHEE/device/inc/iodefines/scif_iodefine.h @@ -0,0 +1,154 @@ +/******************************************************************************* +* DISCLAIMER +* This software is supplied by Renesas Electronics Corporation and is only +* intended for use with Renesas products. No other uses are authorized. This +* software is owned by Renesas Electronics Corporation and is protected under +* all applicable laws, including copyright laws. +* THIS SOFTWARE IS PROVIDED "AS IS" AND RENESAS MAKES NO WARRANTIES REGARDING +* THIS SOFTWARE, WHETHER EXPRESS, IMPLIED OR STATUTORY, INCLUDING BUT NOT +* LIMITED TO WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE +* AND NON-INFRINGEMENT. ALL SUCH WARRANTIES ARE EXPRESSLY DISCLAIMED. +* TO THE MAXIMUM EXTENT PERMITTED NOT PROHIBITED BY LAW, NEITHER RENESAS +* ELECTRONICS CORPORATION NOR ANY OF ITS AFFILIATED COMPANIES SHALL BE LIABLE +* FOR ANY DIRECT, INDIRECT, SPECIAL, INCIDENTAL OR CONSEQUENTIAL DAMAGES FOR +* ANY REASON RELATED TO THIS SOFTWARE, EVEN IF RENESAS OR ITS AFFILIATES HAVE +* BEEN ADVISED OF THE POSSIBILITY OF SUCH DAMAGES. +* Renesas reserves the right, without notice, to make changes to this software +* and to discontinue the availability of this software. By using this software, +* you agree to the additional terms and conditions found by accessing the +* following link: +* http://www.renesas.com/disclaimer* +* Copyright (C) 2013-2016 Renesas Electronics Corporation. All rights reserved. +*******************************************************************************/ +/******************************************************************************* +* File Name : scif_iodefine.h +* $Rev: $ +* $Date:: $ +* Description : Definition of I/O Register for RZ/A1LU (V3.00l) +******************************************************************************/ +#ifndef SCIF_IODEFINE_H +#define SCIF_IODEFINE_H +/* ->QAC 0639 : Over 127 members (C90) */ +/* ->QAC 0857 : Over 1024 #define (C90) */ +/* ->MISRA 18.4 : Pack unpack union */ /* ->SEC M1.6.2 */ +/* ->SEC M1.10.1 : Not magic number */ + +#define SCIF0 (*(struct st_scif *)0xE8007000uL) /* SCIF0 */ +#define SCIF1 (*(struct st_scif *)0xE8007800uL) /* SCIF1 */ +#define SCIF2 (*(struct st_scif *)0xE8008000uL) /* SCIF2 */ +#define SCIF3 (*(struct st_scif *)0xE8008800uL) /* SCIF3 */ +#define SCIF4 (*(struct st_scif *)0xE8009000uL) /* SCIF4 */ + + +/* Start of channel array defines of SCIF */ + +/* Channel array defines of SCIF */ +/*(Sample) value = SCIF[ channel ]->SCSMR; */ +#define SCIF_COUNT (5) +#define SCIF_ADDRESS_LIST \ +{ /* ->MISRA 11.3 */ /* ->SEC R2.7.1 */ \ + &SCIF0, &SCIF1, &SCIF2, &SCIF3, &SCIF4 \ +} /* <-MISRA 11.3 */ /* <-SEC R2.7.1 */ /* { } is for MISRA 19.4 */ + +/* End of channel array defines of SCIF */ + + +#define SCSMR_0 (SCIF0.SCSMR) +#define SCBRR_0 (SCIF0.SCBRR) +#define SCSCR_0 (SCIF0.SCSCR) +#define SCFTDR_0 (SCIF0.SCFTDR) +#define SCFSR_0 (SCIF0.SCFSR) +#define SCFRDR_0 (SCIF0.SCFRDR) +#define SCFCR_0 (SCIF0.SCFCR) +#define SCFDR_0 (SCIF0.SCFDR) +#define SCSPTR_0 (SCIF0.SCSPTR) +#define SCLSR_0 (SCIF0.SCLSR) +#define SCEMR_0 (SCIF0.SCEMR) +#define SCSMR_1 (SCIF1.SCSMR) +#define SCBRR_1 (SCIF1.SCBRR) +#define SCSCR_1 (SCIF1.SCSCR) +#define SCFTDR_1 (SCIF1.SCFTDR) +#define SCFSR_1 (SCIF1.SCFSR) +#define SCFRDR_1 (SCIF1.SCFRDR) +#define SCFCR_1 (SCIF1.SCFCR) +#define SCFDR_1 (SCIF1.SCFDR) +#define SCSPTR_1 (SCIF1.SCSPTR) +#define SCLSR_1 (SCIF1.SCLSR) +#define SCEMR_1 (SCIF1.SCEMR) +#define SCSMR_2 (SCIF2.SCSMR) +#define SCBRR_2 (SCIF2.SCBRR) +#define SCSCR_2 (SCIF2.SCSCR) +#define SCFTDR_2 (SCIF2.SCFTDR) +#define SCFSR_2 (SCIF2.SCFSR) +#define SCFRDR_2 (SCIF2.SCFRDR) +#define SCFCR_2 (SCIF2.SCFCR) +#define SCFDR_2 (SCIF2.SCFDR) +#define SCSPTR_2 (SCIF2.SCSPTR) +#define SCLSR_2 (SCIF2.SCLSR) +#define SCEMR_2 (SCIF2.SCEMR) +#define SCSMR_3 (SCIF3.SCSMR) +#define SCBRR_3 (SCIF3.SCBRR) +#define SCSCR_3 (SCIF3.SCSCR) +#define SCFTDR_3 (SCIF3.SCFTDR) +#define SCFSR_3 (SCIF3.SCFSR) +#define SCFRDR_3 (SCIF3.SCFRDR) +#define SCFCR_3 (SCIF3.SCFCR) +#define SCFDR_3 (SCIF3.SCFDR) +#define SCSPTR_3 (SCIF3.SCSPTR) +#define SCLSR_3 (SCIF3.SCLSR) +#define SCEMR_3 (SCIF3.SCEMR) +#define SCSMR_4 (SCIF4.SCSMR) +#define SCBRR_4 (SCIF4.SCBRR) +#define SCSCR_4 (SCIF4.SCSCR) +#define SCFTDR_4 (SCIF4.SCFTDR) +#define SCFSR_4 (SCIF4.SCFSR) +#define SCFRDR_4 (SCIF4.SCFRDR) +#define SCFCR_4 (SCIF4.SCFCR) +#define SCFDR_4 (SCIF4.SCFDR) +#define SCSPTR_4 (SCIF4.SCSPTR) +#define SCLSR_4 (SCIF4.SCLSR) +#define SCEMR_4 (SCIF4.SCEMR) + + +typedef struct st_scif +{ + /* SCIF */ + volatile uint16_t SCSMR; /* SCSMR */ + volatile uint8_t dummy1[2]; /* */ + volatile uint8_t SCBRR; /* SCBRR */ + volatile uint8_t dummy2[3]; /* */ + volatile uint16_t SCSCR; /* SCSCR */ + volatile uint8_t dummy3[2]; /* */ + volatile uint8_t SCFTDR; /* SCFTDR */ + volatile uint8_t dummy4[3]; /* */ + volatile uint16_t SCFSR; /* SCFSR */ + volatile uint8_t dummy5[2]; /* */ + volatile uint8_t SCFRDR; /* SCFRDR */ + volatile uint8_t dummy6[3]; /* */ + volatile uint16_t SCFCR; /* SCFCR */ + volatile uint8_t dummy7[2]; /* */ + volatile uint16_t SCFDR; /* SCFDR */ + volatile uint8_t dummy8[2]; /* */ + volatile uint16_t SCSPTR; /* SCSPTR */ + volatile uint8_t dummy9[2]; /* */ + volatile uint16_t SCLSR; /* SCLSR */ + volatile uint8_t dummy10[2]; /* */ + volatile uint16_t SCEMR; /* SCEMR */ +} r_io_scif_t; + + +/* Channel array defines of SCIF (2)*/ +#ifdef DECLARE_SCIF_CHANNELS +volatile struct st_scif* SCIF[ SCIF_COUNT ] = + /* ->MISRA 11.3 */ /* ->SEC R2.7.1 */ + SCIF_ADDRESS_LIST; + /* <-MISRA 11.3 */ /* <-SEC R2.7.1 */ +#endif /* DECLARE_SCIF_CHANNELS */ +/* End of channel array defines of SCIF (2)*/ + + +/* <-SEC M1.10.1 */ +/* <-MISRA 18.4 */ /* <-SEC M1.6.2 */ +/* <-QAC 0857 */ +/* <-QAC 0639 */ +#endif diff --git a/targets/TARGET_RENESAS/TARGET_RZ_A1XX/TARGET_GR_LYCHEE/device/inc/iodefines/scim_iodefine.h b/targets/TARGET_RENESAS/TARGET_RZ_A1XX/TARGET_GR_LYCHEE/device/inc/iodefines/scim_iodefine.h new file mode 100644 index 0000000..f612c8c --- /dev/null +++ b/targets/TARGET_RENESAS/TARGET_RZ_A1XX/TARGET_GR_LYCHEE/device/inc/iodefines/scim_iodefine.h @@ -0,0 +1,106 @@ +/******************************************************************************* +* DISCLAIMER +* This software is supplied by Renesas Electronics Corporation and is only +* intended for use with Renesas products. No other uses are authorized. This +* software is owned by Renesas Electronics Corporation and is protected under +* all applicable laws, including copyright laws. +* THIS SOFTWARE IS PROVIDED "AS IS" AND RENESAS MAKES NO WARRANTIES REGARDING +* THIS SOFTWARE, WHETHER EXPRESS, IMPLIED OR STATUTORY, INCLUDING BUT NOT +* LIMITED TO WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE +* AND NON-INFRINGEMENT. ALL SUCH WARRANTIES ARE EXPRESSLY DISCLAIMED. +* TO THE MAXIMUM EXTENT PERMITTED NOT PROHIBITED BY LAW, NEITHER RENESAS +* ELECTRONICS CORPORATION NOR ANY OF ITS AFFILIATED COMPANIES SHALL BE LIABLE +* FOR ANY DIRECT, INDIRECT, SPECIAL, INCIDENTAL OR CONSEQUENTIAL DAMAGES FOR +* ANY REASON RELATED TO THIS SOFTWARE, EVEN IF RENESAS OR ITS AFFILIATES HAVE +* BEEN ADVISED OF THE POSSIBILITY OF SUCH DAMAGES. +* Renesas reserves the right, without notice, to make changes to this software +* and to discontinue the availability of this software. By using this software, +* you agree to the additional terms and conditions found by accessing the +* following link: +* http://www.renesas.com/disclaimer* +* Copyright (C) 2013-2016 Renesas Electronics Corporation. All rights reserved. +*******************************************************************************/ +/******************************************************************************* +* File Name : scim_iodefine.h +* $Rev: $ +* $Date:: $ +* Description : Definition of I/O Register for RZ/A1LU (V3.00l) +******************************************************************************/ +#ifndef SCIM_IODEFINE_H +#define SCIM_IODEFINE_H +/* ->QAC 0639 : Over 127 members (C90) */ +/* ->QAC 0857 : Over 1024 #define (C90) */ +/* ->MISRA 18.4 : Pack unpack union */ /* ->SEC M1.6.2 */ +/* ->SEC M1.10.1 : Not magic number */ + +#define SCIM0 (*(struct st_scim *)0xE800B000uL) /* SCIM0 */ +#define SCIM1 (*(struct st_scim *)0xE800B800uL) /* SCIM1 */ + + +/* Start of channel array defines of SCIM */ + +/* Channel array defines of SCIM */ +/*(Sample) value = SCIM[ channel ]->SMR; */ +#define SCIM_COUNT (2) +#define SCIM_ADDRESS_LIST \ +{ /* ->MISRA 11.3 */ /* ->SEC R2.7.1 */ \ + &SCIM0, &SCIM1 \ +} /* <-MISRA 11.3 */ /* <-SEC R2.7.1 */ /* { } is for MISRA 19.4 */ + +/* End of channel array defines of SCIM */ + + +#define SMR0 (SCIM0.SMR) +#define BRR0 (SCIM0.BRR) +#define SCR0 (SCIM0.SCR) +#define TDR0 (SCIM0.TDR) +#define SSR0 (SCIM0.SSR) +#define RDR0 (SCIM0.RDR) +#define SCMR0 (SCIM0.SCMR) +#define SEMR0 (SCIM0.SEMR) +#define SNFR0 (SCIM0.SNFR) +#define SECR0 (SCIM0.SECR) +#define SMR1 (SCIM1.SMR) +#define BRR1 (SCIM1.BRR) +#define SCR1 (SCIM1.SCR) +#define TDR1 (SCIM1.TDR) +#define SSR1 (SCIM1.SSR) +#define RDR1 (SCIM1.RDR) +#define SCMR1 (SCIM1.SCMR) +#define SEMR1 (SCIM1.SEMR) +#define SNFR1 (SCIM1.SNFR) +#define SECR1 (SCIM1.SECR) + + +typedef struct st_scim +{ + /* SCIM */ + volatile uint8_t SMR; /* SMR */ + volatile uint8_t BRR; /* BRR */ + volatile uint8_t SCR; /* SCR */ + volatile uint8_t TDR; /* TDR */ + volatile uint8_t SSR; /* SSR */ + volatile uint8_t RDR; /* RDR */ + volatile uint8_t SCMR; /* SCMR */ + volatile uint8_t SEMR; /* SEMR */ + volatile uint8_t SNFR; /* SNFR */ + volatile uint8_t dummy1[4]; /* */ + volatile uint8_t SECR; /* SECR */ +} r_io_scim_t; + + +/* Channel array defines of SCIM (2)*/ +#ifdef DECLARE_SCIM_CHANNELS +volatile struct st_scim* SCIM[ SCIM_COUNT ] = + /* ->MISRA 11.3 */ /* ->SEC R2.7.1 */ + SCIM_ADDRESS_LIST; + /* <-MISRA 11.3 */ /* <-SEC R2.7.1 */ +#endif /* DECLARE_SCIM_CHANNELS */ +/* End of channel array defines of SCIM (2)*/ + + +/* <-SEC M1.10.1 */ +/* <-MISRA 18.4 */ /* <-SEC M1.6.2 */ +/* <-QAC 0857 */ +/* <-QAC 0639 */ +#endif diff --git a/targets/TARGET_RENESAS/TARGET_RZ_A1XX/TARGET_GR_LYCHEE/device/inc/iodefines/scux_iodefine.h b/targets/TARGET_RENESAS/TARGET_RZ_A1XX/TARGET_GR_LYCHEE/device/inc/iodefines/scux_iodefine.h new file mode 100644 index 0000000..7d8c666 --- /dev/null +++ b/targets/TARGET_RENESAS/TARGET_RZ_A1XX/TARGET_GR_LYCHEE/device/inc/iodefines/scux_iodefine.h @@ -0,0 +1,921 @@ +/******************************************************************************* +* DISCLAIMER +* This software is supplied by Renesas Electronics Corporation and is only +* intended for use with Renesas products. No other uses are authorized. This +* software is owned by Renesas Electronics Corporation and is protected under +* all applicable laws, including copyright laws. +* THIS SOFTWARE IS PROVIDED "AS IS" AND RENESAS MAKES NO WARRANTIES REGARDING +* THIS SOFTWARE, WHETHER EXPRESS, IMPLIED OR STATUTORY, INCLUDING BUT NOT +* LIMITED TO WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE +* AND NON-INFRINGEMENT. ALL SUCH WARRANTIES ARE EXPRESSLY DISCLAIMED. +* TO THE MAXIMUM EXTENT PERMITTED NOT PROHIBITED BY LAW, NEITHER RENESAS +* ELECTRONICS CORPORATION NOR ANY OF ITS AFFILIATED COMPANIES SHALL BE LIABLE +* FOR ANY DIRECT, INDIRECT, SPECIAL, INCIDENTAL OR CONSEQUENTIAL DAMAGES FOR +* ANY REASON RELATED TO THIS SOFTWARE, EVEN IF RENESAS OR ITS AFFILIATES HAVE +* BEEN ADVISED OF THE POSSIBILITY OF SUCH DAMAGES. +* Renesas reserves the right, without notice, to make changes to this software +* and to discontinue the availability of this software. By using this software, +* you agree to the additional terms and conditions found by accessing the +* following link: +* http://www.renesas.com/disclaimer* +* Copyright (C) 2013-2016 Renesas Electronics Corporation. All rights reserved. +*******************************************************************************/ +/******************************************************************************* +* File Name : scux_iodefine.h +* $Rev: $ +* $Date:: $ +* Description : Definition of I/O Register for RZ/A1LU (V3.00l) +******************************************************************************/ +#ifndef SCUX_IODEFINE_H +#define SCUX_IODEFINE_H +/* ->QAC 0639 : Over 127 members (C90) */ +/* ->QAC 0857 : Over 1024 #define (C90) */ +/* ->MISRA 18.4 : Pack unpack union */ /* ->SEC M1.6.2 */ +/* ->SEC M1.10.1 : Not magic number */ + +#define SCUX (*(struct st_scux *)0xE8208000uL) /* SCUX */ + + +/* Start of channel array defines of SCUX */ + +/* Channel array defines of SCUX_FROM_DVUIR_DVU0_0_ARRAY */ +/*(Sample) value = SCUX_FROM_DVUIR_DVU0_0_ARRAY[ channel ]->DVUIR_DVU0_0; */ +#define SCUX_FROM_DVUIR_DVU0_0_ARRAY_COUNT (4) +#define SCUX_FROM_DVUIR_DVU0_0_ARRAY_ADDRESS_LIST \ +{ /* ->MISRA 11.3 */ /* ->SEC R2.7.1 */ \ + &SCUX_FROM_DVUIR_DVU0_0, &SCUX_FROM_DVUIR_DVU0_1, &SCUX_FROM_DVUIR_DVU0_2, &SCUX_FROM_DVUIR_DVU0_3 \ +} /* <-MISRA 11.3 */ /* <-SEC R2.7.1 */ /* { } is for MISRA 19.4 */ +#define SCUX_FROM_DVUIR_DVU0_0 (*(struct st_scux_from_dvuir_dvu0_n *)&SCUX.DVUIR_DVU0_0) /* SCUX_FROM_DVUIR_DVU0_0 */ +#define SCUX_FROM_DVUIR_DVU0_1 (*(struct st_scux_from_dvuir_dvu0_n *)&SCUX.DVUIR_DVU0_1) /* SCUX_FROM_DVUIR_DVU0_1 */ +#define SCUX_FROM_DVUIR_DVU0_2 (*(struct st_scux_from_dvuir_dvu0_n *)&SCUX.DVUIR_DVU0_2) /* SCUX_FROM_DVUIR_DVU0_2 */ +#define SCUX_FROM_DVUIR_DVU0_3 (*(struct st_scux_from_dvuir_dvu0_n *)&SCUX.DVUIR_DVU0_3) /* SCUX_FROM_DVUIR_DVU0_3 */ + + +/* Channel array defines of SCUX_FROM_SRCIR0_2SRC0_0_ARRAY */ +/*(Sample) value = SCUX_FROM_SRCIR0_2SRC0_0_ARRAY[ channel ]->SRCIR0_2SRC0_0; */ +#define SCUX_FROM_SRCIR0_2SRC0_0_ARRAY_COUNT (2) +#define SCUX_FROM_SRCIR0_2SRC0_0_ARRAY_ADDRESS_LIST \ +{ /* ->MISRA 11.3 */ /* ->SEC R2.7.1 */ \ + &SCUX_FROM_SRCIR0_2SRC0_0, &SCUX_FROM_SRCIR0_2SRC0_1 \ +} /* <-MISRA 11.3 */ /* <-SEC R2.7.1 */ /* { } is for MISRA 19.4 */ +#define SCUX_FROM_SRCIR0_2SRC0_0 (*(struct st_scux_from_srcir0_2src0_n *)&SCUX.SRCIR0_2SRC0_0) /* SCUX_FROM_SRCIR0_2SRC0_0 */ +#define SCUX_FROM_SRCIR0_2SRC0_1 (*(struct st_scux_from_srcir0_2src0_n *)&SCUX.SRCIR0_2SRC0_1) /* SCUX_FROM_SRCIR0_2SRC0_1 */ + + +/* Channel array defines of SCUX_FROM_FFUIR_FFU0_0_ARRAY */ +/*(Sample) value = SCUX_FROM_FFUIR_FFU0_0_ARRAY[ channel ]->FFUIR_FFU0_0; */ +#define SCUX_FROM_FFUIR_FFU0_0_ARRAY_COUNT (4) +#define SCUX_FROM_FFUIR_FFU0_0_ARRAY_ADDRESS_LIST \ +{ /* ->MISRA 11.3 */ /* ->SEC R2.7.1 */ \ + &SCUX_FROM_FFUIR_FFU0_0, &SCUX_FROM_FFUIR_FFU0_1, &SCUX_FROM_FFUIR_FFU0_2, &SCUX_FROM_FFUIR_FFU0_3 \ +} /* <-MISRA 11.3 */ /* <-SEC R2.7.1 */ /* { } is for MISRA 19.4 */ +#define SCUX_FROM_FFUIR_FFU0_0 (*(struct st_scux_from_ffuir_ffu0_n *)&SCUX.FFUIR_FFU0_0) /* SCUX_FROM_FFUIR_FFU0_0 */ +#define SCUX_FROM_FFUIR_FFU0_1 (*(struct st_scux_from_ffuir_ffu0_n *)&SCUX.FFUIR_FFU0_1) /* SCUX_FROM_FFUIR_FFU0_1 */ +#define SCUX_FROM_FFUIR_FFU0_2 (*(struct st_scux_from_ffuir_ffu0_n *)&SCUX.FFUIR_FFU0_2) /* SCUX_FROM_FFUIR_FFU0_2 */ +#define SCUX_FROM_FFUIR_FFU0_3 (*(struct st_scux_from_ffuir_ffu0_n *)&SCUX.FFUIR_FFU0_3) /* SCUX_FROM_FFUIR_FFU0_3 */ + + +/* Channel array defines of SCUX_FROM_FFDIR_FFD0_0_ARRAY */ +/*(Sample) value = SCUX_FROM_FFDIR_FFD0_0_ARRAY[ channel ]->FFDIR_FFD0_0; */ +#define SCUX_FROM_FFDIR_FFD0_0_ARRAY_COUNT (4) +#define SCUX_FROM_FFDIR_FFD0_0_ARRAY_ADDRESS_LIST \ +{ /* ->MISRA 11.3 */ /* ->SEC R2.7.1 */ \ + &SCUX_FROM_FFDIR_FFD0_0, &SCUX_FROM_FFDIR_FFD0_1, &SCUX_FROM_FFDIR_FFD0_2, &SCUX_FROM_FFDIR_FFD0_3 \ +} /* <-MISRA 11.3 */ /* <-SEC R2.7.1 */ /* { } is for MISRA 19.4 */ +#define SCUX_FROM_FFDIR_FFD0_0 (*(struct st_scux_from_ffdir_ffd0_n *)&SCUX.FFDIR_FFD0_0) /* SCUX_FROM_FFDIR_FFD0_0 */ +#define SCUX_FROM_FFDIR_FFD0_1 (*(struct st_scux_from_ffdir_ffd0_n *)&SCUX.FFDIR_FFD0_1) /* SCUX_FROM_FFDIR_FFD0_1 */ +#define SCUX_FROM_FFDIR_FFD0_2 (*(struct st_scux_from_ffdir_ffd0_n *)&SCUX.FFDIR_FFD0_2) /* SCUX_FROM_FFDIR_FFD0_2 */ +#define SCUX_FROM_FFDIR_FFD0_3 (*(struct st_scux_from_ffdir_ffd0_n *)&SCUX.FFDIR_FFD0_3) /* SCUX_FROM_FFDIR_FFD0_3 */ + + +/* Channel array defines of SCUX_FROM_OPCIR_OPC0_0_ARRAY */ +/*(Sample) value = SCUX_FROM_OPCIR_OPC0_0_ARRAY[ channel ]->OPCIR_OPC0_0; */ +#define SCUX_FROM_OPCIR_OPC0_0_ARRAY_COUNT (4) +#define SCUX_FROM_OPCIR_OPC0_0_ARRAY_ADDRESS_LIST \ +{ /* ->MISRA 11.3 */ /* ->SEC R2.7.1 */ \ + &SCUX_FROM_OPCIR_OPC0_0, &SCUX_FROM_OPCIR_OPC0_1, &SCUX_FROM_OPCIR_OPC0_2, &SCUX_FROM_OPCIR_OPC0_3 \ +} /* <-MISRA 11.3 */ /* <-SEC R2.7.1 */ /* { } is for MISRA 19.4 */ +#define SCUX_FROM_OPCIR_OPC0_0 (*(struct st_scux_from_opcir_opc0_n *)&SCUX.OPCIR_OPC0_0) /* SCUX_FROM_OPCIR_OPC0_0 */ +#define SCUX_FROM_OPCIR_OPC0_1 (*(struct st_scux_from_opcir_opc0_n *)&SCUX.OPCIR_OPC0_1) /* SCUX_FROM_OPCIR_OPC0_1 */ +#define SCUX_FROM_OPCIR_OPC0_2 (*(struct st_scux_from_opcir_opc0_n *)&SCUX.OPCIR_OPC0_2) /* SCUX_FROM_OPCIR_OPC0_2 */ +#define SCUX_FROM_OPCIR_OPC0_3 (*(struct st_scux_from_opcir_opc0_n *)&SCUX.OPCIR_OPC0_3) /* SCUX_FROM_OPCIR_OPC0_3 */ + + +/* Channel array defines of SCUX_FROM_IPCIR_IPC0_0_ARRAY */ +/*(Sample) value = SCUX_FROM_IPCIR_IPC0_0_ARRAY[ channel ]->IPCIR_IPC0_0; */ +#define SCUX_FROM_IPCIR_IPC0_0_ARRAY_COUNT (4) +#define SCUX_FROM_IPCIR_IPC0_0_ARRAY_ADDRESS_LIST \ +{ /* ->MISRA 11.3 */ /* ->SEC R2.7.1 */ \ + &SCUX_FROM_IPCIR_IPC0_0, &SCUX_FROM_IPCIR_IPC0_1, &SCUX_FROM_IPCIR_IPC0_2, &SCUX_FROM_IPCIR_IPC0_3 \ +} /* <-MISRA 11.3 */ /* <-SEC R2.7.1 */ /* { } is for MISRA 19.4 */ +#define SCUX_FROM_IPCIR_IPC0_0 (*(struct st_scux_from_ipcir_ipc0_n *)&SCUX.IPCIR_IPC0_0) /* SCUX_FROM_IPCIR_IPC0_0 */ +#define SCUX_FROM_IPCIR_IPC0_1 (*(struct st_scux_from_ipcir_ipc0_n *)&SCUX.IPCIR_IPC0_1) /* SCUX_FROM_IPCIR_IPC0_1 */ +#define SCUX_FROM_IPCIR_IPC0_2 (*(struct st_scux_from_ipcir_ipc0_n *)&SCUX.IPCIR_IPC0_2) /* SCUX_FROM_IPCIR_IPC0_2 */ +#define SCUX_FROM_IPCIR_IPC0_3 (*(struct st_scux_from_ipcir_ipc0_n *)&SCUX.IPCIR_IPC0_3) /* SCUX_FROM_IPCIR_IPC0_3 */ + +/* End of channel array defines of SCUX */ + + +#define SCUXIPCIR_IPC0_0 (SCUX.IPCIR_IPC0_0) +#define SCUXIPSLR_IPC0_0 (SCUX.IPSLR_IPC0_0) +#define SCUXIPCIR_IPC0_1 (SCUX.IPCIR_IPC0_1) +#define SCUXIPSLR_IPC0_1 (SCUX.IPSLR_IPC0_1) +#define SCUXIPCIR_IPC0_2 (SCUX.IPCIR_IPC0_2) +#define SCUXIPSLR_IPC0_2 (SCUX.IPSLR_IPC0_2) +#define SCUXIPCIR_IPC0_3 (SCUX.IPCIR_IPC0_3) +#define SCUXIPSLR_IPC0_3 (SCUX.IPSLR_IPC0_3) +#define SCUXOPCIR_OPC0_0 (SCUX.OPCIR_OPC0_0) +#define SCUXOPSLR_OPC0_0 (SCUX.OPSLR_OPC0_0) +#define SCUXOPCIR_OPC0_1 (SCUX.OPCIR_OPC0_1) +#define SCUXOPSLR_OPC0_1 (SCUX.OPSLR_OPC0_1) +#define SCUXOPCIR_OPC0_2 (SCUX.OPCIR_OPC0_2) +#define SCUXOPSLR_OPC0_2 (SCUX.OPSLR_OPC0_2) +#define SCUXOPCIR_OPC0_3 (SCUX.OPCIR_OPC0_3) +#define SCUXOPSLR_OPC0_3 (SCUX.OPSLR_OPC0_3) +#define SCUXFFDIR_FFD0_0 (SCUX.FFDIR_FFD0_0) +#define SCUXFDAIR_FFD0_0 (SCUX.FDAIR_FFD0_0) +#define SCUXDRQSR_FFD0_0 (SCUX.DRQSR_FFD0_0) +#define SCUXFFDPR_FFD0_0 (SCUX.FFDPR_FFD0_0) +#define SCUXFFDBR_FFD0_0 (SCUX.FFDBR_FFD0_0) +#define SCUXDEVMR_FFD0_0 (SCUX.DEVMR_FFD0_0) +#define SCUXDEVCR_FFD0_0 (SCUX.DEVCR_FFD0_0) +#define SCUXFFDIR_FFD0_1 (SCUX.FFDIR_FFD0_1) +#define SCUXFDAIR_FFD0_1 (SCUX.FDAIR_FFD0_1) +#define SCUXDRQSR_FFD0_1 (SCUX.DRQSR_FFD0_1) +#define SCUXFFDPR_FFD0_1 (SCUX.FFDPR_FFD0_1) +#define SCUXFFDBR_FFD0_1 (SCUX.FFDBR_FFD0_1) +#define SCUXDEVMR_FFD0_1 (SCUX.DEVMR_FFD0_1) +#define SCUXDEVCR_FFD0_1 (SCUX.DEVCR_FFD0_1) +#define SCUXFFDIR_FFD0_2 (SCUX.FFDIR_FFD0_2) +#define SCUXFDAIR_FFD0_2 (SCUX.FDAIR_FFD0_2) +#define SCUXDRQSR_FFD0_2 (SCUX.DRQSR_FFD0_2) +#define SCUXFFDPR_FFD0_2 (SCUX.FFDPR_FFD0_2) +#define SCUXFFDBR_FFD0_2 (SCUX.FFDBR_FFD0_2) +#define SCUXDEVMR_FFD0_2 (SCUX.DEVMR_FFD0_2) +#define SCUXDEVCR_FFD0_2 (SCUX.DEVCR_FFD0_2) +#define SCUXFFDIR_FFD0_3 (SCUX.FFDIR_FFD0_3) +#define SCUXFDAIR_FFD0_3 (SCUX.FDAIR_FFD0_3) +#define SCUXDRQSR_FFD0_3 (SCUX.DRQSR_FFD0_3) +#define SCUXFFDPR_FFD0_3 (SCUX.FFDPR_FFD0_3) +#define SCUXFFDBR_FFD0_3 (SCUX.FFDBR_FFD0_3) +#define SCUXDEVMR_FFD0_3 (SCUX.DEVMR_FFD0_3) +#define SCUXDEVCR_FFD0_3 (SCUX.DEVCR_FFD0_3) +#define SCUXFFUIR_FFU0_0 (SCUX.FFUIR_FFU0_0) +#define SCUXFUAIR_FFU0_0 (SCUX.FUAIR_FFU0_0) +#define SCUXURQSR_FFU0_0 (SCUX.URQSR_FFU0_0) +#define SCUXFFUPR_FFU0_0 (SCUX.FFUPR_FFU0_0) +#define SCUXUEVMR_FFU0_0 (SCUX.UEVMR_FFU0_0) +#define SCUXUEVCR_FFU0_0 (SCUX.UEVCR_FFU0_0) +#define SCUXFFUIR_FFU0_1 (SCUX.FFUIR_FFU0_1) +#define SCUXFUAIR_FFU0_1 (SCUX.FUAIR_FFU0_1) +#define SCUXURQSR_FFU0_1 (SCUX.URQSR_FFU0_1) +#define SCUXFFUPR_FFU0_1 (SCUX.FFUPR_FFU0_1) +#define SCUXUEVMR_FFU0_1 (SCUX.UEVMR_FFU0_1) +#define SCUXUEVCR_FFU0_1 (SCUX.UEVCR_FFU0_1) +#define SCUXFFUIR_FFU0_2 (SCUX.FFUIR_FFU0_2) +#define SCUXFUAIR_FFU0_2 (SCUX.FUAIR_FFU0_2) +#define SCUXURQSR_FFU0_2 (SCUX.URQSR_FFU0_2) +#define SCUXFFUPR_FFU0_2 (SCUX.FFUPR_FFU0_2) +#define SCUXUEVMR_FFU0_2 (SCUX.UEVMR_FFU0_2) +#define SCUXUEVCR_FFU0_2 (SCUX.UEVCR_FFU0_2) +#define SCUXFFUIR_FFU0_3 (SCUX.FFUIR_FFU0_3) +#define SCUXFUAIR_FFU0_3 (SCUX.FUAIR_FFU0_3) +#define SCUXURQSR_FFU0_3 (SCUX.URQSR_FFU0_3) +#define SCUXFFUPR_FFU0_3 (SCUX.FFUPR_FFU0_3) +#define SCUXUEVMR_FFU0_3 (SCUX.UEVMR_FFU0_3) +#define SCUXUEVCR_FFU0_3 (SCUX.UEVCR_FFU0_3) +#define SCUXSRCIR0_2SRC0_0 (SCUX.SRCIR0_2SRC0_0) +#define SCUXSADIR0_2SRC0_0 (SCUX.SADIR0_2SRC0_0) +#define SCUXSRCBR0_2SRC0_0 (SCUX.SRCBR0_2SRC0_0) +#define SCUXIFSCR0_2SRC0_0 (SCUX.IFSCR0_2SRC0_0) +#define SCUXIFSVR0_2SRC0_0 (SCUX.IFSVR0_2SRC0_0) +#define SCUXSRCCR0_2SRC0_0 (SCUX.SRCCR0_2SRC0_0) +#define SCUXMNFSR0_2SRC0_0 (SCUX.MNFSR0_2SRC0_0) +#define SCUXBFSSR0_2SRC0_0 (SCUX.BFSSR0_2SRC0_0) +#define SCUXSC2SR0_2SRC0_0 (SCUX.SC2SR0_2SRC0_0) +#define SCUXWATSR0_2SRC0_0 (SCUX.WATSR0_2SRC0_0) +#define SCUXSEVMR0_2SRC0_0 (SCUX.SEVMR0_2SRC0_0) +#define SCUXSEVCR0_2SRC0_0 (SCUX.SEVCR0_2SRC0_0) +#define SCUXSRCIR1_2SRC0_0 (SCUX.SRCIR1_2SRC0_0) +#define SCUXSADIR1_2SRC0_0 (SCUX.SADIR1_2SRC0_0) +#define SCUXSRCBR1_2SRC0_0 (SCUX.SRCBR1_2SRC0_0) +#define SCUXIFSCR1_2SRC0_0 (SCUX.IFSCR1_2SRC0_0) +#define SCUXIFSVR1_2SRC0_0 (SCUX.IFSVR1_2SRC0_0) +#define SCUXSRCCR1_2SRC0_0 (SCUX.SRCCR1_2SRC0_0) +#define SCUXMNFSR1_2SRC0_0 (SCUX.MNFSR1_2SRC0_0) +#define SCUXBFSSR1_2SRC0_0 (SCUX.BFSSR1_2SRC0_0) +#define SCUXSC2SR1_2SRC0_0 (SCUX.SC2SR1_2SRC0_0) +#define SCUXWATSR1_2SRC0_0 (SCUX.WATSR1_2SRC0_0) +#define SCUXSEVMR1_2SRC0_0 (SCUX.SEVMR1_2SRC0_0) +#define SCUXSEVCR1_2SRC0_0 (SCUX.SEVCR1_2SRC0_0) +#define SCUXSRCIRR_2SRC0_0 (SCUX.SRCIRR_2SRC0_0) +#define SCUXSRCIR0_2SRC0_1 (SCUX.SRCIR0_2SRC0_1) +#define SCUXSADIR0_2SRC0_1 (SCUX.SADIR0_2SRC0_1) +#define SCUXSRCBR0_2SRC0_1 (SCUX.SRCBR0_2SRC0_1) +#define SCUXIFSCR0_2SRC0_1 (SCUX.IFSCR0_2SRC0_1) +#define SCUXIFSVR0_2SRC0_1 (SCUX.IFSVR0_2SRC0_1) +#define SCUXSRCCR0_2SRC0_1 (SCUX.SRCCR0_2SRC0_1) +#define SCUXMNFSR0_2SRC0_1 (SCUX.MNFSR0_2SRC0_1) +#define SCUXBFSSR0_2SRC0_1 (SCUX.BFSSR0_2SRC0_1) +#define SCUXSC2SR0_2SRC0_1 (SCUX.SC2SR0_2SRC0_1) +#define SCUXWATSR0_2SRC0_1 (SCUX.WATSR0_2SRC0_1) +#define SCUXSEVMR0_2SRC0_1 (SCUX.SEVMR0_2SRC0_1) +#define SCUXSEVCR0_2SRC0_1 (SCUX.SEVCR0_2SRC0_1) +#define SCUXSRCIR1_2SRC0_1 (SCUX.SRCIR1_2SRC0_1) +#define SCUXSADIR1_2SRC0_1 (SCUX.SADIR1_2SRC0_1) +#define SCUXSRCBR1_2SRC0_1 (SCUX.SRCBR1_2SRC0_1) +#define SCUXIFSCR1_2SRC0_1 (SCUX.IFSCR1_2SRC0_1) +#define SCUXIFSVR1_2SRC0_1 (SCUX.IFSVR1_2SRC0_1) +#define SCUXSRCCR1_2SRC0_1 (SCUX.SRCCR1_2SRC0_1) +#define SCUXMNFSR1_2SRC0_1 (SCUX.MNFSR1_2SRC0_1) +#define SCUXBFSSR1_2SRC0_1 (SCUX.BFSSR1_2SRC0_1) +#define SCUXSC2SR1_2SRC0_1 (SCUX.SC2SR1_2SRC0_1) +#define SCUXWATSR1_2SRC0_1 (SCUX.WATSR1_2SRC0_1) +#define SCUXSEVMR1_2SRC0_1 (SCUX.SEVMR1_2SRC0_1) +#define SCUXSEVCR1_2SRC0_1 (SCUX.SEVCR1_2SRC0_1) +#define SCUXSRCIRR_2SRC0_1 (SCUX.SRCIRR_2SRC0_1) +#define SCUXDVUIR_DVU0_0 (SCUX.DVUIR_DVU0_0) +#define SCUXVADIR_DVU0_0 (SCUX.VADIR_DVU0_0) +#define SCUXDVUBR_DVU0_0 (SCUX.DVUBR_DVU0_0) +#define SCUXDVUCR_DVU0_0 (SCUX.DVUCR_DVU0_0) +#define SCUXZCMCR_DVU0_0 (SCUX.ZCMCR_DVU0_0) +#define SCUXVRCTR_DVU0_0 (SCUX.VRCTR_DVU0_0) +#define SCUXVRPDR_DVU0_0 (SCUX.VRPDR_DVU0_0) +#define SCUXVRDBR_DVU0_0 (SCUX.VRDBR_DVU0_0) +#define SCUXVRWTR_DVU0_0 (SCUX.VRWTR_DVU0_0) +#define SCUXVOL0R_DVU0_0 (SCUX.VOL0R_DVU0_0) +#define SCUXVOL1R_DVU0_0 (SCUX.VOL1R_DVU0_0) +#define SCUXVOL2R_DVU0_0 (SCUX.VOL2R_DVU0_0) +#define SCUXVOL3R_DVU0_0 (SCUX.VOL3R_DVU0_0) +#define SCUXVOL4R_DVU0_0 (SCUX.VOL4R_DVU0_0) +#define SCUXVOL5R_DVU0_0 (SCUX.VOL5R_DVU0_0) +#define SCUXVOL6R_DVU0_0 (SCUX.VOL6R_DVU0_0) +#define SCUXVOL7R_DVU0_0 (SCUX.VOL7R_DVU0_0) +#define SCUXDVUER_DVU0_0 (SCUX.DVUER_DVU0_0) +#define SCUXDVUSR_DVU0_0 (SCUX.DVUSR_DVU0_0) +#define SCUXVEVMR_DVU0_0 (SCUX.VEVMR_DVU0_0) +#define SCUXVEVCR_DVU0_0 (SCUX.VEVCR_DVU0_0) +#define SCUXDVUIR_DVU0_1 (SCUX.DVUIR_DVU0_1) +#define SCUXVADIR_DVU0_1 (SCUX.VADIR_DVU0_1) +#define SCUXDVUBR_DVU0_1 (SCUX.DVUBR_DVU0_1) +#define SCUXDVUCR_DVU0_1 (SCUX.DVUCR_DVU0_1) +#define SCUXZCMCR_DVU0_1 (SCUX.ZCMCR_DVU0_1) +#define SCUXVRCTR_DVU0_1 (SCUX.VRCTR_DVU0_1) +#define SCUXVRPDR_DVU0_1 (SCUX.VRPDR_DVU0_1) +#define SCUXVRDBR_DVU0_1 (SCUX.VRDBR_DVU0_1) +#define SCUXVRWTR_DVU0_1 (SCUX.VRWTR_DVU0_1) +#define SCUXVOL0R_DVU0_1 (SCUX.VOL0R_DVU0_1) +#define SCUXVOL1R_DVU0_1 (SCUX.VOL1R_DVU0_1) +#define SCUXVOL2R_DVU0_1 (SCUX.VOL2R_DVU0_1) +#define SCUXVOL3R_DVU0_1 (SCUX.VOL3R_DVU0_1) +#define SCUXVOL4R_DVU0_1 (SCUX.VOL4R_DVU0_1) +#define SCUXVOL5R_DVU0_1 (SCUX.VOL5R_DVU0_1) +#define SCUXVOL6R_DVU0_1 (SCUX.VOL6R_DVU0_1) +#define SCUXVOL7R_DVU0_1 (SCUX.VOL7R_DVU0_1) +#define SCUXDVUER_DVU0_1 (SCUX.DVUER_DVU0_1) +#define SCUXDVUSR_DVU0_1 (SCUX.DVUSR_DVU0_1) +#define SCUXVEVMR_DVU0_1 (SCUX.VEVMR_DVU0_1) +#define SCUXVEVCR_DVU0_1 (SCUX.VEVCR_DVU0_1) +#define SCUXDVUIR_DVU0_2 (SCUX.DVUIR_DVU0_2) +#define SCUXVADIR_DVU0_2 (SCUX.VADIR_DVU0_2) +#define SCUXDVUBR_DVU0_2 (SCUX.DVUBR_DVU0_2) +#define SCUXDVUCR_DVU0_2 (SCUX.DVUCR_DVU0_2) +#define SCUXZCMCR_DVU0_2 (SCUX.ZCMCR_DVU0_2) +#define SCUXVRCTR_DVU0_2 (SCUX.VRCTR_DVU0_2) +#define SCUXVRPDR_DVU0_2 (SCUX.VRPDR_DVU0_2) +#define SCUXVRDBR_DVU0_2 (SCUX.VRDBR_DVU0_2) +#define SCUXVRWTR_DVU0_2 (SCUX.VRWTR_DVU0_2) +#define SCUXVOL0R_DVU0_2 (SCUX.VOL0R_DVU0_2) +#define SCUXVOL1R_DVU0_2 (SCUX.VOL1R_DVU0_2) +#define SCUXVOL2R_DVU0_2 (SCUX.VOL2R_DVU0_2) +#define SCUXVOL3R_DVU0_2 (SCUX.VOL3R_DVU0_2) +#define SCUXVOL4R_DVU0_2 (SCUX.VOL4R_DVU0_2) +#define SCUXVOL5R_DVU0_2 (SCUX.VOL5R_DVU0_2) +#define SCUXVOL6R_DVU0_2 (SCUX.VOL6R_DVU0_2) +#define SCUXVOL7R_DVU0_2 (SCUX.VOL7R_DVU0_2) +#define SCUXDVUER_DVU0_2 (SCUX.DVUER_DVU0_2) +#define SCUXDVUSR_DVU0_2 (SCUX.DVUSR_DVU0_2) +#define SCUXVEVMR_DVU0_2 (SCUX.VEVMR_DVU0_2) +#define SCUXVEVCR_DVU0_2 (SCUX.VEVCR_DVU0_2) +#define SCUXDVUIR_DVU0_3 (SCUX.DVUIR_DVU0_3) +#define SCUXVADIR_DVU0_3 (SCUX.VADIR_DVU0_3) +#define SCUXDVUBR_DVU0_3 (SCUX.DVUBR_DVU0_3) +#define SCUXDVUCR_DVU0_3 (SCUX.DVUCR_DVU0_3) +#define SCUXZCMCR_DVU0_3 (SCUX.ZCMCR_DVU0_3) +#define SCUXVRCTR_DVU0_3 (SCUX.VRCTR_DVU0_3) +#define SCUXVRPDR_DVU0_3 (SCUX.VRPDR_DVU0_3) +#define SCUXVRDBR_DVU0_3 (SCUX.VRDBR_DVU0_3) +#define SCUXVRWTR_DVU0_3 (SCUX.VRWTR_DVU0_3) +#define SCUXVOL0R_DVU0_3 (SCUX.VOL0R_DVU0_3) +#define SCUXVOL1R_DVU0_3 (SCUX.VOL1R_DVU0_3) +#define SCUXVOL2R_DVU0_3 (SCUX.VOL2R_DVU0_3) +#define SCUXVOL3R_DVU0_3 (SCUX.VOL3R_DVU0_3) +#define SCUXVOL4R_DVU0_3 (SCUX.VOL4R_DVU0_3) +#define SCUXVOL5R_DVU0_3 (SCUX.VOL5R_DVU0_3) +#define SCUXVOL6R_DVU0_3 (SCUX.VOL6R_DVU0_3) +#define SCUXVOL7R_DVU0_3 (SCUX.VOL7R_DVU0_3) +#define SCUXDVUER_DVU0_3 (SCUX.DVUER_DVU0_3) +#define SCUXDVUSR_DVU0_3 (SCUX.DVUSR_DVU0_3) +#define SCUXVEVMR_DVU0_3 (SCUX.VEVMR_DVU0_3) +#define SCUXVEVCR_DVU0_3 (SCUX.VEVCR_DVU0_3) +#define SCUXMIXIR_MIX0_0 (SCUX.MIXIR_MIX0_0) +#define SCUXMADIR_MIX0_0 (SCUX.MADIR_MIX0_0) +#define SCUXMIXBR_MIX0_0 (SCUX.MIXBR_MIX0_0) +#define SCUXMIXMR_MIX0_0 (SCUX.MIXMR_MIX0_0) +#define SCUXMVPDR_MIX0_0 (SCUX.MVPDR_MIX0_0) +#define SCUXMDBAR_MIX0_0 (SCUX.MDBAR_MIX0_0) +#define SCUXMDBBR_MIX0_0 (SCUX.MDBBR_MIX0_0) +#define SCUXMDBCR_MIX0_0 (SCUX.MDBCR_MIX0_0) +#define SCUXMDBDR_MIX0_0 (SCUX.MDBDR_MIX0_0) +#define SCUXMDBER_MIX0_0 (SCUX.MDBER_MIX0_0) +#define SCUXMIXSR_MIX0_0 (SCUX.MIXSR_MIX0_0) +#define SCUXSWRSR_CIM (SCUX.SWRSR_CIM) +#define SCUXDMACR_CIM (SCUX.DMACR_CIM) +#define SCUXDMATD0_CIM (SCUX.DMATD0_CIM.UINT32) +#define SCUXDMATD0_CIML (SCUX.DMATD0_CIM.UINT16[R_IO_L]) +#define SCUXDMATD0_CIMH (SCUX.DMATD0_CIM.UINT16[R_IO_H]) +#define SCUXDMATD1_CIM (SCUX.DMATD1_CIM.UINT32) +#define SCUXDMATD1_CIML (SCUX.DMATD1_CIM.UINT16[R_IO_L]) +#define SCUXDMATD1_CIMH (SCUX.DMATD1_CIM.UINT16[R_IO_H]) +#define SCUXDMATD2_CIM (SCUX.DMATD2_CIM.UINT32) +#define SCUXDMATD2_CIML (SCUX.DMATD2_CIM.UINT16[R_IO_L]) +#define SCUXDMATD2_CIMH (SCUX.DMATD2_CIM.UINT16[R_IO_H]) +#define SCUXDMATD3_CIM (SCUX.DMATD3_CIM.UINT32) +#define SCUXDMATD3_CIML (SCUX.DMATD3_CIM.UINT16[R_IO_L]) +#define SCUXDMATD3_CIMH (SCUX.DMATD3_CIM.UINT16[R_IO_H]) +#define SCUXDMATU0_CIM (SCUX.DMATU0_CIM.UINT32) +#define SCUXDMATU0_CIML (SCUX.DMATU0_CIM.UINT16[R_IO_L]) +#define SCUXDMATU0_CIMH (SCUX.DMATU0_CIM.UINT16[R_IO_H]) +#define SCUXDMATU1_CIM (SCUX.DMATU1_CIM.UINT32) +#define SCUXDMATU1_CIML (SCUX.DMATU1_CIM.UINT16[R_IO_L]) +#define SCUXDMATU1_CIMH (SCUX.DMATU1_CIM.UINT16[R_IO_H]) +#define SCUXDMATU2_CIM (SCUX.DMATU2_CIM.UINT32) +#define SCUXDMATU2_CIML (SCUX.DMATU2_CIM.UINT16[R_IO_L]) +#define SCUXDMATU2_CIMH (SCUX.DMATU2_CIM.UINT16[R_IO_H]) +#define SCUXDMATU3_CIM (SCUX.DMATU3_CIM.UINT32) +#define SCUXDMATU3_CIML (SCUX.DMATU3_CIM.UINT16[R_IO_L]) +#define SCUXDMATU3_CIMH (SCUX.DMATU3_CIM.UINT16[R_IO_H]) +#define SCUXSSIRSEL_CIM (SCUX.SSIRSEL_CIM) +#define SCUXFDTSEL0_CIM (SCUX.FDTSEL0_CIM) +#define SCUXFDTSEL1_CIM (SCUX.FDTSEL1_CIM) +#define SCUXFDTSEL2_CIM (SCUX.FDTSEL2_CIM) +#define SCUXFDTSEL3_CIM (SCUX.FDTSEL3_CIM) +#define SCUXFUTSEL0_CIM (SCUX.FUTSEL0_CIM) +#define SCUXFUTSEL1_CIM (SCUX.FUTSEL1_CIM) +#define SCUXFUTSEL2_CIM (SCUX.FUTSEL2_CIM) +#define SCUXFUTSEL3_CIM (SCUX.FUTSEL3_CIM) +#define SCUXSSIPMD_CIM (SCUX.SSIPMD_CIM) +#define SCUXSSICTRL_CIM (SCUX.SSICTRL_CIM) +#define SCUXSRCRSEL0_CIM (SCUX.SRCRSEL0_CIM) +#define SCUXSRCRSEL1_CIM (SCUX.SRCRSEL1_CIM) +#define SCUXSRCRSEL2_CIM (SCUX.SRCRSEL2_CIM) +#define SCUXSRCRSEL3_CIM (SCUX.SRCRSEL3_CIM) +#define SCUXMIXRSEL_CIM (SCUX.MIXRSEL_CIM) + +#define SCUX_DMATDnCIM_COUNT (4) +#define SCUX_DMATUnCIM_COUNT (4) +#define SCUX_FDTSELnCIM_COUNT (4) +#define SCUX_FUTSELnCIM_COUNT (4) +#define SCUX_SRCRSELnCIM_COUNT (4) + + +typedef struct st_scux +{ + /* SCUX */ + +/* start of struct st_scux_from_ipcir_ipc0_n */ + volatile uint32_t IPCIR_IPC0_0; /* IPCIR_IPC0_0 */ + volatile uint32_t IPSLR_IPC0_0; /* IPSLR_IPC0_0 */ + volatile uint8_t dummy259[248]; /* */ + +/* end of struct st_scux_from_ipcir_ipc0_n */ + +/* start of struct st_scux_from_ipcir_ipc0_n */ + volatile uint32_t IPCIR_IPC0_1; /* IPCIR_IPC0_1 */ + volatile uint32_t IPSLR_IPC0_1; /* IPSLR_IPC0_1 */ + volatile uint8_t dummy260[248]; /* */ + +/* end of struct st_scux_from_ipcir_ipc0_n */ + +/* start of struct st_scux_from_ipcir_ipc0_n */ + volatile uint32_t IPCIR_IPC0_2; /* IPCIR_IPC0_2 */ + volatile uint32_t IPSLR_IPC0_2; /* IPSLR_IPC0_2 */ + volatile uint8_t dummy261[248]; /* */ + +/* end of struct st_scux_from_ipcir_ipc0_n */ + +/* start of struct st_scux_from_ipcir_ipc0_n */ + volatile uint32_t IPCIR_IPC0_3; /* IPCIR_IPC0_3 */ + volatile uint32_t IPSLR_IPC0_3; /* IPSLR_IPC0_3 */ + volatile uint8_t dummy262[248]; /* */ + +/* end of struct st_scux_from_ipcir_ipc0_n */ + +/* start of struct st_scux_from_opcir_opc0_n */ + volatile uint32_t OPCIR_OPC0_0; /* OPCIR_OPC0_0 */ + volatile uint32_t OPSLR_OPC0_0; /* OPSLR_OPC0_0 */ + volatile uint8_t dummy263[248]; /* */ + +/* end of struct st_scux_from_opcir_opc0_n */ + +/* start of struct st_scux_from_opcir_opc0_n */ + volatile uint32_t OPCIR_OPC0_1; /* OPCIR_OPC0_1 */ + volatile uint32_t OPSLR_OPC0_1; /* OPSLR_OPC0_1 */ + volatile uint8_t dummy264[248]; /* */ + +/* end of struct st_scux_from_opcir_opc0_n */ + +/* start of struct st_scux_from_opcir_opc0_n */ + volatile uint32_t OPCIR_OPC0_2; /* OPCIR_OPC0_2 */ + volatile uint32_t OPSLR_OPC0_2; /* OPSLR_OPC0_2 */ + volatile uint8_t dummy265[248]; /* */ + +/* end of struct st_scux_from_opcir_opc0_n */ + +/* start of struct st_scux_from_opcir_opc0_n */ + volatile uint32_t OPCIR_OPC0_3; /* OPCIR_OPC0_3 */ + volatile uint32_t OPSLR_OPC0_3; /* OPSLR_OPC0_3 */ + volatile uint8_t dummy266[248]; /* */ + +/* end of struct st_scux_from_opcir_opc0_n */ + +/* start of struct st_scux_from_ffdir_ffd0_n */ + volatile uint32_t FFDIR_FFD0_0; /* FFDIR_FFD0_0 */ + volatile uint32_t FDAIR_FFD0_0; /* FDAIR_FFD0_0 */ + volatile uint32_t DRQSR_FFD0_0; /* DRQSR_FFD0_0 */ + volatile uint32_t FFDPR_FFD0_0; /* FFDPR_FFD0_0 */ + volatile uint32_t FFDBR_FFD0_0; /* FFDBR_FFD0_0 */ + volatile uint32_t DEVMR_FFD0_0; /* DEVMR_FFD0_0 */ + volatile uint8_t dummy267[4]; /* */ + volatile uint32_t DEVCR_FFD0_0; /* DEVCR_FFD0_0 */ + +/* end of struct st_scux_from_ffdir_ffd0_n */ + volatile uint8_t dummy268[224]; /* */ + +/* start of struct st_scux_from_ffdir_ffd0_n */ + volatile uint32_t FFDIR_FFD0_1; /* FFDIR_FFD0_1 */ + volatile uint32_t FDAIR_FFD0_1; /* FDAIR_FFD0_1 */ + volatile uint32_t DRQSR_FFD0_1; /* DRQSR_FFD0_1 */ + volatile uint32_t FFDPR_FFD0_1; /* FFDPR_FFD0_1 */ + volatile uint32_t FFDBR_FFD0_1; /* FFDBR_FFD0_1 */ + volatile uint32_t DEVMR_FFD0_1; /* DEVMR_FFD0_1 */ + volatile uint8_t dummy269[4]; /* */ + volatile uint32_t DEVCR_FFD0_1; /* DEVCR_FFD0_1 */ + +/* end of struct st_scux_from_ffdir_ffd0_n */ + volatile uint8_t dummy270[224]; /* */ + +/* start of struct st_scux_from_ffdir_ffd0_n */ + volatile uint32_t FFDIR_FFD0_2; /* FFDIR_FFD0_2 */ + volatile uint32_t FDAIR_FFD0_2; /* FDAIR_FFD0_2 */ + volatile uint32_t DRQSR_FFD0_2; /* DRQSR_FFD0_2 */ + volatile uint32_t FFDPR_FFD0_2; /* FFDPR_FFD0_2 */ + volatile uint32_t FFDBR_FFD0_2; /* FFDBR_FFD0_2 */ + volatile uint32_t DEVMR_FFD0_2; /* DEVMR_FFD0_2 */ + volatile uint8_t dummy271[4]; /* */ + volatile uint32_t DEVCR_FFD0_2; /* DEVCR_FFD0_2 */ + +/* end of struct st_scux_from_ffdir_ffd0_n */ + volatile uint8_t dummy272[224]; /* */ + +/* start of struct st_scux_from_ffdir_ffd0_n */ + volatile uint32_t FFDIR_FFD0_3; /* FFDIR_FFD0_3 */ + volatile uint32_t FDAIR_FFD0_3; /* FDAIR_FFD0_3 */ + volatile uint32_t DRQSR_FFD0_3; /* DRQSR_FFD0_3 */ + volatile uint32_t FFDPR_FFD0_3; /* FFDPR_FFD0_3 */ + volatile uint32_t FFDBR_FFD0_3; /* FFDBR_FFD0_3 */ + volatile uint32_t DEVMR_FFD0_3; /* DEVMR_FFD0_3 */ + volatile uint8_t dummy273[4]; /* */ + volatile uint32_t DEVCR_FFD0_3; /* DEVCR_FFD0_3 */ + +/* end of struct st_scux_from_ffdir_ffd0_n */ + volatile uint8_t dummy274[224]; /* */ + +/* start of struct st_scux_from_ffuir_ffu0_n */ + volatile uint32_t FFUIR_FFU0_0; /* FFUIR_FFU0_0 */ + volatile uint32_t FUAIR_FFU0_0; /* FUAIR_FFU0_0 */ + volatile uint32_t URQSR_FFU0_0; /* URQSR_FFU0_0 */ + volatile uint32_t FFUPR_FFU0_0; /* FFUPR_FFU0_0 */ + volatile uint32_t UEVMR_FFU0_0; /* UEVMR_FFU0_0 */ + volatile uint8_t dummy275[4]; /* */ + volatile uint32_t UEVCR_FFU0_0; /* UEVCR_FFU0_0 */ + +/* end of struct st_scux_from_ffuir_ffu0_n */ + volatile uint8_t dummy276[228]; /* */ + +/* start of struct st_scux_from_ffuir_ffu0_n */ + volatile uint32_t FFUIR_FFU0_1; /* FFUIR_FFU0_1 */ + volatile uint32_t FUAIR_FFU0_1; /* FUAIR_FFU0_1 */ + volatile uint32_t URQSR_FFU0_1; /* URQSR_FFU0_1 */ + volatile uint32_t FFUPR_FFU0_1; /* FFUPR_FFU0_1 */ + volatile uint32_t UEVMR_FFU0_1; /* UEVMR_FFU0_1 */ + volatile uint8_t dummy277[4]; /* */ + volatile uint32_t UEVCR_FFU0_1; /* UEVCR_FFU0_1 */ + +/* end of struct st_scux_from_ffuir_ffu0_n */ + volatile uint8_t dummy278[228]; /* */ + +/* start of struct st_scux_from_ffuir_ffu0_n */ + volatile uint32_t FFUIR_FFU0_2; /* FFUIR_FFU0_2 */ + volatile uint32_t FUAIR_FFU0_2; /* FUAIR_FFU0_2 */ + volatile uint32_t URQSR_FFU0_2; /* URQSR_FFU0_2 */ + volatile uint32_t FFUPR_FFU0_2; /* FFUPR_FFU0_2 */ + volatile uint32_t UEVMR_FFU0_2; /* UEVMR_FFU0_2 */ + volatile uint8_t dummy279[4]; /* */ + volatile uint32_t UEVCR_FFU0_2; /* UEVCR_FFU0_2 */ + +/* end of struct st_scux_from_ffuir_ffu0_n */ + volatile uint8_t dummy280[228]; /* */ + +/* start of struct st_scux_from_ffuir_ffu0_n */ + volatile uint32_t FFUIR_FFU0_3; /* FFUIR_FFU0_3 */ + volatile uint32_t FUAIR_FFU0_3; /* FUAIR_FFU0_3 */ + volatile uint32_t URQSR_FFU0_3; /* URQSR_FFU0_3 */ + volatile uint32_t FFUPR_FFU0_3; /* FFUPR_FFU0_3 */ + volatile uint32_t UEVMR_FFU0_3; /* UEVMR_FFU0_3 */ + volatile uint8_t dummy281[4]; /* */ + volatile uint32_t UEVCR_FFU0_3; /* UEVCR_FFU0_3 */ + +/* end of struct st_scux_from_ffuir_ffu0_n */ + volatile uint8_t dummy282[228]; /* */ + +/* start of struct st_scux_from_srcir0_2src0_n */ + volatile uint32_t SRCIR0_2SRC0_0; /* SRCIR0_2SRC0_0 */ + volatile uint32_t SADIR0_2SRC0_0; /* SADIR0_2SRC0_0 */ + volatile uint32_t SRCBR0_2SRC0_0; /* SRCBR0_2SRC0_0 */ + volatile uint32_t IFSCR0_2SRC0_0; /* IFSCR0_2SRC0_0 */ + volatile uint32_t IFSVR0_2SRC0_0; /* IFSVR0_2SRC0_0 */ + volatile uint32_t SRCCR0_2SRC0_0; /* SRCCR0_2SRC0_0 */ + volatile uint32_t MNFSR0_2SRC0_0; /* MNFSR0_2SRC0_0 */ + volatile uint32_t BFSSR0_2SRC0_0; /* BFSSR0_2SRC0_0 */ + volatile uint32_t SC2SR0_2SRC0_0; /* SC2SR0_2SRC0_0 */ + volatile uint32_t WATSR0_2SRC0_0; /* WATSR0_2SRC0_0 */ + volatile uint32_t SEVMR0_2SRC0_0; /* SEVMR0_2SRC0_0 */ + volatile uint8_t dummy283[4]; /* */ + volatile uint32_t SEVCR0_2SRC0_0; /* SEVCR0_2SRC0_0 */ + volatile uint32_t SRCIR1_2SRC0_0; /* SRCIR1_2SRC0_0 */ + volatile uint32_t SADIR1_2SRC0_0; /* SADIR1_2SRC0_0 */ + volatile uint32_t SRCBR1_2SRC0_0; /* SRCBR1_2SRC0_0 */ + volatile uint32_t IFSCR1_2SRC0_0; /* IFSCR1_2SRC0_0 */ + volatile uint32_t IFSVR1_2SRC0_0; /* IFSVR1_2SRC0_0 */ + volatile uint32_t SRCCR1_2SRC0_0; /* SRCCR1_2SRC0_0 */ + volatile uint32_t MNFSR1_2SRC0_0; /* MNFSR1_2SRC0_0 */ + volatile uint32_t BFSSR1_2SRC0_0; /* BFSSR1_2SRC0_0 */ + volatile uint32_t SC2SR1_2SRC0_0; /* SC2SR1_2SRC0_0 */ + volatile uint32_t WATSR1_2SRC0_0; /* WATSR1_2SRC0_0 */ + volatile uint32_t SEVMR1_2SRC0_0; /* SEVMR1_2SRC0_0 */ + volatile uint8_t dummy284[4]; /* */ + volatile uint32_t SEVCR1_2SRC0_0; /* SEVCR1_2SRC0_0 */ + volatile uint32_t SRCIRR_2SRC0_0; /* SRCIRR_2SRC0_0 */ + +/* end of struct st_scux_from_srcir0_2src0_n */ + volatile uint8_t dummy285[148]; /* */ + +/* start of struct st_scux_from_srcir0_2src0_n */ + volatile uint32_t SRCIR0_2SRC0_1; /* SRCIR0_2SRC0_1 */ + volatile uint32_t SADIR0_2SRC0_1; /* SADIR0_2SRC0_1 */ + volatile uint32_t SRCBR0_2SRC0_1; /* SRCBR0_2SRC0_1 */ + volatile uint32_t IFSCR0_2SRC0_1; /* IFSCR0_2SRC0_1 */ + volatile uint32_t IFSVR0_2SRC0_1; /* IFSVR0_2SRC0_1 */ + volatile uint32_t SRCCR0_2SRC0_1; /* SRCCR0_2SRC0_1 */ + volatile uint32_t MNFSR0_2SRC0_1; /* MNFSR0_2SRC0_1 */ + volatile uint32_t BFSSR0_2SRC0_1; /* BFSSR0_2SRC0_1 */ + volatile uint32_t SC2SR0_2SRC0_1; /* SC2SR0_2SRC0_1 */ + volatile uint32_t WATSR0_2SRC0_1; /* WATSR0_2SRC0_1 */ + volatile uint32_t SEVMR0_2SRC0_1; /* SEVMR0_2SRC0_1 */ + volatile uint8_t dummy286[4]; /* */ + volatile uint32_t SEVCR0_2SRC0_1; /* SEVCR0_2SRC0_1 */ + volatile uint32_t SRCIR1_2SRC0_1; /* SRCIR1_2SRC0_1 */ + volatile uint32_t SADIR1_2SRC0_1; /* SADIR1_2SRC0_1 */ + volatile uint32_t SRCBR1_2SRC0_1; /* SRCBR1_2SRC0_1 */ + volatile uint32_t IFSCR1_2SRC0_1; /* IFSCR1_2SRC0_1 */ + volatile uint32_t IFSVR1_2SRC0_1; /* IFSVR1_2SRC0_1 */ + volatile uint32_t SRCCR1_2SRC0_1; /* SRCCR1_2SRC0_1 */ + volatile uint32_t MNFSR1_2SRC0_1; /* MNFSR1_2SRC0_1 */ + volatile uint32_t BFSSR1_2SRC0_1; /* BFSSR1_2SRC0_1 */ + volatile uint32_t SC2SR1_2SRC0_1; /* SC2SR1_2SRC0_1 */ + volatile uint32_t WATSR1_2SRC0_1; /* WATSR1_2SRC0_1 */ + volatile uint32_t SEVMR1_2SRC0_1; /* SEVMR1_2SRC0_1 */ + volatile uint8_t dummy287[4]; /* */ + volatile uint32_t SEVCR1_2SRC0_1; /* SEVCR1_2SRC0_1 */ + volatile uint32_t SRCIRR_2SRC0_1; /* SRCIRR_2SRC0_1 */ + +/* end of struct st_scux_from_srcir0_2src0_n */ + volatile uint8_t dummy288[148]; /* */ + +/* start of struct st_scux_from_dvuir_dvu0_n */ + volatile uint32_t DVUIR_DVU0_0; /* DVUIR_DVU0_0 */ + volatile uint32_t VADIR_DVU0_0; /* VADIR_DVU0_0 */ + volatile uint32_t DVUBR_DVU0_0; /* DVUBR_DVU0_0 */ + volatile uint32_t DVUCR_DVU0_0; /* DVUCR_DVU0_0 */ + volatile uint32_t ZCMCR_DVU0_0; /* ZCMCR_DVU0_0 */ + volatile uint32_t VRCTR_DVU0_0; /* VRCTR_DVU0_0 */ + volatile uint32_t VRPDR_DVU0_0; /* VRPDR_DVU0_0 */ + volatile uint32_t VRDBR_DVU0_0; /* VRDBR_DVU0_0 */ + volatile uint32_t VRWTR_DVU0_0; /* VRWTR_DVU0_0 */ + volatile uint32_t VOL0R_DVU0_0; /* VOL0R_DVU0_0 */ + volatile uint32_t VOL1R_DVU0_0; /* VOL1R_DVU0_0 */ + volatile uint32_t VOL2R_DVU0_0; /* VOL2R_DVU0_0 */ + volatile uint32_t VOL3R_DVU0_0; /* VOL3R_DVU0_0 */ + volatile uint32_t VOL4R_DVU0_0; /* VOL4R_DVU0_0 */ + volatile uint32_t VOL5R_DVU0_0; /* VOL5R_DVU0_0 */ + volatile uint32_t VOL6R_DVU0_0; /* VOL6R_DVU0_0 */ + volatile uint32_t VOL7R_DVU0_0; /* VOL7R_DVU0_0 */ + volatile uint32_t DVUER_DVU0_0; /* DVUER_DVU0_0 */ + volatile uint32_t DVUSR_DVU0_0; /* DVUSR_DVU0_0 */ + volatile uint32_t VEVMR_DVU0_0; /* VEVMR_DVU0_0 */ + volatile uint8_t dummy289[4]; /* */ + volatile uint32_t VEVCR_DVU0_0; /* VEVCR_DVU0_0 */ + +/* end of struct st_scux_from_dvuir_dvu0_n */ + volatile uint8_t dummy290[168]; /* */ + +/* start of struct st_scux_from_dvuir_dvu0_n */ + volatile uint32_t DVUIR_DVU0_1; /* DVUIR_DVU0_1 */ + volatile uint32_t VADIR_DVU0_1; /* VADIR_DVU0_1 */ + volatile uint32_t DVUBR_DVU0_1; /* DVUBR_DVU0_1 */ + volatile uint32_t DVUCR_DVU0_1; /* DVUCR_DVU0_1 */ + volatile uint32_t ZCMCR_DVU0_1; /* ZCMCR_DVU0_1 */ + volatile uint32_t VRCTR_DVU0_1; /* VRCTR_DVU0_1 */ + volatile uint32_t VRPDR_DVU0_1; /* VRPDR_DVU0_1 */ + volatile uint32_t VRDBR_DVU0_1; /* VRDBR_DVU0_1 */ + volatile uint32_t VRWTR_DVU0_1; /* VRWTR_DVU0_1 */ + volatile uint32_t VOL0R_DVU0_1; /* VOL0R_DVU0_1 */ + volatile uint32_t VOL1R_DVU0_1; /* VOL1R_DVU0_1 */ + volatile uint32_t VOL2R_DVU0_1; /* VOL2R_DVU0_1 */ + volatile uint32_t VOL3R_DVU0_1; /* VOL3R_DVU0_1 */ + volatile uint32_t VOL4R_DVU0_1; /* VOL4R_DVU0_1 */ + volatile uint32_t VOL5R_DVU0_1; /* VOL5R_DVU0_1 */ + volatile uint32_t VOL6R_DVU0_1; /* VOL6R_DVU0_1 */ + volatile uint32_t VOL7R_DVU0_1; /* VOL7R_DVU0_1 */ + volatile uint32_t DVUER_DVU0_1; /* DVUER_DVU0_1 */ + volatile uint32_t DVUSR_DVU0_1; /* DVUSR_DVU0_1 */ + volatile uint32_t VEVMR_DVU0_1; /* VEVMR_DVU0_1 */ + volatile uint8_t dummy291[4]; /* */ + volatile uint32_t VEVCR_DVU0_1; /* VEVCR_DVU0_1 */ + +/* end of struct st_scux_from_dvuir_dvu0_n */ + volatile uint8_t dummy292[168]; /* */ + +/* start of struct st_scux_from_dvuir_dvu0_n */ + volatile uint32_t DVUIR_DVU0_2; /* DVUIR_DVU0_2 */ + volatile uint32_t VADIR_DVU0_2; /* VADIR_DVU0_2 */ + volatile uint32_t DVUBR_DVU0_2; /* DVUBR_DVU0_2 */ + volatile uint32_t DVUCR_DVU0_2; /* DVUCR_DVU0_2 */ + volatile uint32_t ZCMCR_DVU0_2; /* ZCMCR_DVU0_2 */ + volatile uint32_t VRCTR_DVU0_2; /* VRCTR_DVU0_2 */ + volatile uint32_t VRPDR_DVU0_2; /* VRPDR_DVU0_2 */ + volatile uint32_t VRDBR_DVU0_2; /* VRDBR_DVU0_2 */ + volatile uint32_t VRWTR_DVU0_2; /* VRWTR_DVU0_2 */ + volatile uint32_t VOL0R_DVU0_2; /* VOL0R_DVU0_2 */ + volatile uint32_t VOL1R_DVU0_2; /* VOL1R_DVU0_2 */ + volatile uint32_t VOL2R_DVU0_2; /* VOL2R_DVU0_2 */ + volatile uint32_t VOL3R_DVU0_2; /* VOL3R_DVU0_2 */ + volatile uint32_t VOL4R_DVU0_2; /* VOL4R_DVU0_2 */ + volatile uint32_t VOL5R_DVU0_2; /* VOL5R_DVU0_2 */ + volatile uint32_t VOL6R_DVU0_2; /* VOL6R_DVU0_2 */ + volatile uint32_t VOL7R_DVU0_2; /* VOL7R_DVU0_2 */ + volatile uint32_t DVUER_DVU0_2; /* DVUER_DVU0_2 */ + volatile uint32_t DVUSR_DVU0_2; /* DVUSR_DVU0_2 */ + volatile uint32_t VEVMR_DVU0_2; /* VEVMR_DVU0_2 */ + volatile uint8_t dummy293[4]; /* */ + volatile uint32_t VEVCR_DVU0_2; /* VEVCR_DVU0_2 */ + +/* end of struct st_scux_from_dvuir_dvu0_n */ + volatile uint8_t dummy294[168]; /* */ + +/* start of struct st_scux_from_dvuir_dvu0_n */ + volatile uint32_t DVUIR_DVU0_3; /* DVUIR_DVU0_3 */ + volatile uint32_t VADIR_DVU0_3; /* VADIR_DVU0_3 */ + volatile uint32_t DVUBR_DVU0_3; /* DVUBR_DVU0_3 */ + volatile uint32_t DVUCR_DVU0_3; /* DVUCR_DVU0_3 */ + volatile uint32_t ZCMCR_DVU0_3; /* ZCMCR_DVU0_3 */ + volatile uint32_t VRCTR_DVU0_3; /* VRCTR_DVU0_3 */ + volatile uint32_t VRPDR_DVU0_3; /* VRPDR_DVU0_3 */ + volatile uint32_t VRDBR_DVU0_3; /* VRDBR_DVU0_3 */ + volatile uint32_t VRWTR_DVU0_3; /* VRWTR_DVU0_3 */ + volatile uint32_t VOL0R_DVU0_3; /* VOL0R_DVU0_3 */ + volatile uint32_t VOL1R_DVU0_3; /* VOL1R_DVU0_3 */ + volatile uint32_t VOL2R_DVU0_3; /* VOL2R_DVU0_3 */ + volatile uint32_t VOL3R_DVU0_3; /* VOL3R_DVU0_3 */ + volatile uint32_t VOL4R_DVU0_3; /* VOL4R_DVU0_3 */ + volatile uint32_t VOL5R_DVU0_3; /* VOL5R_DVU0_3 */ + volatile uint32_t VOL6R_DVU0_3; /* VOL6R_DVU0_3 */ + volatile uint32_t VOL7R_DVU0_3; /* VOL7R_DVU0_3 */ + volatile uint32_t DVUER_DVU0_3; /* DVUER_DVU0_3 */ + volatile uint32_t DVUSR_DVU0_3; /* DVUSR_DVU0_3 */ + volatile uint32_t VEVMR_DVU0_3; /* VEVMR_DVU0_3 */ + volatile uint8_t dummy295[4]; /* */ + volatile uint32_t VEVCR_DVU0_3; /* VEVCR_DVU0_3 */ + +/* end of struct st_scux_from_dvuir_dvu0_n */ + volatile uint8_t dummy296[168]; /* */ + volatile uint32_t MIXIR_MIX0_0; /* MIXIR_MIX0_0 */ + volatile uint32_t MADIR_MIX0_0; /* MADIR_MIX0_0 */ + volatile uint32_t MIXBR_MIX0_0; /* MIXBR_MIX0_0 */ + volatile uint32_t MIXMR_MIX0_0; /* MIXMR_MIX0_0 */ + volatile uint32_t MVPDR_MIX0_0; /* MVPDR_MIX0_0 */ + volatile uint32_t MDBAR_MIX0_0; /* MDBAR_MIX0_0 */ + volatile uint32_t MDBBR_MIX0_0; /* MDBBR_MIX0_0 */ + volatile uint32_t MDBCR_MIX0_0; /* MDBCR_MIX0_0 */ + volatile uint32_t MDBDR_MIX0_0; /* MDBDR_MIX0_0 */ + volatile uint32_t MDBER_MIX0_0; /* MDBER_MIX0_0 */ + volatile uint32_t MIXSR_MIX0_0; /* MIXSR_MIX0_0 */ + volatile uint8_t dummy297[212]; /* */ + volatile uint32_t SWRSR_CIM; /* SWRSR_CIM */ + volatile uint32_t DMACR_CIM; /* DMACR_CIM */ + +/* #define SCUX_DMATDnCIM_COUNT (4) */ + union iodefine_reg32_16_t DMATD0_CIM; /* DMATD0_CIM */ + union iodefine_reg32_16_t DMATD1_CIM; /* DMATD1_CIM */ + union iodefine_reg32_16_t DMATD2_CIM; /* DMATD2_CIM */ + union iodefine_reg32_16_t DMATD3_CIM; /* DMATD3_CIM */ + +/* #define SCUX_DMATUnCIM_COUNT (4) */ + union iodefine_reg32_16_t DMATU0_CIM; /* DMATU0_CIM */ + union iodefine_reg32_16_t DMATU1_CIM; /* DMATU1_CIM */ + union iodefine_reg32_16_t DMATU2_CIM; /* DMATU2_CIM */ + union iodefine_reg32_16_t DMATU3_CIM; /* DMATU3_CIM */ + + volatile uint8_t dummy298[16]; /* */ + volatile uint32_t SSIRSEL_CIM; /* SSIRSEL_CIM */ + +/* #define SCUX_FDTSELnCIM_COUNT (4) */ + volatile uint32_t FDTSEL0_CIM; /* FDTSEL0_CIM */ + volatile uint32_t FDTSEL1_CIM; /* FDTSEL1_CIM */ + volatile uint32_t FDTSEL2_CIM; /* FDTSEL2_CIM */ + volatile uint32_t FDTSEL3_CIM; /* FDTSEL3_CIM */ + +/* #define SCUX_FUTSELnCIM_COUNT (4) */ + volatile uint32_t FUTSEL0_CIM; /* FUTSEL0_CIM */ + volatile uint32_t FUTSEL1_CIM; /* FUTSEL1_CIM */ + volatile uint32_t FUTSEL2_CIM; /* FUTSEL2_CIM */ + volatile uint32_t FUTSEL3_CIM; /* FUTSEL3_CIM */ + volatile uint32_t SSIPMD_CIM; /* SSIPMD_CIM */ + volatile uint32_t SSICTRL_CIM; /* SSICTRL_CIM */ + +/* #define SCUX_SRCRSELnCIM_COUNT (4) */ + volatile uint32_t SRCRSEL0_CIM; /* SRCRSEL0_CIM */ + volatile uint32_t SRCRSEL1_CIM; /* SRCRSEL1_CIM */ + volatile uint32_t SRCRSEL2_CIM; /* SRCRSEL2_CIM */ + volatile uint32_t SRCRSEL3_CIM; /* SRCRSEL3_CIM */ + volatile uint32_t MIXRSEL_CIM; /* MIXRSEL_CIM */ +} r_io_scux_t; + + +typedef struct st_scux_from_ipcir_ipc0_n +{ + + volatile uint32_t IPCIR_IPC0_0; /* IPCIR_IPC0_0 */ + volatile uint32_t IPSLR_IPC0_0; /* IPSLR_IPC0_0 */ + volatile uint8_t dummy1[248]; /* */ +} r_io_scux_from_ipcir_ipc0_n_t; + + +typedef struct st_scux_from_opcir_opc0_n +{ + + volatile uint32_t OPCIR_OPC0_0; /* OPCIR_OPC0_0 */ + volatile uint32_t OPSLR_OPC0_0; /* OPSLR_OPC0_0 */ + volatile uint8_t dummy1[248]; /* */ +} r_io_scux_from_opcir_opc0_n_t; + + +typedef struct st_scux_from_ffdir_ffd0_n +{ + + volatile uint32_t FFDIR_FFD0_0; /* FFDIR_FFD0_0 */ + volatile uint32_t FDAIR_FFD0_0; /* FDAIR_FFD0_0 */ + volatile uint32_t DRQSR_FFD0_0; /* DRQSR_FFD0_0 */ + volatile uint32_t FFDPR_FFD0_0; /* FFDPR_FFD0_0 */ + volatile uint32_t FFDBR_FFD0_0; /* FFDBR_FFD0_0 */ + volatile uint32_t DEVMR_FFD0_0; /* DEVMR_FFD0_0 */ + volatile uint8_t dummy1[4]; /* */ + volatile uint32_t DEVCR_FFD0_0; /* DEVCR_FFD0_0 */ +} r_io_scux_from_ffdir_ffd0_n_t; + + +typedef struct st_scux_from_ffuir_ffu0_n +{ + + volatile uint32_t FFUIR_FFU0_0; /* FFUIR_FFU0_0 */ + volatile uint32_t FUAIR_FFU0_0; /* FUAIR_FFU0_0 */ + volatile uint32_t URQSR_FFU0_0; /* URQSR_FFU0_0 */ + volatile uint32_t FFUPR_FFU0_0; /* FFUPR_FFU0_0 */ + volatile uint32_t UEVMR_FFU0_0; /* UEVMR_FFU0_0 */ + volatile uint8_t dummy1[4]; /* */ + volatile uint32_t UEVCR_FFU0_0; /* UEVCR_FFU0_0 */ +} r_io_scux_from_ffuir_ffu0_n_t; + + +typedef struct st_scux_from_srcir0_2src0_n +{ + + volatile uint32_t SRCIR0_2SRC0_0; /* SRCIR0_2SRC0_0 */ + volatile uint32_t SADIR0_2SRC0_0; /* SADIR0_2SRC0_0 */ + volatile uint32_t SRCBR0_2SRC0_0; /* SRCBR0_2SRC0_0 */ + volatile uint32_t IFSCR0_2SRC0_0; /* IFSCR0_2SRC0_0 */ + volatile uint32_t IFSVR0_2SRC0_0; /* IFSVR0_2SRC0_0 */ + volatile uint32_t SRCCR0_2SRC0_0; /* SRCCR0_2SRC0_0 */ + volatile uint32_t MNFSR0_2SRC0_0; /* MNFSR0_2SRC0_0 */ + volatile uint32_t BFSSR0_2SRC0_0; /* BFSSR0_2SRC0_0 */ + volatile uint32_t SC2SR0_2SRC0_0; /* SC2SR0_2SRC0_0 */ + volatile uint32_t WATSR0_2SRC0_0; /* WATSR0_2SRC0_0 */ + volatile uint32_t SEVMR0_2SRC0_0; /* SEVMR0_2SRC0_0 */ + volatile uint8_t dummy1[4]; /* */ + volatile uint32_t SEVCR0_2SRC0_0; /* SEVCR0_2SRC0_0 */ + volatile uint32_t SRCIR1_2SRC0_0; /* SRCIR1_2SRC0_0 */ + volatile uint32_t SADIR1_2SRC0_0; /* SADIR1_2SRC0_0 */ + volatile uint32_t SRCBR1_2SRC0_0; /* SRCBR1_2SRC0_0 */ + volatile uint32_t IFSCR1_2SRC0_0; /* IFSCR1_2SRC0_0 */ + volatile uint32_t IFSVR1_2SRC0_0; /* IFSVR1_2SRC0_0 */ + volatile uint32_t SRCCR1_2SRC0_0; /* SRCCR1_2SRC0_0 */ + volatile uint32_t MNFSR1_2SRC0_0; /* MNFSR1_2SRC0_0 */ + volatile uint32_t BFSSR1_2SRC0_0; /* BFSSR1_2SRC0_0 */ + volatile uint32_t SC2SR1_2SRC0_0; /* SC2SR1_2SRC0_0 */ + volatile uint32_t WATSR1_2SRC0_0; /* WATSR1_2SRC0_0 */ + volatile uint32_t SEVMR1_2SRC0_0; /* SEVMR1_2SRC0_0 */ + volatile uint8_t dummy2[4]; /* */ + volatile uint32_t SEVCR1_2SRC0_0; /* SEVCR1_2SRC0_0 */ + volatile uint32_t SRCIRR_2SRC0_0; /* SRCIRR_2SRC0_0 */ +} r_io_scux_from_srcir0_2src0_n_t; + + +typedef struct st_scux_from_dvuir_dvu0_n +{ + + volatile uint32_t DVUIR_DVU0_0; /* DVUIR_DVU0_0 */ + volatile uint32_t VADIR_DVU0_0; /* VADIR_DVU0_0 */ + volatile uint32_t DVUBR_DVU0_0; /* DVUBR_DVU0_0 */ + volatile uint32_t DVUCR_DVU0_0; /* DVUCR_DVU0_0 */ + volatile uint32_t ZCMCR_DVU0_0; /* ZCMCR_DVU0_0 */ + volatile uint32_t VRCTR_DVU0_0; /* VRCTR_DVU0_0 */ + volatile uint32_t VRPDR_DVU0_0; /* VRPDR_DVU0_0 */ + volatile uint32_t VRDBR_DVU0_0; /* VRDBR_DVU0_0 */ + volatile uint32_t VRWTR_DVU0_0; /* VRWTR_DVU0_0 */ + volatile uint32_t VOL0R_DVU0_0; /* VOL0R_DVU0_0 */ + volatile uint32_t VOL1R_DVU0_0; /* VOL1R_DVU0_0 */ + volatile uint32_t VOL2R_DVU0_0; /* VOL2R_DVU0_0 */ + volatile uint32_t VOL3R_DVU0_0; /* VOL3R_DVU0_0 */ + volatile uint32_t VOL4R_DVU0_0; /* VOL4R_DVU0_0 */ + volatile uint32_t VOL5R_DVU0_0; /* VOL5R_DVU0_0 */ + volatile uint32_t VOL6R_DVU0_0; /* VOL6R_DVU0_0 */ + volatile uint32_t VOL7R_DVU0_0; /* VOL7R_DVU0_0 */ + volatile uint32_t DVUER_DVU0_0; /* DVUER_DVU0_0 */ + volatile uint32_t DVUSR_DVU0_0; /* DVUSR_DVU0_0 */ + volatile uint32_t VEVMR_DVU0_0; /* VEVMR_DVU0_0 */ + volatile uint8_t dummy1[4]; /* */ + volatile uint32_t VEVCR_DVU0_0; /* VEVCR_DVU0_0 */ +} r_io_scux_from_dvuir_dvu0_n_t; + + +/* Channel array defines of SCUX (2)*/ +#ifdef DECLARE_SCUX_FROM_DVUIR_DVU0_0_ARRAY_CHANNELS +volatile struct st_scux_from_dvuir_dvu0_n* SCUX_FROM_DVUIR_DVU0_0_ARRAY[ SCUX_FROM_DVUIR_DVU0_0_ARRAY_COUNT ] = + /* ->MISRA 11.3 */ /* ->SEC R2.7.1 */ + SCUX_FROM_DVUIR_DVU0_0_ARRAY_ADDRESS_LIST; + /* <-MISRA 11.3 */ /* <-SEC R2.7.1 */ +#endif /* DECLARE_SCUX_FROM_DVUIR_DVU0_0_ARRAY_CHANNELS */ + +#ifdef DECLARE_SCUX_FROM_SRCIR0_2SRC0_0_ARRAY_CHANNELS +volatile struct st_scux_from_srcir0_2src0_n* SCUX_FROM_SRCIR0_2SRC0_0_ARRAY[ SCUX_FROM_SRCIR0_2SRC0_0_ARRAY_COUNT ] = + /* ->MISRA 11.3 */ /* ->SEC R2.7.1 */ + SCUX_FROM_SRCIR0_2SRC0_0_ARRAY_ADDRESS_LIST; + /* <-MISRA 11.3 */ /* <-SEC R2.7.1 */ +#endif /* DECLARE_SCUX_FROM_SRCIR0_2SRC0_0_ARRAY_CHANNELS */ + +#ifdef DECLARE_SCUX_FROM_FFUIR_FFU0_0_ARRAY_CHANNELS +volatile struct st_scux_from_ffuir_ffu0_n* SCUX_FROM_FFUIR_FFU0_0_ARRAY[ SCUX_FROM_FFUIR_FFU0_0_ARRAY_COUNT ] = + /* ->MISRA 11.3 */ /* ->SEC R2.7.1 */ + SCUX_FROM_FFUIR_FFU0_0_ARRAY_ADDRESS_LIST; + /* <-MISRA 11.3 */ /* <-SEC R2.7.1 */ +#endif /* DECLARE_SCUX_FROM_FFUIR_FFU0_0_ARRAY_CHANNELS */ + +#ifdef DECLARE_SCUX_FROM_FFDIR_FFD0_0_ARRAY_CHANNELS +volatile struct st_scux_from_ffdir_ffd0_n* SCUX_FROM_FFDIR_FFD0_0_ARRAY[ SCUX_FROM_FFDIR_FFD0_0_ARRAY_COUNT ] = + /* ->MISRA 11.3 */ /* ->SEC R2.7.1 */ + SCUX_FROM_FFDIR_FFD0_0_ARRAY_ADDRESS_LIST; + /* <-MISRA 11.3 */ /* <-SEC R2.7.1 */ +#endif /* DECLARE_SCUX_FROM_FFDIR_FFD0_0_ARRAY_CHANNELS */ + +#ifdef DECLARE_SCUX_FROM_OPCIR_OPC0_0_ARRAY_CHANNELS +volatile struct st_scux_from_opcir_opc0_n* SCUX_FROM_OPCIR_OPC0_0_ARRAY[ SCUX_FROM_OPCIR_OPC0_0_ARRAY_COUNT ] = + /* ->MISRA 11.3 */ /* ->SEC R2.7.1 */ + SCUX_FROM_OPCIR_OPC0_0_ARRAY_ADDRESS_LIST; + /* <-MISRA 11.3 */ /* <-SEC R2.7.1 */ +#endif /* DECLARE_SCUX_FROM_OPCIR_OPC0_0_ARRAY_CHANNELS */ + +#ifdef DECLARE_SCUX_FROM_IPCIR_IPC0_0_ARRAY_CHANNELS +volatile struct st_scux_from_ipcir_ipc0_n* SCUX_FROM_IPCIR_IPC0_0_ARRAY[ SCUX_FROM_IPCIR_IPC0_0_ARRAY_COUNT ] = + /* ->MISRA 11.3 */ /* ->SEC R2.7.1 */ + SCUX_FROM_IPCIR_IPC0_0_ARRAY_ADDRESS_LIST; + /* <-MISRA 11.3 */ /* <-SEC R2.7.1 */ +#endif /* DECLARE_SCUX_FROM_IPCIR_IPC0_0_ARRAY_CHANNELS */ +/* End of channel array defines of SCUX (2)*/ + + +/* <-SEC M1.10.1 */ +/* <-MISRA 18.4 */ /* <-SEC M1.6.2 */ +/* <-QAC 0857 */ +/* <-QAC 0639 */ +#endif diff --git a/targets/TARGET_RENESAS/TARGET_RZ_A1XX/TARGET_GR_LYCHEE/device/inc/iodefines/spdif_iodefine.h b/targets/TARGET_RENESAS/TARGET_RZ_A1XX/TARGET_GR_LYCHEE/device/inc/iodefines/spdif_iodefine.h new file mode 100644 index 0000000..f9960fa --- /dev/null +++ b/targets/TARGET_RENESAS/TARGET_RZ_A1XX/TARGET_GR_LYCHEE/device/inc/iodefines/spdif_iodefine.h @@ -0,0 +1,79 @@ +/******************************************************************************* +* DISCLAIMER +* This software is supplied by Renesas Electronics Corporation and is only +* intended for use with Renesas products. No other uses are authorized. This +* software is owned by Renesas Electronics Corporation and is protected under +* all applicable laws, including copyright laws. +* THIS SOFTWARE IS PROVIDED "AS IS" AND RENESAS MAKES NO WARRANTIES REGARDING +* THIS SOFTWARE, WHETHER EXPRESS, IMPLIED OR STATUTORY, INCLUDING BUT NOT +* LIMITED TO WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE +* AND NON-INFRINGEMENT. ALL SUCH WARRANTIES ARE EXPRESSLY DISCLAIMED. +* TO THE MAXIMUM EXTENT PERMITTED NOT PROHIBITED BY LAW, NEITHER RENESAS +* ELECTRONICS CORPORATION NOR ANY OF ITS AFFILIATED COMPANIES SHALL BE LIABLE +* FOR ANY DIRECT, INDIRECT, SPECIAL, INCIDENTAL OR CONSEQUENTIAL DAMAGES FOR +* ANY REASON RELATED TO THIS SOFTWARE, EVEN IF RENESAS OR ITS AFFILIATES HAVE +* BEEN ADVISED OF THE POSSIBILITY OF SUCH DAMAGES. +* Renesas reserves the right, without notice, to make changes to this software +* and to discontinue the availability of this software. By using this software, +* you agree to the additional terms and conditions found by accessing the +* following link: +* http://www.renesas.com/disclaimer* +* Copyright (C) 2013-2016 Renesas Electronics Corporation. All rights reserved. +*******************************************************************************/ +/******************************************************************************* +* File Name : spdif_iodefine.h +* $Rev: $ +* $Date:: $ +* Description : Definition of I/O Register for RZ/A1LU (V3.00l) +******************************************************************************/ +#ifndef SPDIF_IODEFINE_H +#define SPDIF_IODEFINE_H +/* ->QAC 0639 : Over 127 members (C90) */ +/* ->QAC 0857 : Over 1024 #define (C90) */ +/* ->MISRA 18.4 : Pack unpack union */ /* ->SEC M1.6.2 */ +/* ->SEC M1.10.1 : Not magic number */ + +#define SPDIF (*(struct st_spdif *)0xE8012000uL) /* SPDIF */ + + +#define SPDIFTLCA (SPDIF.TLCA) +#define SPDIFTRCA (SPDIF.TRCA) +#define SPDIFTLCS (SPDIF.TLCS) +#define SPDIFTRCS (SPDIF.TRCS) +#define SPDIFTUI (SPDIF.TUI) +#define SPDIFRLCA (SPDIF.RLCA) +#define SPDIFRRCA (SPDIF.RRCA) +#define SPDIFRLCS (SPDIF.RLCS) +#define SPDIFRRCS (SPDIF.RRCS) +#define SPDIFRUI (SPDIF.RUI) +#define SPDIFCTRL (SPDIF.CTRL) +#define SPDIFSTAT (SPDIF.STAT) +#define SPDIFTDAD (SPDIF.TDAD) +#define SPDIFRDAD (SPDIF.RDAD) + + +typedef struct st_spdif +{ + /* SPDIF */ + volatile uint32_t TLCA; /* TLCA */ + volatile uint32_t TRCA; /* TRCA */ + volatile uint32_t TLCS; /* TLCS */ + volatile uint32_t TRCS; /* TRCS */ + volatile uint32_t TUI; /* TUI */ + volatile uint32_t RLCA; /* RLCA */ + volatile uint32_t RRCA; /* RRCA */ + volatile uint32_t RLCS; /* RLCS */ + volatile uint32_t RRCS; /* RRCS */ + volatile uint32_t RUI; /* RUI */ + volatile uint32_t CTRL; /* CTRL */ + volatile uint32_t STAT; /* STAT */ + volatile uint32_t TDAD; /* TDAD */ + volatile uint32_t RDAD; /* RDAD */ +} r_io_spdif_t; + + +/* <-SEC M1.10.1 */ +/* <-MISRA 18.4 */ /* <-SEC M1.6.2 */ +/* <-QAC 0857 */ +/* <-QAC 0639 */ +#endif diff --git a/targets/TARGET_RENESAS/TARGET_RZ_A1XX/TARGET_GR_LYCHEE/device/inc/iodefines/spibsc_iodefine.h b/targets/TARGET_RENESAS/TARGET_RZ_A1XX/TARGET_GR_LYCHEE/device/inc/iodefines/spibsc_iodefine.h new file mode 100644 index 0000000..1879733 --- /dev/null +++ b/targets/TARGET_RENESAS/TARGET_RZ_A1XX/TARGET_GR_LYCHEE/device/inc/iodefines/spibsc_iodefine.h @@ -0,0 +1,150 @@ +/******************************************************************************* +* DISCLAIMER +* This software is supplied by Renesas Electronics Corporation and is only +* intended for use with Renesas products. No other uses are authorized. This +* software is owned by Renesas Electronics Corporation and is protected under +* all applicable laws, including copyright laws. +* THIS SOFTWARE IS PROVIDED "AS IS" AND RENESAS MAKES NO WARRANTIES REGARDING +* THIS SOFTWARE, WHETHER EXPRESS, IMPLIED OR STATUTORY, INCLUDING BUT NOT +* LIMITED TO WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE +* AND NON-INFRINGEMENT. ALL SUCH WARRANTIES ARE EXPRESSLY DISCLAIMED. +* TO THE MAXIMUM EXTENT PERMITTED NOT PROHIBITED BY LAW, NEITHER RENESAS +* ELECTRONICS CORPORATION NOR ANY OF ITS AFFILIATED COMPANIES SHALL BE LIABLE +* FOR ANY DIRECT, INDIRECT, SPECIAL, INCIDENTAL OR CONSEQUENTIAL DAMAGES FOR +* ANY REASON RELATED TO THIS SOFTWARE, EVEN IF RENESAS OR ITS AFFILIATES HAVE +* BEEN ADVISED OF THE POSSIBILITY OF SUCH DAMAGES. +* Renesas reserves the right, without notice, to make changes to this software +* and to discontinue the availability of this software. By using this software, +* you agree to the additional terms and conditions found by accessing the +* following link: +* http://www.renesas.com/disclaimer* +* Copyright (C) 2013-2016 Renesas Electronics Corporation. All rights reserved. +*******************************************************************************/ +/******************************************************************************* +* File Name : spibsc_iodefine.h +* $Rev: $ +* $Date:: $ +* Description : Definition of I/O Register for RZ/A1LU (V3.00l) +******************************************************************************/ +#ifndef SPIBSC_IODEFINE_H +#define SPIBSC_IODEFINE_H +/* ->QAC 0639 : Over 127 members (C90) */ +/* ->QAC 0857 : Over 1024 #define (C90) */ +/* ->MISRA 18.4 : Pack unpack union */ /* ->SEC M1.6.2 */ +/* ->SEC M1.10.1 : Not magic number */ + +#define SPIBSC0 (*(struct st_spibsc *)0x3FEFA000uL) /* SPIBSC0 */ + + +/* Start of channel array defines of SPIBSC */ + +/* Channel array defines of SPIBSC */ +/*(Sample) value = SPIBSC[ channel ]->CMNCR; */ +#define SPIBSC_COUNT (1) +#define SPIBSC_ADDRESS_LIST \ +{ /* ->MISRA 11.3 */ /* ->SEC R2.7.1 */ \ + &SPIBSC0 \ +} /* <-MISRA 11.3 */ /* <-SEC R2.7.1 */ /* { } is for MISRA 19.4 */ + +/* End of channel array defines of SPIBSC */ + + +#define CMNCR_0 (SPIBSC0.CMNCR) +#define SSLDR_0 (SPIBSC0.SSLDR) +#define SPBCR_0 (SPIBSC0.SPBCR) +#define DRCR_0 (SPIBSC0.DRCR) +#define DRCMR_0 (SPIBSC0.DRCMR) +#define DREAR_0 (SPIBSC0.DREAR) +#define DROPR_0 (SPIBSC0.DROPR) +#define DRENR_0 (SPIBSC0.DRENR) +#define SMCR_0 (SPIBSC0.SMCR) +#define SMCMR_0 (SPIBSC0.SMCMR) +#define SMADR_0 (SPIBSC0.SMADR) +#define SMOPR_0 (SPIBSC0.SMOPR) +#define SMENR_0 (SPIBSC0.SMENR) +#define SMRDR0_0 (SPIBSC0.SMRDR0.UINT32) +#define SMRDR0_0L (SPIBSC0.SMRDR0.UINT16[R_IO_L]) +#define SMRDR0_0H (SPIBSC0.SMRDR0.UINT16[R_IO_H]) +#define SMRDR0_0LL (SPIBSC0.SMRDR0.UINT8[R_IO_LL]) +#define SMRDR0_0LH (SPIBSC0.SMRDR0.UINT8[R_IO_LH]) +#define SMRDR0_0HL (SPIBSC0.SMRDR0.UINT8[R_IO_HL]) +#define SMRDR0_0HH (SPIBSC0.SMRDR0.UINT8[R_IO_HH]) +#define SMRDR1_0 (SPIBSC0.SMRDR1.UINT32) +#define SMRDR1_0L (SPIBSC0.SMRDR1.UINT16[R_IO_L]) +#define SMRDR1_0H (SPIBSC0.SMRDR1.UINT16[R_IO_H]) +#define SMRDR1_0LL (SPIBSC0.SMRDR1.UINT8[R_IO_LL]) +#define SMRDR1_0LH (SPIBSC0.SMRDR1.UINT8[R_IO_LH]) +#define SMRDR1_0HL (SPIBSC0.SMRDR1.UINT8[R_IO_HL]) +#define SMRDR1_0HH (SPIBSC0.SMRDR1.UINT8[R_IO_HH]) +#define SMWDR0_0 (SPIBSC0.SMWDR0.UINT32) +#define SMWDR0_0L (SPIBSC0.SMWDR0.UINT16[R_IO_L]) +#define SMWDR0_0H (SPIBSC0.SMWDR0.UINT16[R_IO_H]) +#define SMWDR0_0LL (SPIBSC0.SMWDR0.UINT8[R_IO_LL]) +#define SMWDR0_0LH (SPIBSC0.SMWDR0.UINT8[R_IO_LH]) +#define SMWDR0_0HL (SPIBSC0.SMWDR0.UINT8[R_IO_HL]) +#define SMWDR0_0HH (SPIBSC0.SMWDR0.UINT8[R_IO_HH]) +#define SMWDR1_0 (SPIBSC0.SMWDR1.UINT32) +#define SMWDR1_0L (SPIBSC0.SMWDR1.UINT16[R_IO_L]) +#define SMWDR1_0H (SPIBSC0.SMWDR1.UINT16[R_IO_H]) +#define SMWDR1_0LL (SPIBSC0.SMWDR1.UINT8[R_IO_LL]) +#define SMWDR1_0LH (SPIBSC0.SMWDR1.UINT8[R_IO_LH]) +#define SMWDR1_0HL (SPIBSC0.SMWDR1.UINT8[R_IO_HL]) +#define SMWDR1_0HH (SPIBSC0.SMWDR1.UINT8[R_IO_HH]) +#define CMNSR_0 (SPIBSC0.CMNSR) +#define CKDLY_0 (SPIBSC0.CKDLY) +#define DRDMCR_0 (SPIBSC0.DRDMCR) +#define DRDRENR_0 (SPIBSC0.DRDRENR) +#define SMDMCR_0 (SPIBSC0.SMDMCR) +#define SMDRENR_0 (SPIBSC0.SMDRENR) +#define SPODLY_0 (SPIBSC0.SPODLY) + + +typedef struct st_spibsc +{ + /* SPIBSC */ + volatile uint32_t CMNCR; /* CMNCR */ + volatile uint32_t SSLDR; /* SSLDR */ + volatile uint32_t SPBCR; /* SPBCR */ + volatile uint32_t DRCR; /* DRCR */ + volatile uint32_t DRCMR; /* DRCMR */ + volatile uint32_t DREAR; /* DREAR */ + volatile uint32_t DROPR; /* DROPR */ + volatile uint32_t DRENR; /* DRENR */ + volatile uint32_t SMCR; /* SMCR */ + volatile uint32_t SMCMR; /* SMCMR */ + volatile uint32_t SMADR; /* SMADR */ + volatile uint32_t SMOPR; /* SMOPR */ + volatile uint32_t SMENR; /* SMENR */ + volatile uint8_t dummy1[4]; /* */ + union iodefine_reg32_t SMRDR0; /* SMRDR0 */ + union iodefine_reg32_t SMRDR1; /* SMRDR1 */ + union iodefine_reg32_t SMWDR0; /* SMWDR0 */ + union iodefine_reg32_t SMWDR1; /* SMWDR1 */ + + volatile uint32_t CMNSR; /* CMNSR */ + volatile uint8_t dummy2[4]; /* */ + volatile uint32_t CKDLY; /* CKDLY */ + volatile uint8_t dummy3[4]; /* */ + volatile uint32_t DRDMCR; /* DRDMCR */ + volatile uint32_t DRDRENR; /* DRDRENR */ + volatile uint32_t SMDMCR; /* SMDMCR */ + volatile uint32_t SMDRENR; /* SMDRENR */ + volatile uint32_t SPODLY; /* SPODLY */ +} r_io_spibsc_t; + + +/* Channel array defines of SPIBSC (2)*/ +#ifdef DECLARE_SPIBSC_CHANNELS +volatile struct st_spibsc* SPIBSC[ SPIBSC_COUNT ] = + /* ->MISRA 11.3 */ /* ->SEC R2.7.1 */ + SPIBSC_ADDRESS_LIST; + /* <-MISRA 11.3 */ /* <-SEC R2.7.1 */ +#endif /* DECLARE_SPIBSC_CHANNELS */ +/* End of channel array defines of SPIBSC (2)*/ + + +/* <-SEC M1.10.1 */ +/* <-MISRA 18.4 */ /* <-SEC M1.6.2 */ +/* <-QAC 0857 */ +/* <-QAC 0639 */ +#endif diff --git a/targets/TARGET_RENESAS/TARGET_RZ_A1XX/TARGET_GR_LYCHEE/device/inc/iodefines/ssif_iodefine.h b/targets/TARGET_RENESAS/TARGET_RZ_A1XX/TARGET_GR_LYCHEE/device/inc/iodefines/ssif_iodefine.h new file mode 100644 index 0000000..84ed1cf --- /dev/null +++ b/targets/TARGET_RENESAS/TARGET_RZ_A1XX/TARGET_GR_LYCHEE/device/inc/iodefines/ssif_iodefine.h @@ -0,0 +1,128 @@ +/******************************************************************************* +* DISCLAIMER +* This software is supplied by Renesas Electronics Corporation and is only +* intended for use with Renesas products. No other uses are authorized. This +* software is owned by Renesas Electronics Corporation and is protected under +* all applicable laws, including copyright laws. +* THIS SOFTWARE IS PROVIDED "AS IS" AND RENESAS MAKES NO WARRANTIES REGARDING +* THIS SOFTWARE, WHETHER EXPRESS, IMPLIED OR STATUTORY, INCLUDING BUT NOT +* LIMITED TO WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE +* AND NON-INFRINGEMENT. ALL SUCH WARRANTIES ARE EXPRESSLY DISCLAIMED. +* TO THE MAXIMUM EXTENT PERMITTED NOT PROHIBITED BY LAW, NEITHER RENESAS +* ELECTRONICS CORPORATION NOR ANY OF ITS AFFILIATED COMPANIES SHALL BE LIABLE +* FOR ANY DIRECT, INDIRECT, SPECIAL, INCIDENTAL OR CONSEQUENTIAL DAMAGES FOR +* ANY REASON RELATED TO THIS SOFTWARE, EVEN IF RENESAS OR ITS AFFILIATES HAVE +* BEEN ADVISED OF THE POSSIBILITY OF SUCH DAMAGES. +* Renesas reserves the right, without notice, to make changes to this software +* and to discontinue the availability of this software. By using this software, +* you agree to the additional terms and conditions found by accessing the +* following link: +* http://www.renesas.com/disclaimer* +* Copyright (C) 2013-2016 Renesas Electronics Corporation. All rights reserved. +*******************************************************************************/ +/******************************************************************************* +* File Name : ssif_iodefine.h +* $Rev: $ +* $Date:: $ +* Description : Definition of I/O Register for RZ/A1LU (V3.00l) +******************************************************************************/ +#ifndef SSIF_IODEFINE_H +#define SSIF_IODEFINE_H +/* ->QAC 0639 : Over 127 members (C90) */ +/* ->QAC 0857 : Over 1024 #define (C90) */ +/* ->MISRA 18.4 : Pack unpack union */ /* ->SEC M1.6.2 */ +/* ->SEC M1.10.1 : Not magic number */ + +#define SSIF0 (*(struct st_ssif *)0xE820B000uL) /* SSIF0 */ +#define SSIF1 (*(struct st_ssif *)0xE820B800uL) /* SSIF1 */ +#define SSIF2 (*(struct st_ssif *)0xE820C000uL) /* SSIF2 */ +#define SSIF3 (*(struct st_ssif *)0xE820C800uL) /* SSIF3 */ + + +/* Start of channel array defines of SSIF */ + +/* Channel array defines of SSIF */ +/*(Sample) value = SSIF[ channel ]->SSICR; */ +#define SSIF_COUNT (4) +#define SSIF_ADDRESS_LIST \ +{ /* ->MISRA 11.3 */ /* ->SEC R2.7.1 */ \ + &SSIF0, &SSIF1, &SSIF2, &SSIF3 \ +} /* <-MISRA 11.3 */ /* <-SEC R2.7.1 */ /* { } is for MISRA 19.4 */ + +/* End of channel array defines of SSIF */ + + +#define SSICR_0 (SSIF0.SSICR) +#define SSISR_0 (SSIF0.SSISR) +#define SSIFCR_0 (SSIF0.SSIFCR) +#define SSIFSR_0 (SSIF0.SSIFSR) +#define SSIFTDR_0 (SSIF0.SSIFTDR) +#define SSIFRDR_0 (SSIF0.SSIFRDR) +#define SSITDMR_0 (SSIF0.SSITDMR) +#define SSIFCCR_0 (SSIF0.SSIFCCR) +#define SSIFCMR_0 (SSIF0.SSIFCMR) +#define SSIFCSR_0 (SSIF0.SSIFCSR) +#define SSICR_1 (SSIF1.SSICR) +#define SSISR_1 (SSIF1.SSISR) +#define SSIFCR_1 (SSIF1.SSIFCR) +#define SSIFSR_1 (SSIF1.SSIFSR) +#define SSIFTDR_1 (SSIF1.SSIFTDR) +#define SSIFRDR_1 (SSIF1.SSIFRDR) +#define SSITDMR_1 (SSIF1.SSITDMR) +#define SSIFCCR_1 (SSIF1.SSIFCCR) +#define SSIFCMR_1 (SSIF1.SSIFCMR) +#define SSIFCSR_1 (SSIF1.SSIFCSR) +#define SSICR_2 (SSIF2.SSICR) +#define SSISR_2 (SSIF2.SSISR) +#define SSIFCR_2 (SSIF2.SSIFCR) +#define SSIFSR_2 (SSIF2.SSIFSR) +#define SSIFTDR_2 (SSIF2.SSIFTDR) +#define SSIFRDR_2 (SSIF2.SSIFRDR) +#define SSITDMR_2 (SSIF2.SSITDMR) +#define SSIFCCR_2 (SSIF2.SSIFCCR) +#define SSIFCMR_2 (SSIF2.SSIFCMR) +#define SSIFCSR_2 (SSIF2.SSIFCSR) +#define SSICR_3 (SSIF3.SSICR) +#define SSISR_3 (SSIF3.SSISR) +#define SSIFCR_3 (SSIF3.SSIFCR) +#define SSIFSR_3 (SSIF3.SSIFSR) +#define SSIFTDR_3 (SSIF3.SSIFTDR) +#define SSIFRDR_3 (SSIF3.SSIFRDR) +#define SSITDMR_3 (SSIF3.SSITDMR) +#define SSIFCCR_3 (SSIF3.SSIFCCR) +#define SSIFCMR_3 (SSIF3.SSIFCMR) +#define SSIFCSR_3 (SSIF3.SSIFCSR) + + +typedef struct st_ssif +{ + /* SSIF */ + volatile uint32_t SSICR; /* SSICR */ + volatile uint32_t SSISR; /* SSISR */ + volatile uint8_t dummy1[8]; /* */ + volatile uint32_t SSIFCR; /* SSIFCR */ + volatile uint32_t SSIFSR; /* SSIFSR */ + volatile uint32_t SSIFTDR; /* SSIFTDR */ + volatile uint32_t SSIFRDR; /* SSIFRDR */ + volatile uint32_t SSITDMR; /* SSITDMR */ + volatile uint32_t SSIFCCR; /* SSIFCCR */ + volatile uint32_t SSIFCMR; /* SSIFCMR */ + volatile uint32_t SSIFCSR; /* SSIFCSR */ +} r_io_ssif_t; + + +/* Channel array defines of SSIF (2)*/ +#ifdef DECLARE_SSIF_CHANNELS +volatile struct st_ssif* SSIF[ SSIF_COUNT ] = + /* ->MISRA 11.3 */ /* ->SEC R2.7.1 */ + SSIF_ADDRESS_LIST; + /* <-MISRA 11.3 */ /* <-SEC R2.7.1 */ +#endif /* DECLARE_SSIF_CHANNELS */ +/* End of channel array defines of SSIF (2)*/ + + +/* <-SEC M1.10.1 */ +/* <-MISRA 18.4 */ /* <-SEC M1.6.2 */ +/* <-QAC 0857 */ +/* <-QAC 0639 */ +#endif diff --git a/targets/TARGET_RENESAS/TARGET_RZ_A1XX/TARGET_GR_LYCHEE/device/inc/iodefines/usb20_iodefine.h b/targets/TARGET_RENESAS/TARGET_RZ_A1XX/TARGET_GR_LYCHEE/device/inc/iodefines/usb20_iodefine.h new file mode 100644 index 0000000..1ad3fbd --- /dev/null +++ b/targets/TARGET_RENESAS/TARGET_RZ_A1XX/TARGET_GR_LYCHEE/device/inc/iodefines/usb20_iodefine.h @@ -0,0 +1,622 @@ +/******************************************************************************* +* DISCLAIMER +* This software is supplied by Renesas Electronics Corporation and is only +* intended for use with Renesas products. No other uses are authorized. This +* software is owned by Renesas Electronics Corporation and is protected under +* all applicable laws, including copyright laws. +* THIS SOFTWARE IS PROVIDED "AS IS" AND RENESAS MAKES NO WARRANTIES REGARDING +* THIS SOFTWARE, WHETHER EXPRESS, IMPLIED OR STATUTORY, INCLUDING BUT NOT +* LIMITED TO WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE +* AND NON-INFRINGEMENT. ALL SUCH WARRANTIES ARE EXPRESSLY DISCLAIMED. +* TO THE MAXIMUM EXTENT PERMITTED NOT PROHIBITED BY LAW, NEITHER RENESAS +* ELECTRONICS CORPORATION NOR ANY OF ITS AFFILIATED COMPANIES SHALL BE LIABLE +* FOR ANY DIRECT, INDIRECT, SPECIAL, INCIDENTAL OR CONSEQUENTIAL DAMAGES FOR +* ANY REASON RELATED TO THIS SOFTWARE, EVEN IF RENESAS OR ITS AFFILIATES HAVE +* BEEN ADVISED OF THE POSSIBILITY OF SUCH DAMAGES. +* Renesas reserves the right, without notice, to make changes to this software +* and to discontinue the availability of this software. By using this software, +* you agree to the additional terms and conditions found by accessing the +* following link: +* http://www.renesas.com/disclaimer* +* Copyright (C) 2013-2016 Renesas Electronics Corporation. All rights reserved. +*******************************************************************************/ +/******************************************************************************* +* File Name : usb20_iodefine.h +* $Rev: $ +* $Date:: $ +* Description : Definition of I/O Register for RZ/A1LU (V3.00l) +******************************************************************************/ +#ifndef USB20_IODEFINE_H +#define USB20_IODEFINE_H +/* ->QAC 0639 : Over 127 members (C90) */ +/* ->QAC 0857 : Over 1024 #define (C90) */ +/* ->MISRA 18.4 : Pack unpack union */ /* ->SEC M1.6.2 */ +/* ->SEC M1.10.1 : Not magic number */ + +#define USB200 (*(struct st_usb20 *)0xE8010000uL) /* USB200 */ +#define USB201 (*(struct st_usb20 *)0xE8207000uL) /* USB201 */ + + +/* Start of channel array defines of USB20 */ + +/* Channel array defines of USB20 */ +/*(Sample) value = USB20[ channel ]->SYSCFG0; */ +#define USB20_COUNT (2) +#define USB20_ADDRESS_LIST \ +{ /* ->MISRA 11.3 */ /* ->SEC R2.7.1 */ \ + &USB200, &USB201 \ +} /* <-MISRA 11.3 */ /* <-SEC R2.7.1 */ /* { } is for MISRA 19.4 */ + + + +/* Channel array defines of USB20_FROM_D0FIFOB0 */ +/*(Sample) value = USB20_FROM_D0FIFOB0[ channel ][ index ]->D0FIFOB0; */ +#define USB20_FROM_D0FIFOB0_COUNT (2) +#define USB20_FROM_D0FIFOB0_ADDRESS_LIST \ +{ /* ->MISRA 11.3 */ /* ->SEC R2.7.1 */ \ +{ \ + &USB200_FROM_D0FIFOB0, &USB200_FROM_D1FIFOB0 },{ \ + &USB201_FROM_D0FIFOB0, &USB201_FROM_D1FIFOB0 \ +} \ +} /* <-MISRA 11.3 */ /* <-SEC R2.7.1 */ /* { } is for MISRA 19.4 */ +#define USB200_FROM_D0FIFOB0 (*(struct st_usb20_from_dmfifob0 *)&USB200.D0FIFOB0) /* USB200_FROM_D0FIFOB0 */ +#define USB200_FROM_D1FIFOB0 (*(struct st_usb20_from_dmfifob0 *)&USB200.D1FIFOB0) /* USB200_FROM_D1FIFOB0 */ +#define USB201_FROM_D0FIFOB0 (*(struct st_usb20_from_dmfifob0 *)&USB201.D0FIFOB0) /* USB201_FROM_D0FIFOB0 */ +#define USB201_FROM_D1FIFOB0 (*(struct st_usb20_from_dmfifob0 *)&USB201.D1FIFOB0) /* USB201_FROM_D1FIFOB0 */ + + + + +/* Channel array defines of USB20_FROM_PIPE1ATRE */ +/*(Sample) value = USB20_FROM_PIPE1ATRE[ channel ][ index ]->PIPE1TRE; */ +#define USB20_FROM_PIPE1ATRE_COUNT (5) +#define USB20_FROM_PIPE1ATRE_ADDRESS_LIST \ +{ /* ->MISRA 11.3 */ /* ->SEC R2.7.1 */ \ +{ \ + &USB200_FROM_PIPE1TRE, &USB200_FROM_PIPE2TRE, &USB200_FROM_PIPE3TRE, &USB200_FROM_PIPE4TRE, &USB200_FROM_PIPE5TRE },{ \ + &USB201_FROM_PIPE1TRE, &USB201_FROM_PIPE2TRE, &USB201_FROM_PIPE3TRE, &USB201_FROM_PIPE4TRE, &USB201_FROM_PIPE5TRE \ +} \ +} /* <-MISRA 11.3 */ /* <-SEC R2.7.1 */ /* { } is for MISRA 19.4 */ +#define USB200_FROM_PIPE1TRE (*(struct st_usb20_from_pipe1tre *)&USB200.PIPE1TRE) /* USB200_FROM_PIPE1TRE */ +#define USB200_FROM_PIPE2TRE (*(struct st_usb20_from_pipe1tre *)&USB200.PIPE2TRE) /* USB200_FROM_PIPE2TRE */ +#define USB200_FROM_PIPE3TRE (*(struct st_usb20_from_pipe1tre *)&USB200.PIPE3TRE) /* USB200_FROM_PIPE3TRE */ +#define USB200_FROM_PIPE4TRE (*(struct st_usb20_from_pipe1tre *)&USB200.PIPE4TRE) /* USB200_FROM_PIPE4TRE */ +#define USB200_FROM_PIPE5TRE (*(struct st_usb20_from_pipe1tre *)&USB200.PIPE5TRE) /* USB200_FROM_PIPE5TRE */ +#define USB201_FROM_PIPE1TRE (*(struct st_usb20_from_pipe1tre *)&USB201.PIPE1TRE) /* USB201_FROM_PIPE1TRE */ +#define USB201_FROM_PIPE2TRE (*(struct st_usb20_from_pipe1tre *)&USB201.PIPE2TRE) /* USB201_FROM_PIPE2TRE */ +#define USB201_FROM_PIPE3TRE (*(struct st_usb20_from_pipe1tre *)&USB201.PIPE3TRE) /* USB201_FROM_PIPE3TRE */ +#define USB201_FROM_PIPE4TRE (*(struct st_usb20_from_pipe1tre *)&USB201.PIPE4TRE) /* USB201_FROM_PIPE4TRE */ +#define USB201_FROM_PIPE5TRE (*(struct st_usb20_from_pipe1tre *)&USB201.PIPE5TRE) /* USB201_FROM_PIPE5TRE */ + + + + +/* Channel array defines of USB20_FROM_D0FIFOSEL */ +/*(Sample) value = USB20_FROM_D0FIFOSEL[ channel ][ index ]->D0FIFOSEL; */ +#define USB20_FROM_D0FIFOSEL_COUNT (2) +#define USB20_FROM_D0FIFOSEL_ADDRESS_LIST \ +{ /* ->MISRA 11.3 */ /* ->SEC R2.7.1 */ \ +{ \ + &USB200_FROM_D0FIFOSEL, &USB200_FROM_D1FIFOSEL },{ \ + &USB201_FROM_D0FIFOSEL, &USB201_FROM_D1FIFOSEL \ +} \ +} /* <-MISRA 11.3 */ /* <-SEC R2.7.1 */ /* { } is for MISRA 19.4 */ +#define USB200_FROM_D0FIFOSEL (*(struct st_usb20_from_d0fifosel *)&USB200.D0FIFOSEL) /* USB200_FROM_D0FIFOSEL */ +#define USB200_FROM_D1FIFOSEL (*(struct st_usb20_from_d0fifosel *)&USB200.D1FIFOSEL) /* USB200_FROM_D1FIFOSEL */ +#define USB201_FROM_D0FIFOSEL (*(struct st_usb20_from_d0fifosel *)&USB201.D0FIFOSEL) /* USB201_FROM_D0FIFOSEL */ +#define USB201_FROM_D1FIFOSEL (*(struct st_usb20_from_d0fifosel *)&USB201.D1FIFOSEL) /* USB201_FROM_D1FIFOSEL */ + + +/* End of channel array defines of USB20 */ + + +#define SYSCFG0_0 (USB200.SYSCFG0) +#define BUSWAIT_0 (USB200.BUSWAIT) +#define SYSSTS0_0 (USB200.SYSSTS0) +#define DVSTCTR0_0 (USB200.DVSTCTR0) +#define TESTMODE_0 (USB200.TESTMODE) +#define D0FBCFG_0 (USB200.D0FBCFG) +#define D1FBCFG_0 (USB200.D1FBCFG) +#define CFIFO_0 (USB200.CFIFO.UINT32) +#define CFIFO_0L (USB200.CFIFO.UINT16[R_IO_L]) +#define CFIFO_0H (USB200.CFIFO.UINT16[R_IO_H]) +#define CFIFO_0LL (USB200.CFIFO.UINT8[R_IO_LL]) +#define CFIFO_0LH (USB200.CFIFO.UINT8[R_IO_LH]) +#define CFIFO_0HL (USB200.CFIFO.UINT8[R_IO_HL]) +#define CFIFO_0HH (USB200.CFIFO.UINT8[R_IO_HH]) +#define D0FIFO_0 (USB200.D0FIFO.UINT32) +#define D0FIFO_0L (USB200.D0FIFO.UINT16[R_IO_L]) +#define D0FIFO_0H (USB200.D0FIFO.UINT16[R_IO_H]) +#define D0FIFO_0LL (USB200.D0FIFO.UINT8[R_IO_LL]) +#define D0FIFO_0LH (USB200.D0FIFO.UINT8[R_IO_LH]) +#define D0FIFO_0HL (USB200.D0FIFO.UINT8[R_IO_HL]) +#define D0FIFO_0HH (USB200.D0FIFO.UINT8[R_IO_HH]) +#define D1FIFO_0 (USB200.D1FIFO.UINT32) +#define D1FIFO_0L (USB200.D1FIFO.UINT16[R_IO_L]) +#define D1FIFO_0H (USB200.D1FIFO.UINT16[R_IO_H]) +#define D1FIFO_0LL (USB200.D1FIFO.UINT8[R_IO_LL]) +#define D1FIFO_0LH (USB200.D1FIFO.UINT8[R_IO_LH]) +#define D1FIFO_0HL (USB200.D1FIFO.UINT8[R_IO_HL]) +#define D1FIFO_0HH (USB200.D1FIFO.UINT8[R_IO_HH]) +#define CFIFOSEL_0 (USB200.CFIFOSEL) +#define CFIFOCTR_0 (USB200.CFIFOCTR) +#define D0FIFOSEL_0 (USB200.D0FIFOSEL) +#define D0FIFOCTR_0 (USB200.D0FIFOCTR) +#define D1FIFOSEL_0 (USB200.D1FIFOSEL) +#define D1FIFOCTR_0 (USB200.D1FIFOCTR) +#define INTENB0_0 (USB200.INTENB0) +#define INTENB1_0 (USB200.INTENB1) +#define BRDYENB_0 (USB200.BRDYENB) +#define NRDYENB_0 (USB200.NRDYENB) +#define BEMPENB_0 (USB200.BEMPENB) +#define SOFCFG_0 (USB200.SOFCFG) +#define INTSTS0_0 (USB200.INTSTS0) +#define INTSTS1_0 (USB200.INTSTS1) +#define BRDYSTS_0 (USB200.BRDYSTS) +#define NRDYSTS_0 (USB200.NRDYSTS) +#define BEMPSTS_0 (USB200.BEMPSTS) +#define FRMNUM_0 (USB200.FRMNUM) +#define UFRMNUM_0 (USB200.UFRMNUM) +#define USBADDR_0 (USB200.USBADDR) +#define USBREQ_0 (USB200.USBREQ) +#define USBVAL_0 (USB200.USBVAL) +#define USBINDX_0 (USB200.USBINDX) +#define USBLENG_0 (USB200.USBLENG) +#define DCPCFG_0 (USB200.DCPCFG) +#define DCPMAXP_0 (USB200.DCPMAXP) +#define DCPCTR_0 (USB200.DCPCTR) +#define PIPESEL_0 (USB200.PIPESEL) +#define PIPECFG_0 (USB200.PIPECFG) +#define PIPEBUF_0 (USB200.PIPEBUF) +#define PIPEMAXP_0 (USB200.PIPEMAXP) +#define PIPEPERI_0 (USB200.PIPEPERI) +#define PIPE1CTR_0 (USB200.PIPE1CTR) +#define PIPE2CTR_0 (USB200.PIPE2CTR) +#define PIPE3CTR_0 (USB200.PIPE3CTR) +#define PIPE4CTR_0 (USB200.PIPE4CTR) +#define PIPE5CTR_0 (USB200.PIPE5CTR) +#define PIPE6CTR_0 (USB200.PIPE6CTR) +#define PIPE7CTR_0 (USB200.PIPE7CTR) +#define PIPE8CTR_0 (USB200.PIPE8CTR) +#define PIPE9CTR_0 (USB200.PIPE9CTR) +#define PIPEACTR_0 (USB200.PIPEACTR) +#define PIPEBCTR_0 (USB200.PIPEBCTR) +#define PIPECCTR_0 (USB200.PIPECCTR) +#define PIPEDCTR_0 (USB200.PIPEDCTR) +#define PIPEECTR_0 (USB200.PIPEECTR) +#define PIPEFCTR_0 (USB200.PIPEFCTR) +#define PIPE1TRE_0 (USB200.PIPE1TRE) +#define PIPE1TRN_0 (USB200.PIPE1TRN) +#define PIPE2TRE_0 (USB200.PIPE2TRE) +#define PIPE2TRN_0 (USB200.PIPE2TRN) +#define PIPE3TRE_0 (USB200.PIPE3TRE) +#define PIPE3TRN_0 (USB200.PIPE3TRN) +#define PIPE4TRE_0 (USB200.PIPE4TRE) +#define PIPE4TRN_0 (USB200.PIPE4TRN) +#define PIPE5TRE_0 (USB200.PIPE5TRE) +#define PIPE5TRN_0 (USB200.PIPE5TRN) +#define PIPEBTRE_0 (USB200.PIPEBTRE) +#define PIPEBTRN_0 (USB200.PIPEBTRN) +#define PIPECTRE_0 (USB200.PIPECTRE) +#define PIPECTRN_0 (USB200.PIPECTRN) +#define PIPEDTRE_0 (USB200.PIPEDTRE) +#define PIPEDTRN_0 (USB200.PIPEDTRN) +#define PIPEETRE_0 (USB200.PIPEETRE) +#define PIPEETRN_0 (USB200.PIPEETRN) +#define PIPEFTRE_0 (USB200.PIPEFTRE) +#define PIPEFTRN_0 (USB200.PIPEFTRN) +#define PIPE9TRE_0 (USB200.PIPE9TRE) +#define PIPE9TRN_0 (USB200.PIPE9TRN) +#define PIPEATRE_0 (USB200.PIPEATRE) +#define PIPEATRN_0 (USB200.PIPEATRN) +#define DEVADD0_0 (USB200.DEVADD0) +#define DEVADD1_0 (USB200.DEVADD1) +#define DEVADD2_0 (USB200.DEVADD2) +#define DEVADD3_0 (USB200.DEVADD3) +#define DEVADD4_0 (USB200.DEVADD4) +#define DEVADD5_0 (USB200.DEVADD5) +#define DEVADD6_0 (USB200.DEVADD6) +#define DEVADD7_0 (USB200.DEVADD7) +#define DEVADD8_0 (USB200.DEVADD8) +#define DEVADD9_0 (USB200.DEVADD9) +#define DEVADDA_0 (USB200.DEVADDA) +#define SUSPMODE_0 (USB200.SUSPMODE) +#define D0FIFOB0_0 (USB200.D0FIFOB0) +#define D0FIFOB1_0 (USB200.D0FIFOB1) +#define D0FIFOB2_0 (USB200.D0FIFOB2) +#define D0FIFOB3_0 (USB200.D0FIFOB3) +#define D0FIFOB4_0 (USB200.D0FIFOB4) +#define D0FIFOB5_0 (USB200.D0FIFOB5) +#define D0FIFOB6_0 (USB200.D0FIFOB6) +#define D0FIFOB7_0 (USB200.D0FIFOB7) +#define D1FIFOB0_0 (USB200.D1FIFOB0) +#define D1FIFOB1_0 (USB200.D1FIFOB1) +#define D1FIFOB2_0 (USB200.D1FIFOB2) +#define D1FIFOB3_0 (USB200.D1FIFOB3) +#define D1FIFOB4_0 (USB200.D1FIFOB4) +#define D1FIFOB5_0 (USB200.D1FIFOB5) +#define D1FIFOB6_0 (USB200.D1FIFOB6) +#define D1FIFOB7_0 (USB200.D1FIFOB7) +#define SYSCFG0_1 (USB201.SYSCFG0) +#define BUSWAIT_1 (USB201.BUSWAIT) +#define SYSSTS0_1 (USB201.SYSSTS0) +#define DVSTCTR0_1 (USB201.DVSTCTR0) +#define TESTMODE_1 (USB201.TESTMODE) +#define D0FBCFG_1 (USB201.D0FBCFG) +#define D1FBCFG_1 (USB201.D1FBCFG) +#define CFIFO_1 (USB201.CFIFO.UINT32) +#define CFIFO_1L (USB201.CFIFO.UINT16[R_IO_L]) +#define CFIFO_1H (USB201.CFIFO.UINT16[R_IO_H]) +#define CFIFO_1LL (USB201.CFIFO.UINT8[R_IO_LL]) +#define CFIFO_1LH (USB201.CFIFO.UINT8[R_IO_LH]) +#define CFIFO_1HL (USB201.CFIFO.UINT8[R_IO_HL]) +#define CFIFO_1HH (USB201.CFIFO.UINT8[R_IO_HH]) +#define D0FIFO_1 (USB201.D0FIFO.UINT32) +#define D0FIFO_1L (USB201.D0FIFO.UINT16[R_IO_L]) +#define D0FIFO_1H (USB201.D0FIFO.UINT16[R_IO_H]) +#define D0FIFO_1LL (USB201.D0FIFO.UINT8[R_IO_LL]) +#define D0FIFO_1LH (USB201.D0FIFO.UINT8[R_IO_LH]) +#define D0FIFO_1HL (USB201.D0FIFO.UINT8[R_IO_HL]) +#define D0FIFO_1HH (USB201.D0FIFO.UINT8[R_IO_HH]) +#define D1FIFO_1 (USB201.D1FIFO.UINT32) +#define D1FIFO_1L (USB201.D1FIFO.UINT16[R_IO_L]) +#define D1FIFO_1H (USB201.D1FIFO.UINT16[R_IO_H]) +#define D1FIFO_1LL (USB201.D1FIFO.UINT8[R_IO_LL]) +#define D1FIFO_1LH (USB201.D1FIFO.UINT8[R_IO_LH]) +#define D1FIFO_1HL (USB201.D1FIFO.UINT8[R_IO_HL]) +#define D1FIFO_1HH (USB201.D1FIFO.UINT8[R_IO_HH]) +#define CFIFOSEL_1 (USB201.CFIFOSEL) +#define CFIFOCTR_1 (USB201.CFIFOCTR) +#define D0FIFOSEL_1 (USB201.D0FIFOSEL) +#define D0FIFOCTR_1 (USB201.D0FIFOCTR) +#define D1FIFOSEL_1 (USB201.D1FIFOSEL) +#define D1FIFOCTR_1 (USB201.D1FIFOCTR) +#define INTENB0_1 (USB201.INTENB0) +#define INTENB1_1 (USB201.INTENB1) +#define BRDYENB_1 (USB201.BRDYENB) +#define NRDYENB_1 (USB201.NRDYENB) +#define BEMPENB_1 (USB201.BEMPENB) +#define SOFCFG_1 (USB201.SOFCFG) +#define INTSTS0_1 (USB201.INTSTS0) +#define INTSTS1_1 (USB201.INTSTS1) +#define BRDYSTS_1 (USB201.BRDYSTS) +#define NRDYSTS_1 (USB201.NRDYSTS) +#define BEMPSTS_1 (USB201.BEMPSTS) +#define FRMNUM_1 (USB201.FRMNUM) +#define UFRMNUM_1 (USB201.UFRMNUM) +#define USBADDR_1 (USB201.USBADDR) +#define USBREQ_1 (USB201.USBREQ) +#define USBVAL_1 (USB201.USBVAL) +#define USBINDX_1 (USB201.USBINDX) +#define USBLENG_1 (USB201.USBLENG) +#define DCPCFG_1 (USB201.DCPCFG) +#define DCPMAXP_1 (USB201.DCPMAXP) +#define DCPCTR_1 (USB201.DCPCTR) +#define PIPESEL_1 (USB201.PIPESEL) +#define PIPECFG_1 (USB201.PIPECFG) +#define PIPEBUF_1 (USB201.PIPEBUF) +#define PIPEMAXP_1 (USB201.PIPEMAXP) +#define PIPEPERI_1 (USB201.PIPEPERI) +#define PIPE1CTR_1 (USB201.PIPE1CTR) +#define PIPE2CTR_1 (USB201.PIPE2CTR) +#define PIPE3CTR_1 (USB201.PIPE3CTR) +#define PIPE4CTR_1 (USB201.PIPE4CTR) +#define PIPE5CTR_1 (USB201.PIPE5CTR) +#define PIPE6CTR_1 (USB201.PIPE6CTR) +#define PIPE7CTR_1 (USB201.PIPE7CTR) +#define PIPE8CTR_1 (USB201.PIPE8CTR) +#define PIPE9CTR_1 (USB201.PIPE9CTR) +#define PIPEACTR_1 (USB201.PIPEACTR) +#define PIPEBCTR_1 (USB201.PIPEBCTR) +#define PIPECCTR_1 (USB201.PIPECCTR) +#define PIPEDCTR_1 (USB201.PIPEDCTR) +#define PIPEECTR_1 (USB201.PIPEECTR) +#define PIPEFCTR_1 (USB201.PIPEFCTR) +#define PIPE1TRE_1 (USB201.PIPE1TRE) +#define PIPE1TRN_1 (USB201.PIPE1TRN) +#define PIPE2TRE_1 (USB201.PIPE2TRE) +#define PIPE2TRN_1 (USB201.PIPE2TRN) +#define PIPE3TRE_1 (USB201.PIPE3TRE) +#define PIPE3TRN_1 (USB201.PIPE3TRN) +#define PIPE4TRE_1 (USB201.PIPE4TRE) +#define PIPE4TRN_1 (USB201.PIPE4TRN) +#define PIPE5TRE_1 (USB201.PIPE5TRE) +#define PIPE5TRN_1 (USB201.PIPE5TRN) +#define PIPEBTRE_1 (USB201.PIPEBTRE) +#define PIPEBTRN_1 (USB201.PIPEBTRN) +#define PIPECTRE_1 (USB201.PIPECTRE) +#define PIPECTRN_1 (USB201.PIPECTRN) +#define PIPEDTRE_1 (USB201.PIPEDTRE) +#define PIPEDTRN_1 (USB201.PIPEDTRN) +#define PIPEETRE_1 (USB201.PIPEETRE) +#define PIPEETRN_1 (USB201.PIPEETRN) +#define PIPEFTRE_1 (USB201.PIPEFTRE) +#define PIPEFTRN_1 (USB201.PIPEFTRN) +#define PIPE9TRE_1 (USB201.PIPE9TRE) +#define PIPE9TRN_1 (USB201.PIPE9TRN) +#define PIPEATRE_1 (USB201.PIPEATRE) +#define PIPEATRN_1 (USB201.PIPEATRN) +#define DEVADD0_1 (USB201.DEVADD0) +#define DEVADD1_1 (USB201.DEVADD1) +#define DEVADD2_1 (USB201.DEVADD2) +#define DEVADD3_1 (USB201.DEVADD3) +#define DEVADD4_1 (USB201.DEVADD4) +#define DEVADD5_1 (USB201.DEVADD5) +#define DEVADD6_1 (USB201.DEVADD6) +#define DEVADD7_1 (USB201.DEVADD7) +#define DEVADD8_1 (USB201.DEVADD8) +#define DEVADD9_1 (USB201.DEVADD9) +#define DEVADDA_1 (USB201.DEVADDA) +#define SUSPMODE_1 (USB201.SUSPMODE) +#define D0FIFOB0_1 (USB201.D0FIFOB0) +#define D0FIFOB1_1 (USB201.D0FIFOB1) +#define D0FIFOB2_1 (USB201.D0FIFOB2) +#define D0FIFOB3_1 (USB201.D0FIFOB3) +#define D0FIFOB4_1 (USB201.D0FIFOB4) +#define D0FIFOB5_1 (USB201.D0FIFOB5) +#define D0FIFOB6_1 (USB201.D0FIFOB6) +#define D0FIFOB7_1 (USB201.D0FIFOB7) +#define D1FIFOB0_1 (USB201.D1FIFOB0) +#define D1FIFOB1_1 (USB201.D1FIFOB1) +#define D1FIFOB2_1 (USB201.D1FIFOB2) +#define D1FIFOB3_1 (USB201.D1FIFOB3) +#define D1FIFOB4_1 (USB201.D1FIFOB4) +#define D1FIFOB5_1 (USB201.D1FIFOB5) +#define D1FIFOB6_1 (USB201.D1FIFOB6) +#define D1FIFOB7_1 (USB201.D1FIFOB7) + +#define USB20_D0FBCFG_COUNT (2) +#define USB20_D0FIFO_COUNT (2) +#define USB20_INTENB0_COUNT (2) +#define USB20_INTSTS0_COUNT (2) +#define USB20_PIPE1CTR_COUNT (0xF) +#define USB20_DEVADD0_COUNT (0xB) +#define USB20_D0FIFOB0_COUNT (0x8) + + +typedef struct st_usb20 +{ + /* USB20 */ + volatile uint16_t SYSCFG0; /* SYSCFG0 */ + volatile uint16_t BUSWAIT; /* BUSWAIT */ + volatile uint16_t SYSSTS0; /* SYSSTS0 */ + volatile uint8_t dummy1[2]; /* */ + volatile uint16_t DVSTCTR0; /* DVSTCTR0 */ + volatile uint8_t dummy2[2]; /* */ + volatile uint16_t TESTMODE; /* TESTMODE */ + volatile uint8_t dummy3[2]; /* */ + +/* #define USB20_D0FBCFG_COUNT (2) */ + volatile uint16_t D0FBCFG; /* D0FBCFG */ + volatile uint16_t D1FBCFG; /* D1FBCFG */ + union iodefine_reg32_t CFIFO; /* CFIFO */ + +/* #define USB20_D0FIFO_COUNT (2) */ + union iodefine_reg32_t D0FIFO; /* D0FIFO */ + union iodefine_reg32_t D1FIFO; /* D1FIFO */ + + volatile uint16_t CFIFOSEL; /* CFIFOSEL */ + volatile uint16_t CFIFOCTR; /* CFIFOCTR */ + volatile uint8_t dummy4[4]; /* */ + +/* start of struct st_usb20_from_d0fifosel */ + volatile uint16_t D0FIFOSEL; /* D0FIFOSEL */ + volatile uint16_t D0FIFOCTR; /* D0FIFOCTR */ + +/* end of struct st_usb20_from_d0fifosel */ + +/* start of struct st_usb20_from_d0fifosel */ + volatile uint16_t D1FIFOSEL; /* D1FIFOSEL */ + volatile uint16_t D1FIFOCTR; /* D1FIFOCTR */ + +/* end of struct st_usb20_from_d0fifosel */ + +/* #define USB20_INTENB0_COUNT (2) */ + volatile uint16_t INTENB0; /* INTENB0 */ + volatile uint16_t INTENB1; /* INTENB1 */ + volatile uint8_t dummy5[2]; /* */ + volatile uint16_t BRDYENB; /* BRDYENB */ + volatile uint16_t NRDYENB; /* NRDYENB */ + volatile uint16_t BEMPENB; /* BEMPENB */ + volatile uint16_t SOFCFG; /* SOFCFG */ + volatile uint8_t dummy6[2]; /* */ + +/* #define USB20_INTSTS0_COUNT (2) */ + volatile uint16_t INTSTS0; /* INTSTS0 */ + volatile uint16_t INTSTS1; /* INTSTS1 */ + volatile uint8_t dummy7[2]; /* */ + volatile uint16_t BRDYSTS; /* BRDYSTS */ + volatile uint16_t NRDYSTS; /* NRDYSTS */ + volatile uint16_t BEMPSTS; /* BEMPSTS */ + volatile uint16_t FRMNUM; /* FRMNUM */ + volatile uint16_t UFRMNUM; /* UFRMNUM */ + volatile uint16_t USBADDR; /* USBADDR */ + volatile uint8_t dummy8[2]; /* */ + volatile uint16_t USBREQ; /* USBREQ */ + volatile uint16_t USBVAL; /* USBVAL */ + volatile uint16_t USBINDX; /* USBINDX */ + volatile uint16_t USBLENG; /* USBLENG */ + volatile uint16_t DCPCFG; /* DCPCFG */ + volatile uint16_t DCPMAXP; /* DCPMAXP */ + volatile uint16_t DCPCTR; /* DCPCTR */ + volatile uint8_t dummy9[2]; /* */ + volatile uint16_t PIPESEL; /* PIPESEL */ + volatile uint8_t dummy10[2]; /* */ + volatile uint16_t PIPECFG; /* PIPECFG */ + volatile uint16_t PIPEBUF; /* PIPEBUF */ + volatile uint16_t PIPEMAXP; /* PIPEMAXP */ + volatile uint16_t PIPEPERI; /* PIPEPERI */ + +/* #define USB20_PIPE1CTR_COUNT (0xF) */ + volatile uint16_t PIPE1CTR; /* PIPE1CTR */ + volatile uint16_t PIPE2CTR; /* PIPE2CTR */ + volatile uint16_t PIPE3CTR; /* PIPE3CTR */ + volatile uint16_t PIPE4CTR; /* PIPE4CTR */ + volatile uint16_t PIPE5CTR; /* PIPE5CTR */ + volatile uint16_t PIPE6CTR; /* PIPE6CTR */ + volatile uint16_t PIPE7CTR; /* PIPE7CTR */ + volatile uint16_t PIPE8CTR; /* PIPE8CTR */ + volatile uint16_t PIPE9CTR; /* PIPE9CTR */ + volatile uint16_t PIPEACTR; /* PIPEACTR */ + volatile uint16_t PIPEBCTR; /* PIPEBCTR */ + volatile uint16_t PIPECCTR; /* PIPECCTR */ + volatile uint16_t PIPEDCTR; /* PIPEDCTR */ + volatile uint16_t PIPEECTR; /* PIPEECTR */ + volatile uint16_t PIPEFCTR; /* PIPEFCTR */ + volatile uint8_t dummy11[2]; /* */ + +/* start of struct st_usb20_from_pipe1tre */ + volatile uint16_t PIPE1TRE; /* PIPE1TRE */ + volatile uint16_t PIPE1TRN; /* PIPE1TRN */ + +/* end of struct st_usb20_from_pipe1tre */ + +/* start of struct st_usb20_from_pipe1tre */ + volatile uint16_t PIPE2TRE; /* PIPE2TRE */ + volatile uint16_t PIPE2TRN; /* PIPE2TRN */ + +/* end of struct st_usb20_from_pipe1tre */ + +/* start of struct st_usb20_from_pipe1tre */ + volatile uint16_t PIPE3TRE; /* PIPE3TRE */ + volatile uint16_t PIPE3TRN; /* PIPE3TRN */ + +/* end of struct st_usb20_from_pipe1tre */ + +/* start of struct st_usb20_from_pipe1tre */ + volatile uint16_t PIPE4TRE; /* PIPE4TRE */ + volatile uint16_t PIPE4TRN; /* PIPE4TRN */ + +/* end of struct st_usb20_from_pipe1tre */ + +/* start of struct st_usb20_from_pipe1tre */ + volatile uint16_t PIPE5TRE; /* PIPE5TRE */ + volatile uint16_t PIPE5TRN; /* PIPE5TRN */ + +/* end of struct st_usb20_from_pipe1tre */ + volatile uint16_t PIPEBTRE; /* PIPEBTRE */ + volatile uint16_t PIPEBTRN; /* PIPEBTRN */ + volatile uint16_t PIPECTRE; /* PIPECTRE */ + volatile uint16_t PIPECTRN; /* PIPECTRN */ + volatile uint16_t PIPEDTRE; /* PIPEDTRE */ + volatile uint16_t PIPEDTRN; /* PIPEDTRN */ + volatile uint16_t PIPEETRE; /* PIPEETRE */ + volatile uint16_t PIPEETRN; /* PIPEETRN */ + volatile uint16_t PIPEFTRE; /* PIPEFTRE */ + volatile uint16_t PIPEFTRN; /* PIPEFTRN */ + volatile uint16_t PIPE9TRE; /* PIPE9TRE */ + volatile uint16_t PIPE9TRN; /* PIPE9TRN */ + volatile uint16_t PIPEATRE; /* PIPEATRE */ + volatile uint16_t PIPEATRN; /* PIPEATRN */ + volatile uint8_t dummy12[16]; /* */ + +/* #define USB20_DEVADD0_COUNT (0xB) */ + volatile uint16_t DEVADD0; /* DEVADD0 */ + volatile uint16_t DEVADD1; /* DEVADD1 */ + volatile uint16_t DEVADD2; /* DEVADD2 */ + volatile uint16_t DEVADD3; /* DEVADD3 */ + volatile uint16_t DEVADD4; /* DEVADD4 */ + volatile uint16_t DEVADD5; /* DEVADD5 */ + volatile uint16_t DEVADD6; /* DEVADD6 */ + volatile uint16_t DEVADD7; /* DEVADD7 */ + volatile uint16_t DEVADD8; /* DEVADD8 */ + volatile uint16_t DEVADD9; /* DEVADD9 */ + volatile uint16_t DEVADDA; /* DEVADDA */ + volatile uint8_t dummy13[28]; /* */ + volatile uint16_t SUSPMODE; /* SUSPMODE */ + volatile uint8_t dummy14[92]; /* */ + +/* start of struct st_usb20_from_dmfifob0 */ + volatile uint32_t D0FIFOB0; /* D0FIFOB0 */ + volatile uint32_t D0FIFOB1; /* D0FIFOB1 */ + volatile uint32_t D0FIFOB2; /* D0FIFOB2 */ + volatile uint32_t D0FIFOB3; /* D0FIFOB3 */ + volatile uint32_t D0FIFOB4; /* D0FIFOB4 */ + volatile uint32_t D0FIFOB5; /* D0FIFOB5 */ + volatile uint32_t D0FIFOB6; /* D0FIFOB6 */ + volatile uint32_t D0FIFOB7; /* D0FIFOB7 */ + +/* end of struct st_usb20_from_dmfifob0 */ + +/* start of struct st_usb20_from_dmfifob0 */ + volatile uint32_t D1FIFOB0; /* D1FIFOB0 */ + volatile uint32_t D1FIFOB1; /* D1FIFOB1 */ + volatile uint32_t D1FIFOB2; /* D1FIFOB2 */ + volatile uint32_t D1FIFOB3; /* D1FIFOB3 */ + volatile uint32_t D1FIFOB4; /* D1FIFOB4 */ + volatile uint32_t D1FIFOB5; /* D1FIFOB5 */ + volatile uint32_t D1FIFOB6; /* D1FIFOB6 */ + volatile uint32_t D1FIFOB7; /* D1FIFOB7 */ + +/* end of struct st_usb20_from_dmfifob0 */ +} r_io_usb20_t; + + +typedef struct st_usb20_from_d0fifosel +{ + + volatile uint16_t D0FIFOSEL; /* D0FIFOSEL */ + volatile uint16_t D0FIFOCTR; /* D0FIFOCTR */ +} r_io_usb20_from_d0fifosel_t; + + +typedef struct st_usb20_from_pipe1tre +{ + + volatile uint16_t PIPE1TRE; /* PIPE1TRE */ + volatile uint16_t PIPE1TRN; /* PIPE1TRN */ +} r_io_usb20_from_pipe1tre_t; + + +typedef struct st_usb20_from_dmfifob0 +{ + + +/* #define USB20_D0FIFOB0_COUNT (0x8) */ + volatile uint32_t D0FIFOB0; /* D0FIFOB0 */ + volatile uint32_t D0FIFOB1; /* D0FIFOB1 */ + volatile uint32_t D0FIFOB2; /* D0FIFOB2 */ + volatile uint32_t D0FIFOB3; /* D0FIFOB3 */ + volatile uint32_t D0FIFOB4; /* D0FIFOB4 */ + volatile uint32_t D0FIFOB5; /* D0FIFOB5 */ + volatile uint32_t D0FIFOB6; /* D0FIFOB6 */ + volatile uint32_t D0FIFOB7; /* D0FIFOB7 */ +} r_io_usb20_from_dmfifob0_t; + + +/* Channel array defines of USB20 (2)*/ +#ifdef DECLARE_USB20_CHANNELS +volatile struct st_usb20* USB20[ USB20_COUNT ] = + /* ->MISRA 11.3 */ /* ->SEC R2.7.1 */ + USB20_ADDRESS_LIST; + /* <-MISRA 11.3 */ /* <-SEC R2.7.1 */ +#endif /* DECLARE_USB20_CHANNELS */ + +#ifdef DECLARE_USB20_FROM_D0FIFOB0_CHANNELS +volatile struct st_usb20_from_dmfifob0* USB20_FROM_D0FIFOB0[ USB20_COUNT ][ USB20_FROM_D0FIFOB0_COUNT ] = + /* ->MISRA 11.3 */ /* ->SEC R2.7.1 */ + USB20_FROM_D0FIFOB0_ADDRESS_LIST; + /* <-MISRA 11.3 */ /* <-SEC R2.7.1 */ +#endif /* DECLARE_USB20_FROM_D0FIFOB0_CHANNELS */ + +#ifdef DECLARE_USB20_FROM_PIPE1ATRE_CHANNELS +volatile struct st_usb20_from_pipe1tre* USB20_FROM_PIPE1ATRE[ USB20_COUNT ][ USB20_FROM_PIPE1ATRE_COUNT ] = + /* ->MISRA 11.3 */ /* ->SEC R2.7.1 */ + USB20_FROM_PIPE1ATRE_ADDRESS_LIST; + /* <-MISRA 11.3 */ /* <-SEC R2.7.1 */ +#endif /* DECLARE_USB20_FROM_PIPE1ATRE_CHANNELS */ + +#ifdef DECLARE_USB20_FROM_D0FIFOSEL_CHANNELS +volatile struct st_usb20_from_d0fifosel* USB20_FROM_D0FIFOSEL[ USB20_COUNT ][ USB20_FROM_D0FIFOSEL_COUNT ] = + /* ->MISRA 11.3 */ /* ->SEC R2.7.1 */ + USB20_FROM_D0FIFOSEL_ADDRESS_LIST; + /* <-MISRA 11.3 */ /* <-SEC R2.7.1 */ +#endif /* DECLARE_USB20_FROM_D0FIFOSEL_CHANNELS */ +/* End of channel array defines of USB20 (2)*/ + + +/* <-SEC M1.10.1 */ +/* <-MISRA 18.4 */ /* <-SEC M1.6.2 */ +/* <-QAC 0857 */ +/* <-QAC 0639 */ +#endif diff --git a/targets/TARGET_RENESAS/TARGET_RZ_A1XX/TARGET_GR_LYCHEE/device/inc/iodefines/vdc5_iodefine.h b/targets/TARGET_RENESAS/TARGET_RZ_A1XX/TARGET_GR_LYCHEE/device/inc/iodefines/vdc5_iodefine.h new file mode 100644 index 0000000..300c4ac --- /dev/null +++ b/targets/TARGET_RENESAS/TARGET_RZ_A1XX/TARGET_GR_LYCHEE/device/inc/iodefines/vdc5_iodefine.h @@ -0,0 +1,855 @@ +/******************************************************************************* +* DISCLAIMER +* This software is supplied by Renesas Electronics Corporation and is only +* intended for use with Renesas products. No other uses are authorized. This +* software is owned by Renesas Electronics Corporation and is protected under +* all applicable laws, including copyright laws. +* THIS SOFTWARE IS PROVIDED "AS IS" AND RENESAS MAKES NO WARRANTIES REGARDING +* THIS SOFTWARE, WHETHER EXPRESS, IMPLIED OR STATUTORY, INCLUDING BUT NOT +* LIMITED TO WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE +* AND NON-INFRINGEMENT. ALL SUCH WARRANTIES ARE EXPRESSLY DISCLAIMED. +* TO THE MAXIMUM EXTENT PERMITTED NOT PROHIBITED BY LAW, NEITHER RENESAS +* ELECTRONICS CORPORATION NOR ANY OF ITS AFFILIATED COMPANIES SHALL BE LIABLE +* FOR ANY DIRECT, INDIRECT, SPECIAL, INCIDENTAL OR CONSEQUENTIAL DAMAGES FOR +* ANY REASON RELATED TO THIS SOFTWARE, EVEN IF RENESAS OR ITS AFFILIATES HAVE +* BEEN ADVISED OF THE POSSIBILITY OF SUCH DAMAGES. +* Renesas reserves the right, without notice, to make changes to this software +* and to discontinue the availability of this software. By using this software, +* you agree to the additional terms and conditions found by accessing the +* following link: +* http://www.renesas.com/disclaimer* +* Copyright (C) 2013-2016 Renesas Electronics Corporation. All rights reserved. +*******************************************************************************/ +/******************************************************************************* +* File Name : vdc5_iodefine.h +* $Rev: $ +* $Date:: $ +* Description : Definition of I/O Register for RZ/A1LU (V3.00l) +******************************************************************************/ +#ifndef VDC5_IODEFINE_H +#define VDC5_IODEFINE_H +/* ->QAC 0639 : Over 127 members (C90) */ +/* ->QAC 0857 : Over 1024 #define (C90) */ +/* ->MISRA 18.4 : Pack unpack union */ /* ->SEC M1.6.2 */ +/* ->SEC M1.10.1 : Not magic number */ + +#define VDC50 (*(struct st_vdc5 *)0xFCFF7400uL) /* VDC50 */ + + +/* Start of channel array defines of VDC5 */ + +/* Channel array defines of VDC5 */ +/*(Sample) value = VDC5[ channel ]->INP_UPDATE; */ +#define VDC5_COUNT (1) +#define VDC5_ADDRESS_LIST \ +{ /* ->MISRA 11.3 */ /* ->SEC R2.7.1 */ \ + &VDC50 \ +} /* <-MISRA 11.3 */ /* <-SEC R2.7.1 */ /* { } is for MISRA 19.4 */ + + + +/* Channel array defines of VDC50_FROM_GR2_AB7_ARRAY */ +/*(Sample) value = VDC50_FROM_GR2_AB7_ARRAY[ channel ][ index ]->GR0_AB7; */ +#define VDC50_FROM_GR2_AB7_ARRAY_COUNT (2) +#define VDC50_FROM_GR2_AB7_ARRAY_ADDRESS_LIST \ +{ /* ->MISRA 11.3 */ /* ->SEC R2.7.1 */ \ +{ \ + &VDC50_FROM_GR2_AB7, &VDC50_FROM_GR3_AB7 \ +} \ +} /* <-MISRA 11.3 */ /* <-SEC R2.7.1 */ /* { } is for MISRA 19.4 */ +#define VDC50_FROM_GR2_AB7 (*(struct st_vdc5_from_gr0_ab7 *)&VDC50.GR2_AB7) /* VDC50_FROM_GR2_AB7 */ +#define VDC50_FROM_GR3_AB7 (*(struct st_vdc5_from_gr0_ab7 *)&VDC50.GR3_AB7) /* VDC50_FROM_GR3_AB7 */ + + + + +/* Channel array defines of VDC50_FROM_GR2_UPDATE_ARRAY */ +/*(Sample) value = VDC50_FROM_GR2_UPDATE_ARRAY[ channel ][ index ]->GR0_UPDATE; */ +#define VDC50_FROM_GR2_UPDATE_ARRAY_COUNT (2) +#define VDC50_FROM_GR2_UPDATE_ARRAY_ADDRESS_LIST \ +{ /* ->MISRA 11.3 */ /* ->SEC R2.7.1 */ \ +{ \ + &VDC50_FROM_GR2_UPDATE, &VDC50_FROM_GR3_UPDATE \ +} \ +} /* <-MISRA 11.3 */ /* <-SEC R2.7.1 */ /* { } is for MISRA 19.4 */ +#define VDC50_FROM_GR2_UPDATE (*(struct st_vdc5_from_gr0_update *)&VDC50.GR2_UPDATE) /* VDC50_FROM_GR2_UPDATE */ +#define VDC50_FROM_GR3_UPDATE (*(struct st_vdc5_from_gr0_update *)&VDC50.GR3_UPDATE) /* VDC50_FROM_GR3_UPDATE */ + + + + +/* Channel array defines of VDC50_FROM_GR0_AB7_ARRAY */ +/*(Sample) value = VDC50_FROM_GR0_AB7_ARRAY[ channel ][ index ]->GR0_AB7; */ +#define VDC50_FROM_GR0_AB7_ARRAY_COUNT (3) +#define VDC50_FROM_GR0_AB7_ARRAY_ADDRESS_LIST \ +{ /* ->MISRA 11.3 */ /* ->SEC R2.7.1 */ \ +{ \ + &VDC50_FROM_GR0_AB7, &VDC50_FROM_GR2_AB7, &VDC50_FROM_GR3_AB7 \ +} \ +} /* <-MISRA 11.3 */ /* <-SEC R2.7.1 */ /* { } is for MISRA 19.4 */ +#define VDC50_FROM_GR0_AB7 (*(struct st_vdc5_from_gr0_ab7 *)&VDC50.GR0_AB7) /* VDC50_FROM_GR0_AB7 */ +#define VDC50_FROM_GR2_AB7 (*(struct st_vdc5_from_gr0_ab7 *)&VDC50.GR2_AB7) /* VDC50_FROM_GR2_AB7 */ +#define VDC50_FROM_GR3_AB7 (*(struct st_vdc5_from_gr0_ab7 *)&VDC50.GR3_AB7) /* VDC50_FROM_GR3_AB7 */ + + + + +/* Channel array defines of VDC50_FROM_GR0_UPDATE_ARRAY */ +/*(Sample) value = VDC50_FROM_GR0_UPDATE_ARRAY[ channel ][ index ]->GR0_UPDATE; */ +#define VDC50_FROM_GR0_UPDATE_ARRAY_COUNT (3) +#define VDC50_FROM_GR0_UPDATE_ARRAY_ADDRESS_LIST \ +{ /* ->MISRA 11.3 */ /* ->SEC R2.7.1 */ \ +{ \ + &VDC50_FROM_GR0_UPDATE, &VDC50_FROM_GR2_UPDATE, &VDC50_FROM_GR3_UPDATE \ +} \ +} /* <-MISRA 11.3 */ /* <-SEC R2.7.1 */ /* { } is for MISRA 19.4 */ +#define VDC50_FROM_GR0_UPDATE (*(struct st_vdc5_from_gr0_update *)&VDC50.GR0_UPDATE) /* VDC50_FROM_GR0_UPDATE */ +#define VDC50_FROM_GR2_UPDATE (*(struct st_vdc5_from_gr0_update *)&VDC50.GR2_UPDATE) /* VDC50_FROM_GR2_UPDATE */ +#define VDC50_FROM_GR3_UPDATE (*(struct st_vdc5_from_gr0_update *)&VDC50.GR3_UPDATE) /* VDC50_FROM_GR3_UPDATE */ + + +/* End of channel array defines of VDC5 */ + + +#define VDC50INP_UPDATE (VDC50.INP_UPDATE) +#define VDC50INP_SEL_CNT (VDC50.INP_SEL_CNT) +#define VDC50INP_EXT_SYNC_CNT (VDC50.INP_EXT_SYNC_CNT) +#define VDC50INP_VSYNC_PH_ADJ (VDC50.INP_VSYNC_PH_ADJ) +#define VDC50INP_DLY_ADJ (VDC50.INP_DLY_ADJ) +#define VDC50IMGCNT_UPDATE (VDC50.IMGCNT_UPDATE) +#define VDC50IMGCNT_NR_CNT0 (VDC50.IMGCNT_NR_CNT0) +#define VDC50IMGCNT_NR_CNT1 (VDC50.IMGCNT_NR_CNT1) +#define VDC50IMGCNT_MTX_MODE (VDC50.IMGCNT_MTX_MODE) +#define VDC50IMGCNT_MTX_YG_ADJ0 (VDC50.IMGCNT_MTX_YG_ADJ0) +#define VDC50IMGCNT_MTX_YG_ADJ1 (VDC50.IMGCNT_MTX_YG_ADJ1) +#define VDC50IMGCNT_MTX_CBB_ADJ0 (VDC50.IMGCNT_MTX_CBB_ADJ0) +#define VDC50IMGCNT_MTX_CBB_ADJ1 (VDC50.IMGCNT_MTX_CBB_ADJ1) +#define VDC50IMGCNT_MTX_CRR_ADJ0 (VDC50.IMGCNT_MTX_CRR_ADJ0) +#define VDC50IMGCNT_MTX_CRR_ADJ1 (VDC50.IMGCNT_MTX_CRR_ADJ1) +#define VDC50SC0_SCL0_UPDATE (VDC50.SC0_SCL0_UPDATE) +#define VDC50SC0_SCL0_FRC1 (VDC50.SC0_SCL0_FRC1) +#define VDC50SC0_SCL0_FRC2 (VDC50.SC0_SCL0_FRC2) +#define VDC50SC0_SCL0_FRC3 (VDC50.SC0_SCL0_FRC3) +#define VDC50SC0_SCL0_FRC4 (VDC50.SC0_SCL0_FRC4) +#define VDC50SC0_SCL0_FRC5 (VDC50.SC0_SCL0_FRC5) +#define VDC50SC0_SCL0_FRC6 (VDC50.SC0_SCL0_FRC6) +#define VDC50SC0_SCL0_FRC7 (VDC50.SC0_SCL0_FRC7) +#define VDC50SC0_SCL0_FRC9 (VDC50.SC0_SCL0_FRC9) +#define VDC50SC0_SCL0_MON0 (VDC50.SC0_SCL0_MON0) +#define VDC50SC0_SCL0_INT (VDC50.SC0_SCL0_INT) +#define VDC50SC0_SCL0_DS1 (VDC50.SC0_SCL0_DS1) +#define VDC50SC0_SCL0_DS2 (VDC50.SC0_SCL0_DS2) +#define VDC50SC0_SCL0_DS3 (VDC50.SC0_SCL0_DS3) +#define VDC50SC0_SCL0_DS4 (VDC50.SC0_SCL0_DS4) +#define VDC50SC0_SCL0_DS5 (VDC50.SC0_SCL0_DS5) +#define VDC50SC0_SCL0_DS6 (VDC50.SC0_SCL0_DS6) +#define VDC50SC0_SCL0_DS7 (VDC50.SC0_SCL0_DS7) +#define VDC50SC0_SCL0_US1 (VDC50.SC0_SCL0_US1) +#define VDC50SC0_SCL0_US2 (VDC50.SC0_SCL0_US2) +#define VDC50SC0_SCL0_US3 (VDC50.SC0_SCL0_US3) +#define VDC50SC0_SCL0_US4 (VDC50.SC0_SCL0_US4) +#define VDC50SC0_SCL0_US5 (VDC50.SC0_SCL0_US5) +#define VDC50SC0_SCL0_US6 (VDC50.SC0_SCL0_US6) +#define VDC50SC0_SCL0_US7 (VDC50.SC0_SCL0_US7) +#define VDC50SC0_SCL0_US8 (VDC50.SC0_SCL0_US8) +#define VDC50SC0_SCL0_OVR1 (VDC50.SC0_SCL0_OVR1) +#define VDC50SC0_SCL1_UPDATE (VDC50.SC0_SCL1_UPDATE) +#define VDC50SC0_SCL1_WR1 (VDC50.SC0_SCL1_WR1) +#define VDC50SC0_SCL1_WR2 (VDC50.SC0_SCL1_WR2) +#define VDC50SC0_SCL1_WR3 (VDC50.SC0_SCL1_WR3) +#define VDC50SC0_SCL1_WR4 (VDC50.SC0_SCL1_WR4) +#define VDC50SC0_SCL1_WR5 (VDC50.SC0_SCL1_WR5) +#define VDC50SC0_SCL1_WR6 (VDC50.SC0_SCL1_WR6) +#define VDC50SC0_SCL1_WR7 (VDC50.SC0_SCL1_WR7) +#define VDC50SC0_SCL1_WR8 (VDC50.SC0_SCL1_WR8) +#define VDC50SC0_SCL1_WR9 (VDC50.SC0_SCL1_WR9) +#define VDC50SC0_SCL1_WR10 (VDC50.SC0_SCL1_WR10) +#define VDC50SC0_SCL1_WR11 (VDC50.SC0_SCL1_WR11) +#define VDC50SC0_SCL1_MON1 (VDC50.SC0_SCL1_MON1) +#define VDC50SC0_SCL1_PBUF0 (VDC50.SC0_SCL1_PBUF0) +#define VDC50SC0_SCL1_PBUF1 (VDC50.SC0_SCL1_PBUF1) +#define VDC50SC0_SCL1_PBUF2 (VDC50.SC0_SCL1_PBUF2) +#define VDC50SC0_SCL1_PBUF3 (VDC50.SC0_SCL1_PBUF3) +#define VDC50SC0_SCL1_PBUF_FLD (VDC50.SC0_SCL1_PBUF_FLD) +#define VDC50SC0_SCL1_PBUF_CNT (VDC50.SC0_SCL1_PBUF_CNT) +#define VDC50GR0_UPDATE (VDC50.GR0_UPDATE) +#define VDC50GR0_FLM_RD (VDC50.GR0_FLM_RD) +#define VDC50GR0_FLM1 (VDC50.GR0_FLM1) +#define VDC50GR0_FLM2 (VDC50.GR0_FLM2) +#define VDC50GR0_FLM3 (VDC50.GR0_FLM3) +#define VDC50GR0_FLM4 (VDC50.GR0_FLM4) +#define VDC50GR0_FLM5 (VDC50.GR0_FLM5) +#define VDC50GR0_FLM6 (VDC50.GR0_FLM6) +#define VDC50GR0_AB1 (VDC50.GR0_AB1) +#define VDC50GR0_AB2 (VDC50.GR0_AB2) +#define VDC50GR0_AB3 (VDC50.GR0_AB3) +#define VDC50GR0_AB7 (VDC50.GR0_AB7) +#define VDC50GR0_AB8 (VDC50.GR0_AB8) +#define VDC50GR0_AB9 (VDC50.GR0_AB9) +#define VDC50GR0_AB10 (VDC50.GR0_AB10) +#define VDC50GR0_AB11 (VDC50.GR0_AB11) +#define VDC50GR0_BASE (VDC50.GR0_BASE) +#define VDC50GR0_CLUT (VDC50.GR0_CLUT) +#define VDC50ADJ0_UPDATE (VDC50.ADJ0_UPDATE) +#define VDC50ADJ0_BKSTR_SET (VDC50.ADJ0_BKSTR_SET) +#define VDC50ADJ0_ENH_TIM1 (VDC50.ADJ0_ENH_TIM1) +#define VDC50ADJ0_ENH_TIM2 (VDC50.ADJ0_ENH_TIM2) +#define VDC50ADJ0_ENH_TIM3 (VDC50.ADJ0_ENH_TIM3) +#define VDC50ADJ0_ENH_SHP1 (VDC50.ADJ0_ENH_SHP1) +#define VDC50ADJ0_ENH_SHP2 (VDC50.ADJ0_ENH_SHP2) +#define VDC50ADJ0_ENH_SHP3 (VDC50.ADJ0_ENH_SHP3) +#define VDC50ADJ0_ENH_SHP4 (VDC50.ADJ0_ENH_SHP4) +#define VDC50ADJ0_ENH_SHP5 (VDC50.ADJ0_ENH_SHP5) +#define VDC50ADJ0_ENH_SHP6 (VDC50.ADJ0_ENH_SHP6) +#define VDC50ADJ0_ENH_LTI1 (VDC50.ADJ0_ENH_LTI1) +#define VDC50ADJ0_ENH_LTI2 (VDC50.ADJ0_ENH_LTI2) +#define VDC50ADJ0_MTX_MODE (VDC50.ADJ0_MTX_MODE) +#define VDC50ADJ0_MTX_YG_ADJ0 (VDC50.ADJ0_MTX_YG_ADJ0) +#define VDC50ADJ0_MTX_YG_ADJ1 (VDC50.ADJ0_MTX_YG_ADJ1) +#define VDC50ADJ0_MTX_CBB_ADJ0 (VDC50.ADJ0_MTX_CBB_ADJ0) +#define VDC50ADJ0_MTX_CBB_ADJ1 (VDC50.ADJ0_MTX_CBB_ADJ1) +#define VDC50ADJ0_MTX_CRR_ADJ0 (VDC50.ADJ0_MTX_CRR_ADJ0) +#define VDC50ADJ0_MTX_CRR_ADJ1 (VDC50.ADJ0_MTX_CRR_ADJ1) +#define VDC50GR2_UPDATE (VDC50.GR2_UPDATE) +#define VDC50GR2_FLM_RD (VDC50.GR2_FLM_RD) +#define VDC50GR2_FLM1 (VDC50.GR2_FLM1) +#define VDC50GR2_FLM2 (VDC50.GR2_FLM2) +#define VDC50GR2_FLM3 (VDC50.GR2_FLM3) +#define VDC50GR2_FLM4 (VDC50.GR2_FLM4) +#define VDC50GR2_FLM5 (VDC50.GR2_FLM5) +#define VDC50GR2_FLM6 (VDC50.GR2_FLM6) +#define VDC50GR2_AB1 (VDC50.GR2_AB1) +#define VDC50GR2_AB2 (VDC50.GR2_AB2) +#define VDC50GR2_AB3 (VDC50.GR2_AB3) +#define VDC50GR2_AB4 (VDC50.GR2_AB4) +#define VDC50GR2_AB5 (VDC50.GR2_AB5) +#define VDC50GR2_AB6 (VDC50.GR2_AB6) +#define VDC50GR2_AB7 (VDC50.GR2_AB7) +#define VDC50GR2_AB8 (VDC50.GR2_AB8) +#define VDC50GR2_AB9 (VDC50.GR2_AB9) +#define VDC50GR2_AB10 (VDC50.GR2_AB10) +#define VDC50GR2_AB11 (VDC50.GR2_AB11) +#define VDC50GR2_BASE (VDC50.GR2_BASE) +#define VDC50GR2_CLUT (VDC50.GR2_CLUT) +#define VDC50GR2_MON (VDC50.GR2_MON) +#define VDC50GR3_UPDATE (VDC50.GR3_UPDATE) +#define VDC50GR3_FLM_RD (VDC50.GR3_FLM_RD) +#define VDC50GR3_FLM1 (VDC50.GR3_FLM1) +#define VDC50GR3_FLM2 (VDC50.GR3_FLM2) +#define VDC50GR3_FLM3 (VDC50.GR3_FLM3) +#define VDC50GR3_FLM4 (VDC50.GR3_FLM4) +#define VDC50GR3_FLM5 (VDC50.GR3_FLM5) +#define VDC50GR3_FLM6 (VDC50.GR3_FLM6) +#define VDC50GR3_AB1 (VDC50.GR3_AB1) +#define VDC50GR3_AB2 (VDC50.GR3_AB2) +#define VDC50GR3_AB3 (VDC50.GR3_AB3) +#define VDC50GR3_AB4 (VDC50.GR3_AB4) +#define VDC50GR3_AB5 (VDC50.GR3_AB5) +#define VDC50GR3_AB6 (VDC50.GR3_AB6) +#define VDC50GR3_AB7 (VDC50.GR3_AB7) +#define VDC50GR3_AB8 (VDC50.GR3_AB8) +#define VDC50GR3_AB9 (VDC50.GR3_AB9) +#define VDC50GR3_AB10 (VDC50.GR3_AB10) +#define VDC50GR3_AB11 (VDC50.GR3_AB11) +#define VDC50GR3_BASE (VDC50.GR3_BASE) +#define VDC50GR3_CLUT_INT (VDC50.GR3_CLUT_INT) +#define VDC50GR3_MON (VDC50.GR3_MON) +#define VDC50GAM_G_UPDATE (VDC50.GAM_G_UPDATE) +#define VDC50GAM_SW (VDC50.GAM_SW) +#define VDC50GAM_G_LUT1 (VDC50.GAM_G_LUT1) +#define VDC50GAM_G_LUT2 (VDC50.GAM_G_LUT2) +#define VDC50GAM_G_LUT3 (VDC50.GAM_G_LUT3) +#define VDC50GAM_G_LUT4 (VDC50.GAM_G_LUT4) +#define VDC50GAM_G_LUT5 (VDC50.GAM_G_LUT5) +#define VDC50GAM_G_LUT6 (VDC50.GAM_G_LUT6) +#define VDC50GAM_G_LUT7 (VDC50.GAM_G_LUT7) +#define VDC50GAM_G_LUT8 (VDC50.GAM_G_LUT8) +#define VDC50GAM_G_LUT9 (VDC50.GAM_G_LUT9) +#define VDC50GAM_G_LUT10 (VDC50.GAM_G_LUT10) +#define VDC50GAM_G_LUT11 (VDC50.GAM_G_LUT11) +#define VDC50GAM_G_LUT12 (VDC50.GAM_G_LUT12) +#define VDC50GAM_G_LUT13 (VDC50.GAM_G_LUT13) +#define VDC50GAM_G_LUT14 (VDC50.GAM_G_LUT14) +#define VDC50GAM_G_LUT15 (VDC50.GAM_G_LUT15) +#define VDC50GAM_G_LUT16 (VDC50.GAM_G_LUT16) +#define VDC50GAM_G_AREA1 (VDC50.GAM_G_AREA1) +#define VDC50GAM_G_AREA2 (VDC50.GAM_G_AREA2) +#define VDC50GAM_G_AREA3 (VDC50.GAM_G_AREA3) +#define VDC50GAM_G_AREA4 (VDC50.GAM_G_AREA4) +#define VDC50GAM_G_AREA5 (VDC50.GAM_G_AREA5) +#define VDC50GAM_G_AREA6 (VDC50.GAM_G_AREA6) +#define VDC50GAM_G_AREA7 (VDC50.GAM_G_AREA7) +#define VDC50GAM_G_AREA8 (VDC50.GAM_G_AREA8) +#define VDC50GAM_B_UPDATE (VDC50.GAM_B_UPDATE) +#define VDC50GAM_B_LUT1 (VDC50.GAM_B_LUT1) +#define VDC50GAM_B_LUT2 (VDC50.GAM_B_LUT2) +#define VDC50GAM_B_LUT3 (VDC50.GAM_B_LUT3) +#define VDC50GAM_B_LUT4 (VDC50.GAM_B_LUT4) +#define VDC50GAM_B_LUT5 (VDC50.GAM_B_LUT5) +#define VDC50GAM_B_LUT6 (VDC50.GAM_B_LUT6) +#define VDC50GAM_B_LUT7 (VDC50.GAM_B_LUT7) +#define VDC50GAM_B_LUT8 (VDC50.GAM_B_LUT8) +#define VDC50GAM_B_LUT9 (VDC50.GAM_B_LUT9) +#define VDC50GAM_B_LUT10 (VDC50.GAM_B_LUT10) +#define VDC50GAM_B_LUT11 (VDC50.GAM_B_LUT11) +#define VDC50GAM_B_LUT12 (VDC50.GAM_B_LUT12) +#define VDC50GAM_B_LUT13 (VDC50.GAM_B_LUT13) +#define VDC50GAM_B_LUT14 (VDC50.GAM_B_LUT14) +#define VDC50GAM_B_LUT15 (VDC50.GAM_B_LUT15) +#define VDC50GAM_B_LUT16 (VDC50.GAM_B_LUT16) +#define VDC50GAM_B_AREA1 (VDC50.GAM_B_AREA1) +#define VDC50GAM_B_AREA2 (VDC50.GAM_B_AREA2) +#define VDC50GAM_B_AREA3 (VDC50.GAM_B_AREA3) +#define VDC50GAM_B_AREA4 (VDC50.GAM_B_AREA4) +#define VDC50GAM_B_AREA5 (VDC50.GAM_B_AREA5) +#define VDC50GAM_B_AREA6 (VDC50.GAM_B_AREA6) +#define VDC50GAM_B_AREA7 (VDC50.GAM_B_AREA7) +#define VDC50GAM_B_AREA8 (VDC50.GAM_B_AREA8) +#define VDC50GAM_R_UPDATE (VDC50.GAM_R_UPDATE) +#define VDC50GAM_R_LUT1 (VDC50.GAM_R_LUT1) +#define VDC50GAM_R_LUT2 (VDC50.GAM_R_LUT2) +#define VDC50GAM_R_LUT3 (VDC50.GAM_R_LUT3) +#define VDC50GAM_R_LUT4 (VDC50.GAM_R_LUT4) +#define VDC50GAM_R_LUT5 (VDC50.GAM_R_LUT5) +#define VDC50GAM_R_LUT6 (VDC50.GAM_R_LUT6) +#define VDC50GAM_R_LUT7 (VDC50.GAM_R_LUT7) +#define VDC50GAM_R_LUT8 (VDC50.GAM_R_LUT8) +#define VDC50GAM_R_LUT9 (VDC50.GAM_R_LUT9) +#define VDC50GAM_R_LUT10 (VDC50.GAM_R_LUT10) +#define VDC50GAM_R_LUT11 (VDC50.GAM_R_LUT11) +#define VDC50GAM_R_LUT12 (VDC50.GAM_R_LUT12) +#define VDC50GAM_R_LUT13 (VDC50.GAM_R_LUT13) +#define VDC50GAM_R_LUT14 (VDC50.GAM_R_LUT14) +#define VDC50GAM_R_LUT15 (VDC50.GAM_R_LUT15) +#define VDC50GAM_R_LUT16 (VDC50.GAM_R_LUT16) +#define VDC50GAM_R_AREA1 (VDC50.GAM_R_AREA1) +#define VDC50GAM_R_AREA2 (VDC50.GAM_R_AREA2) +#define VDC50GAM_R_AREA3 (VDC50.GAM_R_AREA3) +#define VDC50GAM_R_AREA4 (VDC50.GAM_R_AREA4) +#define VDC50GAM_R_AREA5 (VDC50.GAM_R_AREA5) +#define VDC50GAM_R_AREA6 (VDC50.GAM_R_AREA6) +#define VDC50GAM_R_AREA7 (VDC50.GAM_R_AREA7) +#define VDC50GAM_R_AREA8 (VDC50.GAM_R_AREA8) +#define VDC50TCON_UPDATE (VDC50.TCON_UPDATE) +#define VDC50TCON_TIM (VDC50.TCON_TIM) +#define VDC50TCON_TIM_STVA1 (VDC50.TCON_TIM_STVA1) +#define VDC50TCON_TIM_STVA2 (VDC50.TCON_TIM_STVA2) +#define VDC50TCON_TIM_STVB1 (VDC50.TCON_TIM_STVB1) +#define VDC50TCON_TIM_STVB2 (VDC50.TCON_TIM_STVB2) +#define VDC50TCON_TIM_STH1 (VDC50.TCON_TIM_STH1) +#define VDC50TCON_TIM_STH2 (VDC50.TCON_TIM_STH2) +#define VDC50TCON_TIM_STB1 (VDC50.TCON_TIM_STB1) +#define VDC50TCON_TIM_STB2 (VDC50.TCON_TIM_STB2) +#define VDC50TCON_TIM_CPV1 (VDC50.TCON_TIM_CPV1) +#define VDC50TCON_TIM_CPV2 (VDC50.TCON_TIM_CPV2) +#define VDC50TCON_TIM_POLA1 (VDC50.TCON_TIM_POLA1) +#define VDC50TCON_TIM_POLA2 (VDC50.TCON_TIM_POLA2) +#define VDC50TCON_TIM_POLB1 (VDC50.TCON_TIM_POLB1) +#define VDC50TCON_TIM_POLB2 (VDC50.TCON_TIM_POLB2) +#define VDC50TCON_TIM_DE (VDC50.TCON_TIM_DE) +#define VDC50OUT_UPDATE (VDC50.OUT_UPDATE) +#define VDC50OUT_SET (VDC50.OUT_SET) +#define VDC50OUT_BRIGHT1 (VDC50.OUT_BRIGHT1) +#define VDC50OUT_BRIGHT2 (VDC50.OUT_BRIGHT2) +#define VDC50OUT_CONTRAST (VDC50.OUT_CONTRAST) +#define VDC50OUT_PDTHA (VDC50.OUT_PDTHA) +#define VDC50OUT_CLK_PHASE (VDC50.OUT_CLK_PHASE) +#define VDC50SYSCNT_INT1 (VDC50.SYSCNT_INT1) +#define VDC50SYSCNT_INT2 (VDC50.SYSCNT_INT2) +#define VDC50SYSCNT_INT4 (VDC50.SYSCNT_INT4) +#define VDC50SYSCNT_INT5 (VDC50.SYSCNT_INT5) +#define VDC50SYSCNT_PANEL_CLK (VDC50.SYSCNT_PANEL_CLK) +#define VDC50SYSCNT_CLUT (VDC50.SYSCNT_CLUT) +#define VDC50GR_VIN_UPDATE (VDC50.GR_VIN_UPDATE) +#define VDC50GR_VIN_AB1 (VDC50.GR_VIN_AB1) + +#define VDC5_IMGCNT_NR_CNT0_COUNT (2) +#define VDC5_SC0_SCL0_FRC1_COUNT (7) +#define VDC5_SC0_SCL0_DS1_COUNT (7) +#define VDC5_SC0_SCL0_US1_COUNT (8) +#define VDC5_SC0_SCL1_WR1_COUNT (4) +#define VDC5_SC0_SCL1_PBUF0_COUNT (4) +#define VDC5_GR0_FLM1_COUNT (6) +#define VDC5_GR0_AB1_COUNT (3) +#define VDC5_ADJ0_ENH_TIM1_COUNT (3) +#define VDC5_ADJ0_ENH_SHP1_COUNT (6) +#define VDC5_ADJ0_ENH_LTI1_COUNT (2) +#define VDC5_GR2_FLM1_COUNT (6) +#define VDC5_GR2_AB1_COUNT (3) +#define VDC5_GR3_FLM1_COUNT (6) +#define VDC5_GR3_AB1_COUNT (3) +#define VDC5_GAM_G_LUT1_COUNT (16) +#define VDC5_GAM_G_AREA1_COUNT (8) +#define VDC5_GAM_B_LUT1_COUNT (16) +#define VDC5_GAM_B_AREA1_COUNT (8) +#define VDC5_GAM_R_LUT1_COUNT (16) +#define VDC5_GAM_R_AREA1_COUNT (8) +#define VDC5_TCON_TIM_STVA1_COUNT (2) +#define VDC5_TCON_TIM_STVB1_COUNT (2) +#define VDC5_TCON_TIM_STH1_COUNT (2) +#define VDC5_TCON_TIM_STB1_COUNT (2) +#define VDC5_TCON_TIM_CPV1_COUNT (2) +#define VDC5_TCON_TIM_POLA1_COUNT (2) +#define VDC5_TCON_TIM_POLB1_COUNT (2) +#define VDC5_OUT_BRIGHT1_COUNT (2) +#define VDC5_SYSCNT_INT1_COUNT (2) +#define VDC5_GR_VIN_AB1_COUNT (1) + + +typedef struct st_vdc5 +{ + /* VDC5 */ + volatile uint32_t INP_UPDATE; /* INP_UPDATE */ + volatile uint32_t INP_SEL_CNT; /* INP_SEL_CNT */ + volatile uint32_t INP_EXT_SYNC_CNT; /* INP_EXT_SYNC_CNT */ + volatile uint32_t INP_VSYNC_PH_ADJ; /* INP_VSYNC_PH_ADJ */ + volatile uint32_t INP_DLY_ADJ; /* INP_DLY_ADJ */ + volatile uint8_t dummy1[108]; /* */ + volatile uint32_t IMGCNT_UPDATE; /* IMGCNT_UPDATE */ + +/* #define VDC5_IMGCNT_NR_CNT0_COUNT (2) */ + volatile uint32_t IMGCNT_NR_CNT0; /* IMGCNT_NR_CNT0 */ + volatile uint32_t IMGCNT_NR_CNT1; /* IMGCNT_NR_CNT1 */ + volatile uint8_t dummy2[20]; /* */ + volatile uint32_t IMGCNT_MTX_MODE; /* IMGCNT_MTX_MODE */ + volatile uint32_t IMGCNT_MTX_YG_ADJ0; /* IMGCNT_MTX_YG_ADJ0 */ + volatile uint32_t IMGCNT_MTX_YG_ADJ1; /* IMGCNT_MTX_YG_ADJ1 */ + volatile uint32_t IMGCNT_MTX_CBB_ADJ0; /* IMGCNT_MTX_CBB_ADJ0 */ + volatile uint32_t IMGCNT_MTX_CBB_ADJ1; /* IMGCNT_MTX_CBB_ADJ1 */ + volatile uint32_t IMGCNT_MTX_CRR_ADJ0; /* IMGCNT_MTX_CRR_ADJ0 */ + volatile uint32_t IMGCNT_MTX_CRR_ADJ1; /* IMGCNT_MTX_CRR_ADJ1 */ + volatile uint8_t dummy3[68]; /* */ + volatile uint32_t SC0_SCL0_UPDATE; /* SC0_SCL0_UPDATE */ + +/* #define VDC5_SC0_SCL0_FRC1_COUNT (7) */ + volatile uint32_t SC0_SCL0_FRC1; /* SC0_SCL0_FRC1 */ + volatile uint32_t SC0_SCL0_FRC2; /* SC0_SCL0_FRC2 */ + volatile uint32_t SC0_SCL0_FRC3; /* SC0_SCL0_FRC3 */ + volatile uint32_t SC0_SCL0_FRC4; /* SC0_SCL0_FRC4 */ + volatile uint32_t SC0_SCL0_FRC5; /* SC0_SCL0_FRC5 */ + volatile uint32_t SC0_SCL0_FRC6; /* SC0_SCL0_FRC6 */ + volatile uint32_t SC0_SCL0_FRC7; /* SC0_SCL0_FRC7 */ + volatile uint8_t dummy4[4]; /* */ + volatile uint32_t SC0_SCL0_FRC9; /* SC0_SCL0_FRC9 */ + volatile uint16_t SC0_SCL0_MON0; /* SC0_SCL0_MON0 */ + volatile uint16_t SC0_SCL0_INT; /* SC0_SCL0_INT */ + +/* #define VDC5_SC0_SCL0_DS1_COUNT (7) */ + volatile uint32_t SC0_SCL0_DS1; /* SC0_SCL0_DS1 */ + volatile uint32_t SC0_SCL0_DS2; /* SC0_SCL0_DS2 */ + volatile uint32_t SC0_SCL0_DS3; /* SC0_SCL0_DS3 */ + volatile uint32_t SC0_SCL0_DS4; /* SC0_SCL0_DS4 */ + volatile uint32_t SC0_SCL0_DS5; /* SC0_SCL0_DS5 */ + volatile uint32_t SC0_SCL0_DS6; /* SC0_SCL0_DS6 */ + volatile uint32_t SC0_SCL0_DS7; /* SC0_SCL0_DS7 */ + +/* #define VDC5_SC0_SCL0_US1_COUNT (8) */ + volatile uint32_t SC0_SCL0_US1; /* SC0_SCL0_US1 */ + volatile uint32_t SC0_SCL0_US2; /* SC0_SCL0_US2 */ + volatile uint32_t SC0_SCL0_US3; /* SC0_SCL0_US3 */ + volatile uint32_t SC0_SCL0_US4; /* SC0_SCL0_US4 */ + volatile uint32_t SC0_SCL0_US5; /* SC0_SCL0_US5 */ + volatile uint32_t SC0_SCL0_US6; /* SC0_SCL0_US6 */ + volatile uint32_t SC0_SCL0_US7; /* SC0_SCL0_US7 */ + volatile uint32_t SC0_SCL0_US8; /* SC0_SCL0_US8 */ + volatile uint8_t dummy5[4]; /* */ + volatile uint32_t SC0_SCL0_OVR1; /* SC0_SCL0_OVR1 */ + volatile uint8_t dummy6[16]; /* */ + volatile uint32_t SC0_SCL1_UPDATE; /* SC0_SCL1_UPDATE */ + volatile uint8_t dummy7[4]; /* */ + +/* #define VDC5_SC0_SCL1_WR1_COUNT (4) */ + volatile uint32_t SC0_SCL1_WR1; /* SC0_SCL1_WR1 */ + volatile uint32_t SC0_SCL1_WR2; /* SC0_SCL1_WR2 */ + volatile uint32_t SC0_SCL1_WR3; /* SC0_SCL1_WR3 */ + volatile uint32_t SC0_SCL1_WR4; /* SC0_SCL1_WR4 */ + volatile uint8_t dummy8[4]; /* */ + volatile uint32_t SC0_SCL1_WR5; /* SC0_SCL1_WR5 */ + volatile uint32_t SC0_SCL1_WR6; /* SC0_SCL1_WR6 */ + volatile uint32_t SC0_SCL1_WR7; /* SC0_SCL1_WR7 */ + volatile uint32_t SC0_SCL1_WR8; /* SC0_SCL1_WR8 */ + volatile uint32_t SC0_SCL1_WR9; /* SC0_SCL1_WR9 */ + volatile uint32_t SC0_SCL1_WR10; /* SC0_SCL1_WR10 */ + volatile uint32_t SC0_SCL1_WR11; /* SC0_SCL1_WR11 */ + volatile uint32_t SC0_SCL1_MON1; /* SC0_SCL1_MON1 */ + +/* #define VDC5_SC0_SCL1_PBUF0_COUNT (4) */ + volatile uint32_t SC0_SCL1_PBUF0; /* SC0_SCL1_PBUF0 */ + volatile uint32_t SC0_SCL1_PBUF1; /* SC0_SCL1_PBUF1 */ + volatile uint32_t SC0_SCL1_PBUF2; /* SC0_SCL1_PBUF2 */ + volatile uint32_t SC0_SCL1_PBUF3; /* SC0_SCL1_PBUF3 */ + volatile uint32_t SC0_SCL1_PBUF_FLD; /* SC0_SCL1_PBUF_FLD */ + volatile uint32_t SC0_SCL1_PBUF_CNT; /* SC0_SCL1_PBUF_CNT */ + volatile uint8_t dummy9[44]; /* */ + +/* start of struct st_vdc5_from_gr0_update */ + volatile uint32_t GR0_UPDATE; /* GR0_UPDATE */ + volatile uint32_t GR0_FLM_RD; /* GR0_FLM_RD */ + +/* #define VDC5_GR0_FLM1_COUNT (6) */ + volatile uint32_t GR0_FLM1; /* GR0_FLM1 */ + volatile uint32_t GR0_FLM2; /* GR0_FLM2 */ + volatile uint32_t GR0_FLM3; /* GR0_FLM3 */ + volatile uint32_t GR0_FLM4; /* GR0_FLM4 */ + volatile uint32_t GR0_FLM5; /* GR0_FLM5 */ + volatile uint32_t GR0_FLM6; /* GR0_FLM6 */ + +/* #define VDC5_GR0_AB1_COUNT (3) */ + volatile uint32_t GR0_AB1; /* GR0_AB1 */ + volatile uint32_t GR0_AB2; /* GR0_AB2 */ + volatile uint32_t GR0_AB3; /* GR0_AB3 */ + +/* end of struct st_vdc5_from_gr0_update */ + volatile uint8_t dummy10[12]; /* */ + +/* start of struct st_vdc5_from_gr0_ab7 */ + volatile uint32_t GR0_AB7; /* GR0_AB7 */ + volatile uint32_t GR0_AB8; /* GR0_AB8 */ + volatile uint32_t GR0_AB9; /* GR0_AB9 */ + volatile uint32_t GR0_AB10; /* GR0_AB10 */ + volatile uint32_t GR0_AB11; /* GR0_AB11 */ + volatile uint32_t GR0_BASE; /* GR0_BASE */ + +/* end of struct st_vdc5_from_gr0_ab7 */ + volatile uint32_t GR0_CLUT; /* GR0_CLUT */ + volatile uint8_t dummy11[44]; /* */ + volatile uint32_t ADJ0_UPDATE; /* ADJ0_UPDATE */ + volatile uint32_t ADJ0_BKSTR_SET; /* ADJ0_BKSTR_SET */ + +/* #define VDC5_ADJ0_ENH_TIM1_COUNT (3) */ + volatile uint32_t ADJ0_ENH_TIM1; /* ADJ0_ENH_TIM1 */ + volatile uint32_t ADJ0_ENH_TIM2; /* ADJ0_ENH_TIM2 */ + volatile uint32_t ADJ0_ENH_TIM3; /* ADJ0_ENH_TIM3 */ + +/* #define VDC5_ADJ0_ENH_SHP1_COUNT (6) */ + volatile uint32_t ADJ0_ENH_SHP1; /* ADJ0_ENH_SHP1 */ + volatile uint32_t ADJ0_ENH_SHP2; /* ADJ0_ENH_SHP2 */ + volatile uint32_t ADJ0_ENH_SHP3; /* ADJ0_ENH_SHP3 */ + volatile uint32_t ADJ0_ENH_SHP4; /* ADJ0_ENH_SHP4 */ + volatile uint32_t ADJ0_ENH_SHP5; /* ADJ0_ENH_SHP5 */ + volatile uint32_t ADJ0_ENH_SHP6; /* ADJ0_ENH_SHP6 */ + +/* #define VDC5_ADJ0_ENH_LTI1_COUNT (2) */ + volatile uint32_t ADJ0_ENH_LTI1; /* ADJ0_ENH_LTI1 */ + volatile uint32_t ADJ0_ENH_LTI2; /* ADJ0_ENH_LTI2 */ + volatile uint32_t ADJ0_MTX_MODE; /* ADJ0_MTX_MODE */ + volatile uint32_t ADJ0_MTX_YG_ADJ0; /* ADJ0_MTX_YG_ADJ0 */ + volatile uint32_t ADJ0_MTX_YG_ADJ1; /* ADJ0_MTX_YG_ADJ1 */ + volatile uint32_t ADJ0_MTX_CBB_ADJ0; /* ADJ0_MTX_CBB_ADJ0 */ + volatile uint32_t ADJ0_MTX_CBB_ADJ1; /* ADJ0_MTX_CBB_ADJ1 */ + volatile uint32_t ADJ0_MTX_CRR_ADJ0; /* ADJ0_MTX_CRR_ADJ0 */ + volatile uint32_t ADJ0_MTX_CRR_ADJ1; /* ADJ0_MTX_CRR_ADJ1 */ + volatile uint8_t dummy12[48]; /* */ + +/* start of struct st_vdc5_from_gr0_update */ + +/* start of struct st_vdc5_from_gr0_update */ + volatile uint32_t GR2_UPDATE; /* GR2_UPDATE */ + volatile uint32_t GR2_FLM_RD; /* GR2_FLM_RD */ + +/* #define VDC5_GR2_FLM1_COUNT (6) */ + volatile uint32_t GR2_FLM1; /* GR2_FLM1 */ + volatile uint32_t GR2_FLM2; /* GR2_FLM2 */ + volatile uint32_t GR2_FLM3; /* GR2_FLM3 */ + volatile uint32_t GR2_FLM4; /* GR2_FLM4 */ + volatile uint32_t GR2_FLM5; /* GR2_FLM5 */ + volatile uint32_t GR2_FLM6; /* GR2_FLM6 */ + +/* #define VDC5_GR2_AB1_COUNT (3) */ + volatile uint32_t GR2_AB1; /* GR2_AB1 */ + volatile uint32_t GR2_AB2; /* GR2_AB2 */ + volatile uint32_t GR2_AB3; /* GR2_AB3 */ + +/* end of struct st_vdc5_from_gr0_update */ + +/* end of struct st_vdc5_from_gr0_update */ + volatile uint32_t GR2_AB4; /* GR2_AB4 */ + volatile uint32_t GR2_AB5; /* GR2_AB5 */ + volatile uint32_t GR2_AB6; /* GR2_AB6 */ + +/* start of struct st_vdc5_from_gr0_ab7 */ + +/* start of struct st_vdc5_from_gr0_ab7 */ + volatile uint32_t GR2_AB7; /* GR2_AB7 */ + volatile uint32_t GR2_AB8; /* GR2_AB8 */ + volatile uint32_t GR2_AB9; /* GR2_AB9 */ + volatile uint32_t GR2_AB10; /* GR2_AB10 */ + volatile uint32_t GR2_AB11; /* GR2_AB11 */ + volatile uint32_t GR2_BASE; /* GR2_BASE */ + +/* end of struct st_vdc5_from_gr0_ab7 */ + +/* end of struct st_vdc5_from_gr0_ab7 */ + volatile uint32_t GR2_CLUT; /* GR2_CLUT */ + volatile uint32_t GR2_MON; /* GR2_MON */ + volatile uint8_t dummy13[40]; /* */ + +/* start of struct st_vdc5_from_gr0_update */ + +/* start of struct st_vdc5_from_gr0_update */ + volatile uint32_t GR3_UPDATE; /* GR3_UPDATE */ + volatile uint32_t GR3_FLM_RD; /* GR3_FLM_RD */ + +/* #define VDC5_GR3_FLM1_COUNT (6) */ + volatile uint32_t GR3_FLM1; /* GR3_FLM1 */ + volatile uint32_t GR3_FLM2; /* GR3_FLM2 */ + volatile uint32_t GR3_FLM3; /* GR3_FLM3 */ + volatile uint32_t GR3_FLM4; /* GR3_FLM4 */ + volatile uint32_t GR3_FLM5; /* GR3_FLM5 */ + volatile uint32_t GR3_FLM6; /* GR3_FLM6 */ + +/* #define VDC5_GR3_AB1_COUNT (3) */ + volatile uint32_t GR3_AB1; /* GR3_AB1 */ + volatile uint32_t GR3_AB2; /* GR3_AB2 */ + volatile uint32_t GR3_AB3; /* GR3_AB3 */ + +/* end of struct st_vdc5_from_gr0_update */ + +/* end of struct st_vdc5_from_gr0_update */ + volatile uint32_t GR3_AB4; /* GR3_AB4 */ + volatile uint32_t GR3_AB5; /* GR3_AB5 */ + volatile uint32_t GR3_AB6; /* GR3_AB6 */ + +/* start of struct st_vdc5_from_gr0_ab7 */ + +/* start of struct st_vdc5_from_gr0_ab7 */ + volatile uint32_t GR3_AB7; /* GR3_AB7 */ + volatile uint32_t GR3_AB8; /* GR3_AB8 */ + volatile uint32_t GR3_AB9; /* GR3_AB9 */ + volatile uint32_t GR3_AB10; /* GR3_AB10 */ + volatile uint32_t GR3_AB11; /* GR3_AB11 */ + volatile uint32_t GR3_BASE; /* GR3_BASE */ + +/* end of struct st_vdc5_from_gr0_ab7 */ + +/* end of struct st_vdc5_from_gr0_ab7 */ + volatile uint32_t GR3_CLUT_INT; /* GR3_CLUT_INT */ + volatile uint32_t GR3_MON; /* GR3_MON */ + volatile uint8_t dummy14[40]; /* */ + volatile uint32_t GAM_G_UPDATE; /* GAM_G_UPDATE */ + volatile uint32_t GAM_SW; /* GAM_SW */ + +/* #define VDC5_GAM_G_LUT1_COUNT (16) */ + volatile uint32_t GAM_G_LUT1; /* GAM_G_LUT1 */ + volatile uint32_t GAM_G_LUT2; /* GAM_G_LUT2 */ + volatile uint32_t GAM_G_LUT3; /* GAM_G_LUT3 */ + volatile uint32_t GAM_G_LUT4; /* GAM_G_LUT4 */ + volatile uint32_t GAM_G_LUT5; /* GAM_G_LUT5 */ + volatile uint32_t GAM_G_LUT6; /* GAM_G_LUT6 */ + volatile uint32_t GAM_G_LUT7; /* GAM_G_LUT7 */ + volatile uint32_t GAM_G_LUT8; /* GAM_G_LUT8 */ + volatile uint32_t GAM_G_LUT9; /* GAM_G_LUT9 */ + volatile uint32_t GAM_G_LUT10; /* GAM_G_LUT10 */ + volatile uint32_t GAM_G_LUT11; /* GAM_G_LUT11 */ + volatile uint32_t GAM_G_LUT12; /* GAM_G_LUT12 */ + volatile uint32_t GAM_G_LUT13; /* GAM_G_LUT13 */ + volatile uint32_t GAM_G_LUT14; /* GAM_G_LUT14 */ + volatile uint32_t GAM_G_LUT15; /* GAM_G_LUT15 */ + volatile uint32_t GAM_G_LUT16; /* GAM_G_LUT16 */ + +/* #define VDC5_GAM_G_AREA1_COUNT (8) */ + volatile uint32_t GAM_G_AREA1; /* GAM_G_AREA1 */ + volatile uint32_t GAM_G_AREA2; /* GAM_G_AREA2 */ + volatile uint32_t GAM_G_AREA3; /* GAM_G_AREA3 */ + volatile uint32_t GAM_G_AREA4; /* GAM_G_AREA4 */ + volatile uint32_t GAM_G_AREA5; /* GAM_G_AREA5 */ + volatile uint32_t GAM_G_AREA6; /* GAM_G_AREA6 */ + volatile uint32_t GAM_G_AREA7; /* GAM_G_AREA7 */ + volatile uint32_t GAM_G_AREA8; /* GAM_G_AREA8 */ + volatile uint8_t dummy15[24]; /* */ + volatile uint32_t GAM_B_UPDATE; /* GAM_B_UPDATE */ + volatile uint8_t dummy16[4]; /* */ + +/* #define VDC5_GAM_B_LUT1_COUNT (16) */ + volatile uint32_t GAM_B_LUT1; /* GAM_B_LUT1 */ + volatile uint32_t GAM_B_LUT2; /* GAM_B_LUT2 */ + volatile uint32_t GAM_B_LUT3; /* GAM_B_LUT3 */ + volatile uint32_t GAM_B_LUT4; /* GAM_B_LUT4 */ + volatile uint32_t GAM_B_LUT5; /* GAM_B_LUT5 */ + volatile uint32_t GAM_B_LUT6; /* GAM_B_LUT6 */ + volatile uint32_t GAM_B_LUT7; /* GAM_B_LUT7 */ + volatile uint32_t GAM_B_LUT8; /* GAM_B_LUT8 */ + volatile uint32_t GAM_B_LUT9; /* GAM_B_LUT9 */ + volatile uint32_t GAM_B_LUT10; /* GAM_B_LUT10 */ + volatile uint32_t GAM_B_LUT11; /* GAM_B_LUT11 */ + volatile uint32_t GAM_B_LUT12; /* GAM_B_LUT12 */ + volatile uint32_t GAM_B_LUT13; /* GAM_B_LUT13 */ + volatile uint32_t GAM_B_LUT14; /* GAM_B_LUT14 */ + volatile uint32_t GAM_B_LUT15; /* GAM_B_LUT15 */ + volatile uint32_t GAM_B_LUT16; /* GAM_B_LUT16 */ + +/* #define VDC5_GAM_B_AREA1_COUNT (8) */ + volatile uint32_t GAM_B_AREA1; /* GAM_B_AREA1 */ + volatile uint32_t GAM_B_AREA2; /* GAM_B_AREA2 */ + volatile uint32_t GAM_B_AREA3; /* GAM_B_AREA3 */ + volatile uint32_t GAM_B_AREA4; /* GAM_B_AREA4 */ + volatile uint32_t GAM_B_AREA5; /* GAM_B_AREA5 */ + volatile uint32_t GAM_B_AREA6; /* GAM_B_AREA6 */ + volatile uint32_t GAM_B_AREA7; /* GAM_B_AREA7 */ + volatile uint32_t GAM_B_AREA8; /* GAM_B_AREA8 */ + volatile uint8_t dummy17[24]; /* */ + volatile uint32_t GAM_R_UPDATE; /* GAM_R_UPDATE */ + volatile uint8_t dummy18[4]; /* */ + +/* #define VDC5_GAM_R_LUT1_COUNT (16) */ + volatile uint32_t GAM_R_LUT1; /* GAM_R_LUT1 */ + volatile uint32_t GAM_R_LUT2; /* GAM_R_LUT2 */ + volatile uint32_t GAM_R_LUT3; /* GAM_R_LUT3 */ + volatile uint32_t GAM_R_LUT4; /* GAM_R_LUT4 */ + volatile uint32_t GAM_R_LUT5; /* GAM_R_LUT5 */ + volatile uint32_t GAM_R_LUT6; /* GAM_R_LUT6 */ + volatile uint32_t GAM_R_LUT7; /* GAM_R_LUT7 */ + volatile uint32_t GAM_R_LUT8; /* GAM_R_LUT8 */ + volatile uint32_t GAM_R_LUT9; /* GAM_R_LUT9 */ + volatile uint32_t GAM_R_LUT10; /* GAM_R_LUT10 */ + volatile uint32_t GAM_R_LUT11; /* GAM_R_LUT11 */ + volatile uint32_t GAM_R_LUT12; /* GAM_R_LUT12 */ + volatile uint32_t GAM_R_LUT13; /* GAM_R_LUT13 */ + volatile uint32_t GAM_R_LUT14; /* GAM_R_LUT14 */ + volatile uint32_t GAM_R_LUT15; /* GAM_R_LUT15 */ + volatile uint32_t GAM_R_LUT16; /* GAM_R_LUT16 */ + +/* #define VDC5_GAM_R_AREA1_COUNT (8) */ + volatile uint32_t GAM_R_AREA1; /* GAM_R_AREA1 */ + volatile uint32_t GAM_R_AREA2; /* GAM_R_AREA2 */ + volatile uint32_t GAM_R_AREA3; /* GAM_R_AREA3 */ + volatile uint32_t GAM_R_AREA4; /* GAM_R_AREA4 */ + volatile uint32_t GAM_R_AREA5; /* GAM_R_AREA5 */ + volatile uint32_t GAM_R_AREA6; /* GAM_R_AREA6 */ + volatile uint32_t GAM_R_AREA7; /* GAM_R_AREA7 */ + volatile uint32_t GAM_R_AREA8; /* GAM_R_AREA8 */ + volatile uint8_t dummy19[24]; /* */ + volatile uint32_t TCON_UPDATE; /* TCON_UPDATE */ + volatile uint32_t TCON_TIM; /* TCON_TIM */ + +/* #define VDC5_TCON_TIM_STVA1_COUNT (2) */ + volatile uint32_t TCON_TIM_STVA1; /* TCON_TIM_STVA1 */ + volatile uint32_t TCON_TIM_STVA2; /* TCON_TIM_STVA2 */ + +/* #define VDC5_TCON_TIM_STVB1_COUNT (2) */ + volatile uint32_t TCON_TIM_STVB1; /* TCON_TIM_STVB1 */ + volatile uint32_t TCON_TIM_STVB2; /* TCON_TIM_STVB2 */ + +/* #define VDC5_TCON_TIM_STH1_COUNT (2) */ + volatile uint32_t TCON_TIM_STH1; /* TCON_TIM_STH1 */ + volatile uint32_t TCON_TIM_STH2; /* TCON_TIM_STH2 */ + +/* #define VDC5_TCON_TIM_STB1_COUNT (2) */ + volatile uint32_t TCON_TIM_STB1; /* TCON_TIM_STB1 */ + volatile uint32_t TCON_TIM_STB2; /* TCON_TIM_STB2 */ + +/* #define VDC5_TCON_TIM_CPV1_COUNT (2) */ + volatile uint32_t TCON_TIM_CPV1; /* TCON_TIM_CPV1 */ + volatile uint32_t TCON_TIM_CPV2; /* TCON_TIM_CPV2 */ + +/* #define VDC5_TCON_TIM_POLA1_COUNT (2) */ + volatile uint32_t TCON_TIM_POLA1; /* TCON_TIM_POLA1 */ + volatile uint32_t TCON_TIM_POLA2; /* TCON_TIM_POLA2 */ + +/* #define VDC5_TCON_TIM_POLB1_COUNT (2) */ + volatile uint32_t TCON_TIM_POLB1; /* TCON_TIM_POLB1 */ + volatile uint32_t TCON_TIM_POLB2; /* TCON_TIM_POLB2 */ + volatile uint32_t TCON_TIM_DE; /* TCON_TIM_DE */ + volatile uint8_t dummy20[60]; /* */ + volatile uint32_t OUT_UPDATE; /* OUT_UPDATE */ + volatile uint32_t OUT_SET; /* OUT_SET */ + +/* #define VDC5_OUT_BRIGHT1_COUNT (2) */ + volatile uint32_t OUT_BRIGHT1; /* OUT_BRIGHT1 */ + volatile uint32_t OUT_BRIGHT2; /* OUT_BRIGHT2 */ + volatile uint32_t OUT_CONTRAST; /* OUT_CONTRAST */ + volatile uint32_t OUT_PDTHA; /* OUT_PDTHA */ + volatile uint8_t dummy21[12]; /* */ + volatile uint32_t OUT_CLK_PHASE; /* OUT_CLK_PHASE */ + volatile uint8_t dummy22[88]; /* */ + +/* #define VDC5_SYSCNT_INT1_COUNT (2) */ + volatile uint32_t SYSCNT_INT1; /* SYSCNT_INT1 */ + volatile uint32_t SYSCNT_INT2; /* SYSCNT_INT2 */ + volatile uint8_t dummy23[4]; /* */ + volatile uint32_t SYSCNT_INT4; /* SYSCNT_INT4 */ + volatile uint32_t SYSCNT_INT5; /* SYSCNT_INT5 */ + volatile uint8_t dummy24[4]; /* */ + volatile uint16_t SYSCNT_PANEL_CLK; /* SYSCNT_PANEL_CLK */ + volatile uint16_t SYSCNT_CLUT; /* SYSCNT_CLUT */ + volatile uint8_t dummy25[868]; /* */ + volatile uint32_t GR_VIN_UPDATE; /* GR_VIN_UPDATE */ + volatile uint8_t dummy26[28]; /* */ + +/* #define VDC5_GR_VIN_AB1_COUNT (1) */ + volatile uint32_t GR_VIN_AB1; /* GR_VIN_AB1 */ +} r_io_vdc5_t; + + +typedef struct st_vdc5_from_gr0_update +{ + + volatile uint32_t GR0_UPDATE; /* GR0_UPDATE */ + volatile uint32_t GR0_FLM_RD; /* GR0_FLM_RD */ + volatile uint32_t GR0_FLM1; /* GR0_FLM1 */ + volatile uint32_t GR0_FLM2; /* GR0_FLM2 */ + volatile uint32_t GR0_FLM3; /* GR0_FLM3 */ + volatile uint32_t GR0_FLM4; /* GR0_FLM4 */ + volatile uint32_t GR0_FLM5; /* GR0_FLM5 */ + volatile uint32_t GR0_FLM6; /* GR0_FLM6 */ + volatile uint32_t GR0_AB1; /* GR0_AB1 */ + volatile uint32_t GR0_AB2; /* GR0_AB2 */ + volatile uint32_t GR0_AB3; /* GR0_AB3 */ +} r_io_vdc5_from_gr0_update_t; + + +typedef struct st_vdc5_from_gr0_ab7 +{ + + volatile uint32_t GR0_AB7; /* GR0_AB7 */ + volatile uint32_t GR0_AB8; /* GR0_AB8 */ + volatile uint32_t GR0_AB9; /* GR0_AB9 */ + volatile uint32_t GR0_AB10; /* GR0_AB10 */ + volatile uint32_t GR0_AB11; /* GR0_AB11 */ + volatile uint32_t GR0_BASE; /* GR0_BASE */ +} r_io_vdc5_from_gr0_ab7_t; + + +/* Channel array defines of VDC5 (2)*/ +#ifdef DECLARE_VDC5_CHANNELS +volatile struct st_vdc5* VDC5[ VDC5_COUNT ] = + /* ->MISRA 11.3 */ /* ->SEC R2.7.1 */ + VDC5_ADDRESS_LIST; + /* <-MISRA 11.3 */ /* <-SEC R2.7.1 */ +#endif /* DECLARE_VDC5_CHANNELS */ + +#ifdef DECLARE_VDC50_FROM_GR2_AB7_ARRAY_CHANNELS +volatile struct st_vdc5_from_gr0_ab7* VDC50_FROM_GR2_AB7_ARRAY[ VDC5_COUNT ][ VDC50_FROM_GR2_AB7_ARRAY_COUNT ] = + /* ->MISRA 11.3 */ /* ->SEC R2.7.1 */ + VDC50_FROM_GR2_AB7_ARRAY_ADDRESS_LIST; + /* <-MISRA 11.3 */ /* <-SEC R2.7.1 */ +#endif /* DECLARE_VDC50_FROM_GR2_AB7_ARRAY_CHANNELS */ + +#ifdef DECLARE_VDC50_FROM_GR2_UPDATE_ARRAY_CHANNELS +volatile struct st_vdc5_from_gr0_update* VDC50_FROM_GR2_UPDATE_ARRAY[ VDC5_COUNT ][ VDC50_FROM_GR2_UPDATE_ARRAY_COUNT ] = + /* ->MISRA 11.3 */ /* ->SEC R2.7.1 */ + VDC50_FROM_GR2_UPDATE_ARRAY_ADDRESS_LIST; + /* <-MISRA 11.3 */ /* <-SEC R2.7.1 */ +#endif /* DECLARE_VDC50_FROM_GR2_UPDATE_ARRAY_CHANNELS */ + +#ifdef DECLARE_VDC50_FROM_GR0_AB7_ARRAY_CHANNELS +volatile struct st_vdc5_from_gr0_ab7* VDC50_FROM_GR0_AB7_ARRAY[ VDC5_COUNT ][ VDC50_FROM_GR0_AB7_ARRAY_COUNT ] = + /* ->MISRA 11.3 */ /* ->SEC R2.7.1 */ + VDC50_FROM_GR0_AB7_ARRAY_ADDRESS_LIST; + /* <-MISRA 11.3 */ /* <-SEC R2.7.1 */ +#endif /* DECLARE_VDC50_FROM_GR0_AB7_ARRAY_CHANNELS */ + +#ifdef DECLARE_VDC50_FROM_GR0_UPDATE_ARRAY_CHANNELS +volatile struct st_vdc5_from_gr0_update* VDC50_FROM_GR0_UPDATE_ARRAY[ VDC5_COUNT ][ VDC50_FROM_GR0_UPDATE_ARRAY_COUNT ] = + /* ->MISRA 11.3 */ /* ->SEC R2.7.1 */ + VDC50_FROM_GR0_UPDATE_ARRAY_ADDRESS_LIST; + /* <-MISRA 11.3 */ /* <-SEC R2.7.1 */ +#endif /* DECLARE_VDC50_FROM_GR0_UPDATE_ARRAY_CHANNELS */ +/* End of channel array defines of VDC5 (2)*/ + + +/* <-SEC M1.10.1 */ +/* <-MISRA 18.4 */ /* <-SEC M1.6.2 */ +/* <-QAC 0857 */ +/* <-QAC 0639 */ +#endif diff --git a/targets/TARGET_RENESAS/TARGET_RZ_A1XX/TARGET_GR_LYCHEE/device/inc/iodefines/wdt_iodefine.h b/targets/TARGET_RENESAS/TARGET_RZ_A1XX/TARGET_GR_LYCHEE/device/inc/iodefines/wdt_iodefine.h new file mode 100644 index 0000000..774c594 --- /dev/null +++ b/targets/TARGET_RENESAS/TARGET_RZ_A1XX/TARGET_GR_LYCHEE/device/inc/iodefines/wdt_iodefine.h @@ -0,0 +1,57 @@ +/******************************************************************************* +* DISCLAIMER +* This software is supplied by Renesas Electronics Corporation and is only +* intended for use with Renesas products. No other uses are authorized. This +* software is owned by Renesas Electronics Corporation and is protected under +* all applicable laws, including copyright laws. +* THIS SOFTWARE IS PROVIDED "AS IS" AND RENESAS MAKES NO WARRANTIES REGARDING +* THIS SOFTWARE, WHETHER EXPRESS, IMPLIED OR STATUTORY, INCLUDING BUT NOT +* LIMITED TO WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE +* AND NON-INFRINGEMENT. ALL SUCH WARRANTIES ARE EXPRESSLY DISCLAIMED. +* TO THE MAXIMUM EXTENT PERMITTED NOT PROHIBITED BY LAW, NEITHER RENESAS +* ELECTRONICS CORPORATION NOR ANY OF ITS AFFILIATED COMPANIES SHALL BE LIABLE +* FOR ANY DIRECT, INDIRECT, SPECIAL, INCIDENTAL OR CONSEQUENTIAL DAMAGES FOR +* ANY REASON RELATED TO THIS SOFTWARE, EVEN IF RENESAS OR ITS AFFILIATES HAVE +* BEEN ADVISED OF THE POSSIBILITY OF SUCH DAMAGES. +* Renesas reserves the right, without notice, to make changes to this software +* and to discontinue the availability of this software. By using this software, +* you agree to the additional terms and conditions found by accessing the +* following link: +* http://www.renesas.com/disclaimer* +* Copyright (C) 2013-2016 Renesas Electronics Corporation. All rights reserved. +*******************************************************************************/ +/******************************************************************************* +* File Name : wdt_iodefine.h +* $Rev: $ +* $Date:: $ +* Description : Definition of I/O Register for RZ/A1LU (V3.00l) +******************************************************************************/ +#ifndef WDT_IODEFINE_H +#define WDT_IODEFINE_H +/* ->QAC 0639 : Over 127 members (C90) */ +/* ->QAC 0857 : Over 1024 #define (C90) */ +/* ->MISRA 18.4 : Pack unpack union */ /* ->SEC M1.6.2 */ +/* ->SEC M1.10.1 : Not magic number */ + +#define WDT (*(struct st_wdt *)0xFCFE0000uL) /* WDT */ + + +#define WDTWTCSR (WDT.WTCSR) +#define WDTWTCNT (WDT.WTCNT) +#define WDTWRCSR (WDT.WRCSR) + + +typedef struct st_wdt +{ + /* WDT */ + volatile uint16_t WTCSR; /* WTCSR */ + volatile uint16_t WTCNT; /* WTCNT */ + volatile uint16_t WRCSR; /* WRCSR */ +} r_io_wdt_t; + + +/* <-SEC M1.10.1 */ +/* <-MISRA 18.4 */ /* <-SEC M1.6.2 */ +/* <-QAC 0857 */ +/* <-QAC 0639 */ +#endif diff --git a/targets/TARGET_RENESAS/TARGET_RZ_A1XX/TARGET_GR_LYCHEE/device/mbed_sf_boot.c b/targets/TARGET_RENESAS/TARGET_RZ_A1XX/TARGET_GR_LYCHEE/device/mbed_sf_boot.c new file mode 100644 index 0000000..2c7620a --- /dev/null +++ b/targets/TARGET_RENESAS/TARGET_RZ_A1XX/TARGET_GR_LYCHEE/device/mbed_sf_boot.c @@ -0,0 +1,827 @@ +/******************************************************************************* +* DISCLAIMER +* This software is supplied by Renesas Electronics Corporation and is only +* intended for use with Renesas products. No other uses are authorized. This +* software is owned by Renesas Electronics Corporation and is protected under +* all applicable laws, including copyright laws. +* THIS SOFTWARE IS PROVIDED "AS IS" AND RENESAS MAKES NO WARRANTIES REGARDING +* THIS SOFTWARE, WHETHER EXPRESS, IMPLIED OR STATUTORY, INCLUDING BUT NOT +* LIMITED TO WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE +* AND NON-INFRINGEMENT. ALL SUCH WARRANTIES ARE EXPRESSLY DISCLAIMED. +* TO THE MAXIMUM EXTENT PERMITTED NOT PROHIBITED BY LAW, NEITHER RENESAS +* ELECTRONICS CORPORATION NOR ANY OF ITS AFFILIATED COMPANIES SHALL BE LIABLE +* FOR ANY DIRECT, INDIRECT, SPECIAL, INCIDENTAL OR CONSEQUENTIAL DAMAGES FOR +* ANY REASON RELATED TO THIS SOFTWARE, EVEN IF RENESAS OR ITS AFFILIATES HAVE +* BEEN ADVISED OF THE POSSIBILITY OF SUCH DAMAGES. +* Renesas reserves the right, without notice, to make changes to this software +* and to discontinue the availability of this software. By using this software, +* you agree to the additional terms and conditions found by accessing the +* following link: +* http://www.renesas.com/disclaimer +* Copyright (C) 2012 - 2014 Renesas Electronics Corporation. All rights reserved. +*******************************************************************************/ +/**************************************************************************//** +* @file mbed_sf_boot.c +* $Rev: $ +* $Date:: $ +* @brief RZ_A1 serial flash boot loader +******************************************************************************/ +#if defined (__CC_ARM) +#pragma arm section rodata = "BOOT_LOADER" +const char boot_loader[] __attribute__((used)) = + +#elif defined (__ICCARM__) +__root const char boot_loader[] @ 0x18000000 = +#else +const char boot_loader[] __attribute__ ((section(".boot_loader"), used)) = + +#endif +{ + 0x18,0xF0,0x9F,0xE5,0x18,0xF0,0x9F,0xE5,0x18,0xF0,0x9F,0xE5,0x18,0xF0,0x9F,0xE5, + 0x18,0xF0,0x9F,0xE5,0x18,0xF0,0x9F,0xE5,0x18,0xF0,0x9F,0xE5,0x18,0xF0,0x9F,0xE5, + 0x00,0x30,0x00,0x18,0x60,0x30,0x00,0x18,0x64,0x30,0x00,0x18,0x68,0x30,0x00,0x18, + 0x6C,0x30,0x00,0x18,0x70,0x30,0x00,0x18,0x74,0x30,0x00,0x18,0x78,0x30,0x00,0x18, + 0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF, + 0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF, + 0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF, + 0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF, + 0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF, + 0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF, + 0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF, + 0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF, + 0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF, + 0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF, + 0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF, + 0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF, + 0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF, + 0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF, + 0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF, + 0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF, + 0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF, + 0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF, + 0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF, + 0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF, + 0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF, + 0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF, + 0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF, + 0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF, + 0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF, + 0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF, + 0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF, + 0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF, + 0x2C,0x30,0x9F,0xE5,0x00,0x20,0xA0,0xE3,0x28,0x10,0x9F,0xE5,0x28,0x00,0x9F,0xE5, + 0x10,0x40,0x2D,0xE9,0x23,0x31,0xA0,0xE1,0x02,0x00,0x00,0xEA,0x04,0x40,0x91,0xE4, + 0x01,0x20,0x82,0xE2,0x04,0x40,0x80,0xE4,0x03,0x00,0x52,0xE1,0xFA,0xFF,0xFF,0x3A, + 0x10,0x80,0xBD,0xE8,0xB3,0x1B,0x00,0x00,0x00,0x04,0x00,0x18,0x00,0x02,0x02,0x20, + 0xF8,0x40,0x2D,0xE9,0x01,0x34,0xA0,0xE3,0xB4,0x50,0x9F,0xE5,0x18,0x20,0xA0,0xE3, + 0x01,0x10,0xA0,0xE3,0x05,0x00,0xA0,0xE1,0x39,0x00,0x00,0xEB,0x3C,0x40,0x85,0xE2, + 0x02,0x20,0xA0,0xE3,0x01,0x10,0xA0,0xE3,0x04,0x00,0xA0,0xE1,0x43,0x00,0x00,0xEB, + 0x00,0x00,0x50,0xE3,0xF9,0xFF,0xFF,0x1A,0x01,0x20,0xA0,0xE3,0x00,0x10,0xA0,0xE3, + 0x04,0x00,0xA0,0xE1,0x3D,0x00,0x00,0xEB,0x01,0x00,0x50,0xE3,0xF9,0xFF,0xFF,0x1A, + 0x00,0x00,0xA0,0xE3,0x6C,0x40,0x9F,0xE5,0x04,0x00,0x84,0xE5,0x00,0x20,0xA0,0xE1, + 0x00,0x10,0xA0,0xE1,0x08,0x60,0x84,0xE2,0x03,0x30,0xA0,0xE3,0x06,0x00,0xA0,0xE1, + 0x23,0x00,0x00,0xEB,0xFF,0x3C,0xA0,0xE3,0x08,0x20,0xA0,0xE3,0x02,0x10,0xA0,0xE3, + 0x06,0x00,0xA0,0xE1,0x1E,0x00,0x00,0xEB,0x02,0x3C,0xA0,0xE3,0x09,0x20,0xA0,0xE3, + 0x01,0x10,0xA0,0xE3,0x05,0x00,0xA0,0xE1,0x19,0x00,0x00,0xEB,0x0C,0x00,0x94,0xE5, + 0x01,0x3C,0xA0,0xE3,0x08,0x20,0xA0,0xE3,0x01,0x10,0xA0,0xE3,0x00,0x00,0x8D,0xE5, + 0x05,0x00,0xA0,0xE1,0x12,0x00,0x00,0xEB,0x0C,0x00,0x94,0xE5,0x00,0x00,0x8D,0xE5, + 0xF8,0x80,0xBD,0xE8,0x0C,0xA0,0xEF,0x3F,0x00,0xA0,0xEF,0x3F,0x10,0x40,0x2D,0xE9, + 0x00,0x40,0xD0,0xE5,0x11,0x12,0xA0,0xE1,0x03,0x20,0xC4,0xE1,0x02,0x10,0x81,0xE1, + 0x00,0x10,0xC0,0xE5,0x10,0x80,0xBD,0xE8,0x10,0x40,0x2D,0xE9,0xB0,0x40,0xD0,0xE1, + 0x11,0x12,0xA0,0xE1,0x03,0x20,0xC4,0xE1,0x02,0x10,0x81,0xE1,0xB0,0x10,0xC0,0xE1, + 0x10,0x80,0xBD,0xE8,0x10,0x40,0x2D,0xE9,0x00,0x40,0x90,0xE5,0x11,0x12,0xA0,0xE1, + 0x03,0x20,0xC4,0xE1,0x02,0x10,0x81,0xE1,0x00,0x10,0x80,0xE5,0x10,0x80,0xBD,0xE8, + 0x00,0x00,0xD0,0xE5,0x02,0x00,0x00,0xE0,0x30,0x01,0xA0,0xE1,0x1E,0xFF,0x2F,0xE1, + 0xB0,0x00,0xD0,0xE1,0x02,0x00,0x00,0xE0,0x30,0x01,0xA0,0xE1,0x1E,0xFF,0x2F,0xE1, + 0x00,0x00,0x90,0xE5,0x02,0x00,0x00,0xE0,0x30,0x01,0xA0,0xE1,0x1E,0xFF,0x2F,0xE1, + 0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF, + 0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF, + 0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF, + 0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF, + 0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF, + 0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF, + 0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF, + 0x10,0xFF,0x2F,0xE1,0xF0,0x41,0x2D,0xE9,0x01,0x70,0xA0,0xE1,0x08,0x43,0x9F,0xE5, + 0x01,0x10,0xA0,0xE3,0x18,0x80,0x9D,0xE5,0x00,0x50,0xA0,0xE3,0x02,0x60,0xA0,0xE1, + 0x14,0x10,0x84,0xE5,0x00,0x50,0x84,0xE5,0x46,0x00,0xC4,0xE5,0x08,0x00,0xA0,0xE3, + 0x18,0x50,0x84,0xE5,0x04,0x50,0x84,0xE5,0x47,0x50,0xC4,0xE5,0x1C,0x50,0x84,0xE5, + 0x38,0x50,0x84,0xE5,0x08,0x50,0x84,0xE5,0x48,0x50,0x84,0xE5,0x20,0x50,0x84,0xE5, + 0x3C,0x50,0x84,0xE5,0x0C,0x50,0x84,0xE5,0x4C,0x50,0xC4,0xE5,0x4D,0x50,0xC4,0xE5, + 0x4E,0x50,0xC4,0xE5,0x4F,0x50,0xC4,0xE5,0x34,0x50,0x84,0xE5,0x44,0x50,0xC4,0xE5, + 0x45,0x50,0xC4,0xE5,0x2C,0x10,0x84,0xE5,0x28,0x50,0x84,0xE5,0x24,0x00,0x84,0xE5, + 0x03,0x00,0xA0,0xE1,0x30,0x10,0x84,0xE5,0x00,0x10,0x84,0xE2,0x40,0x50,0x84,0xE5, + 0x10,0x50,0x84,0xE5,0x58,0x50,0x84,0xE5,0x5C,0x50,0x84,0xE5,0x39,0x01,0x00,0xEB, + 0x00,0x00,0x50,0xE3,0xF0,0x81,0xBD,0x18,0x00,0x00,0x58,0xE3,0x50,0x10,0xD4,0xE5, + 0x00,0x10,0xC7,0xE5,0xB0,0x15,0xD4,0x11,0x21,0x14,0xA0,0x11,0x00,0x10,0xC6,0x15, + 0x00,0x50,0xC6,0x05,0xF0,0x81,0xBD,0xE8,0x7F,0x40,0x2D,0xE9,0x02,0x50,0xA0,0xE1, + 0x01,0x40,0xA0,0xE1,0x00,0x60,0xA0,0xE1,0x06,0x30,0xA0,0xE1,0x0C,0x20,0x8D,0xE2, + 0x08,0x10,0x8D,0xE2,0x05,0x00,0xA0,0xE3,0xF0,0x40,0xCD,0xE1,0xC4,0xFF,0xFF,0xEB, + 0x00,0x00,0x50,0xE3,0x09,0x00,0x00,0x1A,0x01,0x00,0x54,0xE3,0x08,0x00,0xDD,0x05, + 0x0C,0x10,0xDD,0x05,0x01,0x00,0x80,0x01,0x02,0x00,0x00,0x0A,0x00,0x00,0x54,0xE3, + 0x08,0x00,0xDD,0x05,0xEF,0xFF,0xFF,0x1A,0x01,0x00,0x10,0xE2,0xED,0xFF,0xFF,0x1A, + 0x10,0xD0,0x8D,0xE2,0x70,0x80,0xBD,0xE8,0xEC,0x11,0x9F,0xE5,0x00,0x20,0xA0,0xE3, + 0x30,0x00,0x2D,0xE9,0x01,0x40,0xA0,0xE3,0x06,0x30,0xA0,0xE3,0x00,0x20,0x81,0xE5, + 0x14,0x40,0x81,0xE5,0x46,0x30,0xC1,0xE5,0x18,0x20,0x81,0xE5,0x04,0x20,0x81,0xE5, + 0x47,0x20,0xC1,0xE5,0x1C,0x20,0x81,0xE5,0x38,0x20,0x81,0xE5,0x08,0x20,0x81,0xE5, + 0x48,0x20,0x81,0xE5,0x20,0x20,0x81,0xE5,0x3C,0x20,0x81,0xE5,0x0C,0x20,0x81,0xE5, + 0x4C,0x20,0xC1,0xE5,0x4D,0x20,0xC1,0xE5,0x4E,0x20,0xC1,0xE5,0x4F,0x20,0xC1,0xE5, + 0x34,0x20,0x81,0xE5,0x44,0x20,0xC1,0xE5,0x45,0x20,0xC1,0xE5,0x24,0x20,0x81,0xE5, + 0x40,0x20,0x81,0xE5,0x10,0x20,0x81,0xE5,0x28,0x20,0x81,0xE5,0x2C,0x20,0x81,0xE5, + 0x30,0x20,0x81,0xE5,0x30,0x00,0xBD,0xE8,0xF6,0x00,0x00,0xEA,0xF0,0x41,0x2D,0xE9, + 0x00,0x50,0xA0,0xE1,0x03,0x60,0xA0,0xE1,0x02,0x70,0xA0,0xE1,0x18,0x80,0x9D,0xE5, + 0x01,0x40,0xA0,0xE1,0x02,0x00,0xA0,0xE1,0xD6,0xFF,0xFF,0xEB,0x00,0x00,0x50,0xE3, + 0xF0,0x81,0xBD,0x18,0x00,0x10,0xA0,0xE3,0x01,0x30,0xA0,0xE3,0x08,0x20,0xA0,0xE3, + 0x34,0x01,0x9F,0xE5,0x00,0x10,0x80,0xE5,0x14,0x30,0x80,0xE5,0x46,0x50,0xC0,0xE5, + 0x18,0x10,0x80,0xE5,0x04,0x10,0x80,0xE5,0x47,0x10,0xC0,0xE5,0x1C,0x10,0x80,0xE5, + 0x38,0x10,0x80,0xE5,0x08,0x10,0x80,0xE5,0x48,0x10,0x80,0xE5,0x20,0x20,0x80,0xE5, + 0x3C,0x10,0x80,0xE5,0x0C,0x10,0x80,0xE5,0x4C,0x40,0xC0,0xE5,0x4D,0x10,0xC0,0xE5, + 0x4E,0x10,0xC0,0xE5,0x4F,0x10,0xC0,0xE5,0x34,0x10,0x80,0xE5,0x44,0x10,0xC0,0xE5, + 0x45,0x10,0xC0,0xE5,0x28,0x10,0x80,0xE5,0x2C,0x10,0x80,0xE5,0x30,0x10,0x80,0xE5, + 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0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF, + 0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF, + 0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF, + 0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF, + 0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF, + 0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF, + 0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF, + 0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF, + 0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF, + 0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF, + 0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF, + 0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF, + 0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF, + 0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF, + 0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF, + 0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF, + 0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF, + 0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF, + 0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF, + 0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF, + 0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF, + 0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF, + 0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF, + 0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF, + 0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF, + 0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF, + 0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF, + 0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF, + 0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF, + 0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF, + 0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF, + 0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF, + 0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF, + 0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF, + 0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF, + 0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF, + 0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF, + 0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF, + 0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF, + 0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF, + 0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF, + 0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF, + 0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF, + 0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF, + 0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF, + 0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF, + 0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF, + 0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF, + 0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF, + 0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF, + 0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF, + 0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF, + 0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF, + 0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF, + 0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF, + 0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF, + 0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF, + 0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF, + 0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF, + 0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF, + 0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF, + 0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF, + 0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF, + 0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF, + 0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF, + 0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF, + 0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF, + 0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF, + 0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF, + 0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF, + 0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF, + 0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF, + 0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF, + 0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF, + 0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF, + 0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF, + 0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF, + 0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF, + 0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF, + 0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF, + 0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF, + 0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF, + 0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF, + 0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF, + 0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF, + 0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF, + 0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF, + 0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF, + 0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF, + 0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF, + 0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF, + 0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF, + 0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF, + 0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF, + 0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF, + 0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF, + 0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF, + 0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF, + 0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF, + 0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF, + 0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF, + 0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF, + 0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF, + 0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF, + 0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF, + 0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF, + 0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF, + 0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF, + 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0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF, + 0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF, + 0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF, + 0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF, + 0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF, + 0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF, + 0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF, + 0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF, + 0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF, + 0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF, + 0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF, + 0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF, + 0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF, + 0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF, + 0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF, + 0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF, + 0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF, + 0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF, + 0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF, + 0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF, + 0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF, + 0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF, + 0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF, + 0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF, + 0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF, + 0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF, + 0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF, + 0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF, + 0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF, + 0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF, + 0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF, + 0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF, + 0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF, + 0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF, + 0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF, + 0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF, + 0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF, + 0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF, + 0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF, + 0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF, + 0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF, + 0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF, + 0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF, + 0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF, + 0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF, + 0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF, + 0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF, + 0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF, + 0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF, + 0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF, + 0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF, + 0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF, + 0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF, + 0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF, + 0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF, + 0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF, + 0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF, + 0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF, + 0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF, + 0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF, + 0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF, + 0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF, + 0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF, + 0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF, + 0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF, + 0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF, + 0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF, + 0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF, + 0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF, + 0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF, + 0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF, + 0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF, + 0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF, + 0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF, + 0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF, + 0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF, + 0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF, + 0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF, + 0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF, + 0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF, + 0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF, + 0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF, + 0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF, + 0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF, + 0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF, + 0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF, + 0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF, + 0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF, + 0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF, + 0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF, + 0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF, + 0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF, + 0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF, + 0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF, + 0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF, + 0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF, + 0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF, + 0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF, + 0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF, + 0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF, + 0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF, + 0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF, + 0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF, + 0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF, + 0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF, + 0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF, + 0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF, + 0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF, + 0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF, + 0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF, + 0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF, + 0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF, + 0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF, + 0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF, + 0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF, + 0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF, + 0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF, + 0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF, + 0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF, + 0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF, + 0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF, + 0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF, + 0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF, + 0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF, + 0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF, + 0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF, + 0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF, + 0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF, + 0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF, + 0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF, + 0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF, + 0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF, + 0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF, + 0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF, + 0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF, + 0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF, + 0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF, + 0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF, + 0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF, + 0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF, + 0x4C,0x00,0x9F,0xE5,0x01,0x10,0xA0,0xE3,0x00,0x10,0x80,0xE5,0x00,0x00,0x90,0xE5, + 0x40,0x00,0x9F,0xE5,0x35,0x10,0x01,0xE3,0xB0,0x10,0xC0,0xE1,0xB0,0x00,0xD0,0xE1, + 0x10,0x0F,0x11,0xEE,0x02,0x0A,0xC0,0xE3,0x01,0x0A,0xC0,0xE3,0x04,0x00,0xC0,0xE3, + 0x01,0x00,0xC0,0xE3,0x10,0x0F,0x01,0xEE,0x25,0x00,0x00,0xEB,0x18,0xD0,0x9F,0xE5, + 0x13,0x00,0x00,0xEB,0x0C,0x00,0x00,0xEB,0x0D,0x00,0x00,0xEB,0x0E,0x00,0x00,0xEB, + 0xFE,0xFF,0xFF,0xEA,0x80,0xFF,0xFF,0x3F,0x10,0x00,0xFE,0xFC,0x00,0x00,0x03,0x20, + 0xFE,0xFF,0xFF,0xEA,0xFE,0xFF,0xFF,0xEA,0xFE,0xFF,0xFF,0xEA,0xFE,0xFF,0xFF,0xEA, + 0xFE,0xFF,0xFF,0xEA,0xFE,0xFF,0xFF,0xEA,0xFE,0xFF,0xFF,0xEA,0x04,0xF0,0x1F,0xE5, + 0x40,0x00,0x02,0x20,0x04,0xF0,0x1F,0xE5,0x00,0x00,0x02,0x20,0x04,0xF0,0x1F,0xE5, + 0x58,0x1D,0x02,0x20,0x2C,0x30,0x9F,0xE5,0x00,0x20,0xA0,0xE3,0x28,0x10,0x9F,0xE5, + 0x28,0x00,0x9F,0xE5,0x10,0x40,0x2D,0xE9,0x23,0x31,0xA0,0xE1,0x02,0x00,0x00,0xEA, + 0x04,0x40,0x91,0xE4,0x01,0x20,0x82,0xE2,0x04,0x40,0x80,0xE4,0x03,0x00,0x52,0xE1, + 0xFA,0xFF,0xFF,0x3A,0x10,0x80,0xBD,0xE8,0x93,0x01,0x00,0x00,0x00,0x02,0x00,0x18, + 0x00,0x00,0x02,0x20,0x04,0x00,0x9F,0xE5,0x10,0x0F,0x0C,0xEE,0x1E,0xFF,0x2F,0xE1, + 0x00,0x00,0x00,0x18,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF, +}; +#if defined (__CC_ARM) +#pragma arm section +#endif + diff --git a/targets/TARGET_RENESAS/TARGET_RZ_A1XX/TARGET_GR_LYCHEE/device/mmu_RZ_A1LU.c b/targets/TARGET_RENESAS/TARGET_RZ_A1XX/TARGET_GR_LYCHEE/device/mmu_RZ_A1LU.c new file mode 100644 index 0000000..ffa9337 --- /dev/null +++ b/targets/TARGET_RENESAS/TARGET_RZ_A1XX/TARGET_GR_LYCHEE/device/mmu_RZ_A1LU.c @@ -0,0 +1,280 @@ +/**************************************************************************//** + * @file mmu_RZ_A1LU.c + * @brief MMU Configuration for RZ_A1LU Device Series + * @version V1.00 + * @date 10 Mar 2017 + * + * @note + * + ******************************************************************************/ +/* + * Copyright (c) 2009-2017 ARM Limited. All rights reserved. + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the License); you may + * not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an AS IS BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ + +/* Memory map description from: Renesas RZ_A1H_05E_121130.pdf + + Memory Type +0xffffffff |--------------------------| ------------ + | Peripherals | Device +0xfcf00000 |--------------------------| ------------ + | Page Fault | Fault +0xe8300000 |--------------------------| ------------ + | Peripherals | Device +0xe8000000 |--------------------------| ------------ + | Page Fault | Fault +0x60A00000 |--------------------------| ------------ + | On Chip RAM (10M) Mirror | Fault +0x60000000 |--------------------------| ------------ + | SPI multi I/O 64MB | Fault +0x5c000000 |--------------------------| ------------ + | SPI multi I/O 64MB | Fault +0x58000000 |--------------------------| ------------ + | CS5 Mirror | Fault +0x54000000 |--------------------------| ------------ + | CS4 Mirror | Fault +0x50000000 |--------------------------| ------------ + | CS3 Mirror | Fault +0x4c000000 |--------------------------| ------------ + | CS2 Mirror | Fault +0x48000000 |--------------------------| ------------ + | CS1 Mirror | Fault +0x44000000 |--------------------------| ------------ + | CS0 Mirror | Fault +0x40000000 |--------------------------| ------------ + | BSC | RW +0x3ff00000 |--------------------------| ------------ + | SPI_MIO_BASE | RW +0x3fe00000 |--------------------------| ------------ + | Page Fault | Fault +0x20A00000 |--------------------------| ------------ + | On Chip RAM (10M) | RW +0x20000000 |--------------------------| ------------ + | SPI multi I/O 64MB | RO +0x1c000000 |--------------------------| ------------ + | SPI multi I/O 64MB | RO +0x18000000 |--------------------------| ------------ + | CS5 User Area 64MB | RW +0x14000000 |--------------------------| ------------ + | CS4 User Area 64MB | RW +0x10000000 |--------------------------| ------------ + | CS3 SDRAM 64MB | RW +0x0c000000 |--------------------------| ------------ + | CS2 SDRAM 64MB | RW +0x08000000 |--------------------------| ------------ + | CS1 NOR Flash 64MB | RO +0x04000000 |--------------------------| ------------ + | CS0 NOR Flash 64MB | RO +0x00000000 |--------------------------| ------------ +*/ + +// L1 Cache info and restrictions about architecture of the caches (CCSIR register): +// Write-Through support *not* available +// Write-Back support available. +// Read allocation support available. +// Write allocation support available. + +//Note: You should use the Shareable attribute carefully. +//For cores without coherency logic (such as SCU) marking a region as shareable forces the processor to not cache that region regardless of the inner cache settings. +//Cortex-A versions of RTX use LDREX/STREX instructions relying on Local monitors. Local monitors will be used only when the region gets cached, regions that are not cached will use the Global Monitor. +//Some Cortex-A implementations do not include Global Monitors, so wrongly setting the attribute Shareable may cause STREX to fail. + +//Recall: When the Shareable attribute is applied to a memory region that is not Write-Back, Normal memory, data held in this region is treated as Non-cacheable. +//When SMP bit = 0, Inner WB/WA Cacheable Shareable attributes are treated as Non-cacheable. +//When SMP bit = 1, Inner WB/WA Cacheable Shareable attributes are treated as Cacheable. + + +//Following MMU configuration is expected +//SCTLR.AFE == 1 (Simplified access permissions model - AP[2:1] define access permissions, AP[0] is an access flag) +//SCTLR.TRE == 0 (TEX remap disabled, so memory type and attributes are described directly by bits in the descriptor) +//Domain 0 is always the Client domain +//Descriptors should place all memory in domain 0 +//There are no restrictions by privilege level (PL0 can access all memory) + + +#include "RZ_A1LU.h" + +//Import symbols from linker +extern uint32_t Image$$VECTORS$$Base; +extern uint32_t Image$$RO_DATA$$Base; +extern uint32_t Image$$RW_DATA$$Base; +extern uint32_t Image$$RW_IRAM1$$Base; +#if !defined ( __ICCARM__ ) +extern uint32_t Image$$TTB$$ZI$$Base; +#endif + +#if defined( __CC_ARM ) +#elif defined( __ICCARM__ ) +#else +extern uint32_t Image$$RW_DATA_NC$$Base; +extern uint32_t Image$$ZI_DATA_NC$$Base; +#endif + +extern uint32_t Image$$VECTORS$$Limit; +extern uint32_t Image$$RO_DATA$$Limit; +extern uint32_t Image$$RW_DATA$$Limit; +extern uint32_t Image$$RW_IRAM1$$Limit; +#if defined( __CC_ARM ) +#else +extern uint32_t Image$$RW_DATA_NC$$Limit; +extern uint32_t Image$$ZI_DATA_NC$$Limit; +#endif + +#if defined( __ICCARM__ ) +#define VECTORS_SIZE (((uint32_t)Image$$VECTORS$$Limit >> 20) - ((uint32_t)Image$$VECTORS$$Base >> 20) + 1) +#define RO_DATA_SIZE (((uint32_t)Image$$RO_DATA$$Limit >> 20) - ((uint32_t)Image$$RO_DATA$$Base >> 20) + 1) +#define RW_DATA_SIZE (((uint32_t)Image$$RW_DATA$$Limit >> 20) - ((uint32_t)Image$$RW_DATA$$Base >> 20) + 1) +#define RW_IRAM1_SIZE (((uint32_t)Image$$RW_IRAM1$$Limit >> 20) - ((uint32_t)Image$$RW_IRAM1$$Base >> 20) + 1) +#else +#define VECTORS_SIZE (((uint32_t)&Image$$VECTORS$$Limit >> 20) - ((uint32_t)&Image$$VECTORS$$Base >> 20) + 1) +#define RO_DATA_SIZE (((uint32_t)&Image$$RO_DATA$$Limit >> 20) - ((uint32_t)&Image$$RO_DATA$$Base >> 20) + 1) +#define RW_DATA_SIZE (((uint32_t)&Image$$RW_DATA$$Limit >> 20) - ((uint32_t)&Image$$RW_DATA$$Base >> 20) + 1) +#define RW_IRAM1_SIZE (((uint32_t)&Image$$RW_IRAM1$$Limit >> 20) - ((uint32_t)&Image$$RW_IRAM1$$Base >> 20) + 1) +#endif + +#if defined( __CC_ARM ) +#else +#define RW_DATA_NC_SIZE (((uint32_t)&Image$$RW_DATA_NC$$Limit >> 20) - ((uint32_t)&Image$$RW_DATA_NC$$Base >> 20) + 1) +#define ZI_DATA_NC_SIZE (((uint32_t)&Image$$ZI_DATA_NC$$Limit >> 20) - ((uint32_t)&Image$$ZI_DATA_NC$$Base >> 20) + 1) +#endif + +static uint32_t Sect_Normal; //outer & inner wb/wa, non-shareable, executable, rw, domain 0, base addr 0 +static uint32_t Sect_Normal_NC; //non-shareable, non-executable, rw, domain 0, base addr 0 +static uint32_t Sect_Normal_Cod; //outer & inner wb/wa, non-shareable, executable, ro, domain 0, base addr 0 +static uint32_t Sect_Normal_RO; //as Sect_Normal_Cod, but not executable +static uint32_t Sect_Normal_RW; //as Sect_Normal_Cod, but writeable and not executable +static uint32_t Sect_Device_RO; //device, non-shareable, non-executable, ro, domain 0, base addr 0 +static uint32_t Sect_Device_RW; //as Sect_Device_RO, but writeable + +/* Define global descriptors */ +static uint32_t Page_L1_4k = 0x0; //generic +static uint32_t Page_L1_64k = 0x0; //generic +static uint32_t Page_4k_Device_RW; //Shared device, not executable, rw, domain 0 +static uint32_t Page_64k_Device_RW; //Shared device, not executable, rw, domain 0 + +#if defined ( __ICCARM__ ) +__no_init uint32_t Image$$TTB$$ZI$$Base @ ".retram"; +uint32_t Image$$VECTORS$$Base; +uint32_t Image$$RO_DATA$$Base; +uint32_t Image$$RW_DATA$$Base; +uint32_t Image$$RW_IRAM1$$Base; + +uint32_t Image$$VECTORS$$Limit; +uint32_t Image$$RO_DATA$$Limit; +uint32_t Image$$RW_DATA$$Limit; +uint32_t Image$$RW_IRAM1$$Limit; +#endif + +void MMU_CreateTranslationTable(void) +{ + mmu_region_attributes_Type region; +#if defined ( __ICCARM__ ) +#pragma section=".intvec" +#pragma section=".rodata" +#pragma section=".rwdata" +#pragma section=".bss" + + Image$$VECTORS$$Base = (uint32_t) __section_begin(".intvec"); + Image$$VECTORS$$Limit= ((uint32_t)__section_begin(".intvec")+(uint32_t)__section_size(".intvec")); + Image$$RO_DATA$$Base = (uint32_t) __section_begin(".rodata"); + Image$$RO_DATA$$Limit= ((uint32_t)__section_begin(".rodata")+(uint32_t)__section_size(".rodata")); + Image$$RW_DATA$$Base = (uint32_t) __section_begin(".rwdata"); + Image$$RW_DATA$$Limit= ((uint32_t)__section_begin(".rwdata")+(uint32_t)__section_size(".rwdata")); + Image$$RW_IRAM1$$Base = (uint32_t) __section_begin(".bss"); + Image$$RW_IRAM1$$Limit= ((uint32_t)__section_begin(".bss")+(uint32_t)__section_size(".bss")); +#endif + /* + * Generate descriptors. Refer to core_ca.h to get information about attributes + * + */ + //Create descriptors for Vectors, RO, RW, ZI sections + section_normal(Sect_Normal, region); + section_normal_cod(Sect_Normal_Cod, region); + section_normal_ro(Sect_Normal_RO, region); + section_normal_rw(Sect_Normal_RW, region); + //Create descriptors for peripherals + section_device_ro(Sect_Device_RO, region); + section_device_rw(Sect_Device_RW, region); + section_normal_nc(Sect_Normal_NC, region); + //Create descriptors for 64k pages + page64k_device_rw(Page_L1_64k, Page_64k_Device_RW, region); + //Create descriptors for 4k pages + page4k_device_rw(Page_L1_4k, Page_4k_Device_RW, region); + + /* + * Define MMU flat-map regions and attributes + * + */ + + //Create 4GB of faulting entries + MMU_TTSection (&Image$$TTB$$ZI$$Base, 0, 4096, DESCRIPTOR_FAULT); + + // R7S721030 memory map. + MMU_TTSection (&Image$$TTB$$ZI$$Base, RZ_A1_NORFLASH_BASE0 , 64, Sect_Normal_RO); + MMU_TTSection (&Image$$TTB$$ZI$$Base, RZ_A1_NORFLASH_BASE1 , 64, Sect_Normal_RO); + MMU_TTSection (&Image$$TTB$$ZI$$Base, RZ_A1_SDRAM_BASE0 , 64, Sect_Normal_RW); + MMU_TTSection (&Image$$TTB$$ZI$$Base, RZ_A1_SDRAM_BASE1 , 64, Sect_Normal_RW); + MMU_TTSection (&Image$$TTB$$ZI$$Base, RZ_A1_USER_AREA0 , 64, Sect_Normal_RW); + MMU_TTSection (&Image$$TTB$$ZI$$Base, RZ_A1_USER_AREA1 , 64, Sect_Normal_RW); + MMU_TTSection (&Image$$TTB$$ZI$$Base, RZ_A1_SPI_IO0 , 64, Sect_Normal_RO); + MMU_TTSection (&Image$$TTB$$ZI$$Base, RZ_A1_ONCHIP_SRAM_BASE , 3, Sect_Normal_RW); + MMU_TTSection (&Image$$TTB$$ZI$$Base, RZ_A1_SPI_MIO_BASE , 1, Sect_Device_RW); + MMU_TTSection (&Image$$TTB$$ZI$$Base, RZ_A1_BSC_BASE , 1, Sect_Device_RW); + MMU_TTSection (&Image$$TTB$$ZI$$Base, RZ_A1_PERIPH_BASE0 , 3, Sect_Device_RW); + MMU_TTSection (&Image$$TTB$$ZI$$Base, RZ_A1_PERIPH_BASE1 , 49, Sect_Device_RW); + +#if defined( __ICCARM__ ) + //Define Image + MMU_TTSection (&Image$$TTB$$ZI$$Base, (uint32_t)Image$$RO_DATA$$Base , RO_DATA_SIZE , Sect_Normal_Cod); + MMU_TTSection (&Image$$TTB$$ZI$$Base, (uint32_t)Image$$VECTORS$$Base , VECTORS_SIZE , Sect_Normal_Cod); + MMU_TTSection (&Image$$TTB$$ZI$$Base, (uint32_t)Image$$RW_DATA$$Base , RW_DATA_SIZE , Sect_Normal_RW); + MMU_TTSection (&Image$$TTB$$ZI$$Base, (uint32_t)Image$$RW_IRAM1$$Base, RW_IRAM1_SIZE, Sect_Normal_RW); +#else + //Define Image + MMU_TTSection (&Image$$TTB$$ZI$$Base, (uint32_t)&Image$$RO_DATA$$Base , RO_DATA_SIZE , Sect_Normal_Cod); + MMU_TTSection (&Image$$TTB$$ZI$$Base, (uint32_t)&Image$$VECTORS$$Base , VECTORS_SIZE , Sect_Normal_Cod); + MMU_TTSection (&Image$$TTB$$ZI$$Base, (uint32_t)&Image$$RW_DATA$$Base , RW_DATA_SIZE , Sect_Normal_RW); + MMU_TTSection (&Image$$TTB$$ZI$$Base, (uint32_t)&Image$$RW_IRAM1$$Base, RW_IRAM1_SIZE, Sect_Normal_RW); +#endif + +#if defined( __CC_ARM ) + MMU_TTSection (&Image$$TTB$$ZI$$Base, RZ_A1_ONCHIP_SRAM_NC_BASE , 10, Sect_Normal_NC); +#elif defined ( __ICCARM__ ) + MMU_TTSection (&Image$$TTB$$ZI$$Base, RZ_A1_ONCHIP_SRAM_NC_BASE , 10, Sect_Normal_NC); + +#else + MMU_TTSection (&Image$$TTB$$ZI$$Base, (uint32_t)&Image$$RW_DATA_NC$$Base, RW_DATA_NC_SIZE, Sect_Normal_NC); + MMU_TTSection (&Image$$TTB$$ZI$$Base, (uint32_t)&Image$$ZI_DATA_NC$$Base, ZI_DATA_NC_SIZE, Sect_Normal_NC); +#endif + + /* Set location of level 1 page table + ; 31:14 - Translation table base addr (31:14-TTBCR.N, TTBCR.N is 0 out of reset) + ; 13:7 - 0x0 + ; 6 - IRGN[0] 0x0 (Inner WB WA) + ; 5 - NOS 0x0 (Non-shared) + ; 4:3 - RGN 0x1 (Outer WB WA) + ; 2 - IMP 0x0 (Implementation Defined) + ; 1 - S 0x0 (Non-shared) + ; 0 - IRGN[1] 0x1 (Inner WB WA) */ + __set_TTBR0(((uint32_t)&Image$$TTB$$ZI$$Base) | 9); + __ISB(); + + /* Set up domain access control register + ; We set domain 0 to Client and all other domains to No Access. + ; All translation table entries specify domain 0 */ + __set_DACR(1); + __ISB(); +} diff --git a/targets/TARGET_RENESAS/TARGET_RZ_A1XX/TARGET_GR_LYCHEE/device/nvic_wrapper.c b/targets/TARGET_RENESAS/TARGET_RZ_A1XX/TARGET_GR_LYCHEE/device/nvic_wrapper.c new file mode 100644 index 0000000..11b3f7b --- /dev/null +++ b/targets/TARGET_RENESAS/TARGET_RZ_A1XX/TARGET_GR_LYCHEE/device/nvic_wrapper.c @@ -0,0 +1,228 @@ +/******************************************************************************* +* DISCLAIMER +* This software is supplied by Renesas Electronics Corporation and is only +* intended for use with Renesas products. No other uses are authorized. This +* software is owned by Renesas Electronics Corporation and is protected under +* all applicable laws, including copyright laws. +* THIS SOFTWARE IS PROVIDED "AS IS" AND RENESAS MAKES NO WARRANTIES REGARDING +* THIS SOFTWARE, WHETHER EXPRESS, IMPLIED OR STATUTORY, INCLUDING BUT NOT +* LIMITED TO WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE +* AND NON-INFRINGEMENT. ALL SUCH WARRANTIES ARE EXPRESSLY DISCLAIMED. +* TO THE MAXIMUM EXTENT PERMITTED NOT PROHIBITED BY LAW, NEITHER RENESAS +* ELECTRONICS CORPORATION NOR ANY OF ITS AFFILIATED COMPANIES SHALL BE LIABLE +* FOR ANY DIRECT, INDIRECT, SPECIAL, INCIDENTAL OR CONSEQUENTIAL DAMAGES FOR +* ANY REASON RELATED TO THIS SOFTWARE, EVEN IF RENESAS OR ITS AFFILIATES HAVE +* BEEN ADVISED OF THE POSSIBILITY OF SUCH DAMAGES. +* Renesas reserves the right, without notice, to make changes to this software +* and to discontinue the availability of this software. By using this software, +* you agree to the additional terms and conditions found by accessing the +* following link: +* http://www.renesas.com/disclaimer +* Copyright (C) 2012 - 2015 Renesas Electronics Corporation. All rights reserved. +*******************************************************************************/ +/**************************************************************************//** +* @file nvic_wrapper.c +* $Rev: $ +* $Date:: $ +* @brief Wrapper between NVIC(for Cortex-M) and GIC(for Cortex-A9) +******************************************************************************/ + +/****************************************************************************** +Includes , "Project Includes" +******************************************************************************/ +#include "MBRZA1LU.h" +#include "wdt_iodefine.h" +#include "nvic_wrapper.h" + +/****************************************************************************** +Typedef definitions +******************************************************************************/ + +/****************************************************************************** +Macro definitions +******************************************************************************/ +#define PRIO_BITS (7) /* Set binary point to 0 in gic.c */ +#define WDT_WTCNT_WRITE (0x5A00) +#define WDT_WTCSR_WRITE (0xA500) +#define WDT_WRCSR_WOVF_WRITE (0xA500) +#define WDT_WRCSR_RSTE_WRITE (0x5A00) + +/****************************************************************************** +Imported global variables and functions (from other files) +******************************************************************************/ + +/****************************************************************************** +Exported global variables and functions (to be accessed by other files) +******************************************************************************/ + +/****************************************************************************** +Private global variables and functions +******************************************************************************/ + + + +/* ########################## NVIC functions #################################### */ +void NVIC_SetPriorityGrouping(uint32_t PriorityGroup) +{ + GIC_SetBinaryPoint(PriorityGroup); +} + + +uint32_t NVIC_GetPriorityGrouping(void) +{ + return GIC_GetBinaryPoint(); +} + + +void NVIC_EnableIRQ(IRQn_Type IRQn) +{ + GIC_EnableIRQ(IRQn); +} + + +void NVIC_DisableIRQ(IRQn_Type IRQn) +{ + GIC_DisableIRQ(IRQn); +} + + +uint32_t NVIC_GetPendingIRQ(IRQn_Type IRQn) +{ + uint32_t pending; + + pending = GIC_GetIRQStatus(IRQn); + pending = (pending & 0x00000001); + + return pending; +} + + +void NVIC_SetPendingIRQ(IRQn_Type IRQn) +{ + GIC_SetPendingIRQ(IRQn); +} + + +void NVIC_ClearPendingIRQ(IRQn_Type IRQn) +{ + GIC_ClearPendingIRQ(IRQn); +} + + +uint32_t NVIC_GetActive(IRQn_Type IRQn) +{ + uint32_t active; + + active = GIC_GetIRQStatus(IRQn); + active = ((active >> 1) & 0x00000001); + + return active; +} + + +void NVIC_SetPriority(IRQn_Type IRQn, uint32_t priority) +{ + GIC_SetPriority(IRQn, (priority << 3)); +} + + +uint32_t NVIC_GetPriority(IRQn_Type IRQn) +{ + uint32_t priority_field; + + priority_field = GIC_GetPriority(IRQn); + priority_field = (priority_field >> 3); + return priority_field; +} + + +uint32_t NVIC_EncodePriority (uint32_t PriorityGroup, uint32_t PreemptPriority, uint32_t SubPriority) +{ + uint32_t PriorityGroupTmp = (PriorityGroup & 0x07); /* only values 0..7 are used */ + uint32_t PreemptPriorityBits; + uint32_t SubPriorityBits; + + PreemptPriorityBits = ((7 - PriorityGroupTmp) > PRIO_BITS) ? PRIO_BITS : 7 - PriorityGroupTmp; + SubPriorityBits = ((PriorityGroupTmp + PRIO_BITS) < 7) ? 0 : PriorityGroupTmp - 7 + PRIO_BITS; + + return ( + ((PreemptPriority & ((1 << (PreemptPriorityBits)) - 1)) << SubPriorityBits) | + ((SubPriority & ((1 << (SubPriorityBits )) - 1))) + ); +} + + +void NVIC_DecodePriority (uint32_t Priority, uint32_t PriorityGroup, uint32_t* pPreemptPriority, uint32_t* pSubPriority) +{ + uint32_t PriorityGroupTmp = (PriorityGroup & 0x07); /* only values 0..7 are used */ + uint32_t PreemptPriorityBits; + uint32_t SubPriorityBits; + + PreemptPriorityBits = ((7 - PriorityGroupTmp) > PRIO_BITS) ? PRIO_BITS : 7 - PriorityGroupTmp; + SubPriorityBits = ((PriorityGroupTmp + PRIO_BITS) < 7) ? 0 : PriorityGroupTmp - 7 + PRIO_BITS; + + *pPreemptPriority = (Priority >> SubPriorityBits) & ((1 << (PreemptPriorityBits)) - 1); + *pSubPriority = (Priority ) & ((1 << (SubPriorityBits )) - 1); +} + +void NVIC_SystemReset(void) +{ + uint16_t reg; + uint8_t dummy_read; + /* Use Watch Dog Timer to system reset */ + + /* Set WT/IT bit of WTCSR to 1 = Watch Dog */ + /* CLK = 000, 1xP0phi(=33.3333MHz) = 7.7us */ + reg = (WDT_WTCSR_WRITE | 0x0058); + WDTWTCSR = reg; + + /* Clear Count reg */ + reg = (WDT_WTCNT_WRITE | 0x0000); + WDTWTCNT = reg; + + /* Clear WOVF flag */ + dummy_read = WDTWRCSR; + reg = (WDT_WRCSR_WOVF_WRITE | (dummy_read & 0x0000)); + WDTWRCSR = reg; + /* Enable Internal Reset */ + reg = (WDT_WRCSR_RSTE_WRITE | 0x005F); + WDTWRCSR = reg; + + /* Watch Dog start */ + reg = (WDT_WTCSR_WRITE | 0x0078); + WDTWTCSR = reg; + + while(1); /* wait Internal Reset */ +} + +/* ################################## SysTick function ############################################ */ +uint32_t SysTick_Config(uint32_t ticks) +{ + /* Not support this function */ + /* Use mbed Ticker */ + return (1); /* impossible */ +} + + +/* ##################################### Debug In/Output function ########################################### */ +uint32_t ITM_SendChar (uint32_t ch) +{ + /* Not support this function */ + /* Use mbed Serial */ + return (ch); +} + + +int32_t ITM_ReceiveChar (void) { + /* Not support this function */ + /* Use mbed Serial */ + return (-1); /* no character available */ +} + + +int32_t ITM_CheckChar (void) { + /* Not support this function */ + /* Use mbed Serial */ + return (0); /* no character available */ +} + diff --git a/targets/TARGET_RENESAS/TARGET_RZ_A1XX/TARGET_GR_LYCHEE/device/os_tick_ostm.c b/targets/TARGET_RENESAS/TARGET_RZ_A1XX/TARGET_GR_LYCHEE/device/os_tick_ostm.c new file mode 100644 index 0000000..b2d1991 --- /dev/null +++ b/targets/TARGET_RENESAS/TARGET_RZ_A1XX/TARGET_GR_LYCHEE/device/os_tick_ostm.c @@ -0,0 +1,192 @@ +/**************************************************************************//** + * @file os_tick_ostm.c + * @brief CMSIS OS Tick implementation for OS Timer + * @version V1.0.1 + * @date 19. September 2017 + ******************************************************************************/ +/* + * Copyright (c) 2017-2017 ARM Limited. All rights reserved. + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the License); you may + * not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an AS IS BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ + +#ifdef MBED_CONF_RTOS_PRESENT + +#include "os_tick.h" +#include "irq_ctrl.h" + +#include + +#include + + +// Define OS TImer interrupt priority +#ifndef OSTM_IRQ_PRIORITY +#define OSTM_IRQ_PRIORITY 0xFFU +#endif + +// Define OS Timer channel and interrupt number +#define OSTM (OSTM0) +#define OSTM_IRQn ((IRQn_ID_t)OSTMI0TINT_IRQn) + + +static uint32_t OSTM_Clock; // Timer tick frequency +static uint8_t OSTM_PendIRQ; // Timer interrupt pending flag + + +// Setup OS Tick. +int32_t OS_Tick_Setup (uint32_t freq, IRQHandler_t handler) { + uint32_t clock; + uint32_t prio; + uint32_t bits; + + if (freq == 0U) { + return (-1); + } + + OSTM_PendIRQ = 0U; + + // Get CPG.FRQCR[IFC] bits + clock = (CPG.FRQCR >> 8) & 0x03; + + // Determine Divider 2 output clock by using SystemCoreClock + if (clock == 0x03U) { + clock = (SystemCoreClock * 3U); + } + else if (clock == 0x01U) { + clock = (SystemCoreClock * 3U)/2U; + } + else { + clock = SystemCoreClock; + } + + // Determine tick frequency + clock = clock / freq; + + // Save frequency for later + OSTM_Clock = clock; + + // Enable OSTM clock + CPG.STBCR5 &= ~(CPG_STBCR5_BIT_MSTP51); + + // Stop the OSTM counter + OSTM.OSTMnTT = 0x01U; + + // Set interval timer mode and disable interrupts when counting starts + OSTM.OSTMnCTL = 0x00U; + + // Set compare value + OSTM.OSTMnCMP = clock - 1U; + + // Disable corresponding IRQ + IRQ_Disable (OSTM_IRQn); + IRQ_ClearPending(OSTM_IRQn); + + // Determine number of implemented priority bits + IRQ_SetPriority (OSTM_IRQn, 0xFFU); + + prio = IRQ_GetPriority (OSTM_IRQn); + + // At least bits [7:4] must be implemented + if ((prio & 0xF0U) == 0U) { + return (-1); + } + + for (bits = 0; bits < 4; bits++) { + if ((prio & 0x01) != 0) { + break; + } + prio >>= 1; + } + + // Adjust configured priority to the number of implemented priority bits + prio = (OSTM_IRQ_PRIORITY << bits) & 0xFFUL; + + // Set OSTM interrupt priority + IRQ_SetPriority(OSTM_IRQn, prio-1U); + + // Set edge-triggered, non-secure, single CPU targeted IRQ + IRQ_SetMode (OSTM_IRQn, IRQ_MODE_TRIG_EDGE); + + // Register tick interrupt handler function + IRQ_SetHandler(OSTM_IRQn, (IRQHandler_t)handler); + + // Enable corresponding IRQ + IRQ_Enable (OSTM_IRQn); + + return (0); +} + +/// Enable OS Tick. +int32_t OS_Tick_Enable (void) { + + if (OSTM_PendIRQ != 0U) { + OSTM_PendIRQ = 0U; + IRQ_SetPending (OSTM_IRQn); + } + + // Start the OSTM counter + OSTM.OSTMnTS = 0x01U; + + return (0); +} + +/// Disable OS Tick. +int32_t OS_Tick_Disable (void) { + + // Stop the OSTM counter + OSTM.OSTMnTT = 0x01U; + + if (IRQ_GetPending(OSTM_IRQn) != 0) { + IRQ_ClearPending (OSTM_IRQn); + OSTM_PendIRQ = 1U; + } + + return (0); +} + +// Acknowledge OS Tick IRQ. +int32_t OS_Tick_AcknowledgeIRQ (void) { + return (IRQ_ClearPending (OSTM_IRQn)); +} + +// Get OS Tick IRQ number. +int32_t OS_Tick_GetIRQn (void) { + return (OSTM_IRQn); +} + +// Get OS Tick clock. +uint32_t OS_Tick_GetClock (void) { + return (OSTM_Clock); +} + +// Get OS Tick interval. +uint32_t OS_Tick_GetInterval (void) { + return (OSTM.OSTMnCMP + 1U); +} + +// Get OS Tick count value. +uint32_t OS_Tick_GetCount (void) { + uint32_t cmp = OSTM.OSTMnCMP; + return (cmp - OSTM.OSTMnCNT); +} + +// Get OS Tick overflow status. +uint32_t OS_Tick_GetOverflow (void) { + return (IRQ_GetPending(OSTM_IRQn)); +} + +#endif + diff --git a/targets/TARGET_RENESAS/TARGET_RZ_A1XX/TARGET_GR_LYCHEE/device/system_RZ_A1LU.c b/targets/TARGET_RENESAS/TARGET_RZ_A1XX/TARGET_GR_LYCHEE/device/system_RZ_A1LU.c new file mode 100644 index 0000000..71a28a1 --- /dev/null +++ b/targets/TARGET_RENESAS/TARGET_RZ_A1XX/TARGET_GR_LYCHEE/device/system_RZ_A1LU.c @@ -0,0 +1,157 @@ +/****************************************************************************** + * @file system_RZ_A1LU.c + * @brief CMSIS Device System Source File for ARM Cortex-A9 Device Series + * @version V1.00 + * @date 10 Mar 2017 + * + * @note + * + ******************************************************************************/ +/* + * Copyright (c) 2013-2014 Renesas Electronics Corporation. All rights reserved. + * Copyright (c) 2009-2017 ARM Limited. All rights reserved. + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the License); you may + * not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an AS IS BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ + +#include +#include "RZ_A1_Init.h" +#include "irq_ctrl.h" + +#define CS2_SDRAM_MODE_16BIT_CAS2_BR_BW (*(volatile uint16_t*)0x3FFFD040) +#define CS3_SDRAM_MODE_16BIT_CAS2_BR_BW (*(volatile uint16_t*)0x3FFFE040) +#define GPIO_PORT0_BOOTMODE_BITMASK (0x000fu) + +/* + Port 0 (P0) MD pin assignment + P0_0: MD_BOOT0 + P0_1: MD_BOOT1 + P0_2: MD_CLK + P0_3: MD_CLKS + */ + +/*---------------------------------------------------------------------------- + System Core Clock Variable + *----------------------------------------------------------------------------*/ +uint32_t SystemCoreClock = CM1_RENESAS_RZ_A1_P0_CLK; + +/*---------------------------------------------------------------------------- + System Core Clock update function + *----------------------------------------------------------------------------*/ +void SystemCoreClockUpdate (void) +{ + uint32_t freq; + uint16_t mode; + uint16_t ifc; + + mode = (GPIO.PPR0 >> 2U) & 0x01U; + + if (mode == 0) { + /* Clock Mode 0 */ + /* CLKIN is between 10MHz and 13.33MHz */ + /* Divider 1 uses 1/1 ratio, PLL x30 is ON */ + freq = CM0_RENESAS_RZ_A1_CLKIN * 30U; + } else { + /* Clock Mode 1 */ + /* CLKIN is 48MHz */ + /* Divider 1 uses 1/4 ratio, PLL x32 is ON */ + freq = (CM1_RENESAS_RZ_A1_CLKIN * 32U) / 4U; + } + + /* Get CPG.FRQCR[IFC] bits */ + ifc = (CPG.FRQCR >> 8U) & 0x03U; + + /* Determine Divider 2 output clock */ + if (ifc == 0x03U) { + /* Division ratio is 1/3 */ + freq = (freq / 3U); + } + else { + if (ifc == 0x01U) { + /* Division ratio is 2/3 */ + freq = (freq * 2U) / 3U; + } + } + + SystemCoreClock = freq; +} + +/*---------------------------------------------------------------------------- + IRQ Handler Register/Unregister + *----------------------------------------------------------------------------*/ +uint32_t InterruptHandlerRegister (IRQn_Type irq, IRQHandler handler) +{ + return IRQ_SetHandler(irq, handler); +} + +uint32_t InterruptHandlerUnregister (IRQn_Type irq) +{ + return IRQ_SetHandler(irq, (IRQHandler_t)NULL); +} + +/*---------------------------------------------------------------------------- + System Initialization + *----------------------------------------------------------------------------*/ +void SystemInit (void) +{ +/* do not use global variables because this function is called before + reaching pre-main. RW section may be overwritten afterwards. */ + + // Enable SRAM write access + CPG.SYSCR3 = 0x0F; + + RZ_A1_InitClock(); + RZ_A1_InitBus(); + + // Invalidate entire Unified TLB + __set_TLBIALL(0); + + // Invalidate entire branch predictor array + __set_BPIALL(0); + __DSB(); + __ISB(); + + // Invalidate instruction cache and flush branch target cache + __set_ICIALLU(0); + __DSB(); + __ISB(); + + // Invalidate data cache + L1C_InvalidateDCacheAll(); + + // Create Translation Table + MMU_CreateTranslationTable(); + + // Enable MMU + MMU_Enable(); + + // Enable Caches + L1C_EnableCaches(); + L1C_EnableBTAC(); + +#if (__L2C_PRESENT == 1) + L2C_InvAllByWay(); + // Enable L2C + L2C_Enable(); +#endif + +#if ((__FPU_PRESENT == 1) && (__FPU_USED == 1)) + // Enable FPU + __FPU_Enable(); +#endif + + // IRQ Initialize + IRQ_Initialize(); +} diff --git a/targets/TARGET_RENESAS/TARGET_RZ_A1XX/TARGET_GR_LYCHEE/device/system_RZ_A1LU.h b/targets/TARGET_RENESAS/TARGET_RZ_A1XX/TARGET_GR_LYCHEE/device/system_RZ_A1LU.h new file mode 100644 index 0000000..9f8cc7d --- /dev/null +++ b/targets/TARGET_RENESAS/TARGET_RZ_A1XX/TARGET_GR_LYCHEE/device/system_RZ_A1LU.h @@ -0,0 +1,81 @@ +/****************************************************************************** + * @file system_RZ_A1LU.h + * @brief CMSIS Device System Header File for ARM Cortex-A Device Series + * @version V1.00 + * @date 10 Mar 2017 + * + * @note + * + ******************************************************************************/ +/* + * Copyright (c) 2009-2017 ARM Limited. All rights reserved. + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the License); you may + * not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an AS IS BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ + +#ifndef __SYSTEM_RZ_A1LU_H +#define __SYSTEM_RZ_A1LU_H + +#ifdef __cplusplus +extern "C" { +#endif + +#include + +extern uint32_t SystemCoreClock; /*!< System Clock Frequency (Core Clock) */ + +typedef void(*IRQHandler)(); /*!< Type Definition for Interrupt Handlers */ + +/** + \brief Setup the microcontroller system. + + Initialize the System and update the SystemCoreClock variable. + */ +extern void SystemInit (void); + + +/** + \brief Update SystemCoreClock variable. + + Updates the SystemCoreClock with current core Clock retrieved from cpu registers. + */ +extern void SystemCoreClockUpdate (void); + +/** + \brief Interrupt Handler Register. + + Registers an Interrupt Handler into the IRQ Table. + */ +extern uint32_t InterruptHandlerRegister(IRQn_Type, IRQHandler); + +/** + \brief Interrupt Handler Unregister. + + Unregisters an Interrupt Handler from the IRQ Table. + */ +extern uint32_t InterruptHandlerUnregister(IRQn_Type); + +/** + \brief Create Translation Table. + + Creates Memory Management Unit Translation Table. + */ +extern void MMU_CreateTranslationTable(void); + +#ifdef __cplusplus +} +#endif + +#endif /* __SYSTEM_RZ_A1LU_H */ diff --git a/targets/TARGET_RENESAS/TARGET_RZ_A1XX/TARGET_GR_LYCHEE/mbed_drv_cfg.h b/targets/TARGET_RENESAS/TARGET_RZ_A1XX/TARGET_GR_LYCHEE/mbed_drv_cfg.h new file mode 100644 index 0000000..05ad76f --- /dev/null +++ b/targets/TARGET_RENESAS/TARGET_RZ_A1XX/TARGET_GR_LYCHEE/mbed_drv_cfg.h @@ -0,0 +1,35 @@ +/* mbed Microcontroller Library + * Copyright (c) 2006-2017 ARM Limited + * + * Licensed under the Apache License, Version 2.0 (the "License"); + * you may not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, + * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ + +#ifndef MBED_DRV_CFG_H +#define MBED_DRV_CFG_H + +/* can_api.c */ +#define CAN_TEST_GLOBAL_CH 0 + +/* gpio_api.c */ +#define GPIO_GROUP_MAX 7 + +/* pwmout_api.c */ +#undef FUNC_MOTOR_CTL_PWM +#define FUMC_MTU2_PWM + +/* rtc_api.c */ +#define USE_RTCX1_CLK +//#define USE_EXTAL_CLK +//#define USE_RTCX3_CLK + +#endif