diff --git a/targets/TARGET_STM/TARGET_STM32WL/TARGET_STM32WL54xC/TOOLCHAIN_ARM/startup_stm32wl54xx.S b/targets/TARGET_STM/TARGET_STM32WL/TARGET_STM32WL54xC/TOOLCHAIN_ARM/startup_stm32wl54xx.S
new file mode 100644
index 0000000..8e5c4c7
--- /dev/null
+++ b/targets/TARGET_STM/TARGET_STM32WL/TARGET_STM32WL54xC/TOOLCHAIN_ARM/startup_stm32wl54xx.S
@@ -0,0 +1,320 @@
+;******************************************************************************
+;* File Name : startup_stm32wl54xx_cm4.s
+;* Author : MCD Application Team
+;* Description : STM32WL54xx devices vector table for MDK-ARM toolchain.
+;* This module performs:
+;* - Set the initial SP
+;* - Set the initial PC == Reset_Handler
+;* - Set the vector table entries with the exceptions ISR address
+;* - Branches to __main in the C library (which eventually
+;* calls main()).
+;* After Reset the CortexM4 processor is in Thread mode,
+;* priority is Privileged, and the Stack is set to Main.
+;* <<< Use Configuration Wizard in Context Menu >>>
+;******************************************************************************
+;* @attention
+;*
+;* Copyright (c) 2020 STMicroelectronics. All rights reserved.
+;*
+;* This software component is licensed by ST under Apache License, Version 2.0,
+;* the "License"; You may not use this file except in compliance with the
+;* License. You may obtain a copy of the License at:
+;* opensource.org/licenses/Apache-2.0
+;*
+;******************************************************************************
+
+ PRESERVE8
+ THUMB
+
+
+; Vector Table Mapped to Address 0 at Reset
+ AREA RESET, DATA, READONLY
+ EXPORT __Vectors
+ EXPORT __Vectors_End
+ EXPORT __Vectors_Size
+
+ IMPORT |Image$$ARM_LIB_STACK$$ZI$$Limit|
+__Vectors DCD |Image$$ARM_LIB_STACK$$ZI$$Limit| ; Top of Stack
+ DCD Reset_Handler ; Reset Handler
+ DCD NMI_Handler ; NMI Handler
+ DCD HardFault_Handler ; Hard Fault Handler
+ DCD MemManage_Handler ; MPU Fault Handler
+ DCD BusFault_Handler ; Bus Fault Handler
+ DCD UsageFault_Handler ; Usage Fault Handler
+ DCD 0 ; Reserved
+ DCD 0 ; Reserved
+ DCD 0 ; Reserved
+ DCD 0 ; Reserved
+ DCD SVC_Handler ; SVCall Handler
+ DCD DebugMon_Handler ; Debug Monitor Handler
+ DCD 0 ; Reserved
+ DCD PendSV_Handler ; PendSV Handler
+ DCD SysTick_Handler ; SysTick Handler
+
+ ; External Interrupts
+ DCD WWDG_IRQHandler ; Window WatchDog
+ DCD PVD_PVM_IRQHandler ; PVD and PVM detector
+ DCD TAMP_STAMP_LSECSS_SSRU_IRQHandler ; RTC Tamper, RTC TimeStamp, LSECSS and RTC SSR Underflow Interrupts
+ DCD RTC_WKUP_IRQHandler ; RTC Wakeup Interrupt
+ DCD FLASH_IRQHandler ; FLASH global Interrupt
+ DCD RCC_IRQHandler ; RCC Interrupt
+ DCD EXTI0_IRQHandler ; EXTI Line 0 Interrupt
+ DCD EXTI1_IRQHandler ; EXTI Line 1 Interrupt
+ DCD EXTI2_IRQHandler ; EXTI Line 2 Interrupt
+ DCD EXTI3_IRQHandler ; EXTI Line 3 Interrup
+ DCD EXTI4_IRQHandler ; EXTI Line 4 Interrupt
+ DCD DMA1_Channel1_IRQHandler ; DMA1 Channel 1 Interrupt
+ DCD DMA1_Channel2_IRQHandler ; DMA1 Channel 2 Interrupt
+ DCD DMA1_Channel3_IRQHandler ; DMA1 Channel 3 Interrupt
+ DCD DMA1_Channel4_IRQHandler ; DMA1 Channel 4 Interrupt
+ DCD DMA1_Channel5_IRQHandler ; DMA1 Channel 5 Interrupt
+ DCD DMA1_Channel6_IRQHandler ; DMA1 Channel 6 Interrupt
+ DCD DMA1_Channel7_IRQHandler ; DMA1 Channel 7 Interrupt
+ DCD ADC_IRQHandler ; ADC Interrupt
+ DCD DAC_IRQHandler ; DAC Interrupt
+ DCD C2SEV_PWR_C2H_IRQHandler ; CPU M0+ SEV and PWR CPU M0+ HOLD wakeup Interrupt
+ DCD COMP_IRQHandler ; COMP1 and COMP2 Interrupts
+ DCD EXTI9_5_IRQHandler ; EXTI Lines [9:5] Interrupt
+ DCD TIM1_BRK_IRQHandler ; TIM1 Break Interrupt
+ DCD TIM1_UP_IRQHandler ; TIM1 Update Interrupts
+ DCD TIM1_TRG_COM_IRQHandler ; TIM1 Trigger and Communication Interrupts
+ DCD TIM1_CC_IRQHandler ; TIM1 Capture Compare Interrupt
+ DCD TIM2_IRQHandler ; TIM2 Global Interrupt
+ DCD TIM16_IRQHandler ; TIM16 Global Interrupt
+ DCD TIM17_IRQHandler ; TIM17 Global Interrupt
+ DCD I2C1_EV_IRQHandler ; I2C1 Event Interrupt
+ DCD I2C1_ER_IRQHandler ; I2C1 Error Interrupt
+ DCD I2C2_EV_IRQHandler ; I2C2 Event Interrupt
+ DCD I2C2_ER_IRQHandler ; I2C2 Error Interrupt
+ DCD SPI1_IRQHandler ; SPI1 Interrupt
+ DCD SPI2_IRQHandler ; SPI2 Interrupt
+ DCD USART1_IRQHandler ; USART1 Interrupt
+ DCD USART2_IRQHandler ; USART2 Interrupt
+ DCD LPUART1_IRQHandler ; LPUART1 Interrupt
+ DCD LPTIM1_IRQHandler ; LPTIM1 Interrupt
+ DCD LPTIM2_IRQHandler ; LPTIM2 Interrupt
+ DCD EXTI15_10_IRQHandler ; EXTI Lines1[15:10 ]Interrupts
+ DCD RTC_Alarm_IRQHandler ; RTC Alarms (A and B) Interrupt
+ DCD LPTIM3_IRQHandler ; LPTIM3 Interrupt
+ DCD SUBGHZSPI_IRQHandler ; SUBGHZSPI Interrupt
+ DCD IPCC_C1_RX_IRQHandler ; IPCC CPU1 RX occupied interrupt
+ DCD IPCC_C1_TX_IRQHandler ; IPCC CPU1 RX free interrupt
+ DCD HSEM_IRQHandler ; HSEM0 Interrupt
+ DCD I2C3_EV_IRQHandler ; I2C3 Event Interrupt
+ DCD I2C3_ER_IRQHandler ; I2C3 Error Interrupt
+ DCD SUBGHZ_Radio_IRQHandler ; SUBGHZ Radio Interrupt
+ DCD AES_IRQHandler ; AES Interrupt
+ DCD RNG_IRQHandler ; RNG1 Interrupt
+ DCD PKA_IRQHandler ; PKA Interrupt
+ DCD DMA2_Channel1_IRQHandler ; DMA2 Channel 1 Interrupt
+ DCD DMA2_Channel2_IRQHandler ; DMA2 Channel 2 Interrupt
+ DCD DMA2_Channel3_IRQHandler ; DMA2 Channel 3 Interrupt
+ DCD DMA2_Channel4_IRQHandler ; DMA2 Channel 4 Interrupt
+ DCD DMA2_Channel5_IRQHandler ; DMA2 Channel 5 Interrupt
+ DCD DMA2_Channel6_IRQHandler ; DMA2 Channel 6 Interrupt
+ DCD DMA2_Channel7_IRQHandler ; DMA2 Channel 7 Interrupt
+ DCD DMAMUX1_OVR_IRQHandler ; DMAMUX overrun Interrupt
+
+__Vectors_End
+
+__Vectors_Size EQU __Vectors_End - __Vectors
+
+ AREA |.text|, CODE, READONLY
+
+; Reset handler
+Reset_Handler PROC
+ EXPORT Reset_Handler [WEAK]
+ IMPORT SystemInit
+ IMPORT __main
+
+ LDR R0, =SystemInit
+ BLX R0
+ LDR R0, =__main
+ BX R0
+ ENDP
+
+; Dummy Exception Handlers (infinite loops which can be modified)
+
+NMI_Handler PROC
+ EXPORT NMI_Handler [WEAK]
+ B .
+ ENDP
+HardFault_Handler\
+ PROC
+ EXPORT HardFault_Handler [WEAK]
+ B .
+ ENDP
+MemManage_Handler\
+ PROC
+ EXPORT MemManage_Handler [WEAK]
+ B .
+ ENDP
+BusFault_Handler\
+ PROC
+ EXPORT BusFault_Handler [WEAK]
+ B .
+ ENDP
+UsageFault_Handler\
+ PROC
+ EXPORT UsageFault_Handler [WEAK]
+ B .
+ ENDP
+SVC_Handler PROC
+ EXPORT SVC_Handler [WEAK]
+ B .
+ ENDP
+DebugMon_Handler\
+ PROC
+ EXPORT DebugMon_Handler [WEAK]
+ B .
+ ENDP
+PendSV_Handler PROC
+ EXPORT PendSV_Handler [WEAK]
+ B .
+ ENDP
+SysTick_Handler PROC
+ EXPORT SysTick_Handler [WEAK]
+ B .
+ ENDP
+
+Default_Handler PROC
+
+ EXPORT WWDG_IRQHandler [WEAK]
+ EXPORT PVD_PVM_IRQHandler [WEAK]
+ EXPORT TAMP_STAMP_LSECSS_SSRU_IRQHandler [WEAK]
+ EXPORT RTC_WKUP_IRQHandler [WEAK]
+ EXPORT FLASH_IRQHandler [WEAK]
+ EXPORT RCC_IRQHandler [WEAK]
+ EXPORT EXTI0_IRQHandler [WEAK]
+ EXPORT EXTI1_IRQHandler [WEAK]
+ EXPORT EXTI2_IRQHandler [WEAK]
+ EXPORT EXTI3_IRQHandler [WEAK]
+ EXPORT EXTI4_IRQHandler [WEAK]
+ EXPORT DMA1_Channel1_IRQHandler [WEAK]
+ EXPORT DMA1_Channel2_IRQHandler [WEAK]
+ EXPORT DMA1_Channel3_IRQHandler [WEAK]
+ EXPORT DMA1_Channel4_IRQHandler [WEAK]
+ EXPORT DMA1_Channel5_IRQHandler [WEAK]
+ EXPORT DMA1_Channel6_IRQHandler [WEAK]
+ EXPORT DMA1_Channel7_IRQHandler [WEAK]
+ EXPORT ADC_IRQHandler [WEAK]
+ EXPORT DAC_IRQHandler [WEAK]
+ EXPORT C2SEV_PWR_C2H_IRQHandler [WEAK]
+ EXPORT COMP_IRQHandler [WEAK]
+ EXPORT EXTI9_5_IRQHandler [WEAK]
+ EXPORT TIM1_BRK_IRQHandler [WEAK]
+ EXPORT TIM1_UP_IRQHandler [WEAK]
+ EXPORT TIM1_TRG_COM_IRQHandler [WEAK]
+ EXPORT TIM1_CC_IRQHandler [WEAK]
+ EXPORT TIM2_IRQHandler [WEAK]
+ EXPORT TIM16_IRQHandler [WEAK]
+ EXPORT TIM17_IRQHandler [WEAK]
+ EXPORT I2C1_EV_IRQHandler [WEAK]
+ EXPORT I2C1_ER_IRQHandler [WEAK]
+ EXPORT I2C2_EV_IRQHandler [WEAK]
+ EXPORT I2C2_ER_IRQHandler [WEAK]
+ EXPORT SPI1_IRQHandler [WEAK]
+ EXPORT SPI2_IRQHandler [WEAK]
+ EXPORT USART1_IRQHandler [WEAK]
+ EXPORT USART2_IRQHandler [WEAK]
+ EXPORT LPUART1_IRQHandler [WEAK]
+ EXPORT LPTIM1_IRQHandler [WEAK]
+ EXPORT LPTIM2_IRQHandler [WEAK]
+ EXPORT EXTI15_10_IRQHandler [WEAK]
+ EXPORT RTC_Alarm_IRQHandler [WEAK]
+ EXPORT LPTIM3_IRQHandler [WEAK]
+ EXPORT SUBGHZSPI_IRQHandler [WEAK]
+ EXPORT IPCC_C1_RX_IRQHandler [WEAK]
+ EXPORT IPCC_C1_TX_IRQHandler [WEAK]
+ EXPORT HSEM_IRQHandler [WEAK]
+ EXPORT I2C3_EV_IRQHandler [WEAK]
+ EXPORT I2C3_ER_IRQHandler [WEAK]
+ EXPORT SUBGHZ_Radio_IRQHandler [WEAK]
+ EXPORT AES_IRQHandler [WEAK]
+ EXPORT RNG_IRQHandler [WEAK]
+ EXPORT PKA_IRQHandler [WEAK]
+ EXPORT DMA2_Channel1_IRQHandler [WEAK]
+ EXPORT DMA2_Channel2_IRQHandler [WEAK]
+ EXPORT DMA2_Channel3_IRQHandler [WEAK]
+ EXPORT DMA2_Channel4_IRQHandler [WEAK]
+ EXPORT DMA2_Channel5_IRQHandler [WEAK]
+ EXPORT DMA2_Channel6_IRQHandler [WEAK]
+ EXPORT DMA2_Channel7_IRQHandler [WEAK]
+ EXPORT DMAMUX1_OVR_IRQHandler [WEAK]
+
+WWDG_IRQHandler
+PVD_PVM_IRQHandler
+TAMP_STAMP_LSECSS_SSRU_IRQHandler
+RTC_WKUP_IRQHandler
+FLASH_IRQHandler
+RCC_IRQHandler
+EXTI0_IRQHandler
+EXTI1_IRQHandler
+EXTI2_IRQHandler
+EXTI3_IRQHandler
+EXTI4_IRQHandler
+DMA1_Channel1_IRQHandler
+DMA1_Channel2_IRQHandler
+DMA1_Channel3_IRQHandler
+DMA1_Channel4_IRQHandler
+DMA1_Channel5_IRQHandler
+DMA1_Channel6_IRQHandler
+DMA1_Channel7_IRQHandler
+ADC_IRQHandler
+DAC_IRQHandler
+C2SEV_PWR_C2H_IRQHandler
+COMP_IRQHandler
+EXTI9_5_IRQHandler
+TIM1_BRK_IRQHandler
+TIM1_UP_IRQHandler
+TIM1_TRG_COM_IRQHandler
+TIM1_CC_IRQHandler
+TIM2_IRQHandler
+TIM16_IRQHandler
+TIM17_IRQHandler
+I2C1_EV_IRQHandler
+I2C1_ER_IRQHandler
+I2C2_EV_IRQHandler
+I2C2_ER_IRQHandler
+SPI1_IRQHandler
+SPI2_IRQHandler
+USART1_IRQHandler
+USART2_IRQHandler
+LPUART1_IRQHandler
+LPTIM1_IRQHandler
+LPTIM2_IRQHandler
+EXTI15_10_IRQHandler
+RTC_Alarm_IRQHandler
+LPTIM3_IRQHandler
+SUBGHZSPI_IRQHandler
+IPCC_C1_RX_IRQHandler
+IPCC_C1_TX_IRQHandler
+HSEM_IRQHandler
+I2C3_EV_IRQHandler
+I2C3_ER_IRQHandler
+SUBGHZ_Radio_IRQHandler
+AES_IRQHandler
+RNG_IRQHandler
+PKA_IRQHandler
+DMA2_Channel1_IRQHandler
+DMA2_Channel2_IRQHandler
+DMA2_Channel3_IRQHandler
+DMA2_Channel4_IRQHandler
+DMA2_Channel5_IRQHandler
+DMA2_Channel6_IRQHandler
+DMA2_Channel7_IRQHandler
+DMAMUX1_OVR_IRQHandler
+
+ B .
+
+ ENDP
+
+ ALIGN
+
+;*******************************************************************************
+; User Stack and Heap initialization
+;*******************************************************************************
+
+ END
+
+;************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE*****
diff --git a/targets/TARGET_STM/TARGET_STM32WL/TARGET_STM32WL54xC/TOOLCHAIN_ARM/stm32wl54xc.sct b/targets/TARGET_STM/TARGET_STM32WL/TARGET_STM32WL54xC/TOOLCHAIN_ARM/stm32wl54xc.sct
new file mode 100644
index 0000000..9258e6a
--- /dev/null
+++ b/targets/TARGET_STM/TARGET_STM32WL/TARGET_STM32WL54xC/TOOLCHAIN_ARM/stm32wl54xc.sct
@@ -0,0 +1,57 @@
+#! armclang -E --target=arm-arm-none-eabi -x c -mcpu=cortex-M4
+; Scatter-Loading Description File
+;
+; SPDX-License-Identifier: BSD-3-Clause
+;******************************************************************************
+;* @attention
+;*
+;* Copyright (c) 2016-2020 STMicroelectronics.
+;* All rights reserved.
+;*
+;* This software component is licensed by ST under BSD 3-Clause license,
+;* the "License"; You may not use this file except in compliance with the
+;* License. You may obtain a copy of the License at:
+;* opensource.org/licenses/BSD-3-Clause
+;*
+;******************************************************************************
+
+#include "../cmsis_nvic.h"
+
+#if !defined(MBED_APP_START)
+ #define MBED_APP_START MBED_ROM_START
+#endif
+
+#if !defined(MBED_APP_SIZE)
+ #define MBED_APP_SIZE MBED_ROM_SIZE
+#endif
+
+#if !defined(MBED_CONF_TARGET_BOOT_STACK_SIZE)
+/* This value is normally defined by the tools to 0x1000 for bare metal and 0x400 for RTOS */
+#if defined(MBED_BOOT_STACK_SIZE)
+#define MBED_CONF_TARGET_BOOT_STACK_SIZE MBED_BOOT_STACK_SIZE
+#else
+#define MBED_CONF_TARGET_BOOT_STACK_SIZE 0x400
+#endif
+#endif
+
+/* Round up VECTORS_SIZE to 8 bytes */
+#define VECTORS_SIZE (((NVIC_NUM_VECTORS * 4) + 7) AND ~7)
+
+LR_IROM1 MBED_APP_START MBED_APP_SIZE {
+
+ ER_IROM1 MBED_APP_START MBED_APP_SIZE {
+ *.o (RESET, +First)
+ *(InRoot$$Sections)
+ .ANY (+RO)
+ }
+
+ RW_IRAM1 (MBED_RAM_START + VECTORS_SIZE) { ; RW data
+ .ANY (+RW +ZI)
+ }
+
+ ARM_LIB_HEAP AlignExpr(+0, 16) EMPTY (MBED_RAM_START + MBED_RAM_SIZE - MBED_CONF_TARGET_BOOT_STACK_SIZE - AlignExpr(ImageLimit(RW_IRAM1), 16)) { ; Heap growing up
+ }
+
+ ARM_LIB_STACK (MBED_RAM_START + MBED_RAM_SIZE) EMPTY -MBED_CONF_TARGET_BOOT_STACK_SIZE { ; Stack region growing down
+ }
+}
diff --git a/targets/TARGET_STM/TARGET_STM32WL/TARGET_STM32WL54xC/TOOLCHAIN_GCC_ARM/startup_stm32wl54xx.S b/targets/TARGET_STM/TARGET_STM32WL/TARGET_STM32WL54xC/TOOLCHAIN_GCC_ARM/startup_stm32wl54xx.S
new file mode 100644
index 0000000..522022f
--- /dev/null
+++ b/targets/TARGET_STM/TARGET_STM32WL/TARGET_STM32WL54xC/TOOLCHAIN_GCC_ARM/startup_stm32wl54xx.S
@@ -0,0 +1,434 @@
+/**
+ ******************************************************************************
+ * @file startup_stm32wl54xx_cm4.s
+ * @author MCD Application Team
+ * @brief STM32WL54xx devices Cortex-M4 vector table for GCC toolchain.
+ * This module performs:
+ * - Set the initial SP
+ * - Set the initial PC == Reset_Handler,
+ * - Set the vector table entries with the exceptions ISR address,
+ * - Branches to main in the C library (which eventually
+ * calls main()).
+ * After Reset the Cortex-M4 processor is in Thread mode,
+ * priority is Privileged, and the Stack is set to Main.
+ ******************************************************************************
+ * @attention
+ *
+ * © Copyright (c) 2020 STMicroelectronics.
+ * All rights reserved.
+ *
+ * This software component is licensed by ST under Apache License, Version 2.0,
+ * the "License"; You may not use this file except in compliance with the
+ * License. You may obtain a copy of the License at:
+ * opensource.org/licenses/Apache-2.0
+ *
+ ******************************************************************************
+ */
+
+.syntax unified
+.cpu cortex-m4
+.fpu softvfp
+.thumb
+
+.global g_pfnVectors
+.global Default_Handler
+
+/* start address for the initialization values of the .data section.
+defined in linker script */
+.word _sidata
+/* start address for the .data section. defined in linker script */
+.word _sdata
+/* end address for the .data section. defined in linker script */
+.word _edata
+/* start address for the .bss section. defined in linker script */
+.word _sbss
+/* end address for the .bss section. defined in linker script */
+.word _ebss
+
+/**
+ * @brief This is the code that gets called when the processor first
+ * starts execution following a reset event. Only the absolutely
+ * necessary set is performed, after which the application
+ * supplied main() routine is called.
+ * @param None
+ * @retval : None
+*/
+
+ .section .text.Reset_Handler
+ .weak Reset_Handler
+ .type Reset_Handler, %function
+Reset_Handler:
+ ldr r0, =_estack
+ mov sp, r0 /* set stack pointer */
+
+/* Call the clock system initialization function.*/
+ bl SystemInit
+
+/* Copy the data segment initializers from flash to SRAM */
+ ldr r0, =_sdata
+ ldr r1, =_edata
+ ldr r2, =_sidata
+ movs r3, #0
+ b LoopCopyDataInit
+
+CopyDataInit:
+ ldr r4, [r2, r3]
+ str r4, [r0, r3]
+ adds r3, r3, #4
+
+LoopCopyDataInit:
+ adds r4, r0, r3
+ cmp r4, r1
+ bcc CopyDataInit
+
+/* Zero fill the bss segment. */
+ ldr r2, =_sbss
+ ldr r4, =_ebss
+ movs r3, #0
+ b LoopFillZerobss
+
+FillZerobss:
+ str r3, [r2]
+ adds r2, r2, #4
+
+LoopFillZerobss:
+ cmp r2, r4
+ bcc FillZerobss
+
+ bl _start
+ bx lr
+
+LoopForever:
+ b LoopForever
+
+ .size Reset_Handler, .-Reset_Handler
+
+/**
+ * @brief This is the code that gets called when the processor receives an
+ * unexpected interrupt. This simply enters an infinite loop, preserving
+ * the system state for examination by a debugger.
+ *
+ * @param None
+ * @retval : None
+*/
+ .section .text.Default_Handler,"ax",%progbits
+Default_Handler:
+Infinite_Loop:
+ b Infinite_Loop
+ .size Default_Handler, .-Default_Handler
+
+/******************************************************************************
+*
+* The STM32WL54xx Cortex-M4 vector table. Note that the proper constructs
+* must be placed on this to ensure that it ends up at physical address
+* 0x0000.0000.
+*
+******************************************************************************/
+ .section .isr_vector,"a",%progbits
+ .type g_pfnVectors, %object
+ .size g_pfnVectors, .-g_pfnVectors
+
+g_pfnVectors:
+ .word _estack
+ .word Reset_Handler
+ .word NMI_Handler
+ .word HardFault_Handler
+ .word MemManage_Handler
+ .word BusFault_Handler
+ .word UsageFault_Handler
+ .word 0
+ .word 0
+ .word 0
+ .word 0
+ .word SVC_Handler
+ .word DebugMon_Handler
+ .word 0
+ .word PendSV_Handler
+ .word SysTick_Handler
+ .word WWDG_IRQHandler /* Window Watchdog interrupt */
+ .word PVD_PVM_IRQHandler /* PVD and PVM interrupt through EXTI */
+ .word TAMP_STAMP_LSECSS_SSRU_IRQHandler /* RTC Tamper, RTC TimeStamp, LSECSS and RTC SSRU int.*/
+ .word RTC_WKUP_IRQHandler /* RTC wakeup interrupt through EXTI[19] */
+ .word FLASH_IRQHandler /* Flash memory global interrupt and Flash memory ECC */
+ .word RCC_IRQHandler /* RCC global interrupt */
+ .word EXTI0_IRQHandler /* EXTI line 0 interrupt */
+ .word EXTI1_IRQHandler /* EXTI line 1 interrupt */
+ .word EXTI2_IRQHandler /* EXTI line 2 interrupt */
+ .word EXTI3_IRQHandler /* EXTI line 3 interrupt */
+ .word EXTI4_IRQHandler /* EXTI line 4 interrupt */
+ .word DMA1_Channel1_IRQHandler /* DMA1 channel 1 interrupt */
+ .word DMA1_Channel2_IRQHandler /* DMA1 channel 2 interrupt */
+ .word DMA1_Channel3_IRQHandler /* DMA1 channel 3 interrupt */
+ .word DMA1_Channel4_IRQHandler /* DMA1 channel 4 interrupt */
+ .word DMA1_Channel5_IRQHandler /* DMA1 channel 5 interrupt */
+ .word DMA1_Channel6_IRQHandler /* DMA1 channel 6 interrupt */
+ .word DMA1_Channel7_IRQHandler /* DMA1 channel 7 interrupt */
+ .word ADC_IRQHandler /* ADC interrupt */
+ .word DAC_IRQHandler /* DAC interrupt */
+ .word C2SEV_PWR_C2H_IRQHandler /* CPU M0+ SEV Interrupt */
+ .word COMP_IRQHandler /* COMP1 and COMP2 interrupt through EXTI */
+ .word EXTI9_5_IRQHandler /* EXTI line 9_5 interrupt */
+ .word TIM1_BRK_IRQHandler /* Timer 1 break interrupt */
+ .word TIM1_UP_IRQHandler /* Timer 1 Update */
+ .word TIM1_TRG_COM_IRQHandler /* Timer 1 trigger and communication */
+ .word TIM1_CC_IRQHandler /* Timer 1 capture compare interrupt */
+ .word TIM2_IRQHandler /* TIM2 global interrupt */
+ .word TIM16_IRQHandler /* Timer 16 global interrupt */
+ .word TIM17_IRQHandler /* Timer 17 global interrupt */
+ .word I2C1_EV_IRQHandler /* I2C1 event interrupt */
+ .word I2C1_ER_IRQHandler /* I2C1 event interrupt */
+ .word I2C2_EV_IRQHandler /* I2C2 error interrupt */
+ .word I2C2_ER_IRQHandler /* I2C2 error interrupt */
+ .word SPI1_IRQHandler /* SPI1 global interrupt */
+ .word SPI2_IRQHandler /* SPI2 global interrupt */
+ .word USART1_IRQHandler /* USART1 global interrupt */
+ .word USART2_IRQHandler /* USART2 global interrupt */
+ .word LPUART1_IRQHandler /* LPUART1 global interrupt */
+ .word LPTIM1_IRQHandler /* LPtimer 1 global interrupt */
+ .word LPTIM2_IRQHandler /* LPtimer 2 global interrupt */
+ .word EXTI15_10_IRQHandler /* EXTI line 15_10] interrupt through EXTI */
+ .word RTC_Alarm_IRQHandler /* RTC Alarms A & B interrupt */
+ .word LPTIM3_IRQHandler /* LPtimer 3 global interrupt */
+ .word SUBGHZSPI_IRQHandler /* SUBGHZSPI global interrupt */
+ .word IPCC_C1_RX_IRQHandler /* IPCC CPU1 RX occupied interrupt */
+ .word IPCC_C1_TX_IRQHandler /* IPCC CPU1 RX free interrupt */
+ .word HSEM_IRQHandler /* Semaphore interrupt 0 to CPU1 */
+ .word I2C3_EV_IRQHandler /* I2C3 event interrupt */
+ .word I2C3_ER_IRQHandler /* I2C3 error interrupt */
+ .word SUBGHZ_Radio_IRQHandler /* Radio IRQs RFBUSY interrupt through EXTI */
+ .word AES_IRQHandler /* AES global interrupt */
+ .word RNG_IRQHandler /* RNG interrupt */
+ .word PKA_IRQHandler /* PKA interrupt */
+ .word DMA2_Channel1_IRQHandler /* DMA2 channel 1 interrupt */
+ .word DMA2_Channel2_IRQHandler /* DMA2 channel 2 interrupt */
+ .word DMA2_Channel3_IRQHandler /* DMA2 channel 3 interrupt */
+ .word DMA2_Channel4_IRQHandler /* DMA2 channel 4 interrupt */
+ .word DMA2_Channel5_IRQHandler /* DMA2 channel 5 interrupt */
+ .word DMA2_Channel6_IRQHandler /* DMA2 channel 6 interrupt */
+ .word DMA2_Channel7_IRQHandler /* DMA2 channel 7 interrupt */
+ .word DMAMUX1_OVR_IRQHandler /* DMAMUX overrun interrupt */
+
+/*******************************************************************************
+*
+* Provide weak aliases for each Exception handler to the Default_Handler.
+* As they are weak aliases, any function with the same name will override
+* this definition.
+*
+*******************************************************************************/
+
+ .weak NMI_Handler
+ .thumb_set NMI_Handler,Default_Handler
+
+ .weak HardFault_Handler
+ .thumb_set HardFault_Handler,Default_Handler
+
+ .weak MemManage_Handler
+ .thumb_set MemManage_Handler,Default_Handler
+
+ .weak BusFault_Handler
+ .thumb_set BusFault_Handler,Default_Handler
+
+ .weak UsageFault_Handler
+ .thumb_set UsageFault_Handler,Default_Handler
+
+ .weak SVC_Handler
+ .thumb_set SVC_Handler,Default_Handler
+
+ .weak DebugMon_Handler
+ .thumb_set DebugMon_Handler,Default_Handler
+
+ .weak PendSV_Handler
+ .thumb_set PendSV_Handler,Default_Handler
+
+ .weak SysTick_Handler
+ .thumb_set SysTick_Handler,Default_Handler
+
+ .weak WWDG_IRQHandler
+ .thumb_set WWDG_IRQHandler,Default_Handler
+
+ .weak PVD_PVM_IRQHandler
+ .thumb_set PVD_PVM_IRQHandler,Default_Handler
+
+ .weak TAMP_STAMP_LSECSS_SSRU_IRQHandler
+ .thumb_set TAMP_STAMP_LSECSS_SSRU_IRQHandler,Default_Handler
+
+ .weak RTC_WKUP_IRQHandler
+ .thumb_set RTC_WKUP_IRQHandler,Default_Handler
+
+ .weak FLASH_IRQHandler
+ .thumb_set FLASH_IRQHandler,Default_Handler
+
+ .weak RCC_IRQHandler
+ .thumb_set RCC_IRQHandler,Default_Handler
+
+ .weak EXTI0_IRQHandler
+ .thumb_set EXTI0_IRQHandler,Default_Handler
+
+ .weak EXTI1_IRQHandler
+ .thumb_set EXTI1_IRQHandler,Default_Handler
+
+ .weak EXTI2_IRQHandler
+ .thumb_set EXTI2_IRQHandler,Default_Handler
+
+ .weak EXTI3_IRQHandler
+ .thumb_set EXTI3_IRQHandler,Default_Handler
+
+ .weak EXTI4_IRQHandler
+ .thumb_set EXTI4_IRQHandler,Default_Handler
+
+ .weak DMA1_Channel1_IRQHandler
+ .thumb_set DMA1_Channel1_IRQHandler,Default_Handler
+
+ .weak DMA1_Channel2_IRQHandler
+ .thumb_set DMA1_Channel2_IRQHandler,Default_Handler
+
+ .weak DMA1_Channel3_IRQHandler
+ .thumb_set DMA1_Channel3_IRQHandler,Default_Handler
+
+ .weak DMA1_Channel4_IRQHandler
+ .thumb_set DMA1_Channel4_IRQHandler,Default_Handler
+
+ .weak DMA1_Channel5_IRQHandler
+ .thumb_set DMA1_Channel5_IRQHandler,Default_Handler
+
+ .weak DMA1_Channel6_IRQHandler
+ .thumb_set DMA1_Channel6_IRQHandler,Default_Handler
+
+ .weak DMA1_Channel7_IRQHandler
+ .thumb_set DMA1_Channel7_IRQHandler,Default_Handler
+
+ .weak ADC_IRQHandler
+ .thumb_set ADC_IRQHandler,Default_Handler
+
+ .weak DAC_IRQHandler
+ .thumb_set DAC_IRQHandler,Default_Handler
+
+ .weak C2SEV_PWR_C2H_IRQHandler
+ .thumb_set C2SEV_PWR_C2H_IRQHandler,Default_Handler
+
+ .weak COMP_IRQHandler
+ .thumb_set COMP_IRQHandler,Default_Handler
+
+ .weak EXTI9_5_IRQHandler
+ .thumb_set EXTI9_5_IRQHandler,Default_Handler
+
+ .weak TIM1_BRK_IRQHandler
+ .thumb_set TIM1_BRK_IRQHandler,Default_Handler
+
+ .weak TIM1_UP_IRQHandler
+ .thumb_set TIM1_UP_IRQHandler,Default_Handler
+
+ .weak TIM1_TRG_COM_IRQHandler
+ .thumb_set TIM1_TRG_COM_IRQHandler,Default_Handler
+
+ .weak TIM1_CC_IRQHandler
+ .thumb_set TIM1_CC_IRQHandler,Default_Handler
+
+ .weak TIM2_IRQHandler
+ .thumb_set TIM2_IRQHandler,Default_Handler
+
+ .weak TIM16_IRQHandler
+ .thumb_set TIM16_IRQHandler,Default_Handler
+
+ .weak TIM17_IRQHandler
+ .thumb_set TIM17_IRQHandler,Default_Handler
+
+ .weak I2C1_EV_IRQHandler
+ .thumb_set I2C1_EV_IRQHandler,Default_Handler
+
+ .weak I2C1_ER_IRQHandler
+ .thumb_set I2C1_ER_IRQHandler,Default_Handler
+
+ .weak I2C2_EV_IRQHandler
+ .thumb_set I2C2_EV_IRQHandler,Default_Handler
+
+ .weak I2C2_ER_IRQHandler
+ .thumb_set I2C2_ER_IRQHandler,Default_Handler
+
+ .weak SPI1_IRQHandler
+ .thumb_set SPI1_IRQHandler,Default_Handler
+
+ .weak SPI2_IRQHandler
+ .thumb_set SPI2_IRQHandler,Default_Handler
+
+ .weak USART1_IRQHandler
+ .thumb_set USART1_IRQHandler,Default_Handler
+
+ .weak USART2_IRQHandler
+ .thumb_set USART2_IRQHandler,Default_Handler
+
+ .weak LPUART1_IRQHandler
+ .thumb_set LPUART1_IRQHandler,Default_Handler
+
+ .weak LPTIM1_IRQHandler
+ .thumb_set LPTIM1_IRQHandler,Default_Handler
+
+ .weak LPTIM2_IRQHandler
+ .thumb_set LPTIM2_IRQHandler,Default_Handler
+
+ .weak EXTI15_10_IRQHandler
+ .thumb_set EXTI15_10_IRQHandler,Default_Handler
+
+ .weak RTC_Alarm_IRQHandler
+ .thumb_set RTC_Alarm_IRQHandler,Default_Handler
+
+ .weak LPTIM3_IRQHandler
+ .thumb_set LPTIM3_IRQHandler,Default_Handler
+
+ .weak SUBGHZSPI_IRQHandler
+ .thumb_set SUBGHZSPI_IRQHandler,Default_Handler
+
+ .weak IPCC_C1_RX_IRQHandler
+ .thumb_set IPCC_C1_RX_IRQHandler,Default_Handler
+
+ .weak IPCC_C1_TX_IRQHandler
+ .thumb_set IPCC_C1_TX_IRQHandler,Default_Handler
+
+ .weak HSEM_IRQHandler
+ .thumb_set HSEM_IRQHandler,Default_Handler
+
+ .weak I2C3_EV_IRQHandler
+ .thumb_set I2C3_EV_IRQHandler,Default_Handler
+
+ .weak I2C3_ER_IRQHandler
+ .thumb_set I2C3_ER_IRQHandler,Default_Handler
+
+ .weak SUBGHZ_Radio_IRQHandler
+ .thumb_set SUBGHZ_Radio_IRQHandler,Default_Handler
+
+ .weak AES_IRQHandler
+ .thumb_set AES_IRQHandler,Default_Handler
+
+ .weak RNG_IRQHandler
+ .thumb_set RNG_IRQHandler,Default_Handler
+
+ .weak PKA_IRQHandler
+ .thumb_set PKA_IRQHandler,Default_Handler
+
+ .weak DMA2_Channel1_IRQHandler
+ .thumb_set DMA2_Channel1_IRQHandler,Default_Handler
+
+ .weak DMA2_Channel2_IRQHandler
+ .thumb_set DMA2_Channel2_IRQHandler,Default_Handler
+
+ .weak DMA2_Channel3_IRQHandler
+ .thumb_set DMA2_Channel3_IRQHandler,Default_Handler
+
+ .weak DMA2_Channel4_IRQHandler
+ .thumb_set DMA2_Channel4_IRQHandler,Default_Handler
+
+ .weak DMA2_Channel5_IRQHandler
+ .thumb_set DMA2_Channel5_IRQHandler,Default_Handler
+
+ .weak DMA2_Channel6_IRQHandler
+ .thumb_set DMA2_Channel6_IRQHandler,Default_Handler
+
+ .weak DMA2_Channel7_IRQHandler
+ .thumb_set DMA2_Channel7_IRQHandler,Default_Handler
+
+ .weak DMAMUX1_OVR_IRQHandler
+ .thumb_set DMAMUX1_OVR_IRQHandler,Default_Handler
+
+ .weak SystemInit
+
+/************************ (C) COPYRIGHT STMicroelectonics *****END OF FILE****/
diff --git a/targets/TARGET_STM/TARGET_STM32WL/TARGET_STM32WL54xC/TOOLCHAIN_GCC_ARM/stm32wl54xc.ld b/targets/TARGET_STM/TARGET_STM32WL/TARGET_STM32WL54xC/TOOLCHAIN_GCC_ARM/stm32wl54xc.ld
new file mode 100644
index 0000000..5f47993
--- /dev/null
+++ b/targets/TARGET_STM/TARGET_STM32WL/TARGET_STM32WL54xC/TOOLCHAIN_GCC_ARM/stm32wl54xc.ld
@@ -0,0 +1,203 @@
+/* Linker script to configure memory regions. */
+/*
+ * SPDX-License-Identifier: BSD-3-Clause
+ ******************************************************************************
+ * @attention
+ *
+ * Copyright (c) 2016-2020 STMicroelectronics.
+ * All rights reserved.
+ *
+ * This software component is licensed by ST under BSD 3-Clause license,
+ * the "License"; You may not use this file except in compliance with the
+ * License. You may obtain a copy of the License at:
+ * opensource.org/licenses/BSD-3-Clause
+ *
+ ******************************************************************************
+*/
+
+#include "../cmsis_nvic.h"
+
+
+#if !defined(MBED_APP_START)
+ #define MBED_APP_START MBED_ROM_START
+#endif
+
+#if !defined(MBED_APP_SIZE)
+ #define MBED_APP_SIZE MBED_ROM_SIZE
+#endif
+
+#if !defined(MBED_CONF_TARGET_BOOT_STACK_SIZE)
+ /* This value is normally defined by the tools
+ to 0x1000 for bare metal and 0x400 for RTOS */
+ #define MBED_CONF_TARGET_BOOT_STACK_SIZE 0x400
+#endif
+
+/* Round up VECTORS_SIZE to 8 bytes */
+#define VECTORS_SIZE (((NVIC_NUM_VECTORS * 4) + 7) & 0xFFFFFFF8)
+
+MEMORY
+{
+ FLASH (rx) : ORIGIN = MBED_APP_START, LENGTH = MBED_APP_SIZE
+ RAM (rwx) : ORIGIN = MBED_RAM_START + VECTORS_SIZE, LENGTH = MBED_RAM_SIZE - VECTORS_SIZE
+}
+
+/* Linker script to place sections and symbol values. Should be used together
+ * with other linker script that defines memory regions FLASH and RAM.
+ * It references following symbols, which must be defined in code:
+ * Reset_Handler : Entry of reset handler
+ *
+ * It defines following symbols, which code can use without definition:
+ * __exidx_start
+ * __exidx_end
+ * __etext
+ * __data_start__
+ * __preinit_array_start
+ * __preinit_array_end
+ * __init_array_start
+ * __init_array_end
+ * __fini_array_start
+ * __fini_array_end
+ * __data_end__
+ * __bss_start__
+ * __bss_end__
+ * __end__
+ * end
+ * __HeapLimit
+ * __StackLimit
+ * __StackTop
+ * __stack
+ * _estack
+ */
+ENTRY(Reset_Handler)
+
+SECTIONS
+{
+ .text :
+ {
+ KEEP(*(.isr_vector))
+ *(.text*)
+
+ KEEP(*(.init))
+ KEEP(*(.fini))
+
+ /* .ctors */
+ *crtbegin.o(.ctors)
+ *crtbegin?.o(.ctors)
+ *(EXCLUDE_FILE(*crtend?.o *crtend.o) .ctors)
+ *(SORT(.ctors.*))
+ *(.ctors)
+
+ /* .dtors */
+ *crtbegin.o(.dtors)
+ *crtbegin?.o(.dtors)
+ *(EXCLUDE_FILE(*crtend?.o *crtend.o) .dtors)
+ *(SORT(.dtors.*))
+ *(.dtors)
+
+ *(.rodata*)
+
+ KEEP(*(.eh_frame*))
+ } > FLASH
+
+ .ARM.extab :
+ {
+ *(.ARM.extab* .gnu.linkonce.armextab.*)
+ } > FLASH
+
+ __exidx_start = .;
+ .ARM.exidx :
+ {
+ *(.ARM.exidx* .gnu.linkonce.armexidx.*)
+ } > FLASH
+ __exidx_end = .;
+
+ __etext = .;
+ _sidata = .;
+
+ .data : AT (__etext)
+ {
+ __data_start__ = .;
+ _sdata = .;
+ *(vtable)
+ *(.data*)
+
+ . = ALIGN(8);
+ /* preinit data */
+ PROVIDE_HIDDEN (__preinit_array_start = .);
+ KEEP(*(.preinit_array))
+ PROVIDE_HIDDEN (__preinit_array_end = .);
+
+ . = ALIGN(8);
+ /* init data */
+ PROVIDE_HIDDEN (__init_array_start = .);
+ KEEP(*(SORT(.init_array.*)))
+ KEEP(*(.init_array))
+ PROVIDE_HIDDEN (__init_array_end = .);
+
+ . = ALIGN(8);
+ /* finit data */
+ PROVIDE_HIDDEN (__fini_array_start = .);
+ KEEP(*(SORT(.fini_array.*)))
+ KEEP(*(.fini_array))
+ PROVIDE_HIDDEN (__fini_array_end = .);
+
+ KEEP(*(.jcr*))
+ . = ALIGN(8);
+ /* All data end */
+ __data_end__ = .;
+ _edata = .;
+
+ } > RAM
+
+ /* Uninitialized data section
+ * This region is not initialized by the C/C++ library and can be used to
+ * store state across soft reboots. */
+ .uninitialized (NOLOAD):
+ {
+ . = ALIGN(32);
+ __uninitialized_start = .;
+ *(.uninitialized)
+ KEEP(*(.keep.uninitialized))
+ . = ALIGN(32);
+ __uninitialized_end = .;
+ } > RAM
+
+ .bss :
+ {
+ . = ALIGN(8);
+ __bss_start__ = .;
+ _sbss = .;
+ *(.bss*)
+ *(COMMON)
+ . = ALIGN(8);
+ __bss_end__ = .;
+ _ebss = .;
+ } > RAM
+
+ .heap (COPY):
+ {
+ __end__ = .;
+ PROVIDE(end = .);
+ *(.heap*)
+ . = ORIGIN(RAM) + LENGTH(RAM) - MBED_CONF_TARGET_BOOT_STACK_SIZE;
+ __HeapLimit = .;
+ } > RAM
+
+ /* .stack_dummy section doesn't contains any symbols. It is only
+ * used for linker to calculate size of stack sections, and assign
+ * values to stack symbols later */
+ .stack_dummy (COPY):
+ {
+ *(.stack*)
+ } > RAM
+
+ /* Set stack top to end of RAM, and stack limit move down by
+ * size of stack_dummy section */
+ __StackTop = ORIGIN(RAM) + LENGTH(RAM);
+ _estack = __StackTop;
+ __StackLimit = __StackTop - MBED_CONF_TARGET_BOOT_STACK_SIZE;
+ PROVIDE(__stack = __StackTop);
+
+ /* Check if data + heap + stack exceeds RAM limit */
+ ASSERT(__StackLimit >= __HeapLimit, "region RAM overflowed with stack")
+}
diff --git a/targets/TARGET_STM/TARGET_STM32WL/TARGET_STM32WL54xC/TOOLCHAIN_IAR/startup_stm32wl54xx.S b/targets/TARGET_STM/TARGET_STM32WL/TARGET_STM32WL54xC/TOOLCHAIN_IAR/startup_stm32wl54xx.S
new file mode 100644
index 0000000..39d1eb2
--- /dev/null
+++ b/targets/TARGET_STM/TARGET_STM32WL/TARGET_STM32WL54xC/TOOLCHAIN_IAR/startup_stm32wl54xx.S
@@ -0,0 +1,509 @@
+;********************************************************************************
+;* File Name : startup_stm32wl54xx_cm4.s
+;* Author : MCD Application Team
+;* Description : M4 core vector table of the STM32WLxxxx devices for the
+;* IAR (EWARM) toolchain.
+;*
+;* This module performs:
+;* - Set the initial SP
+;* - Set the initial PC == _iar_program_start,
+;* - Set the vector table entries with the exceptions ISR
+;* address.
+;* - Branches to main in the C library (which eventually
+;* calls main()).
+;* After Reset the Cortex-M4 processor is in Thread mode,
+;* priority is Privileged, and the Stack is set to Main.
+;********************************************************************************
+;*
+;* Copyright (c) 2020 STMicroelectronics. All rights reserved.
+;*
+;* This software component is licensed by ST under Apache License, Version 2.0,
+;* the "License"; You may not use this file except in compliance with the
+;* License. You may obtain a copy of the License at:
+;* opensource.org/licenses/Apache-2.0
+;
+;*******************************************************************************
+;
+;
+; The modules in this file are included in the libraries, and may be replaced
+; by any user-defined modules that define the PUBLIC symbol _program_start or
+; a user defined start symbol.
+; To override the cstartup defined in the library, simply add your modified
+; version to the workbench project.
+;
+; The vector table is normally located at address 0.
+; When debugging in RAM, it can be located in RAM, aligned to at least 2^6.
+; The name "__vector_table" has special meaning for C-SPY:
+; it is where the SP start value is found, and the NVIC vector
+; table register (VTOR) is initialized to this address if != 0.
+;
+; Cortex-M version
+;
+
+ MODULE ?cstartup
+
+ ;; Forward declaration of sections.
+ SECTION CSTACK:DATA:NOROOT(3)
+
+ SECTION .intvec:CODE:NOROOT(2)
+
+ EXTERN __iar_program_start
+ EXTERN SystemInit
+ PUBLIC __vector_table
+
+ DATA
+__vector_table
+ DCD sfe(CSTACK)
+ DCD Reset_Handler ; Reset Handler
+
+ DCD NMI_Handler ; NMI Handler
+ DCD HardFault_Handler ; Hard Fault Handler
+ DCD MemManage_Handler ; MPU Fault Handler
+ DCD BusFault_Handler ; Bus Fault Handler
+ DCD UsageFault_Handler ; Usage Fault Handler
+ DCD 0 ; Reserved
+ DCD 0 ; Reserved
+ DCD 0 ; Reserved
+ DCD 0 ; Reserved
+ DCD SVC_Handler ; SVCall Handler
+ DCD DebugMon_Handler ; Debug Monitor Handler
+ DCD 0 ; Reserved
+ DCD PendSV_Handler ; PendSV Handler
+ DCD SysTick_Handler ; SysTick Handler
+
+ ; External Interrupts
+ DCD WWDG_IRQHandler ; Window WatchDog
+ DCD PVD_PVM_IRQHandler ; PVD and PVM Interrupt
+ DCD TAMP_STAMP_LSECSS_SSRU_IRQHandler ; RTC Tamper, RTC TimeStamp, LSECSS and RTC SSRU Interrupts
+ DCD RTC_WKUP_IRQHandler ; RTC Wakeup Interrupt
+ DCD FLASH_IRQHandler ; FLASH global Interrupt
+ DCD RCC_IRQHandler ; RCC Interrupt
+ DCD EXTI0_IRQHandler ; EXTI Line 0 Interrupt
+ DCD EXTI1_IRQHandler ; EXTI Line 1 Interrupt
+ DCD EXTI2_IRQHandler ; EXTI Line 2 Interrupt
+ DCD EXTI3_IRQHandler ; EXTI Line 3 Interrupt
+ DCD EXTI4_IRQHandler ; EXTI Line 4 Interrupt
+ DCD DMA1_Channel1_IRQHandler ; DMA1 Channel 1 Interrupt
+ DCD DMA1_Channel2_IRQHandler ; DMA1 Channel 2 Interrupt
+ DCD DMA1_Channel3_IRQHandler ; DMA1 Channel 3 Interrupt
+ DCD DMA1_Channel4_IRQHandler ; DMA1 Channel 4 Interrupt
+ DCD DMA1_Channel5_IRQHandler ; DMA1 Channel 5 Interrupt
+ DCD DMA1_Channel6_IRQHandler ; DMA1 Channel 6 Interrupt
+ DCD DMA1_Channel7_IRQHandler ; DMA1 Channel 7 Interrupt
+ DCD ADC_IRQHandler ; ADC Interrupt
+ DCD DAC_IRQHandler ; DAC Interrupt
+ DCD C2SEV_PWR_C2H_IRQHandler ; CPU M0+ SEV Interrupt
+ DCD COMP_IRQHandler ; COMP1 and COMP2 Interrupts
+ DCD EXTI9_5_IRQHandler ; EXTI Lines [9:5] Interrupt
+ DCD TIM1_BRK_IRQHandler ; TIM1 Break Interrupt
+ DCD TIM1_UP_IRQHandler ; TIM1 Update Interrupt
+ DCD TIM1_TRG_COM_IRQHandler ; TIM1 Trigger and Communication Interrupts
+ DCD TIM1_CC_IRQHandler ; TIM1 Capture Compare Interrupt
+ DCD TIM2_IRQHandler ; TIM2 Global Interrupt
+ DCD TIM16_IRQHandler ; TIM16 Global Interrupt
+ DCD TIM17_IRQHandler ; TIM17 Global Interrupt
+ DCD I2C1_EV_IRQHandler ; I2C1 Event Interrupt
+ DCD I2C1_ER_IRQHandler ; I2C1 Error Interrupt
+ DCD I2C2_EV_IRQHandler ; I2C2 Event Interrupt
+ DCD I2C2_ER_IRQHandler ; I2C2 Error Interrupt
+ DCD SPI1_IRQHandler ; SPI1 Interrupt
+ DCD SPI2_IRQHandler ; SPI2 Interrupt
+ DCD USART1_IRQHandler ; USART1 Interrupt
+ DCD USART2_IRQHandler ; USART2 Interrupt
+ DCD LPUART1_IRQHandler ; LPUART1 Interrupt
+ DCD LPTIM1_IRQHandler ; LPTIM1 Global Interrupt
+ DCD LPTIM2_IRQHandler ; LPTIM2 Global Interrupt
+ DCD EXTI15_10_IRQHandler ; EXTI Lines [15:10] Interrupt
+ DCD RTC_Alarm_IRQHandler ; RTC Alarms (A and B) Interrupt
+ DCD LPTIM3_IRQHandler ; LPTIM3 Global Interrupt
+ DCD SUBGHZSPI_IRQHandler ; SUBGHZSPI Interrupt
+ DCD IPCC_C1_RX_IRQHandler ; IPCC CPU1 RX occupied interrupt
+ DCD IPCC_C1_TX_IRQHandler ; IPCC CPU1 RX free interrupt
+ DCD HSEM_IRQHandler ; HSEM0 Interrupt
+ DCD I2C3_EV_IRQHandler ; I2C3 Event Interrupt
+ DCD I2C3_ER_IRQHandler ; I2C3 Error Interrupt
+ DCD SUBGHZ_Radio_IRQHandler ; SUBGHZ Radio Interrupt
+ DCD AES_IRQHandler ; AES Interrupt
+ DCD RNG_IRQHandler ; RNG1 Interrupt
+ DCD PKA_IRQHandler ; PKA Interrupt
+ DCD DMA2_Channel1_IRQHandler ; DMA2 Channel 1 Interrupt
+ DCD DMA2_Channel2_IRQHandler ; DMA2 Channel 2 Interrupt
+ DCD DMA2_Channel3_IRQHandler ; DMA2 Channel 3 Interrupt
+ DCD DMA2_Channel4_IRQHandler ; DMA2 Channel 4 Interrupt
+ DCD DMA2_Channel5_IRQHandler ; DMA2 Channel 5 Interrupt
+ DCD DMA2_Channel6_IRQHandler ; DMA2 Channel 6 Interrupt
+ DCD DMA2_Channel7_IRQHandler ; DMA2 Channel 7 Interrupt
+ DCD DMAMUX1_OVR_IRQHandler ; DMAMUX overrun Interrupt
+
+;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;
+;;
+;; Default interrupt handlers.
+;;
+ THUMB
+
+ PUBWEAK Reset_Handler
+ SECTION .text:CODE:NOROOT:REORDER(2)
+Reset_Handler
+ LDR R0, =SystemInit
+ BLX R0
+ LDR R0, =__iar_program_start
+ BX R0
+
+ PUBWEAK NMI_Handler
+ SECTION .text:CODE:NOROOT:REORDER(1)
+NMI_Handler
+ B NMI_Handler
+
+ PUBWEAK HardFault_Handler
+ SECTION .text:CODE:NOROOT:REORDER(1)
+HardFault_Handler
+ B HardFault_Handler
+
+ PUBWEAK MemManage_Handler
+ SECTION .text:CODE:NOROOT:REORDER(1)
+MemManage_Handler
+ B MemManage_Handler
+
+ PUBWEAK BusFault_Handler
+ SECTION .text:CODE:NOROOT:REORDER(1)
+BusFault_Handler
+ B BusFault_Handler
+
+ PUBWEAK UsageFault_Handler
+ SECTION .text:CODE:NOROOT:REORDER(1)
+UsageFault_Handler
+ B UsageFault_Handler
+
+ PUBWEAK SVC_Handler
+ SECTION .text:CODE:NOROOT:REORDER(1)
+SVC_Handler
+ B SVC_Handler
+
+ PUBWEAK DebugMon_Handler
+ SECTION .text:CODE:NOROOT:REORDER(1)
+DebugMon_Handler
+ B DebugMon_Handler
+
+ PUBWEAK PendSV_Handler
+ SECTION .text:CODE:NOROOT:REORDER(1)
+PendSV_Handler
+ B PendSV_Handler
+
+ PUBWEAK SysTick_Handler
+ SECTION .text:CODE:NOROOT:REORDER(1)
+SysTick_Handler
+ B SysTick_Handler
+
+ PUBWEAK WWDG_IRQHandler
+ SECTION .text:CODE:NOROOT:REORDER(1)
+WWDG_IRQHandler
+ B WWDG_IRQHandler
+
+ PUBWEAK PVD_PVM_IRQHandler
+ SECTION .text:CODE:NOROOT:REORDER(1)
+PVD_PVM_IRQHandler
+ B PVD_PVM_IRQHandler
+
+ PUBWEAK TAMP_STAMP_LSECSS_SSRU_IRQHandler
+ SECTION .text:CODE:NOROOT:REORDER(1)
+TAMP_STAMP_LSECSS_SSRU_IRQHandler
+ B TAMP_STAMP_LSECSS_SSRU_IRQHandler
+
+ PUBWEAK RTC_WKUP_IRQHandler
+ SECTION .text:CODE:NOROOT:REORDER(1)
+RTC_WKUP_IRQHandler
+ B RTC_WKUP_IRQHandler
+
+ PUBWEAK FLASH_IRQHandler
+ SECTION .text:CODE:NOROOT:REORDER(1)
+FLASH_IRQHandler
+ B FLASH_IRQHandler
+
+ PUBWEAK RCC_IRQHandler
+ SECTION .text:CODE:NOROOT:REORDER(1)
+RCC_IRQHandler
+ B RCC_IRQHandler
+
+ PUBWEAK EXTI0_IRQHandler
+ SECTION .text:CODE:NOROOT:REORDER(1)
+EXTI0_IRQHandler
+ B EXTI0_IRQHandler
+
+ PUBWEAK EXTI1_IRQHandler
+ SECTION .text:CODE:NOROOT:REORDER(1)
+EXTI1_IRQHandler
+ B EXTI1_IRQHandler
+
+ PUBWEAK EXTI2_IRQHandler
+ SECTION .text:CODE:NOROOT:REORDER(1)
+EXTI2_IRQHandler
+ B EXTI2_IRQHandler
+
+ PUBWEAK EXTI3_IRQHandler
+ SECTION .text:CODE:NOROOT:REORDER(1)
+EXTI3_IRQHandler
+ B EXTI3_IRQHandler
+
+ PUBWEAK EXTI4_IRQHandler
+ SECTION .text:CODE:NOROOT:REORDER(1)
+EXTI4_IRQHandler
+ B EXTI4_IRQHandler
+
+ PUBWEAK DMA1_Channel1_IRQHandler
+ SECTION .text:CODE:NOROOT:REORDER(1)
+DMA1_Channel1_IRQHandler
+ B DMA1_Channel1_IRQHandler
+
+ PUBWEAK DMA1_Channel2_IRQHandler
+ SECTION .text:CODE:NOROOT:REORDER(1)
+DMA1_Channel2_IRQHandler
+ B DMA1_Channel2_IRQHandler
+
+ PUBWEAK DMA1_Channel3_IRQHandler
+ SECTION .text:CODE:NOROOT:REORDER(1)
+DMA1_Channel3_IRQHandler
+ B DMA1_Channel3_IRQHandler
+
+ PUBWEAK DMA1_Channel4_IRQHandler
+ SECTION .text:CODE:NOROOT:REORDER(1)
+DMA1_Channel4_IRQHandler
+ B DMA1_Channel4_IRQHandler
+
+ PUBWEAK DMA1_Channel5_IRQHandler
+ SECTION .text:CODE:NOROOT:REORDER(1)
+DMA1_Channel5_IRQHandler
+ B DMA1_Channel5_IRQHandler
+
+ PUBWEAK DMA1_Channel6_IRQHandler
+ SECTION .text:CODE:NOROOT:REORDER(1)
+DMA1_Channel6_IRQHandler
+ B DMA1_Channel6_IRQHandler
+
+ PUBWEAK DMA1_Channel7_IRQHandler
+ SECTION .text:CODE:NOROOT:REORDER(1)
+DMA1_Channel7_IRQHandler
+ B DMA1_Channel7_IRQHandler
+
+ PUBWEAK ADC_IRQHandler
+ SECTION .text:CODE:NOROOT:REORDER(1)
+ADC_IRQHandler
+ B ADC_IRQHandler
+
+ PUBWEAK DAC_IRQHandler
+ SECTION .text:CODE:NOROOT:REORDER(1)
+DAC_IRQHandler
+ B DAC_IRQHandler
+
+ PUBWEAK C2SEV_PWR_C2H_IRQHandler
+ SECTION .text:CODE:NOROOT:REORDER(1)
+C2SEV_PWR_C2H_IRQHandler
+ B C2SEV_PWR_C2H_IRQHandler
+
+ PUBWEAK COMP_IRQHandler
+ SECTION .text:CODE:NOROOT:REORDER(1)
+COMP_IRQHandler
+ B COMP_IRQHandler
+
+ PUBWEAK EXTI9_5_IRQHandler
+ SECTION .text:CODE:NOROOT:REORDER(1)
+EXTI9_5_IRQHandler
+ B EXTI9_5_IRQHandler
+
+ PUBWEAK TIM1_BRK_IRQHandler
+ SECTION .text:CODE:NOROOT:REORDER(1)
+TIM1_BRK_IRQHandler
+ B TIM1_BRK_IRQHandler
+
+ PUBWEAK TIM1_UP_IRQHandler
+ SECTION .text:CODE:NOROOT:REORDER(1)
+TIM1_UP_IRQHandler
+ B TIM1_UP_IRQHandler
+
+ PUBWEAK TIM1_TRG_COM_IRQHandler
+ SECTION .text:CODE:NOROOT:REORDER(1)
+TIM1_TRG_COM_IRQHandler
+ B TIM1_TRG_COM_IRQHandler
+
+ PUBWEAK TIM1_CC_IRQHandler
+ SECTION .text:CODE:NOROOT:REORDER(1)
+TIM1_CC_IRQHandler
+ B TIM1_CC_IRQHandler
+
+ PUBWEAK TIM2_IRQHandler
+ SECTION .text:CODE:NOROOT:REORDER(1)
+TIM2_IRQHandler
+ B TIM2_IRQHandler
+
+ PUBWEAK TIM16_IRQHandler
+ SECTION .text:CODE:NOROOT:REORDER(1)
+TIM16_IRQHandler
+ B TIM16_IRQHandler
+
+ PUBWEAK TIM17_IRQHandler
+ SECTION .text:CODE:NOROOT:REORDER(1)
+TIM17_IRQHandler
+ B TIM17_IRQHandler
+
+ PUBWEAK I2C1_EV_IRQHandler
+ SECTION .text:CODE:NOROOT:REORDER(1)
+I2C1_EV_IRQHandler
+ B I2C1_EV_IRQHandler
+
+ PUBWEAK I2C1_ER_IRQHandler
+ SECTION .text:CODE:NOROOT:REORDER(1)
+I2C1_ER_IRQHandler
+ B I2C1_ER_IRQHandler
+
+ PUBWEAK I2C2_EV_IRQHandler
+ SECTION .text:CODE:NOROOT:REORDER(1)
+I2C2_EV_IRQHandler
+ B I2C2_EV_IRQHandler
+
+ PUBWEAK I2C2_ER_IRQHandler
+ SECTION .text:CODE:NOROOT:REORDER(1)
+I2C2_ER_IRQHandler
+ B I2C2_ER_IRQHandler
+
+ PUBWEAK SPI1_IRQHandler
+ SECTION .text:CODE:NOROOT:REORDER(1)
+SPI1_IRQHandler
+ B SPI1_IRQHandler
+
+ PUBWEAK SPI2_IRQHandler
+ SECTION .text:CODE:NOROOT:REORDER(1)
+SPI2_IRQHandler
+ B SPI2_IRQHandler
+
+ PUBWEAK USART1_IRQHandler
+ SECTION .text:CODE:NOROOT:REORDER(1)
+USART1_IRQHandler
+ B USART1_IRQHandler
+
+ PUBWEAK USART2_IRQHandler
+ SECTION .text:CODE:NOROOT:REORDER(1)
+USART2_IRQHandler
+ B USART2_IRQHandler
+
+ PUBWEAK LPUART1_IRQHandler
+ SECTION .text:CODE:NOROOT:REORDER(1)
+LPUART1_IRQHandler
+ B LPUART1_IRQHandler
+
+ PUBWEAK LPTIM1_IRQHandler
+ SECTION .text:CODE:NOROOT:REORDER(1)
+LPTIM1_IRQHandler
+ B LPTIM1_IRQHandler
+
+ PUBWEAK LPTIM2_IRQHandler
+ SECTION .text:CODE:NOROOT:REORDER(1)
+LPTIM2_IRQHandler
+ B LPTIM2_IRQHandler
+
+ PUBWEAK EXTI15_10_IRQHandler
+ SECTION .text:CODE:NOROOT:REORDER(1)
+EXTI15_10_IRQHandler
+ B EXTI15_10_IRQHandler
+
+ PUBWEAK RTC_Alarm_IRQHandler
+ SECTION .text:CODE:NOROOT:REORDER(1)
+RTC_Alarm_IRQHandler
+ B RTC_Alarm_IRQHandler
+
+ PUBWEAK LPTIM3_IRQHandler
+ SECTION .text:CODE:NOROOT:REORDER(1)
+LPTIM3_IRQHandler
+ B LPTIM3_IRQHandler
+
+ PUBWEAK SUBGHZSPI_IRQHandler
+ SECTION .text:CODE:NOROOT:REORDER(1)
+SUBGHZSPI_IRQHandler
+ B SUBGHZSPI_IRQHandler
+
+ PUBWEAK IPCC_C1_RX_IRQHandler
+ SECTION .text:CODE:NOROOT:REORDER(1)
+IPCC_C1_RX_IRQHandler
+ B IPCC_C1_RX_IRQHandler
+
+ PUBWEAK IPCC_C1_TX_IRQHandler
+ SECTION .text:CODE:NOROOT:REORDER(1)
+IPCC_C1_TX_IRQHandler
+ B IPCC_C1_TX_IRQHandler
+
+ PUBWEAK HSEM_IRQHandler
+ SECTION .text:CODE:NOROOT:REORDER(1)
+HSEM_IRQHandler
+ B HSEM_IRQHandler
+
+ PUBWEAK I2C3_EV_IRQHandler
+ SECTION .text:CODE:NOROOT:REORDER(1)
+I2C3_EV_IRQHandler
+ B I2C3_EV_IRQHandler
+
+ PUBWEAK I2C3_ER_IRQHandler
+ SECTION .text:CODE:NOROOT:REORDER(1)
+I2C3_ER_IRQHandler
+ B I2C3_ER_IRQHandler
+
+ PUBWEAK SUBGHZ_Radio_IRQHandler
+ SECTION .text:CODE:NOROOT:REORDER(1)
+SUBGHZ_Radio_IRQHandler
+ B SUBGHZ_Radio_IRQHandler
+
+ PUBWEAK AES_IRQHandler
+ SECTION .text:CODE:NOROOT:REORDER(1)
+AES_IRQHandler
+ B AES_IRQHandler
+
+ PUBWEAK RNG_IRQHandler
+ SECTION .text:CODE:NOROOT:REORDER(1)
+RNG_IRQHandler
+ B RNG_IRQHandler
+
+ PUBWEAK PKA_IRQHandler
+ SECTION .text:CODE:NOROOT:REORDER(1)
+PKA_IRQHandler
+ B PKA_IRQHandler
+
+ PUBWEAK DMA2_Channel1_IRQHandler
+ SECTION .text:CODE:NOROOT:REORDER(1)
+DMA2_Channel1_IRQHandler
+ B DMA2_Channel1_IRQHandler
+
+ PUBWEAK DMA2_Channel2_IRQHandler
+ SECTION .text:CODE:NOROOT:REORDER(1)
+DMA2_Channel2_IRQHandler
+ B DMA2_Channel2_IRQHandler
+
+ PUBWEAK DMA2_Channel3_IRQHandler
+ SECTION .text:CODE:NOROOT:REORDER(1)
+DMA2_Channel3_IRQHandler
+ B DMA2_Channel3_IRQHandler
+
+ PUBWEAK DMA2_Channel4_IRQHandler
+ SECTION .text:CODE:NOROOT:REORDER(1)
+DMA2_Channel4_IRQHandler
+ B DMA2_Channel4_IRQHandler
+
+ PUBWEAK DMA2_Channel5_IRQHandler
+ SECTION .text:CODE:NOROOT:REORDER(1)
+DMA2_Channel5_IRQHandler
+ B DMA2_Channel5_IRQHandler
+
+ PUBWEAK DMA2_Channel6_IRQHandler
+ SECTION .text:CODE:NOROOT:REORDER(1)
+DMA2_Channel6_IRQHandler
+ B DMA2_Channel6_IRQHandler
+
+ PUBWEAK DMA2_Channel7_IRQHandler
+ SECTION .text:CODE:NOROOT:REORDER(1)
+DMA2_Channel7_IRQHandler
+ B DMA2_Channel7_IRQHandler
+
+ PUBWEAK DMAMUX1_OVR_IRQHandler
+ SECTION .text:CODE:NOROOT:REORDER(1)
+DMAMUX1_OVR_IRQHandler
+ B DMAMUX1_OVR_IRQHandler
+
+ END
+
+;************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE*****
diff --git a/targets/TARGET_STM/TARGET_STM32WL/TARGET_STM32WL54xC/TOOLCHAIN_IAR/stm32wl54xc.icf b/targets/TARGET_STM/TARGET_STM32WL/TARGET_STM32WL54xC/TOOLCHAIN_IAR/stm32wl54xc.icf
new file mode 100644
index 0000000..7fb4af2
--- /dev/null
+++ b/targets/TARGET_STM/TARGET_STM32WL/TARGET_STM32WL54xC/TOOLCHAIN_IAR/stm32wl54xc.icf
@@ -0,0 +1,59 @@
+/* Linker script to configure memory regions.
+ *
+ * SPDX-License-Identifier: BSD-3-Clause
+ ******************************************************************************
+ * @attention
+ *
+ * Copyright (c) 2016-2020 STMicroelectronics.
+ * All rights reserved.
+ *
+ * This software component is licensed by ST under BSD 3-Clause license,
+ * the "License"; You may not use this file except in compliance with the
+ * License. You may obtain a copy of the License at:
+ * opensource.org/licenses/BSD-3-Clause
+ *
+ ******************************************************************************
+*/
+/* Device specific values */
+
+/* Tools provide -DMBED_ROM_START=xxx -DMBED_ROM_SIZE=xxx -DMBED_RAM_START=xxx -DMBED_RAM_SIZE=xxx */
+
+define symbol VECTORS = 78; /* This value must match NVIC_NUM_VECTORS in cmsis_nvic.h */
+define symbol HEAP_SIZE = 0x1000;
+
+/* Common - Do not change */
+
+if (!isdefinedsymbol(MBED_APP_START)) {
+ define symbol MBED_APP_START = MBED_ROM_START;
+}
+
+if (!isdefinedsymbol(MBED_APP_SIZE)) {
+ define symbol MBED_APP_SIZE = MBED_ROM_SIZE;
+}
+
+if (!isdefinedsymbol(MBED_CONF_TARGET_BOOT_STACK_SIZE)) {
+ /* This value is normally defined by the tools
+ to 0x1000 for bare metal and 0x400 for RTOS */
+ define symbol MBED_CONF_TARGET_BOOT_STACK_SIZE = 0x400;
+}
+
+/* Round up VECTORS_SIZE to 8 bytes */
+define symbol VECTORS_SIZE = ((VECTORS * 4) + 7) & ~7;
+define symbol RAM_REGION_START = MBED_RAM_START + VECTORS_SIZE;
+define symbol RAM_REGION_SIZE = MBED_RAM_SIZE - VECTORS_SIZE;
+
+define memory mem with size = 4G;
+define region ROM_region = mem:[from MBED_APP_START size MBED_APP_SIZE];
+define region RAM_region = mem:[from RAM_REGION_START size RAM_REGION_SIZE];
+
+define block CSTACK with alignment = 8, size = MBED_CONF_TARGET_BOOT_STACK_SIZE { };
+define block HEAP with alignment = 8, size = HEAP_SIZE { };
+
+initialize by copy { readwrite };
+do not initialize { section .noinit };
+
+place at address mem: MBED_APP_START { readonly section .intvec };
+
+place in ROM_region { readonly };
+place in RAM_region { readwrite,
+ block CSTACK, block HEAP };
diff --git a/targets/TARGET_STM/TARGET_STM32WL/TARGET_STM32WL54xC/cmsis_nvic.h b/targets/TARGET_STM/TARGET_STM32WL/TARGET_STM32WL54xC/cmsis_nvic.h
new file mode 100644
index 0000000..a18342e
--- /dev/null
+++ b/targets/TARGET_STM/TARGET_STM32WL/TARGET_STM32WL54xC/cmsis_nvic.h
@@ -0,0 +1,39 @@
+/* mbed Microcontroller Library
+ * SPDX-License-Identifier: BSD-3-Clause
+ ******************************************************************************
+ * @attention
+ *
+ * © Copyright (c) 2016-2020 STMicroelectronics.
+ * All rights reserved.
+ *
+ * This software component is licensed by ST under BSD 3-Clause license,
+ * the "License"; You may not use this file except in compliance with the
+ * License. You may obtain a copy of the License at:
+ * opensource.org/licenses/BSD-3-Clause
+ *
+ ******************************************************************************
+*/
+
+#ifndef MBED_CMSIS_NVIC_H
+#define MBED_CMSIS_NVIC_H
+
+#if !defined(MBED_ROM_START)
+#define MBED_ROM_START 0x8000000
+#endif
+
+#if !defined(MBED_ROM_SIZE)
+#define MBED_ROM_SIZE 0x0 // 0 B
+#endif
+
+#if !defined(MBED_RAM_START)
+#define MBED_RAM_START 0x20000000
+#endif
+
+#if !defined(MBED_RAM_SIZE)
+#define MBED_RAM_SIZE 0x0 // 0 B
+#endif
+
+#define NVIC_NUM_VECTORS 78
+#define NVIC_RAM_VECTOR_ADDRESS MBED_RAM_START
+
+#endif
diff --git a/targets/TARGET_STM/TARGET_STM32WL/TARGET_STM32WL55xC/CMakeLists.txt b/targets/TARGET_STM/TARGET_STM32WL/TARGET_STM32WL55xC/CMakeLists.txt
new file mode 100644
index 0000000..9e15f9a
--- /dev/null
+++ b/targets/TARGET_STM/TARGET_STM32WL/TARGET_STM32WL55xC/CMakeLists.txt
@@ -0,0 +1,28 @@
+# Copyright (c) 2020 ARM Limited. All rights reserved.
+# SPDX-License-Identifier: Apache-2.0
+
+add_subdirectory(TARGET_NUCLEO_WL55JC EXCLUDE_FROM_ALL)
+
+if(${MBED_TOOLCHAIN} STREQUAL "GCC_ARM")
+ set(STARTUP_FILE TOOLCHAIN_GCC_ARM/startup_stm32wl55xx.S)
+ set(LINKER_FILE TOOLCHAIN_GCC_ARM/stm32wl55xc.ld)
+elseif(${MBED_TOOLCHAIN} STREQUAL "ARM")
+ set(STARTUP_FILE TOOLCHAIN_ARM/startup_stm32wl55xx.S)
+ set(LINKER_FILE TOOLCHAIN_ARM/stm32wl55xc.sct)
+endif()
+
+add_library(STM32WL55xC INTERFACE)
+
+target_sources(STM32WL55xC
+ INTERFACE
+ ${STARTUP_FILE}
+)
+
+target_include_directories(STM32WL55xC
+ INTERFACE
+ .
+)
+
+mbed_set_linker_script(STM32WL55xC ${CMAKE_CURRENT_SOURCE_DIR}/${LINKER_FILE})
+
+target_link_libraries(STM32WL55xC INTERFACE STM32WL)
diff --git a/targets/TARGET_STM/TARGET_STM32WL/TARGET_STM32WL55xC/TOOLCHAIN_ARM/startup_stm32wl55xx.S b/targets/TARGET_STM/TARGET_STM32WL/TARGET_STM32WL55xC/TOOLCHAIN_ARM/startup_stm32wl55xx.S
new file mode 100644
index 0000000..95c90b5
--- /dev/null
+++ b/targets/TARGET_STM/TARGET_STM32WL/TARGET_STM32WL55xC/TOOLCHAIN_ARM/startup_stm32wl55xx.S
@@ -0,0 +1,320 @@
+;******************************************************************************
+;* File Name : startup_stm32wl55xx_cm4.s
+;* Author : MCD Application Team
+;* Description : STM32WL55xx devices vector table for MDK-ARM toolchain.
+;* This module performs:
+;* - Set the initial SP
+;* - Set the initial PC == Reset_Handler
+;* - Set the vector table entries with the exceptions ISR address
+;* - Branches to __main in the C library (which eventually
+;* calls main()).
+;* After Reset the CortexM4 processor is in Thread mode,
+;* priority is Privileged, and the Stack is set to Main.
+;* <<< Use Configuration Wizard in Context Menu >>>
+;******************************************************************************
+;* @attention
+;*
+;* Copyright (c) 2020 STMicroelectronics. All rights reserved.
+;*
+;* This software component is licensed by ST under Apache License, Version 2.0,
+;* the "License"; You may not use this file except in compliance with the
+;* License. You may obtain a copy of the License at:
+;* opensource.org/licenses/Apache-2.0
+;*
+;******************************************************************************
+
+ PRESERVE8
+ THUMB
+
+
+; Vector Table Mapped to Address 0 at Reset
+ AREA RESET, DATA, READONLY
+ EXPORT __Vectors
+ EXPORT __Vectors_End
+ EXPORT __Vectors_Size
+
+ IMPORT |Image$$ARM_LIB_STACK$$ZI$$Limit|
+__Vectors DCD |Image$$ARM_LIB_STACK$$ZI$$Limit| ; Top of Stack
+ DCD Reset_Handler ; Reset Handler
+ DCD NMI_Handler ; NMI Handler
+ DCD HardFault_Handler ; Hard Fault Handler
+ DCD MemManage_Handler ; MPU Fault Handler
+ DCD BusFault_Handler ; Bus Fault Handler
+ DCD UsageFault_Handler ; Usage Fault Handler
+ DCD 0 ; Reserved
+ DCD 0 ; Reserved
+ DCD 0 ; Reserved
+ DCD 0 ; Reserved
+ DCD SVC_Handler ; SVCall Handler
+ DCD DebugMon_Handler ; Debug Monitor Handler
+ DCD 0 ; Reserved
+ DCD PendSV_Handler ; PendSV Handler
+ DCD SysTick_Handler ; SysTick Handler
+
+ ; External Interrupts
+ DCD WWDG_IRQHandler ; Window WatchDog
+ DCD PVD_PVM_IRQHandler ; PVD and PVM detector
+ DCD TAMP_STAMP_LSECSS_SSRU_IRQHandler ; RTC Tamper, RTC TimeStamp, LSECSS and RTC SSR Underflow Interrupts
+ DCD RTC_WKUP_IRQHandler ; RTC Wakeup Interrupt
+ DCD FLASH_IRQHandler ; FLASH global Interrupt
+ DCD RCC_IRQHandler ; RCC Interrupt
+ DCD EXTI0_IRQHandler ; EXTI Line 0 Interrupt
+ DCD EXTI1_IRQHandler ; EXTI Line 1 Interrupt
+ DCD EXTI2_IRQHandler ; EXTI Line 2 Interrupt
+ DCD EXTI3_IRQHandler ; EXTI Line 3 Interrup
+ DCD EXTI4_IRQHandler ; EXTI Line 4 Interrupt
+ DCD DMA1_Channel1_IRQHandler ; DMA1 Channel 1 Interrupt
+ DCD DMA1_Channel2_IRQHandler ; DMA1 Channel 2 Interrupt
+ DCD DMA1_Channel3_IRQHandler ; DMA1 Channel 3 Interrupt
+ DCD DMA1_Channel4_IRQHandler ; DMA1 Channel 4 Interrupt
+ DCD DMA1_Channel5_IRQHandler ; DMA1 Channel 5 Interrupt
+ DCD DMA1_Channel6_IRQHandler ; DMA1 Channel 6 Interrupt
+ DCD DMA1_Channel7_IRQHandler ; DMA1 Channel 7 Interrupt
+ DCD ADC_IRQHandler ; ADC Interrupt
+ DCD DAC_IRQHandler ; DAC Interrupt
+ DCD C2SEV_PWR_C2H_IRQHandler ; CPU M0+ SEV and PWR CPU M0+ HOLD wakeup Interrupt
+ DCD COMP_IRQHandler ; COMP1 and COMP2 Interrupts
+ DCD EXTI9_5_IRQHandler ; EXTI Lines [9:5] Interrupt
+ DCD TIM1_BRK_IRQHandler ; TIM1 Break Interrupt
+ DCD TIM1_UP_IRQHandler ; TIM1 Update Interrupts
+ DCD TIM1_TRG_COM_IRQHandler ; TIM1 Trigger and Communication Interrupts
+ DCD TIM1_CC_IRQHandler ; TIM1 Capture Compare Interrupt
+ DCD TIM2_IRQHandler ; TIM2 Global Interrupt
+ DCD TIM16_IRQHandler ; TIM16 Global Interrupt
+ DCD TIM17_IRQHandler ; TIM17 Global Interrupt
+ DCD I2C1_EV_IRQHandler ; I2C1 Event Interrupt
+ DCD I2C1_ER_IRQHandler ; I2C1 Error Interrupt
+ DCD I2C2_EV_IRQHandler ; I2C2 Event Interrupt
+ DCD I2C2_ER_IRQHandler ; I2C2 Error Interrupt
+ DCD SPI1_IRQHandler ; SPI1 Interrupt
+ DCD SPI2_IRQHandler ; SPI2 Interrupt
+ DCD USART1_IRQHandler ; USART1 Interrupt
+ DCD USART2_IRQHandler ; USART2 Interrupt
+ DCD LPUART1_IRQHandler ; LPUART1 Interrupt
+ DCD LPTIM1_IRQHandler ; LPTIM1 Interrupt
+ DCD LPTIM2_IRQHandler ; LPTIM2 Interrupt
+ DCD EXTI15_10_IRQHandler ; EXTI Lines1[15:10 ]Interrupts
+ DCD RTC_Alarm_IRQHandler ; RTC Alarms (A and B) Interrupt
+ DCD LPTIM3_IRQHandler ; LPTIM3 Interrupt
+ DCD SUBGHZSPI_IRQHandler ; SUBGHZSPI Interrupt
+ DCD IPCC_C1_RX_IRQHandler ; IPCC CPU1 RX occupied interrupt
+ DCD IPCC_C1_TX_IRQHandler ; IPCC CPU1 RX free interrupt
+ DCD HSEM_IRQHandler ; HSEM0 Interrupt
+ DCD I2C3_EV_IRQHandler ; I2C3 Event Interrupt
+ DCD I2C3_ER_IRQHandler ; I2C3 Error Interrupt
+ DCD SUBGHZ_Radio_IRQHandler ; SUBGHZ Radio Interrupt
+ DCD AES_IRQHandler ; AES Interrupt
+ DCD RNG_IRQHandler ; RNG1 Interrupt
+ DCD PKA_IRQHandler ; PKA Interrupt
+ DCD DMA2_Channel1_IRQHandler ; DMA2 Channel 1 Interrupt
+ DCD DMA2_Channel2_IRQHandler ; DMA2 Channel 2 Interrupt
+ DCD DMA2_Channel3_IRQHandler ; DMA2 Channel 3 Interrupt
+ DCD DMA2_Channel4_IRQHandler ; DMA2 Channel 4 Interrupt
+ DCD DMA2_Channel5_IRQHandler ; DMA2 Channel 5 Interrupt
+ DCD DMA2_Channel6_IRQHandler ; DMA2 Channel 6 Interrupt
+ DCD DMA2_Channel7_IRQHandler ; DMA2 Channel 7 Interrupt
+ DCD DMAMUX1_OVR_IRQHandler ; DMAMUX overrun Interrupt
+
+__Vectors_End
+
+__Vectors_Size EQU __Vectors_End - __Vectors
+
+ AREA |.text|, CODE, READONLY
+
+; Reset handler
+Reset_Handler PROC
+ EXPORT Reset_Handler [WEAK]
+ IMPORT SystemInit
+ IMPORT __main
+
+ LDR R0, =SystemInit
+ BLX R0
+ LDR R0, =__main
+ BX R0
+ ENDP
+
+; Dummy Exception Handlers (infinite loops which can be modified)
+
+NMI_Handler PROC
+ EXPORT NMI_Handler [WEAK]
+ B .
+ ENDP
+HardFault_Handler\
+ PROC
+ EXPORT HardFault_Handler [WEAK]
+ B .
+ ENDP
+MemManage_Handler\
+ PROC
+ EXPORT MemManage_Handler [WEAK]
+ B .
+ ENDP
+BusFault_Handler\
+ PROC
+ EXPORT BusFault_Handler [WEAK]
+ B .
+ ENDP
+UsageFault_Handler\
+ PROC
+ EXPORT UsageFault_Handler [WEAK]
+ B .
+ ENDP
+SVC_Handler PROC
+ EXPORT SVC_Handler [WEAK]
+ B .
+ ENDP
+DebugMon_Handler\
+ PROC
+ EXPORT DebugMon_Handler [WEAK]
+ B .
+ ENDP
+PendSV_Handler PROC
+ EXPORT PendSV_Handler [WEAK]
+ B .
+ ENDP
+SysTick_Handler PROC
+ EXPORT SysTick_Handler [WEAK]
+ B .
+ ENDP
+
+Default_Handler PROC
+
+ EXPORT WWDG_IRQHandler [WEAK]
+ EXPORT PVD_PVM_IRQHandler [WEAK]
+ EXPORT TAMP_STAMP_LSECSS_SSRU_IRQHandler [WEAK]
+ EXPORT RTC_WKUP_IRQHandler [WEAK]
+ EXPORT FLASH_IRQHandler [WEAK]
+ EXPORT RCC_IRQHandler [WEAK]
+ EXPORT EXTI0_IRQHandler [WEAK]
+ EXPORT EXTI1_IRQHandler [WEAK]
+ EXPORT EXTI2_IRQHandler [WEAK]
+ EXPORT EXTI3_IRQHandler [WEAK]
+ EXPORT EXTI4_IRQHandler [WEAK]
+ EXPORT DMA1_Channel1_IRQHandler [WEAK]
+ EXPORT DMA1_Channel2_IRQHandler [WEAK]
+ EXPORT DMA1_Channel3_IRQHandler [WEAK]
+ EXPORT DMA1_Channel4_IRQHandler [WEAK]
+ EXPORT DMA1_Channel5_IRQHandler [WEAK]
+ EXPORT DMA1_Channel6_IRQHandler [WEAK]
+ EXPORT DMA1_Channel7_IRQHandler [WEAK]
+ EXPORT ADC_IRQHandler [WEAK]
+ EXPORT DAC_IRQHandler [WEAK]
+ EXPORT C2SEV_PWR_C2H_IRQHandler [WEAK]
+ EXPORT COMP_IRQHandler [WEAK]
+ EXPORT EXTI9_5_IRQHandler [WEAK]
+ EXPORT TIM1_BRK_IRQHandler [WEAK]
+ EXPORT TIM1_UP_IRQHandler [WEAK]
+ EXPORT TIM1_TRG_COM_IRQHandler [WEAK]
+ EXPORT TIM1_CC_IRQHandler [WEAK]
+ EXPORT TIM2_IRQHandler [WEAK]
+ EXPORT TIM16_IRQHandler [WEAK]
+ EXPORT TIM17_IRQHandler [WEAK]
+ EXPORT I2C1_EV_IRQHandler [WEAK]
+ EXPORT I2C1_ER_IRQHandler [WEAK]
+ EXPORT I2C2_EV_IRQHandler [WEAK]
+ EXPORT I2C2_ER_IRQHandler [WEAK]
+ EXPORT SPI1_IRQHandler [WEAK]
+ EXPORT SPI2_IRQHandler [WEAK]
+ EXPORT USART1_IRQHandler [WEAK]
+ EXPORT USART2_IRQHandler [WEAK]
+ EXPORT LPUART1_IRQHandler [WEAK]
+ EXPORT LPTIM1_IRQHandler [WEAK]
+ EXPORT LPTIM2_IRQHandler [WEAK]
+ EXPORT EXTI15_10_IRQHandler [WEAK]
+ EXPORT RTC_Alarm_IRQHandler [WEAK]
+ EXPORT LPTIM3_IRQHandler [WEAK]
+ EXPORT SUBGHZSPI_IRQHandler [WEAK]
+ EXPORT IPCC_C1_RX_IRQHandler [WEAK]
+ EXPORT IPCC_C1_TX_IRQHandler [WEAK]
+ EXPORT HSEM_IRQHandler [WEAK]
+ EXPORT I2C3_EV_IRQHandler [WEAK]
+ EXPORT I2C3_ER_IRQHandler [WEAK]
+ EXPORT SUBGHZ_Radio_IRQHandler [WEAK]
+ EXPORT AES_IRQHandler [WEAK]
+ EXPORT RNG_IRQHandler [WEAK]
+ EXPORT PKA_IRQHandler [WEAK]
+ EXPORT DMA2_Channel1_IRQHandler [WEAK]
+ EXPORT DMA2_Channel2_IRQHandler [WEAK]
+ EXPORT DMA2_Channel3_IRQHandler [WEAK]
+ EXPORT DMA2_Channel4_IRQHandler [WEAK]
+ EXPORT DMA2_Channel5_IRQHandler [WEAK]
+ EXPORT DMA2_Channel6_IRQHandler [WEAK]
+ EXPORT DMA2_Channel7_IRQHandler [WEAK]
+ EXPORT DMAMUX1_OVR_IRQHandler [WEAK]
+
+WWDG_IRQHandler
+PVD_PVM_IRQHandler
+TAMP_STAMP_LSECSS_SSRU_IRQHandler
+RTC_WKUP_IRQHandler
+FLASH_IRQHandler
+RCC_IRQHandler
+EXTI0_IRQHandler
+EXTI1_IRQHandler
+EXTI2_IRQHandler
+EXTI3_IRQHandler
+EXTI4_IRQHandler
+DMA1_Channel1_IRQHandler
+DMA1_Channel2_IRQHandler
+DMA1_Channel3_IRQHandler
+DMA1_Channel4_IRQHandler
+DMA1_Channel5_IRQHandler
+DMA1_Channel6_IRQHandler
+DMA1_Channel7_IRQHandler
+ADC_IRQHandler
+DAC_IRQHandler
+C2SEV_PWR_C2H_IRQHandler
+COMP_IRQHandler
+EXTI9_5_IRQHandler
+TIM1_BRK_IRQHandler
+TIM1_UP_IRQHandler
+TIM1_TRG_COM_IRQHandler
+TIM1_CC_IRQHandler
+TIM2_IRQHandler
+TIM16_IRQHandler
+TIM17_IRQHandler
+I2C1_EV_IRQHandler
+I2C1_ER_IRQHandler
+I2C2_EV_IRQHandler
+I2C2_ER_IRQHandler
+SPI1_IRQHandler
+SPI2_IRQHandler
+USART1_IRQHandler
+USART2_IRQHandler
+LPUART1_IRQHandler
+LPTIM1_IRQHandler
+LPTIM2_IRQHandler
+EXTI15_10_IRQHandler
+RTC_Alarm_IRQHandler
+LPTIM3_IRQHandler
+SUBGHZSPI_IRQHandler
+IPCC_C1_RX_IRQHandler
+IPCC_C1_TX_IRQHandler
+HSEM_IRQHandler
+I2C3_EV_IRQHandler
+I2C3_ER_IRQHandler
+SUBGHZ_Radio_IRQHandler
+AES_IRQHandler
+RNG_IRQHandler
+PKA_IRQHandler
+DMA2_Channel1_IRQHandler
+DMA2_Channel2_IRQHandler
+DMA2_Channel3_IRQHandler
+DMA2_Channel4_IRQHandler
+DMA2_Channel5_IRQHandler
+DMA2_Channel6_IRQHandler
+DMA2_Channel7_IRQHandler
+DMAMUX1_OVR_IRQHandler
+
+ B .
+
+ ENDP
+
+ ALIGN
+
+;*******************************************************************************
+; User Stack and Heap initialization
+;*******************************************************************************
+
+ END
+
+;************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE*****
diff --git a/targets/TARGET_STM/TARGET_STM32WL/TARGET_STM32WL55xC/TOOLCHAIN_ARM/stm32wl55xc.sct b/targets/TARGET_STM/TARGET_STM32WL/TARGET_STM32WL55xC/TOOLCHAIN_ARM/stm32wl55xc.sct
new file mode 100644
index 0000000..9258e6a
--- /dev/null
+++ b/targets/TARGET_STM/TARGET_STM32WL/TARGET_STM32WL55xC/TOOLCHAIN_ARM/stm32wl55xc.sct
@@ -0,0 +1,57 @@
+#! armclang -E --target=arm-arm-none-eabi -x c -mcpu=cortex-M4
+; Scatter-Loading Description File
+;
+; SPDX-License-Identifier: BSD-3-Clause
+;******************************************************************************
+;* @attention
+;*
+;* Copyright (c) 2016-2020 STMicroelectronics.
+;* All rights reserved.
+;*
+;* This software component is licensed by ST under BSD 3-Clause license,
+;* the "License"; You may not use this file except in compliance with the
+;* License. You may obtain a copy of the License at:
+;* opensource.org/licenses/BSD-3-Clause
+;*
+;******************************************************************************
+
+#include "../cmsis_nvic.h"
+
+#if !defined(MBED_APP_START)
+ #define MBED_APP_START MBED_ROM_START
+#endif
+
+#if !defined(MBED_APP_SIZE)
+ #define MBED_APP_SIZE MBED_ROM_SIZE
+#endif
+
+#if !defined(MBED_CONF_TARGET_BOOT_STACK_SIZE)
+/* This value is normally defined by the tools to 0x1000 for bare metal and 0x400 for RTOS */
+#if defined(MBED_BOOT_STACK_SIZE)
+#define MBED_CONF_TARGET_BOOT_STACK_SIZE MBED_BOOT_STACK_SIZE
+#else
+#define MBED_CONF_TARGET_BOOT_STACK_SIZE 0x400
+#endif
+#endif
+
+/* Round up VECTORS_SIZE to 8 bytes */
+#define VECTORS_SIZE (((NVIC_NUM_VECTORS * 4) + 7) AND ~7)
+
+LR_IROM1 MBED_APP_START MBED_APP_SIZE {
+
+ ER_IROM1 MBED_APP_START MBED_APP_SIZE {
+ *.o (RESET, +First)
+ *(InRoot$$Sections)
+ .ANY (+RO)
+ }
+
+ RW_IRAM1 (MBED_RAM_START + VECTORS_SIZE) { ; RW data
+ .ANY (+RW +ZI)
+ }
+
+ ARM_LIB_HEAP AlignExpr(+0, 16) EMPTY (MBED_RAM_START + MBED_RAM_SIZE - MBED_CONF_TARGET_BOOT_STACK_SIZE - AlignExpr(ImageLimit(RW_IRAM1), 16)) { ; Heap growing up
+ }
+
+ ARM_LIB_STACK (MBED_RAM_START + MBED_RAM_SIZE) EMPTY -MBED_CONF_TARGET_BOOT_STACK_SIZE { ; Stack region growing down
+ }
+}
diff --git a/targets/TARGET_STM/TARGET_STM32WL/TARGET_STM32WL55xC/TOOLCHAIN_GCC_ARM/startup_stm32wl55xx.S b/targets/TARGET_STM/TARGET_STM32WL/TARGET_STM32WL55xC/TOOLCHAIN_GCC_ARM/startup_stm32wl55xx.S
new file mode 100644
index 0000000..350c3da
--- /dev/null
+++ b/targets/TARGET_STM/TARGET_STM32WL/TARGET_STM32WL55xC/TOOLCHAIN_GCC_ARM/startup_stm32wl55xx.S
@@ -0,0 +1,434 @@
+/**
+ ******************************************************************************
+ * @file startup_stm32wl55xx_cm4.s
+ * @author MCD Application Team
+ * @brief STM32WL55xx devices Cortex-M4 vector table for GCC toolchain.
+ * This module performs:
+ * - Set the initial SP
+ * - Set the initial PC == Reset_Handler,
+ * - Set the vector table entries with the exceptions ISR address,
+ * - Branches to main in the C library (which eventually
+ * calls main()).
+ * After Reset the Cortex-M4 processor is in Thread mode,
+ * priority is Privileged, and the Stack is set to Main.
+ ******************************************************************************
+ * @attention
+ *
+ * © Copyright (c) 2020 STMicroelectronics.
+ * All rights reserved.
+ *
+ * This software component is licensed by ST under Apache License, Version 2.0,
+ * the "License"; You may not use this file except in compliance with the
+ * License. You may obtain a copy of the License at:
+ * opensource.org/licenses/Apache-2.0
+ *
+ ******************************************************************************
+ */
+
+.syntax unified
+.cpu cortex-m4
+.fpu softvfp
+.thumb
+
+.global g_pfnVectors
+.global Default_Handler
+
+/* start address for the initialization values of the .data section.
+defined in linker script */
+.word _sidata
+/* start address for the .data section. defined in linker script */
+.word _sdata
+/* end address for the .data section. defined in linker script */
+.word _edata
+/* start address for the .bss section. defined in linker script */
+.word _sbss
+/* end address for the .bss section. defined in linker script */
+.word _ebss
+
+/**
+ * @brief This is the code that gets called when the processor first
+ * starts execution following a reset event. Only the absolutely
+ * necessary set is performed, after which the application
+ * supplied main() routine is called.
+ * @param None
+ * @retval : None
+*/
+
+ .section .text.Reset_Handler
+ .weak Reset_Handler
+ .type Reset_Handler, %function
+Reset_Handler:
+ ldr r0, =_estack
+ mov sp, r0 /* set stack pointer */
+
+/* Call the clock system initialization function.*/
+ bl SystemInit
+
+/* Copy the data segment initializers from flash to SRAM */
+ ldr r0, =_sdata
+ ldr r1, =_edata
+ ldr r2, =_sidata
+ movs r3, #0
+ b LoopCopyDataInit
+
+CopyDataInit:
+ ldr r4, [r2, r3]
+ str r4, [r0, r3]
+ adds r3, r3, #4
+
+LoopCopyDataInit:
+ adds r4, r0, r3
+ cmp r4, r1
+ bcc CopyDataInit
+
+/* Zero fill the bss segment. */
+ ldr r2, =_sbss
+ ldr r4, =_ebss
+ movs r3, #0
+ b LoopFillZerobss
+
+FillZerobss:
+ str r3, [r2]
+ adds r2, r2, #4
+
+LoopFillZerobss:
+ cmp r2, r4
+ bcc FillZerobss
+
+ bl _start
+ bx lr
+
+LoopForever:
+ b LoopForever
+
+ .size Reset_Handler, .-Reset_Handler
+
+/**
+ * @brief This is the code that gets called when the processor receives an
+ * unexpected interrupt. This simply enters an infinite loop, preserving
+ * the system state for examination by a debugger.
+ *
+ * @param None
+ * @retval : None
+*/
+ .section .text.Default_Handler,"ax",%progbits
+Default_Handler:
+Infinite_Loop:
+ b Infinite_Loop
+ .size Default_Handler, .-Default_Handler
+
+/******************************************************************************
+*
+* The STM32WL55xx Cortex-M4 vector table. Note that the proper constructs
+* must be placed on this to ensure that it ends up at physical address
+* 0x0000.0000.
+*
+******************************************************************************/
+ .section .isr_vector,"a",%progbits
+ .type g_pfnVectors, %object
+ .size g_pfnVectors, .-g_pfnVectors
+
+g_pfnVectors:
+ .word _estack
+ .word Reset_Handler
+ .word NMI_Handler
+ .word HardFault_Handler
+ .word MemManage_Handler
+ .word BusFault_Handler
+ .word UsageFault_Handler
+ .word 0
+ .word 0
+ .word 0
+ .word 0
+ .word SVC_Handler
+ .word DebugMon_Handler
+ .word 0
+ .word PendSV_Handler
+ .word SysTick_Handler
+ .word WWDG_IRQHandler /* Window Watchdog interrupt */
+ .word PVD_PVM_IRQHandler /* PVD and PVM interrupt through EXTI */
+ .word TAMP_STAMP_LSECSS_SSRU_IRQHandler /* RTC Tamper, RTC TimeStamp, LSECSS and RTC SSRU int.*/
+ .word RTC_WKUP_IRQHandler /* RTC wakeup interrupt through EXTI[19] */
+ .word FLASH_IRQHandler /* Flash memory global interrupt and Flash memory ECC */
+ .word RCC_IRQHandler /* RCC global interrupt */
+ .word EXTI0_IRQHandler /* EXTI line 0 interrupt */
+ .word EXTI1_IRQHandler /* EXTI line 1 interrupt */
+ .word EXTI2_IRQHandler /* EXTI line 2 interrupt */
+ .word EXTI3_IRQHandler /* EXTI line 3 interrupt */
+ .word EXTI4_IRQHandler /* EXTI line 4 interrupt */
+ .word DMA1_Channel1_IRQHandler /* DMA1 channel 1 interrupt */
+ .word DMA1_Channel2_IRQHandler /* DMA1 channel 2 interrupt */
+ .word DMA1_Channel3_IRQHandler /* DMA1 channel 3 interrupt */
+ .word DMA1_Channel4_IRQHandler /* DMA1 channel 4 interrupt */
+ .word DMA1_Channel5_IRQHandler /* DMA1 channel 5 interrupt */
+ .word DMA1_Channel6_IRQHandler /* DMA1 channel 6 interrupt */
+ .word DMA1_Channel7_IRQHandler /* DMA1 channel 7 interrupt */
+ .word ADC_IRQHandler /* ADC interrupt */
+ .word DAC_IRQHandler /* DAC interrupt */
+ .word C2SEV_PWR_C2H_IRQHandler /* CPU M0+ SEV Interrupt */
+ .word COMP_IRQHandler /* COMP1 and COMP2 interrupt through EXTI */
+ .word EXTI9_5_IRQHandler /* EXTI line 9_5 interrupt */
+ .word TIM1_BRK_IRQHandler /* Timer 1 break interrupt */
+ .word TIM1_UP_IRQHandler /* Timer 1 Update */
+ .word TIM1_TRG_COM_IRQHandler /* Timer 1 trigger and communication */
+ .word TIM1_CC_IRQHandler /* Timer 1 capture compare interrupt */
+ .word TIM2_IRQHandler /* TIM2 global interrupt */
+ .word TIM16_IRQHandler /* Timer 16 global interrupt */
+ .word TIM17_IRQHandler /* Timer 17 global interrupt */
+ .word I2C1_EV_IRQHandler /* I2C1 event interrupt */
+ .word I2C1_ER_IRQHandler /* I2C1 event interrupt */
+ .word I2C2_EV_IRQHandler /* I2C2 error interrupt */
+ .word I2C2_ER_IRQHandler /* I2C2 error interrupt */
+ .word SPI1_IRQHandler /* SPI1 global interrupt */
+ .word SPI2_IRQHandler /* SPI2 global interrupt */
+ .word USART1_IRQHandler /* USART1 global interrupt */
+ .word USART2_IRQHandler /* USART2 global interrupt */
+ .word LPUART1_IRQHandler /* LPUART1 global interrupt */
+ .word LPTIM1_IRQHandler /* LPtimer 1 global interrupt */
+ .word LPTIM2_IRQHandler /* LPtimer 2 global interrupt */
+ .word EXTI15_10_IRQHandler /* EXTI line 15_10] interrupt through EXTI */
+ .word RTC_Alarm_IRQHandler /* RTC Alarms A & B interrupt */
+ .word LPTIM3_IRQHandler /* LPtimer 3 global interrupt */
+ .word SUBGHZSPI_IRQHandler /* SUBGHZSPI global interrupt */
+ .word IPCC_C1_RX_IRQHandler /* IPCC CPU1 RX occupied interrupt */
+ .word IPCC_C1_TX_IRQHandler /* IPCC CPU1 RX free interrupt */
+ .word HSEM_IRQHandler /* Semaphore interrupt 0 to CPU1 */
+ .word I2C3_EV_IRQHandler /* I2C3 event interrupt */
+ .word I2C3_ER_IRQHandler /* I2C3 error interrupt */
+ .word SUBGHZ_Radio_IRQHandler /* Radio IRQs RFBUSY interrupt through EXTI */
+ .word AES_IRQHandler /* AES global interrupt */
+ .word RNG_IRQHandler /* RNG interrupt */
+ .word PKA_IRQHandler /* PKA interrupt */
+ .word DMA2_Channel1_IRQHandler /* DMA2 channel 1 interrupt */
+ .word DMA2_Channel2_IRQHandler /* DMA2 channel 2 interrupt */
+ .word DMA2_Channel3_IRQHandler /* DMA2 channel 3 interrupt */
+ .word DMA2_Channel4_IRQHandler /* DMA2 channel 4 interrupt */
+ .word DMA2_Channel5_IRQHandler /* DMA2 channel 5 interrupt */
+ .word DMA2_Channel6_IRQHandler /* DMA2 channel 6 interrupt */
+ .word DMA2_Channel7_IRQHandler /* DMA2 channel 7 interrupt */
+ .word DMAMUX1_OVR_IRQHandler /* DMAMUX overrun interrupt */
+
+/*******************************************************************************
+*
+* Provide weak aliases for each Exception handler to the Default_Handler.
+* As they are weak aliases, any function with the same name will override
+* this definition.
+*
+*******************************************************************************/
+
+ .weak NMI_Handler
+ .thumb_set NMI_Handler,Default_Handler
+
+ .weak HardFault_Handler
+ .thumb_set HardFault_Handler,Default_Handler
+
+ .weak MemManage_Handler
+ .thumb_set MemManage_Handler,Default_Handler
+
+ .weak BusFault_Handler
+ .thumb_set BusFault_Handler,Default_Handler
+
+ .weak UsageFault_Handler
+ .thumb_set UsageFault_Handler,Default_Handler
+
+ .weak SVC_Handler
+ .thumb_set SVC_Handler,Default_Handler
+
+ .weak DebugMon_Handler
+ .thumb_set DebugMon_Handler,Default_Handler
+
+ .weak PendSV_Handler
+ .thumb_set PendSV_Handler,Default_Handler
+
+ .weak SysTick_Handler
+ .thumb_set SysTick_Handler,Default_Handler
+
+ .weak WWDG_IRQHandler
+ .thumb_set WWDG_IRQHandler,Default_Handler
+
+ .weak PVD_PVM_IRQHandler
+ .thumb_set PVD_PVM_IRQHandler,Default_Handler
+
+ .weak TAMP_STAMP_LSECSS_SSRU_IRQHandler
+ .thumb_set TAMP_STAMP_LSECSS_SSRU_IRQHandler,Default_Handler
+
+ .weak RTC_WKUP_IRQHandler
+ .thumb_set RTC_WKUP_IRQHandler,Default_Handler
+
+ .weak FLASH_IRQHandler
+ .thumb_set FLASH_IRQHandler,Default_Handler
+
+ .weak RCC_IRQHandler
+ .thumb_set RCC_IRQHandler,Default_Handler
+
+ .weak EXTI0_IRQHandler
+ .thumb_set EXTI0_IRQHandler,Default_Handler
+
+ .weak EXTI1_IRQHandler
+ .thumb_set EXTI1_IRQHandler,Default_Handler
+
+ .weak EXTI2_IRQHandler
+ .thumb_set EXTI2_IRQHandler,Default_Handler
+
+ .weak EXTI3_IRQHandler
+ .thumb_set EXTI3_IRQHandler,Default_Handler
+
+ .weak EXTI4_IRQHandler
+ .thumb_set EXTI4_IRQHandler,Default_Handler
+
+ .weak DMA1_Channel1_IRQHandler
+ .thumb_set DMA1_Channel1_IRQHandler,Default_Handler
+
+ .weak DMA1_Channel2_IRQHandler
+ .thumb_set DMA1_Channel2_IRQHandler,Default_Handler
+
+ .weak DMA1_Channel3_IRQHandler
+ .thumb_set DMA1_Channel3_IRQHandler,Default_Handler
+
+ .weak DMA1_Channel4_IRQHandler
+ .thumb_set DMA1_Channel4_IRQHandler,Default_Handler
+
+ .weak DMA1_Channel5_IRQHandler
+ .thumb_set DMA1_Channel5_IRQHandler,Default_Handler
+
+ .weak DMA1_Channel6_IRQHandler
+ .thumb_set DMA1_Channel6_IRQHandler,Default_Handler
+
+ .weak DMA1_Channel7_IRQHandler
+ .thumb_set DMA1_Channel7_IRQHandler,Default_Handler
+
+ .weak ADC_IRQHandler
+ .thumb_set ADC_IRQHandler,Default_Handler
+
+ .weak DAC_IRQHandler
+ .thumb_set DAC_IRQHandler,Default_Handler
+
+ .weak C2SEV_PWR_C2H_IRQHandler
+ .thumb_set C2SEV_PWR_C2H_IRQHandler,Default_Handler
+
+ .weak COMP_IRQHandler
+ .thumb_set COMP_IRQHandler,Default_Handler
+
+ .weak EXTI9_5_IRQHandler
+ .thumb_set EXTI9_5_IRQHandler,Default_Handler
+
+ .weak TIM1_BRK_IRQHandler
+ .thumb_set TIM1_BRK_IRQHandler,Default_Handler
+
+ .weak TIM1_UP_IRQHandler
+ .thumb_set TIM1_UP_IRQHandler,Default_Handler
+
+ .weak TIM1_TRG_COM_IRQHandler
+ .thumb_set TIM1_TRG_COM_IRQHandler,Default_Handler
+
+ .weak TIM1_CC_IRQHandler
+ .thumb_set TIM1_CC_IRQHandler,Default_Handler
+
+ .weak TIM2_IRQHandler
+ .thumb_set TIM2_IRQHandler,Default_Handler
+
+ .weak TIM16_IRQHandler
+ .thumb_set TIM16_IRQHandler,Default_Handler
+
+ .weak TIM17_IRQHandler
+ .thumb_set TIM17_IRQHandler,Default_Handler
+
+ .weak I2C1_EV_IRQHandler
+ .thumb_set I2C1_EV_IRQHandler,Default_Handler
+
+ .weak I2C1_ER_IRQHandler
+ .thumb_set I2C1_ER_IRQHandler,Default_Handler
+
+ .weak I2C2_EV_IRQHandler
+ .thumb_set I2C2_EV_IRQHandler,Default_Handler
+
+ .weak I2C2_ER_IRQHandler
+ .thumb_set I2C2_ER_IRQHandler,Default_Handler
+
+ .weak SPI1_IRQHandler
+ .thumb_set SPI1_IRQHandler,Default_Handler
+
+ .weak SPI2_IRQHandler
+ .thumb_set SPI2_IRQHandler,Default_Handler
+
+ .weak USART1_IRQHandler
+ .thumb_set USART1_IRQHandler,Default_Handler
+
+ .weak USART2_IRQHandler
+ .thumb_set USART2_IRQHandler,Default_Handler
+
+ .weak LPUART1_IRQHandler
+ .thumb_set LPUART1_IRQHandler,Default_Handler
+
+ .weak LPTIM1_IRQHandler
+ .thumb_set LPTIM1_IRQHandler,Default_Handler
+
+ .weak LPTIM2_IRQHandler
+ .thumb_set LPTIM2_IRQHandler,Default_Handler
+
+ .weak EXTI15_10_IRQHandler
+ .thumb_set EXTI15_10_IRQHandler,Default_Handler
+
+ .weak RTC_Alarm_IRQHandler
+ .thumb_set RTC_Alarm_IRQHandler,Default_Handler
+
+ .weak LPTIM3_IRQHandler
+ .thumb_set LPTIM3_IRQHandler,Default_Handler
+
+ .weak SUBGHZSPI_IRQHandler
+ .thumb_set SUBGHZSPI_IRQHandler,Default_Handler
+
+ .weak IPCC_C1_RX_IRQHandler
+ .thumb_set IPCC_C1_RX_IRQHandler,Default_Handler
+
+ .weak IPCC_C1_TX_IRQHandler
+ .thumb_set IPCC_C1_TX_IRQHandler,Default_Handler
+
+ .weak HSEM_IRQHandler
+ .thumb_set HSEM_IRQHandler,Default_Handler
+
+ .weak I2C3_EV_IRQHandler
+ .thumb_set I2C3_EV_IRQHandler,Default_Handler
+
+ .weak I2C3_ER_IRQHandler
+ .thumb_set I2C3_ER_IRQHandler,Default_Handler
+
+ .weak SUBGHZ_Radio_IRQHandler
+ .thumb_set SUBGHZ_Radio_IRQHandler,Default_Handler
+
+ .weak AES_IRQHandler
+ .thumb_set AES_IRQHandler,Default_Handler
+
+ .weak RNG_IRQHandler
+ .thumb_set RNG_IRQHandler,Default_Handler
+
+ .weak PKA_IRQHandler
+ .thumb_set PKA_IRQHandler,Default_Handler
+
+ .weak DMA2_Channel1_IRQHandler
+ .thumb_set DMA2_Channel1_IRQHandler,Default_Handler
+
+ .weak DMA2_Channel2_IRQHandler
+ .thumb_set DMA2_Channel2_IRQHandler,Default_Handler
+
+ .weak DMA2_Channel3_IRQHandler
+ .thumb_set DMA2_Channel3_IRQHandler,Default_Handler
+
+ .weak DMA2_Channel4_IRQHandler
+ .thumb_set DMA2_Channel4_IRQHandler,Default_Handler
+
+ .weak DMA2_Channel5_IRQHandler
+ .thumb_set DMA2_Channel5_IRQHandler,Default_Handler
+
+ .weak DMA2_Channel6_IRQHandler
+ .thumb_set DMA2_Channel6_IRQHandler,Default_Handler
+
+ .weak DMA2_Channel7_IRQHandler
+ .thumb_set DMA2_Channel7_IRQHandler,Default_Handler
+
+ .weak DMAMUX1_OVR_IRQHandler
+ .thumb_set DMAMUX1_OVR_IRQHandler,Default_Handler
+
+ .weak SystemInit
+
+/************************ (C) COPYRIGHT STMicroelectonics *****END OF FILE****/
diff --git a/targets/TARGET_STM/TARGET_STM32WL/TARGET_STM32WL55xC/TOOLCHAIN_GCC_ARM/stm32wl55xc.ld b/targets/TARGET_STM/TARGET_STM32WL/TARGET_STM32WL55xC/TOOLCHAIN_GCC_ARM/stm32wl55xc.ld
new file mode 100644
index 0000000..5f47993
--- /dev/null
+++ b/targets/TARGET_STM/TARGET_STM32WL/TARGET_STM32WL55xC/TOOLCHAIN_GCC_ARM/stm32wl55xc.ld
@@ -0,0 +1,203 @@
+/* Linker script to configure memory regions. */
+/*
+ * SPDX-License-Identifier: BSD-3-Clause
+ ******************************************************************************
+ * @attention
+ *
+ * Copyright (c) 2016-2020 STMicroelectronics.
+ * All rights reserved.
+ *
+ * This software component is licensed by ST under BSD 3-Clause license,
+ * the "License"; You may not use this file except in compliance with the
+ * License. You may obtain a copy of the License at:
+ * opensource.org/licenses/BSD-3-Clause
+ *
+ ******************************************************************************
+*/
+
+#include "../cmsis_nvic.h"
+
+
+#if !defined(MBED_APP_START)
+ #define MBED_APP_START MBED_ROM_START
+#endif
+
+#if !defined(MBED_APP_SIZE)
+ #define MBED_APP_SIZE MBED_ROM_SIZE
+#endif
+
+#if !defined(MBED_CONF_TARGET_BOOT_STACK_SIZE)
+ /* This value is normally defined by the tools
+ to 0x1000 for bare metal and 0x400 for RTOS */
+ #define MBED_CONF_TARGET_BOOT_STACK_SIZE 0x400
+#endif
+
+/* Round up VECTORS_SIZE to 8 bytes */
+#define VECTORS_SIZE (((NVIC_NUM_VECTORS * 4) + 7) & 0xFFFFFFF8)
+
+MEMORY
+{
+ FLASH (rx) : ORIGIN = MBED_APP_START, LENGTH = MBED_APP_SIZE
+ RAM (rwx) : ORIGIN = MBED_RAM_START + VECTORS_SIZE, LENGTH = MBED_RAM_SIZE - VECTORS_SIZE
+}
+
+/* Linker script to place sections and symbol values. Should be used together
+ * with other linker script that defines memory regions FLASH and RAM.
+ * It references following symbols, which must be defined in code:
+ * Reset_Handler : Entry of reset handler
+ *
+ * It defines following symbols, which code can use without definition:
+ * __exidx_start
+ * __exidx_end
+ * __etext
+ * __data_start__
+ * __preinit_array_start
+ * __preinit_array_end
+ * __init_array_start
+ * __init_array_end
+ * __fini_array_start
+ * __fini_array_end
+ * __data_end__
+ * __bss_start__
+ * __bss_end__
+ * __end__
+ * end
+ * __HeapLimit
+ * __StackLimit
+ * __StackTop
+ * __stack
+ * _estack
+ */
+ENTRY(Reset_Handler)
+
+SECTIONS
+{
+ .text :
+ {
+ KEEP(*(.isr_vector))
+ *(.text*)
+
+ KEEP(*(.init))
+ KEEP(*(.fini))
+
+ /* .ctors */
+ *crtbegin.o(.ctors)
+ *crtbegin?.o(.ctors)
+ *(EXCLUDE_FILE(*crtend?.o *crtend.o) .ctors)
+ *(SORT(.ctors.*))
+ *(.ctors)
+
+ /* .dtors */
+ *crtbegin.o(.dtors)
+ *crtbegin?.o(.dtors)
+ *(EXCLUDE_FILE(*crtend?.o *crtend.o) .dtors)
+ *(SORT(.dtors.*))
+ *(.dtors)
+
+ *(.rodata*)
+
+ KEEP(*(.eh_frame*))
+ } > FLASH
+
+ .ARM.extab :
+ {
+ *(.ARM.extab* .gnu.linkonce.armextab.*)
+ } > FLASH
+
+ __exidx_start = .;
+ .ARM.exidx :
+ {
+ *(.ARM.exidx* .gnu.linkonce.armexidx.*)
+ } > FLASH
+ __exidx_end = .;
+
+ __etext = .;
+ _sidata = .;
+
+ .data : AT (__etext)
+ {
+ __data_start__ = .;
+ _sdata = .;
+ *(vtable)
+ *(.data*)
+
+ . = ALIGN(8);
+ /* preinit data */
+ PROVIDE_HIDDEN (__preinit_array_start = .);
+ KEEP(*(.preinit_array))
+ PROVIDE_HIDDEN (__preinit_array_end = .);
+
+ . = ALIGN(8);
+ /* init data */
+ PROVIDE_HIDDEN (__init_array_start = .);
+ KEEP(*(SORT(.init_array.*)))
+ KEEP(*(.init_array))
+ PROVIDE_HIDDEN (__init_array_end = .);
+
+ . = ALIGN(8);
+ /* finit data */
+ PROVIDE_HIDDEN (__fini_array_start = .);
+ KEEP(*(SORT(.fini_array.*)))
+ KEEP(*(.fini_array))
+ PROVIDE_HIDDEN (__fini_array_end = .);
+
+ KEEP(*(.jcr*))
+ . = ALIGN(8);
+ /* All data end */
+ __data_end__ = .;
+ _edata = .;
+
+ } > RAM
+
+ /* Uninitialized data section
+ * This region is not initialized by the C/C++ library and can be used to
+ * store state across soft reboots. */
+ .uninitialized (NOLOAD):
+ {
+ . = ALIGN(32);
+ __uninitialized_start = .;
+ *(.uninitialized)
+ KEEP(*(.keep.uninitialized))
+ . = ALIGN(32);
+ __uninitialized_end = .;
+ } > RAM
+
+ .bss :
+ {
+ . = ALIGN(8);
+ __bss_start__ = .;
+ _sbss = .;
+ *(.bss*)
+ *(COMMON)
+ . = ALIGN(8);
+ __bss_end__ = .;
+ _ebss = .;
+ } > RAM
+
+ .heap (COPY):
+ {
+ __end__ = .;
+ PROVIDE(end = .);
+ *(.heap*)
+ . = ORIGIN(RAM) + LENGTH(RAM) - MBED_CONF_TARGET_BOOT_STACK_SIZE;
+ __HeapLimit = .;
+ } > RAM
+
+ /* .stack_dummy section doesn't contains any symbols. It is only
+ * used for linker to calculate size of stack sections, and assign
+ * values to stack symbols later */
+ .stack_dummy (COPY):
+ {
+ *(.stack*)
+ } > RAM
+
+ /* Set stack top to end of RAM, and stack limit move down by
+ * size of stack_dummy section */
+ __StackTop = ORIGIN(RAM) + LENGTH(RAM);
+ _estack = __StackTop;
+ __StackLimit = __StackTop - MBED_CONF_TARGET_BOOT_STACK_SIZE;
+ PROVIDE(__stack = __StackTop);
+
+ /* Check if data + heap + stack exceeds RAM limit */
+ ASSERT(__StackLimit >= __HeapLimit, "region RAM overflowed with stack")
+}
diff --git a/targets/TARGET_STM/TARGET_STM32WL/TARGET_STM32WL55xC/TOOLCHAIN_IAR/startup_stm32wl55xx.S b/targets/TARGET_STM/TARGET_STM32WL/TARGET_STM32WL55xC/TOOLCHAIN_IAR/startup_stm32wl55xx.S
new file mode 100644
index 0000000..1431e7f
--- /dev/null
+++ b/targets/TARGET_STM/TARGET_STM32WL/TARGET_STM32WL55xC/TOOLCHAIN_IAR/startup_stm32wl55xx.S
@@ -0,0 +1,509 @@
+;********************************************************************************
+;* File Name : startup_stm32wl55xx_cm4.s
+;* Author : MCD Application Team
+;* Description : M4 core vector table of the STM32WLxxxx devices for the
+;* IAR (EWARM) toolchain.
+;*
+;* This module performs:
+;* - Set the initial SP
+;* - Set the initial PC == _iar_program_start,
+;* - Set the vector table entries with the exceptions ISR
+;* address.
+;* - Branches to main in the C library (which eventually
+;* calls main()).
+;* After Reset the Cortex-M4 processor is in Thread mode,
+;* priority is Privileged, and the Stack is set to Main.
+;********************************************************************************
+;*
+;* Copyright (c) 2020 STMicroelectronics. All rights reserved.
+;*
+;* This software component is licensed by ST under Apache License, Version 2.0,
+;* the "License"; You may not use this file except in compliance with the
+;* License. You may obtain a copy of the License at:
+;* opensource.org/licenses/Apache-2.0
+;
+;*******************************************************************************
+;
+;
+; The modules in this file are included in the libraries, and may be replaced
+; by any user-defined modules that define the PUBLIC symbol _program_start or
+; a user defined start symbol.
+; To override the cstartup defined in the library, simply add your modified
+; version to the workbench project.
+;
+; The vector table is normally located at address 0.
+; When debugging in RAM, it can be located in RAM, aligned to at least 2^6.
+; The name "__vector_table" has special meaning for C-SPY:
+; it is where the SP start value is found, and the NVIC vector
+; table register (VTOR) is initialized to this address if != 0.
+;
+; Cortex-M version
+;
+
+ MODULE ?cstartup
+
+ ;; Forward declaration of sections.
+ SECTION CSTACK:DATA:NOROOT(3)
+
+ SECTION .intvec:CODE:NOROOT(2)
+
+ EXTERN __iar_program_start
+ EXTERN SystemInit
+ PUBLIC __vector_table
+
+ DATA
+__vector_table
+ DCD sfe(CSTACK)
+ DCD Reset_Handler ; Reset Handler
+
+ DCD NMI_Handler ; NMI Handler
+ DCD HardFault_Handler ; Hard Fault Handler
+ DCD MemManage_Handler ; MPU Fault Handler
+ DCD BusFault_Handler ; Bus Fault Handler
+ DCD UsageFault_Handler ; Usage Fault Handler
+ DCD 0 ; Reserved
+ DCD 0 ; Reserved
+ DCD 0 ; Reserved
+ DCD 0 ; Reserved
+ DCD SVC_Handler ; SVCall Handler
+ DCD DebugMon_Handler ; Debug Monitor Handler
+ DCD 0 ; Reserved
+ DCD PendSV_Handler ; PendSV Handler
+ DCD SysTick_Handler ; SysTick Handler
+
+ ; External Interrupts
+ DCD WWDG_IRQHandler ; Window WatchDog
+ DCD PVD_PVM_IRQHandler ; PVD and PVM Interrupt
+ DCD TAMP_STAMP_LSECSS_SSRU_IRQHandler ; RTC Tamper, RTC TimeStamp, LSECSS and RTC SSRU Interrupts
+ DCD RTC_WKUP_IRQHandler ; RTC Wakeup Interrupt
+ DCD FLASH_IRQHandler ; FLASH global Interrupt
+ DCD RCC_IRQHandler ; RCC Interrupt
+ DCD EXTI0_IRQHandler ; EXTI Line 0 Interrupt
+ DCD EXTI1_IRQHandler ; EXTI Line 1 Interrupt
+ DCD EXTI2_IRQHandler ; EXTI Line 2 Interrupt
+ DCD EXTI3_IRQHandler ; EXTI Line 3 Interrupt
+ DCD EXTI4_IRQHandler ; EXTI Line 4 Interrupt
+ DCD DMA1_Channel1_IRQHandler ; DMA1 Channel 1 Interrupt
+ DCD DMA1_Channel2_IRQHandler ; DMA1 Channel 2 Interrupt
+ DCD DMA1_Channel3_IRQHandler ; DMA1 Channel 3 Interrupt
+ DCD DMA1_Channel4_IRQHandler ; DMA1 Channel 4 Interrupt
+ DCD DMA1_Channel5_IRQHandler ; DMA1 Channel 5 Interrupt
+ DCD DMA1_Channel6_IRQHandler ; DMA1 Channel 6 Interrupt
+ DCD DMA1_Channel7_IRQHandler ; DMA1 Channel 7 Interrupt
+ DCD ADC_IRQHandler ; ADC Interrupt
+ DCD DAC_IRQHandler ; DAC Interrupt
+ DCD C2SEV_PWR_C2H_IRQHandler ; CPU M0+ SEV Interrupt
+ DCD COMP_IRQHandler ; COMP1 and COMP2 Interrupts
+ DCD EXTI9_5_IRQHandler ; EXTI Lines [9:5] Interrupt
+ DCD TIM1_BRK_IRQHandler ; TIM1 Break Interrupt
+ DCD TIM1_UP_IRQHandler ; TIM1 Update Interrupt
+ DCD TIM1_TRG_COM_IRQHandler ; TIM1 Trigger and Communication Interrupts
+ DCD TIM1_CC_IRQHandler ; TIM1 Capture Compare Interrupt
+ DCD TIM2_IRQHandler ; TIM2 Global Interrupt
+ DCD TIM16_IRQHandler ; TIM16 Global Interrupt
+ DCD TIM17_IRQHandler ; TIM17 Global Interrupt
+ DCD I2C1_EV_IRQHandler ; I2C1 Event Interrupt
+ DCD I2C1_ER_IRQHandler ; I2C1 Error Interrupt
+ DCD I2C2_EV_IRQHandler ; I2C2 Event Interrupt
+ DCD I2C2_ER_IRQHandler ; I2C2 Error Interrupt
+ DCD SPI1_IRQHandler ; SPI1 Interrupt
+ DCD SPI2_IRQHandler ; SPI2 Interrupt
+ DCD USART1_IRQHandler ; USART1 Interrupt
+ DCD USART2_IRQHandler ; USART2 Interrupt
+ DCD LPUART1_IRQHandler ; LPUART1 Interrupt
+ DCD LPTIM1_IRQHandler ; LPTIM1 Global Interrupt
+ DCD LPTIM2_IRQHandler ; LPTIM2 Global Interrupt
+ DCD EXTI15_10_IRQHandler ; EXTI Lines [15:10] Interrupt
+ DCD RTC_Alarm_IRQHandler ; RTC Alarms (A and B) Interrupt
+ DCD LPTIM3_IRQHandler ; LPTIM3 Global Interrupt
+ DCD SUBGHZSPI_IRQHandler ; SUBGHZSPI Interrupt
+ DCD IPCC_C1_RX_IRQHandler ; IPCC CPU1 RX occupied interrupt
+ DCD IPCC_C1_TX_IRQHandler ; IPCC CPU1 RX free interrupt
+ DCD HSEM_IRQHandler ; HSEM0 Interrupt
+ DCD I2C3_EV_IRQHandler ; I2C3 Event Interrupt
+ DCD I2C3_ER_IRQHandler ; I2C3 Error Interrupt
+ DCD SUBGHZ_Radio_IRQHandler ; SUBGHZ Radio Interrupt
+ DCD AES_IRQHandler ; AES Interrupt
+ DCD RNG_IRQHandler ; RNG1 Interrupt
+ DCD PKA_IRQHandler ; PKA Interrupt
+ DCD DMA2_Channel1_IRQHandler ; DMA2 Channel 1 Interrupt
+ DCD DMA2_Channel2_IRQHandler ; DMA2 Channel 2 Interrupt
+ DCD DMA2_Channel3_IRQHandler ; DMA2 Channel 3 Interrupt
+ DCD DMA2_Channel4_IRQHandler ; DMA2 Channel 4 Interrupt
+ DCD DMA2_Channel5_IRQHandler ; DMA2 Channel 5 Interrupt
+ DCD DMA2_Channel6_IRQHandler ; DMA2 Channel 6 Interrupt
+ DCD DMA2_Channel7_IRQHandler ; DMA2 Channel 7 Interrupt
+ DCD DMAMUX1_OVR_IRQHandler ; DMAMUX overrun Interrupt
+
+;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;
+;;
+;; Default interrupt handlers.
+;;
+ THUMB
+
+ PUBWEAK Reset_Handler
+ SECTION .text:CODE:NOROOT:REORDER(2)
+Reset_Handler
+ LDR R0, =SystemInit
+ BLX R0
+ LDR R0, =__iar_program_start
+ BX R0
+
+ PUBWEAK NMI_Handler
+ SECTION .text:CODE:NOROOT:REORDER(1)
+NMI_Handler
+ B NMI_Handler
+
+ PUBWEAK HardFault_Handler
+ SECTION .text:CODE:NOROOT:REORDER(1)
+HardFault_Handler
+ B HardFault_Handler
+
+ PUBWEAK MemManage_Handler
+ SECTION .text:CODE:NOROOT:REORDER(1)
+MemManage_Handler
+ B MemManage_Handler
+
+ PUBWEAK BusFault_Handler
+ SECTION .text:CODE:NOROOT:REORDER(1)
+BusFault_Handler
+ B BusFault_Handler
+
+ PUBWEAK UsageFault_Handler
+ SECTION .text:CODE:NOROOT:REORDER(1)
+UsageFault_Handler
+ B UsageFault_Handler
+
+ PUBWEAK SVC_Handler
+ SECTION .text:CODE:NOROOT:REORDER(1)
+SVC_Handler
+ B SVC_Handler
+
+ PUBWEAK DebugMon_Handler
+ SECTION .text:CODE:NOROOT:REORDER(1)
+DebugMon_Handler
+ B DebugMon_Handler
+
+ PUBWEAK PendSV_Handler
+ SECTION .text:CODE:NOROOT:REORDER(1)
+PendSV_Handler
+ B PendSV_Handler
+
+ PUBWEAK SysTick_Handler
+ SECTION .text:CODE:NOROOT:REORDER(1)
+SysTick_Handler
+ B SysTick_Handler
+
+ PUBWEAK WWDG_IRQHandler
+ SECTION .text:CODE:NOROOT:REORDER(1)
+WWDG_IRQHandler
+ B WWDG_IRQHandler
+
+ PUBWEAK PVD_PVM_IRQHandler
+ SECTION .text:CODE:NOROOT:REORDER(1)
+PVD_PVM_IRQHandler
+ B PVD_PVM_IRQHandler
+
+ PUBWEAK TAMP_STAMP_LSECSS_SSRU_IRQHandler
+ SECTION .text:CODE:NOROOT:REORDER(1)
+TAMP_STAMP_LSECSS_SSRU_IRQHandler
+ B TAMP_STAMP_LSECSS_SSRU_IRQHandler
+
+ PUBWEAK RTC_WKUP_IRQHandler
+ SECTION .text:CODE:NOROOT:REORDER(1)
+RTC_WKUP_IRQHandler
+ B RTC_WKUP_IRQHandler
+
+ PUBWEAK FLASH_IRQHandler
+ SECTION .text:CODE:NOROOT:REORDER(1)
+FLASH_IRQHandler
+ B FLASH_IRQHandler
+
+ PUBWEAK RCC_IRQHandler
+ SECTION .text:CODE:NOROOT:REORDER(1)
+RCC_IRQHandler
+ B RCC_IRQHandler
+
+ PUBWEAK EXTI0_IRQHandler
+ SECTION .text:CODE:NOROOT:REORDER(1)
+EXTI0_IRQHandler
+ B EXTI0_IRQHandler
+
+ PUBWEAK EXTI1_IRQHandler
+ SECTION .text:CODE:NOROOT:REORDER(1)
+EXTI1_IRQHandler
+ B EXTI1_IRQHandler
+
+ PUBWEAK EXTI2_IRQHandler
+ SECTION .text:CODE:NOROOT:REORDER(1)
+EXTI2_IRQHandler
+ B EXTI2_IRQHandler
+
+ PUBWEAK EXTI3_IRQHandler
+ SECTION .text:CODE:NOROOT:REORDER(1)
+EXTI3_IRQHandler
+ B EXTI3_IRQHandler
+
+ PUBWEAK EXTI4_IRQHandler
+ SECTION .text:CODE:NOROOT:REORDER(1)
+EXTI4_IRQHandler
+ B EXTI4_IRQHandler
+
+ PUBWEAK DMA1_Channel1_IRQHandler
+ SECTION .text:CODE:NOROOT:REORDER(1)
+DMA1_Channel1_IRQHandler
+ B DMA1_Channel1_IRQHandler
+
+ PUBWEAK DMA1_Channel2_IRQHandler
+ SECTION .text:CODE:NOROOT:REORDER(1)
+DMA1_Channel2_IRQHandler
+ B DMA1_Channel2_IRQHandler
+
+ PUBWEAK DMA1_Channel3_IRQHandler
+ SECTION .text:CODE:NOROOT:REORDER(1)
+DMA1_Channel3_IRQHandler
+ B DMA1_Channel3_IRQHandler
+
+ PUBWEAK DMA1_Channel4_IRQHandler
+ SECTION .text:CODE:NOROOT:REORDER(1)
+DMA1_Channel4_IRQHandler
+ B DMA1_Channel4_IRQHandler
+
+ PUBWEAK DMA1_Channel5_IRQHandler
+ SECTION .text:CODE:NOROOT:REORDER(1)
+DMA1_Channel5_IRQHandler
+ B DMA1_Channel5_IRQHandler
+
+ PUBWEAK DMA1_Channel6_IRQHandler
+ SECTION .text:CODE:NOROOT:REORDER(1)
+DMA1_Channel6_IRQHandler
+ B DMA1_Channel6_IRQHandler
+
+ PUBWEAK DMA1_Channel7_IRQHandler
+ SECTION .text:CODE:NOROOT:REORDER(1)
+DMA1_Channel7_IRQHandler
+ B DMA1_Channel7_IRQHandler
+
+ PUBWEAK ADC_IRQHandler
+ SECTION .text:CODE:NOROOT:REORDER(1)
+ADC_IRQHandler
+ B ADC_IRQHandler
+
+ PUBWEAK DAC_IRQHandler
+ SECTION .text:CODE:NOROOT:REORDER(1)
+DAC_IRQHandler
+ B DAC_IRQHandler
+
+ PUBWEAK C2SEV_PWR_C2H_IRQHandler
+ SECTION .text:CODE:NOROOT:REORDER(1)
+C2SEV_PWR_C2H_IRQHandler
+ B C2SEV_PWR_C2H_IRQHandler
+
+ PUBWEAK COMP_IRQHandler
+ SECTION .text:CODE:NOROOT:REORDER(1)
+COMP_IRQHandler
+ B COMP_IRQHandler
+
+ PUBWEAK EXTI9_5_IRQHandler
+ SECTION .text:CODE:NOROOT:REORDER(1)
+EXTI9_5_IRQHandler
+ B EXTI9_5_IRQHandler
+
+ PUBWEAK TIM1_BRK_IRQHandler
+ SECTION .text:CODE:NOROOT:REORDER(1)
+TIM1_BRK_IRQHandler
+ B TIM1_BRK_IRQHandler
+
+ PUBWEAK TIM1_UP_IRQHandler
+ SECTION .text:CODE:NOROOT:REORDER(1)
+TIM1_UP_IRQHandler
+ B TIM1_UP_IRQHandler
+
+ PUBWEAK TIM1_TRG_COM_IRQHandler
+ SECTION .text:CODE:NOROOT:REORDER(1)
+TIM1_TRG_COM_IRQHandler
+ B TIM1_TRG_COM_IRQHandler
+
+ PUBWEAK TIM1_CC_IRQHandler
+ SECTION .text:CODE:NOROOT:REORDER(1)
+TIM1_CC_IRQHandler
+ B TIM1_CC_IRQHandler
+
+ PUBWEAK TIM2_IRQHandler
+ SECTION .text:CODE:NOROOT:REORDER(1)
+TIM2_IRQHandler
+ B TIM2_IRQHandler
+
+ PUBWEAK TIM16_IRQHandler
+ SECTION .text:CODE:NOROOT:REORDER(1)
+TIM16_IRQHandler
+ B TIM16_IRQHandler
+
+ PUBWEAK TIM17_IRQHandler
+ SECTION .text:CODE:NOROOT:REORDER(1)
+TIM17_IRQHandler
+ B TIM17_IRQHandler
+
+ PUBWEAK I2C1_EV_IRQHandler
+ SECTION .text:CODE:NOROOT:REORDER(1)
+I2C1_EV_IRQHandler
+ B I2C1_EV_IRQHandler
+
+ PUBWEAK I2C1_ER_IRQHandler
+ SECTION .text:CODE:NOROOT:REORDER(1)
+I2C1_ER_IRQHandler
+ B I2C1_ER_IRQHandler
+
+ PUBWEAK I2C2_EV_IRQHandler
+ SECTION .text:CODE:NOROOT:REORDER(1)
+I2C2_EV_IRQHandler
+ B I2C2_EV_IRQHandler
+
+ PUBWEAK I2C2_ER_IRQHandler
+ SECTION .text:CODE:NOROOT:REORDER(1)
+I2C2_ER_IRQHandler
+ B I2C2_ER_IRQHandler
+
+ PUBWEAK SPI1_IRQHandler
+ SECTION .text:CODE:NOROOT:REORDER(1)
+SPI1_IRQHandler
+ B SPI1_IRQHandler
+
+ PUBWEAK SPI2_IRQHandler
+ SECTION .text:CODE:NOROOT:REORDER(1)
+SPI2_IRQHandler
+ B SPI2_IRQHandler
+
+ PUBWEAK USART1_IRQHandler
+ SECTION .text:CODE:NOROOT:REORDER(1)
+USART1_IRQHandler
+ B USART1_IRQHandler
+
+ PUBWEAK USART2_IRQHandler
+ SECTION .text:CODE:NOROOT:REORDER(1)
+USART2_IRQHandler
+ B USART2_IRQHandler
+
+ PUBWEAK LPUART1_IRQHandler
+ SECTION .text:CODE:NOROOT:REORDER(1)
+LPUART1_IRQHandler
+ B LPUART1_IRQHandler
+
+ PUBWEAK LPTIM1_IRQHandler
+ SECTION .text:CODE:NOROOT:REORDER(1)
+LPTIM1_IRQHandler
+ B LPTIM1_IRQHandler
+
+ PUBWEAK LPTIM2_IRQHandler
+ SECTION .text:CODE:NOROOT:REORDER(1)
+LPTIM2_IRQHandler
+ B LPTIM2_IRQHandler
+
+ PUBWEAK EXTI15_10_IRQHandler
+ SECTION .text:CODE:NOROOT:REORDER(1)
+EXTI15_10_IRQHandler
+ B EXTI15_10_IRQHandler
+
+ PUBWEAK RTC_Alarm_IRQHandler
+ SECTION .text:CODE:NOROOT:REORDER(1)
+RTC_Alarm_IRQHandler
+ B RTC_Alarm_IRQHandler
+
+ PUBWEAK LPTIM3_IRQHandler
+ SECTION .text:CODE:NOROOT:REORDER(1)
+LPTIM3_IRQHandler
+ B LPTIM3_IRQHandler
+
+ PUBWEAK SUBGHZSPI_IRQHandler
+ SECTION .text:CODE:NOROOT:REORDER(1)
+SUBGHZSPI_IRQHandler
+ B SUBGHZSPI_IRQHandler
+
+ PUBWEAK IPCC_C1_RX_IRQHandler
+ SECTION .text:CODE:NOROOT:REORDER(1)
+IPCC_C1_RX_IRQHandler
+ B IPCC_C1_RX_IRQHandler
+
+ PUBWEAK IPCC_C1_TX_IRQHandler
+ SECTION .text:CODE:NOROOT:REORDER(1)
+IPCC_C1_TX_IRQHandler
+ B IPCC_C1_TX_IRQHandler
+
+ PUBWEAK HSEM_IRQHandler
+ SECTION .text:CODE:NOROOT:REORDER(1)
+HSEM_IRQHandler
+ B HSEM_IRQHandler
+
+ PUBWEAK I2C3_EV_IRQHandler
+ SECTION .text:CODE:NOROOT:REORDER(1)
+I2C3_EV_IRQHandler
+ B I2C3_EV_IRQHandler
+
+ PUBWEAK I2C3_ER_IRQHandler
+ SECTION .text:CODE:NOROOT:REORDER(1)
+I2C3_ER_IRQHandler
+ B I2C3_ER_IRQHandler
+
+ PUBWEAK SUBGHZ_Radio_IRQHandler
+ SECTION .text:CODE:NOROOT:REORDER(1)
+SUBGHZ_Radio_IRQHandler
+ B SUBGHZ_Radio_IRQHandler
+
+ PUBWEAK AES_IRQHandler
+ SECTION .text:CODE:NOROOT:REORDER(1)
+AES_IRQHandler
+ B AES_IRQHandler
+
+ PUBWEAK RNG_IRQHandler
+ SECTION .text:CODE:NOROOT:REORDER(1)
+RNG_IRQHandler
+ B RNG_IRQHandler
+
+ PUBWEAK PKA_IRQHandler
+ SECTION .text:CODE:NOROOT:REORDER(1)
+PKA_IRQHandler
+ B PKA_IRQHandler
+
+ PUBWEAK DMA2_Channel1_IRQHandler
+ SECTION .text:CODE:NOROOT:REORDER(1)
+DMA2_Channel1_IRQHandler
+ B DMA2_Channel1_IRQHandler
+
+ PUBWEAK DMA2_Channel2_IRQHandler
+ SECTION .text:CODE:NOROOT:REORDER(1)
+DMA2_Channel2_IRQHandler
+ B DMA2_Channel2_IRQHandler
+
+ PUBWEAK DMA2_Channel3_IRQHandler
+ SECTION .text:CODE:NOROOT:REORDER(1)
+DMA2_Channel3_IRQHandler
+ B DMA2_Channel3_IRQHandler
+
+ PUBWEAK DMA2_Channel4_IRQHandler
+ SECTION .text:CODE:NOROOT:REORDER(1)
+DMA2_Channel4_IRQHandler
+ B DMA2_Channel4_IRQHandler
+
+ PUBWEAK DMA2_Channel5_IRQHandler
+ SECTION .text:CODE:NOROOT:REORDER(1)
+DMA2_Channel5_IRQHandler
+ B DMA2_Channel5_IRQHandler
+
+ PUBWEAK DMA2_Channel6_IRQHandler
+ SECTION .text:CODE:NOROOT:REORDER(1)
+DMA2_Channel6_IRQHandler
+ B DMA2_Channel6_IRQHandler
+
+ PUBWEAK DMA2_Channel7_IRQHandler
+ SECTION .text:CODE:NOROOT:REORDER(1)
+DMA2_Channel7_IRQHandler
+ B DMA2_Channel7_IRQHandler
+
+ PUBWEAK DMAMUX1_OVR_IRQHandler
+ SECTION .text:CODE:NOROOT:REORDER(1)
+DMAMUX1_OVR_IRQHandler
+ B DMAMUX1_OVR_IRQHandler
+
+ END
+
+;************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE*****
diff --git a/targets/TARGET_STM/TARGET_STM32WL/TARGET_STM32WL55xC/TOOLCHAIN_IAR/stm32wl55xc.icf b/targets/TARGET_STM/TARGET_STM32WL/TARGET_STM32WL55xC/TOOLCHAIN_IAR/stm32wl55xc.icf
new file mode 100644
index 0000000..7fb4af2
--- /dev/null
+++ b/targets/TARGET_STM/TARGET_STM32WL/TARGET_STM32WL55xC/TOOLCHAIN_IAR/stm32wl55xc.icf
@@ -0,0 +1,59 @@
+/* Linker script to configure memory regions.
+ *
+ * SPDX-License-Identifier: BSD-3-Clause
+ ******************************************************************************
+ * @attention
+ *
+ * Copyright (c) 2016-2020 STMicroelectronics.
+ * All rights reserved.
+ *
+ * This software component is licensed by ST under BSD 3-Clause license,
+ * the "License"; You may not use this file except in compliance with the
+ * License. You may obtain a copy of the License at:
+ * opensource.org/licenses/BSD-3-Clause
+ *
+ ******************************************************************************
+*/
+/* Device specific values */
+
+/* Tools provide -DMBED_ROM_START=xxx -DMBED_ROM_SIZE=xxx -DMBED_RAM_START=xxx -DMBED_RAM_SIZE=xxx */
+
+define symbol VECTORS = 78; /* This value must match NVIC_NUM_VECTORS in cmsis_nvic.h */
+define symbol HEAP_SIZE = 0x1000;
+
+/* Common - Do not change */
+
+if (!isdefinedsymbol(MBED_APP_START)) {
+ define symbol MBED_APP_START = MBED_ROM_START;
+}
+
+if (!isdefinedsymbol(MBED_APP_SIZE)) {
+ define symbol MBED_APP_SIZE = MBED_ROM_SIZE;
+}
+
+if (!isdefinedsymbol(MBED_CONF_TARGET_BOOT_STACK_SIZE)) {
+ /* This value is normally defined by the tools
+ to 0x1000 for bare metal and 0x400 for RTOS */
+ define symbol MBED_CONF_TARGET_BOOT_STACK_SIZE = 0x400;
+}
+
+/* Round up VECTORS_SIZE to 8 bytes */
+define symbol VECTORS_SIZE = ((VECTORS * 4) + 7) & ~7;
+define symbol RAM_REGION_START = MBED_RAM_START + VECTORS_SIZE;
+define symbol RAM_REGION_SIZE = MBED_RAM_SIZE - VECTORS_SIZE;
+
+define memory mem with size = 4G;
+define region ROM_region = mem:[from MBED_APP_START size MBED_APP_SIZE];
+define region RAM_region = mem:[from RAM_REGION_START size RAM_REGION_SIZE];
+
+define block CSTACK with alignment = 8, size = MBED_CONF_TARGET_BOOT_STACK_SIZE { };
+define block HEAP with alignment = 8, size = HEAP_SIZE { };
+
+initialize by copy { readwrite };
+do not initialize { section .noinit };
+
+place at address mem: MBED_APP_START { readonly section .intvec };
+
+place in ROM_region { readonly };
+place in RAM_region { readwrite,
+ block CSTACK, block HEAP };
diff --git a/targets/TARGET_STM/TARGET_STM32WL/TARGET_STM32WL55xC/cmsis_nvic.h b/targets/TARGET_STM/TARGET_STM32WL/TARGET_STM32WL55xC/cmsis_nvic.h
new file mode 100644
index 0000000..c5ec327
--- /dev/null
+++ b/targets/TARGET_STM/TARGET_STM32WL/TARGET_STM32WL55xC/cmsis_nvic.h
@@ -0,0 +1,39 @@
+/* mbed Microcontroller Library
+ * SPDX-License-Identifier: BSD-3-Clause
+ ******************************************************************************
+ * @attention
+ *
+ * © Copyright (c) 2016-2020 STMicroelectronics.
+ * All rights reserved.
+ *
+ * This software component is licensed by ST under BSD 3-Clause license,
+ * the "License"; You may not use this file except in compliance with the
+ * License. You may obtain a copy of the License at:
+ * opensource.org/licenses/BSD-3-Clause
+ *
+ ******************************************************************************
+*/
+
+#ifndef MBED_CMSIS_NVIC_H
+#define MBED_CMSIS_NVIC_H
+
+#if !defined(MBED_ROM_START)
+#define MBED_ROM_START 0x8000000
+#endif
+
+#if !defined(MBED_ROM_SIZE)
+#define MBED_ROM_SIZE 0x40000
+#endif
+
+#if !defined(MBED_RAM_START)
+#define MBED_RAM_START 0x20000000
+#endif
+
+#if !defined(MBED_RAM_SIZE)
+#define MBED_RAM_SIZE 0x10000
+#endif
+
+#define NVIC_NUM_VECTORS 78
+#define NVIC_RAM_VECTOR_ADDRESS MBED_RAM_START
+
+#endif
diff --git a/targets/TARGET_STM/TARGET_STM32WL/TARGET_STM32WLE4x8/TOOLCHAIN_ARM/startup_stm32wle4xx.S b/targets/TARGET_STM/TARGET_STM32WL/TARGET_STM32WLE4x8/TOOLCHAIN_ARM/startup_stm32wle4xx.S
new file mode 100644
index 0000000..002a574
--- /dev/null
+++ b/targets/TARGET_STM/TARGET_STM32WL/TARGET_STM32WLE4x8/TOOLCHAIN_ARM/startup_stm32wle4xx.S
@@ -0,0 +1,314 @@
+;******************************************************************************
+;* File Name : startup_stm32wle4xx.s
+;* Author : MCD Application Team
+;* Description : STM32WLE4xx devices vector table for MDK-ARM toolchain.
+;* This module performs:
+;* - Set the initial SP
+;* - Set the initial PC == Reset_Handler
+;* - Set the vector table entries with the exceptions ISR address
+;* - Branches to __main in the C library (which eventually
+;* calls main()).
+;* After Reset the CortexM4 processor is in Thread mode,
+;* priority is Privileged, and the Stack is set to Main.
+;* <<< Use Configuration Wizard in Context Menu >>>
+;******************************************************************************
+;* @attention
+;*
+;* Copyright (c) 2020 STMicroelectronics. All rights reserved.
+;*
+;* This software component is licensed by ST under Apache License, Version 2.0,
+;* the "License"; You may not use this file except in compliance with the
+;* License. You may obtain a copy of the License at:
+;* opensource.org/licenses/Apache-2.0
+;*
+;******************************************************************************
+
+ PRESERVE8
+ THUMB
+
+
+; Vector Table Mapped to Address 0 at Reset
+ AREA RESET, DATA, READONLY
+ EXPORT __Vectors
+ EXPORT __Vectors_End
+ EXPORT __Vectors_Size
+
+ IMPORT |Image$$ARM_LIB_STACK$$ZI$$Limit|
+__Vectors DCD |Image$$ARM_LIB_STACK$$ZI$$Limit| ; Top of Stack
+ DCD Reset_Handler ; Reset Handler
+ DCD NMI_Handler ; NMI Handler
+ DCD HardFault_Handler ; Hard Fault Handler
+ DCD MemManage_Handler ; MPU Fault Handler
+ DCD BusFault_Handler ; Bus Fault Handler
+ DCD UsageFault_Handler ; Usage Fault Handler
+ DCD 0 ; Reserved
+ DCD 0 ; Reserved
+ DCD 0 ; Reserved
+ DCD 0 ; Reserved
+ DCD SVC_Handler ; SVCall Handler
+ DCD DebugMon_Handler ; Debug Monitor Handler
+ DCD 0 ; Reserved
+ DCD PendSV_Handler ; PendSV Handler
+ DCD SysTick_Handler ; SysTick Handler
+
+ ; External Interrupts
+ DCD WWDG_IRQHandler ; Window WatchDog
+ DCD PVD_PVM_IRQHandler ; PVD and PVM detector
+ DCD TAMP_STAMP_LSECSS_SSRU_IRQHandler ; RTC Tamper, RTC TimeStamp, LSECSS and RTC SSR Underflow Interrupts
+ DCD RTC_WKUP_IRQHandler ; RTC Wakeup Interrupt
+ DCD FLASH_IRQHandler ; FLASH global Interrupt
+ DCD RCC_IRQHandler ; RCC Interrupt
+ DCD EXTI0_IRQHandler ; EXTI Line 0 Interrupt
+ DCD EXTI1_IRQHandler ; EXTI Line 1 Interrupt
+ DCD EXTI2_IRQHandler ; EXTI Line 2 Interrupt
+ DCD EXTI3_IRQHandler ; EXTI Line 3 Interrup
+ DCD EXTI4_IRQHandler ; EXTI Line 4 Interrupt
+ DCD DMA1_Channel1_IRQHandler ; DMA1 Channel 1 Interrupt
+ DCD DMA1_Channel2_IRQHandler ; DMA1 Channel 2 Interrupt
+ DCD DMA1_Channel3_IRQHandler ; DMA1 Channel 3 Interrupt
+ DCD DMA1_Channel4_IRQHandler ; DMA1 Channel 4 Interrupt
+ DCD DMA1_Channel5_IRQHandler ; DMA1 Channel 5 Interrupt
+ DCD DMA1_Channel6_IRQHandler ; DMA1 Channel 6 Interrupt
+ DCD DMA1_Channel7_IRQHandler ; DMA1 Channel 7 Interrupt
+ DCD ADC_IRQHandler ; ADC Interrupt
+ DCD DAC_IRQHandler ; DAC Interrupt
+ DCD 0 ; Reserved
+ DCD COMP_IRQHandler ; COMP1 and COMP2 Interrupts
+ DCD EXTI9_5_IRQHandler ; EXTI Lines [9:5] Interrupt
+ DCD TIM1_BRK_IRQHandler ; TIM1 Break Interrupt
+ DCD TIM1_UP_IRQHandler ; TIM1 Update Interrupts
+ DCD TIM1_TRG_COM_IRQHandler ; TIM1 Trigger and Communication Interrupts
+ DCD TIM1_CC_IRQHandler ; TIM1 Capture Compare Interrupt
+ DCD TIM2_IRQHandler ; TIM2 Global Interrupt
+ DCD TIM16_IRQHandler ; TIM16 Global Interrupt
+ DCD TIM17_IRQHandler ; TIM17 Global Interrupt
+ DCD I2C1_EV_IRQHandler ; I2C1 Event Interrupt
+ DCD I2C1_ER_IRQHandler ; I2C1 Error Interrupt
+ DCD I2C2_EV_IRQHandler ; I2C2 Event Interrupt
+ DCD I2C2_ER_IRQHandler ; I2C2 Error Interrupt
+ DCD SPI1_IRQHandler ; SPI1 Interrupt
+ DCD SPI2_IRQHandler ; SPI2 Interrupt
+ DCD USART1_IRQHandler ; USART1 Interrupt
+ DCD USART2_IRQHandler ; USART2 Interrupt
+ DCD LPUART1_IRQHandler ; LPUART1 Interrupt
+ DCD LPTIM1_IRQHandler ; LPTIM1 Interrupt
+ DCD LPTIM2_IRQHandler ; LPTIM2 Interrupt
+ DCD EXTI15_10_IRQHandler ; EXTI Lines1[15:10 ]Interrupts
+ DCD RTC_Alarm_IRQHandler ; RTC Alarms (A and B) Interrupt
+ DCD LPTIM3_IRQHandler ; LPTIM3 Interrupt
+ DCD SUBGHZSPI_IRQHandler ; SUBGHZSPI Interrupt
+ DCD 0 ; Reserved
+ DCD 0 ; Reserved
+ DCD HSEM_IRQHandler ; HSEM0 Interrupt
+ DCD I2C3_EV_IRQHandler ; I2C3 Event Interrupt
+ DCD I2C3_ER_IRQHandler ; I2C3 Error Interrupt
+ DCD SUBGHZ_Radio_IRQHandler ; SUBGHZ Radio Interrupt
+ DCD AES_IRQHandler ; AES Interrupt
+ DCD RNG_IRQHandler ; RNG1 Interrupt
+ DCD PKA_IRQHandler ; PKA Interrupt
+ DCD DMA2_Channel1_IRQHandler ; DMA2 Channel 1 Interrupt
+ DCD DMA2_Channel2_IRQHandler ; DMA2 Channel 2 Interrupt
+ DCD DMA2_Channel3_IRQHandler ; DMA2 Channel 3 Interrupt
+ DCD DMA2_Channel4_IRQHandler ; DMA2 Channel 4 Interrupt
+ DCD DMA2_Channel5_IRQHandler ; DMA2 Channel 5 Interrupt
+ DCD DMA2_Channel6_IRQHandler ; DMA2 Channel 6 Interrupt
+ DCD DMA2_Channel7_IRQHandler ; DMA2 Channel 7 Interrupt
+ DCD DMAMUX1_OVR_IRQHandler ; DMAMUX overrun Interrupt
+
+__Vectors_End
+
+__Vectors_Size EQU __Vectors_End - __Vectors
+
+ AREA |.text|, CODE, READONLY
+
+; Reset handler
+Reset_Handler PROC
+ EXPORT Reset_Handler [WEAK]
+ IMPORT SystemInit
+ IMPORT __main
+
+ LDR R0, =SystemInit
+ BLX R0
+ LDR R0, =__main
+ BX R0
+ ENDP
+
+; Dummy Exception Handlers (infinite loops which can be modified)
+
+NMI_Handler PROC
+ EXPORT NMI_Handler [WEAK]
+ B .
+ ENDP
+HardFault_Handler\
+ PROC
+ EXPORT HardFault_Handler [WEAK]
+ B .
+ ENDP
+MemManage_Handler\
+ PROC
+ EXPORT MemManage_Handler [WEAK]
+ B .
+ ENDP
+BusFault_Handler\
+ PROC
+ EXPORT BusFault_Handler [WEAK]
+ B .
+ ENDP
+UsageFault_Handler\
+ PROC
+ EXPORT UsageFault_Handler [WEAK]
+ B .
+ ENDP
+SVC_Handler PROC
+ EXPORT SVC_Handler [WEAK]
+ B .
+ ENDP
+DebugMon_Handler\
+ PROC
+ EXPORT DebugMon_Handler [WEAK]
+ B .
+ ENDP
+PendSV_Handler PROC
+ EXPORT PendSV_Handler [WEAK]
+ B .
+ ENDP
+SysTick_Handler PROC
+ EXPORT SysTick_Handler [WEAK]
+ B .
+ ENDP
+
+Default_Handler PROC
+
+ EXPORT WWDG_IRQHandler [WEAK]
+ EXPORT PVD_PVM_IRQHandler [WEAK]
+ EXPORT TAMP_STAMP_LSECSS_SSRU_IRQHandler [WEAK]
+ EXPORT RTC_WKUP_IRQHandler [WEAK]
+ EXPORT FLASH_IRQHandler [WEAK]
+ EXPORT RCC_IRQHandler [WEAK]
+ EXPORT EXTI0_IRQHandler [WEAK]
+ EXPORT EXTI1_IRQHandler [WEAK]
+ EXPORT EXTI2_IRQHandler [WEAK]
+ EXPORT EXTI3_IRQHandler [WEAK]
+ EXPORT EXTI4_IRQHandler [WEAK]
+ EXPORT DMA1_Channel1_IRQHandler [WEAK]
+ EXPORT DMA1_Channel2_IRQHandler [WEAK]
+ EXPORT DMA1_Channel3_IRQHandler [WEAK]
+ EXPORT DMA1_Channel4_IRQHandler [WEAK]
+ EXPORT DMA1_Channel5_IRQHandler [WEAK]
+ EXPORT DMA1_Channel6_IRQHandler [WEAK]
+ EXPORT DMA1_Channel7_IRQHandler [WEAK]
+ EXPORT ADC_IRQHandler [WEAK]
+ EXPORT DAC_IRQHandler [WEAK]
+ EXPORT COMP_IRQHandler [WEAK]
+ EXPORT EXTI9_5_IRQHandler [WEAK]
+ EXPORT TIM1_BRK_IRQHandler [WEAK]
+ EXPORT TIM1_UP_IRQHandler [WEAK]
+ EXPORT TIM1_TRG_COM_IRQHandler [WEAK]
+ EXPORT TIM1_CC_IRQHandler [WEAK]
+ EXPORT TIM2_IRQHandler [WEAK]
+ EXPORT TIM16_IRQHandler [WEAK]
+ EXPORT TIM17_IRQHandler [WEAK]
+ EXPORT I2C1_EV_IRQHandler [WEAK]
+ EXPORT I2C1_ER_IRQHandler [WEAK]
+ EXPORT I2C2_EV_IRQHandler [WEAK]
+ EXPORT I2C2_ER_IRQHandler [WEAK]
+ EXPORT SPI1_IRQHandler [WEAK]
+ EXPORT SPI2_IRQHandler [WEAK]
+ EXPORT USART1_IRQHandler [WEAK]
+ EXPORT USART2_IRQHandler [WEAK]
+ EXPORT LPUART1_IRQHandler [WEAK]
+ EXPORT LPTIM1_IRQHandler [WEAK]
+ EXPORT LPTIM2_IRQHandler [WEAK]
+ EXPORT EXTI15_10_IRQHandler [WEAK]
+ EXPORT RTC_Alarm_IRQHandler [WEAK]
+ EXPORT LPTIM3_IRQHandler [WEAK]
+ EXPORT SUBGHZSPI_IRQHandler [WEAK]
+ EXPORT HSEM_IRQHandler [WEAK]
+ EXPORT I2C3_EV_IRQHandler [WEAK]
+ EXPORT I2C3_ER_IRQHandler [WEAK]
+ EXPORT SUBGHZ_Radio_IRQHandler [WEAK]
+ EXPORT AES_IRQHandler [WEAK]
+ EXPORT RNG_IRQHandler [WEAK]
+ EXPORT PKA_IRQHandler [WEAK]
+ EXPORT DMA2_Channel1_IRQHandler [WEAK]
+ EXPORT DMA2_Channel2_IRQHandler [WEAK]
+ EXPORT DMA2_Channel3_IRQHandler [WEAK]
+ EXPORT DMA2_Channel4_IRQHandler [WEAK]
+ EXPORT DMA2_Channel5_IRQHandler [WEAK]
+ EXPORT DMA2_Channel6_IRQHandler [WEAK]
+ EXPORT DMA2_Channel7_IRQHandler [WEAK]
+ EXPORT DMAMUX1_OVR_IRQHandler [WEAK]
+
+WWDG_IRQHandler
+PVD_PVM_IRQHandler
+TAMP_STAMP_LSECSS_SSRU_IRQHandler
+RTC_WKUP_IRQHandler
+FLASH_IRQHandler
+RCC_IRQHandler
+EXTI0_IRQHandler
+EXTI1_IRQHandler
+EXTI2_IRQHandler
+EXTI3_IRQHandler
+EXTI4_IRQHandler
+DMA1_Channel1_IRQHandler
+DMA1_Channel2_IRQHandler
+DMA1_Channel3_IRQHandler
+DMA1_Channel4_IRQHandler
+DMA1_Channel5_IRQHandler
+DMA1_Channel6_IRQHandler
+DMA1_Channel7_IRQHandler
+ADC_IRQHandler
+DAC_IRQHandler
+COMP_IRQHandler
+EXTI9_5_IRQHandler
+TIM1_BRK_IRQHandler
+TIM1_UP_IRQHandler
+TIM1_TRG_COM_IRQHandler
+TIM1_CC_IRQHandler
+TIM2_IRQHandler
+TIM16_IRQHandler
+TIM17_IRQHandler
+I2C1_EV_IRQHandler
+I2C1_ER_IRQHandler
+I2C2_EV_IRQHandler
+I2C2_ER_IRQHandler
+SPI1_IRQHandler
+SPI2_IRQHandler
+USART1_IRQHandler
+USART2_IRQHandler
+LPUART1_IRQHandler
+LPTIM1_IRQHandler
+LPTIM2_IRQHandler
+EXTI15_10_IRQHandler
+RTC_Alarm_IRQHandler
+LPTIM3_IRQHandler
+SUBGHZSPI_IRQHandler
+HSEM_IRQHandler
+I2C3_EV_IRQHandler
+I2C3_ER_IRQHandler
+SUBGHZ_Radio_IRQHandler
+AES_IRQHandler
+RNG_IRQHandler
+PKA_IRQHandler
+DMA2_Channel1_IRQHandler
+DMA2_Channel2_IRQHandler
+DMA2_Channel3_IRQHandler
+DMA2_Channel4_IRQHandler
+DMA2_Channel5_IRQHandler
+DMA2_Channel6_IRQHandler
+DMA2_Channel7_IRQHandler
+DMAMUX1_OVR_IRQHandler
+
+ B .
+
+ ENDP
+
+ ALIGN
+
+;*******************************************************************************
+; User Stack and Heap initialization
+;*******************************************************************************
+
+ END
+
+;************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE*****
diff --git a/targets/TARGET_STM/TARGET_STM32WL/TARGET_STM32WLE4x8/TOOLCHAIN_ARM/stm32wle4x8.sct b/targets/TARGET_STM/TARGET_STM32WL/TARGET_STM32WLE4x8/TOOLCHAIN_ARM/stm32wle4x8.sct
new file mode 100644
index 0000000..9258e6a
--- /dev/null
+++ b/targets/TARGET_STM/TARGET_STM32WL/TARGET_STM32WLE4x8/TOOLCHAIN_ARM/stm32wle4x8.sct
@@ -0,0 +1,57 @@
+#! armclang -E --target=arm-arm-none-eabi -x c -mcpu=cortex-M4
+; Scatter-Loading Description File
+;
+; SPDX-License-Identifier: BSD-3-Clause
+;******************************************************************************
+;* @attention
+;*
+;* Copyright (c) 2016-2020 STMicroelectronics.
+;* All rights reserved.
+;*
+;* This software component is licensed by ST under BSD 3-Clause license,
+;* the "License"; You may not use this file except in compliance with the
+;* License. You may obtain a copy of the License at:
+;* opensource.org/licenses/BSD-3-Clause
+;*
+;******************************************************************************
+
+#include "../cmsis_nvic.h"
+
+#if !defined(MBED_APP_START)
+ #define MBED_APP_START MBED_ROM_START
+#endif
+
+#if !defined(MBED_APP_SIZE)
+ #define MBED_APP_SIZE MBED_ROM_SIZE
+#endif
+
+#if !defined(MBED_CONF_TARGET_BOOT_STACK_SIZE)
+/* This value is normally defined by the tools to 0x1000 for bare metal and 0x400 for RTOS */
+#if defined(MBED_BOOT_STACK_SIZE)
+#define MBED_CONF_TARGET_BOOT_STACK_SIZE MBED_BOOT_STACK_SIZE
+#else
+#define MBED_CONF_TARGET_BOOT_STACK_SIZE 0x400
+#endif
+#endif
+
+/* Round up VECTORS_SIZE to 8 bytes */
+#define VECTORS_SIZE (((NVIC_NUM_VECTORS * 4) + 7) AND ~7)
+
+LR_IROM1 MBED_APP_START MBED_APP_SIZE {
+
+ ER_IROM1 MBED_APP_START MBED_APP_SIZE {
+ *.o (RESET, +First)
+ *(InRoot$$Sections)
+ .ANY (+RO)
+ }
+
+ RW_IRAM1 (MBED_RAM_START + VECTORS_SIZE) { ; RW data
+ .ANY (+RW +ZI)
+ }
+
+ ARM_LIB_HEAP AlignExpr(+0, 16) EMPTY (MBED_RAM_START + MBED_RAM_SIZE - MBED_CONF_TARGET_BOOT_STACK_SIZE - AlignExpr(ImageLimit(RW_IRAM1), 16)) { ; Heap growing up
+ }
+
+ ARM_LIB_STACK (MBED_RAM_START + MBED_RAM_SIZE) EMPTY -MBED_CONF_TARGET_BOOT_STACK_SIZE { ; Stack region growing down
+ }
+}
diff --git a/targets/TARGET_STM/TARGET_STM32WL/TARGET_STM32WLE4x8/TOOLCHAIN_GCC_ARM/startup_stm32wle4xx.S b/targets/TARGET_STM/TARGET_STM32WL/TARGET_STM32WLE4x8/TOOLCHAIN_GCC_ARM/startup_stm32wle4xx.S
new file mode 100644
index 0000000..c919abb
--- /dev/null
+++ b/targets/TARGET_STM/TARGET_STM32WL/TARGET_STM32WLE4x8/TOOLCHAIN_GCC_ARM/startup_stm32wle4xx.S
@@ -0,0 +1,425 @@
+/**
+ ******************************************************************************
+ * @file startup_stm32wle4xx.s
+ * @author MCD Application Team
+ * @brief STM32WLE4xx devices vector table for GCC toolchain.
+ * This module performs:
+ * - Set the initial SP
+ * - Set the initial PC == Reset_Handler,
+ * - Set the vector table entries with the exceptions ISR address,
+ * - Branches to main in the C library (which eventually
+ * calls main()).
+ * After Reset the Cortex-M4 processor is in Thread mode,
+ * priority is Privileged, and the Stack is set to Main.
+ ******************************************************************************
+ * @attention
+ *
+ * © Copyright (c) 2020 STMicroelectronics.
+ * All rights reserved.
+ *
+ * This software component is licensed by ST under Apache License, Version 2.0,
+ * the "License"; You may not use this file except in compliance with the
+ * License. You may obtain a copy of the License at:
+ * opensource.org/licenses/Apache-2.0
+ *
+ ******************************************************************************
+ */
+
+.syntax unified
+.cpu cortex-m4
+.fpu softvfp
+.thumb
+
+.global g_pfnVectors
+.global Default_Handler
+
+/* start address for the initialization values of the .data section.
+defined in linker script */
+.word _sidata
+/* start address for the .data section. defined in linker script */
+.word _sdata
+/* end address for the .data section. defined in linker script */
+.word _edata
+/* start address for the .bss section. defined in linker script */
+.word _sbss
+/* end address for the .bss section. defined in linker script */
+.word _ebss
+
+/**
+ * @brief This is the code that gets called when the processor first
+ * starts execution following a reset event. Only the absolutely
+ * necessary set is performed, after which the application
+ * supplied main() routine is called.
+ * @param None
+ * @retval : None
+*/
+
+ .section .text.Reset_Handler
+ .weak Reset_Handler
+ .type Reset_Handler, %function
+Reset_Handler:
+ ldr r0, =_estack
+ mov sp, r0 /* set stack pointer */
+
+/* Call the clock system initialization function.*/
+ bl SystemInit
+
+/* Copy the data segment initializers from flash to SRAM */
+ ldr r0, =_sdata
+ ldr r1, =_edata
+ ldr r2, =_sidata
+ movs r3, #0
+ b LoopCopyDataInit
+
+CopyDataInit:
+ ldr r4, [r2, r3]
+ str r4, [r0, r3]
+ adds r3, r3, #4
+
+LoopCopyDataInit:
+ adds r4, r0, r3
+ cmp r4, r1
+ bcc CopyDataInit
+
+/* Zero fill the bss segment. */
+ ldr r2, =_sbss
+ ldr r4, =_ebss
+ movs r3, #0
+ b LoopFillZerobss
+
+FillZerobss:
+ str r3, [r2]
+ adds r2, r2, #4
+
+LoopFillZerobss:
+ cmp r2, r4
+ bcc FillZerobss
+
+ bl _start
+ bx lr
+
+LoopForever:
+ b LoopForever
+
+ .size Reset_Handler, .-Reset_Handler
+
+/**
+ * @brief This is the code that gets called when the processor receives an
+ * unexpected interrupt. This simply enters an infinite loop, preserving
+ * the system state for examination by a debugger.
+ *
+ * @param None
+ * @retval : None
+*/
+ .section .text.Default_Handler,"ax",%progbits
+Default_Handler:
+Infinite_Loop:
+ b Infinite_Loop
+ .size Default_Handler, .-Default_Handler
+
+/******************************************************************************
+*
+* The STM32WLE4xx vector table. Note that the proper constructs
+* must be placed on this to ensure that it ends up at physical address
+* 0x0000.0000.
+*
+******************************************************************************/
+ .section .isr_vector,"a",%progbits
+ .type g_pfnVectors, %object
+ .size g_pfnVectors, .-g_pfnVectors
+
+g_pfnVectors:
+ .word _estack
+ .word Reset_Handler
+ .word NMI_Handler
+ .word HardFault_Handler
+ .word MemManage_Handler
+ .word BusFault_Handler
+ .word UsageFault_Handler
+ .word 0
+ .word 0
+ .word 0
+ .word 0
+ .word SVC_Handler
+ .word DebugMon_Handler
+ .word 0
+ .word PendSV_Handler
+ .word SysTick_Handler
+ .word WWDG_IRQHandler /* Window Watchdog interrupt */
+ .word PVD_PVM_IRQHandler /* PVD and PVM interrupt through EXTI */
+ .word TAMP_STAMP_LSECSS_SSRU_IRQHandler /* RTC Tamper, RTC TimeStamp, LSECSS and RTC SSRU int.*/
+ .word RTC_WKUP_IRQHandler /* RTC wakeup interrupt through EXTI[19] */
+ .word FLASH_IRQHandler /* Flash memory global interrupt and Flash memory ECC */
+ .word RCC_IRQHandler /* RCC global interrupt */
+ .word EXTI0_IRQHandler /* EXTI line 0 interrupt */
+ .word EXTI1_IRQHandler /* EXTI line 1 interrupt */
+ .word EXTI2_IRQHandler /* EXTI line 2 interrupt */
+ .word EXTI3_IRQHandler /* EXTI line 3 interrupt */
+ .word EXTI4_IRQHandler /* EXTI line 4 interrupt */
+ .word DMA1_Channel1_IRQHandler /* DMA1 channel 1 interrupt */
+ .word DMA1_Channel2_IRQHandler /* DMA1 channel 2 interrupt */
+ .word DMA1_Channel3_IRQHandler /* DMA1 channel 3 interrupt */
+ .word DMA1_Channel4_IRQHandler /* DMA1 channel 4 interrupt */
+ .word DMA1_Channel5_IRQHandler /* DMA1 channel 5 interrupt */
+ .word DMA1_Channel6_IRQHandler /* DMA1 channel 6 interrupt */
+ .word DMA1_Channel7_IRQHandler /* DMA1 channel 7 interrupt */
+ .word ADC_IRQHandler /* ADC interrupt */
+ .word DAC_IRQHandler /* DAC interrupt */
+ .word 0 /* Reserved */
+ .word COMP_IRQHandler /* COMP1 and COMP2 interrupt through EXTI */
+ .word EXTI9_5_IRQHandler /* EXTI line 9_5 interrupt */
+ .word TIM1_BRK_IRQHandler /* Timer 1 break interrupt */
+ .word TIM1_UP_IRQHandler /* Timer 1 Update */
+ .word TIM1_TRG_COM_IRQHandler /* Timer 1 trigger and communication */
+ .word TIM1_CC_IRQHandler /* Timer 1 capture compare interrupt */
+ .word TIM2_IRQHandler /* TIM2 global interrupt */
+ .word TIM16_IRQHandler /* Timer 16 global interrupt */
+ .word TIM17_IRQHandler /* Timer 17 global interrupt */
+ .word I2C1_EV_IRQHandler /* I2C1 event interrupt */
+ .word I2C1_ER_IRQHandler /* I2C1 event interrupt */
+ .word I2C2_EV_IRQHandler /* I2C2 error interrupt */
+ .word I2C2_ER_IRQHandler /* I2C2 error interrupt */
+ .word SPI1_IRQHandler /* SPI1 global interrupt */
+ .word SPI2_IRQHandler /* SPI2 global interrupt */
+ .word USART1_IRQHandler /* USART1 global interrupt */
+ .word USART2_IRQHandler /* USART2 global interrupt */
+ .word LPUART1_IRQHandler /* LPUART1 global interrupt */
+ .word LPTIM1_IRQHandler /* LPtimer 1 global interrupt */
+ .word LPTIM2_IRQHandler /* LPtimer 2 global interrupt */
+ .word EXTI15_10_IRQHandler /* EXTI line 15_10] interrupt through EXTI */
+ .word RTC_Alarm_IRQHandler /* RTC Alarms A & B interrupt */
+ .word LPTIM3_IRQHandler /* LPtimer 3 global interrupt */
+ .word SUBGHZSPI_IRQHandler /* SUBGHZSPI global interrupt */
+ .word 0 /* Reserved */
+ .word 0 /* Reserved */
+ .word HSEM_IRQHandler /* Semaphore interrupt 0 to CPU1 */
+ .word I2C3_EV_IRQHandler /* I2C3 event interrupt */
+ .word I2C3_ER_IRQHandler /* I2C3 error interrupt */
+ .word SUBGHZ_Radio_IRQHandler /* Radio IRQs RFBUSY interrupt through EXTI */
+ .word AES_IRQHandler /* AES global interrupt */
+ .word RNG_IRQHandler /* RNG interrupt */
+ .word PKA_IRQHandler /* PKA interrupt */
+ .word DMA2_Channel1_IRQHandler /* DMA2 channel 1 interrupt */
+ .word DMA2_Channel2_IRQHandler /* DMA2 channel 2 interrupt */
+ .word DMA2_Channel3_IRQHandler /* DMA2 channel 3 interrupt */
+ .word DMA2_Channel4_IRQHandler /* DMA2 channel 4 interrupt */
+ .word DMA2_Channel5_IRQHandler /* DMA2 channel 5 interrupt */
+ .word DMA2_Channel6_IRQHandler /* DMA2 channel 6 interrupt */
+ .word DMA2_Channel7_IRQHandler /* DMA2 channel 7 interrupt */
+ .word DMAMUX1_OVR_IRQHandler /* DMAMUX overrun interrupt */
+
+/*******************************************************************************
+*
+* Provide weak aliases for each Exception handler to the Default_Handler.
+* As they are weak aliases, any function with the same name will override
+* this definition.
+*
+*******************************************************************************/
+
+ .weak NMI_Handler
+ .thumb_set NMI_Handler,Default_Handler
+
+ .weak HardFault_Handler
+ .thumb_set HardFault_Handler,Default_Handler
+
+ .weak MemManage_Handler
+ .thumb_set MemManage_Handler,Default_Handler
+
+ .weak BusFault_Handler
+ .thumb_set BusFault_Handler,Default_Handler
+
+ .weak UsageFault_Handler
+ .thumb_set UsageFault_Handler,Default_Handler
+
+ .weak SVC_Handler
+ .thumb_set SVC_Handler,Default_Handler
+
+ .weak DebugMon_Handler
+ .thumb_set DebugMon_Handler,Default_Handler
+
+ .weak PendSV_Handler
+ .thumb_set PendSV_Handler,Default_Handler
+
+ .weak SysTick_Handler
+ .thumb_set SysTick_Handler,Default_Handler
+
+ .weak WWDG_IRQHandler
+ .thumb_set WWDG_IRQHandler,Default_Handler
+
+ .weak PVD_PVM_IRQHandler
+ .thumb_set PVD_PVM_IRQHandler,Default_Handler
+
+ .weak TAMP_STAMP_LSECSS_SSRU_IRQHandler
+ .thumb_set TAMP_STAMP_LSECSS_SSRU_IRQHandler,Default_Handler
+
+ .weak RTC_WKUP_IRQHandler
+ .thumb_set RTC_WKUP_IRQHandler,Default_Handler
+
+ .weak FLASH_IRQHandler
+ .thumb_set FLASH_IRQHandler,Default_Handler
+
+ .weak RCC_IRQHandler
+ .thumb_set RCC_IRQHandler,Default_Handler
+
+ .weak EXTI0_IRQHandler
+ .thumb_set EXTI0_IRQHandler,Default_Handler
+
+ .weak EXTI1_IRQHandler
+ .thumb_set EXTI1_IRQHandler,Default_Handler
+
+ .weak EXTI2_IRQHandler
+ .thumb_set EXTI2_IRQHandler,Default_Handler
+
+ .weak EXTI3_IRQHandler
+ .thumb_set EXTI3_IRQHandler,Default_Handler
+
+ .weak EXTI4_IRQHandler
+ .thumb_set EXTI4_IRQHandler,Default_Handler
+
+ .weak DMA1_Channel1_IRQHandler
+ .thumb_set DMA1_Channel1_IRQHandler,Default_Handler
+
+ .weak DMA1_Channel2_IRQHandler
+ .thumb_set DMA1_Channel2_IRQHandler,Default_Handler
+
+ .weak DMA1_Channel3_IRQHandler
+ .thumb_set DMA1_Channel3_IRQHandler,Default_Handler
+
+ .weak DMA1_Channel4_IRQHandler
+ .thumb_set DMA1_Channel4_IRQHandler,Default_Handler
+
+ .weak DMA1_Channel5_IRQHandler
+ .thumb_set DMA1_Channel5_IRQHandler,Default_Handler
+
+ .weak DMA1_Channel6_IRQHandler
+ .thumb_set DMA1_Channel6_IRQHandler,Default_Handler
+
+ .weak DMA1_Channel7_IRQHandler
+ .thumb_set DMA1_Channel7_IRQHandler,Default_Handler
+
+ .weak ADC_IRQHandler
+ .thumb_set ADC_IRQHandler,Default_Handler
+
+ .weak DAC_IRQHandler
+ .thumb_set DAC_IRQHandler,Default_Handler
+
+ .weak COMP_IRQHandler
+ .thumb_set COMP_IRQHandler,Default_Handler
+
+ .weak EXTI9_5_IRQHandler
+ .thumb_set EXTI9_5_IRQHandler,Default_Handler
+
+ .weak TIM1_BRK_IRQHandler
+ .thumb_set TIM1_BRK_IRQHandler,Default_Handler
+
+ .weak TIM1_UP_IRQHandler
+ .thumb_set TIM1_UP_IRQHandler,Default_Handler
+
+ .weak TIM1_TRG_COM_IRQHandler
+ .thumb_set TIM1_TRG_COM_IRQHandler,Default_Handler
+
+ .weak TIM1_CC_IRQHandler
+ .thumb_set TIM1_CC_IRQHandler,Default_Handler
+
+ .weak TIM2_IRQHandler
+ .thumb_set TIM2_IRQHandler,Default_Handler
+
+ .weak TIM16_IRQHandler
+ .thumb_set TIM16_IRQHandler,Default_Handler
+
+ .weak TIM17_IRQHandler
+ .thumb_set TIM17_IRQHandler,Default_Handler
+
+ .weak I2C1_EV_IRQHandler
+ .thumb_set I2C1_EV_IRQHandler,Default_Handler
+
+ .weak I2C1_ER_IRQHandler
+ .thumb_set I2C1_ER_IRQHandler,Default_Handler
+
+ .weak I2C2_EV_IRQHandler
+ .thumb_set I2C2_EV_IRQHandler,Default_Handler
+
+ .weak I2C2_ER_IRQHandler
+ .thumb_set I2C2_ER_IRQHandler,Default_Handler
+
+ .weak SPI1_IRQHandler
+ .thumb_set SPI1_IRQHandler,Default_Handler
+
+ .weak SPI2_IRQHandler
+ .thumb_set SPI2_IRQHandler,Default_Handler
+
+ .weak USART1_IRQHandler
+ .thumb_set USART1_IRQHandler,Default_Handler
+
+ .weak USART2_IRQHandler
+ .thumb_set USART2_IRQHandler,Default_Handler
+
+ .weak LPUART1_IRQHandler
+ .thumb_set LPUART1_IRQHandler,Default_Handler
+
+ .weak LPTIM1_IRQHandler
+ .thumb_set LPTIM1_IRQHandler,Default_Handler
+
+ .weak LPTIM2_IRQHandler
+ .thumb_set LPTIM2_IRQHandler,Default_Handler
+
+ .weak EXTI15_10_IRQHandler
+ .thumb_set EXTI15_10_IRQHandler,Default_Handler
+
+ .weak RTC_Alarm_IRQHandler
+ .thumb_set RTC_Alarm_IRQHandler,Default_Handler
+
+ .weak LPTIM3_IRQHandler
+ .thumb_set LPTIM3_IRQHandler,Default_Handler
+
+ .weak SUBGHZSPI_IRQHandler
+ .thumb_set SUBGHZSPI_IRQHandler,Default_Handler
+
+ .weak HSEM_IRQHandler
+ .thumb_set HSEM_IRQHandler,Default_Handler
+
+ .weak I2C3_EV_IRQHandler
+ .thumb_set I2C3_EV_IRQHandler,Default_Handler
+
+ .weak I2C3_ER_IRQHandler
+ .thumb_set I2C3_ER_IRQHandler,Default_Handler
+
+ .weak SUBGHZ_Radio_IRQHandler
+ .thumb_set SUBGHZ_Radio_IRQHandler,Default_Handler
+
+ .weak AES_IRQHandler
+ .thumb_set AES_IRQHandler,Default_Handler
+
+ .weak RNG_IRQHandler
+ .thumb_set RNG_IRQHandler,Default_Handler
+
+ .weak PKA_IRQHandler
+ .thumb_set PKA_IRQHandler,Default_Handler
+
+ .weak DMA2_Channel1_IRQHandler
+ .thumb_set DMA2_Channel1_IRQHandler,Default_Handler
+
+ .weak DMA2_Channel2_IRQHandler
+ .thumb_set DMA2_Channel2_IRQHandler,Default_Handler
+
+ .weak DMA2_Channel3_IRQHandler
+ .thumb_set DMA2_Channel3_IRQHandler,Default_Handler
+
+ .weak DMA2_Channel4_IRQHandler
+ .thumb_set DMA2_Channel4_IRQHandler,Default_Handler
+
+ .weak DMA2_Channel5_IRQHandler
+ .thumb_set DMA2_Channel5_IRQHandler,Default_Handler
+
+ .weak DMA2_Channel6_IRQHandler
+ .thumb_set DMA2_Channel6_IRQHandler,Default_Handler
+
+ .weak DMA2_Channel7_IRQHandler
+ .thumb_set DMA2_Channel7_IRQHandler,Default_Handler
+
+ .weak DMAMUX1_OVR_IRQHandler
+ .thumb_set DMAMUX1_OVR_IRQHandler,Default_Handler
+
+ .weak SystemInit
+
+/************************ (C) COPYRIGHT STMicroelectonics *****END OF FILE****/
diff --git a/targets/TARGET_STM/TARGET_STM32WL/TARGET_STM32WLE4x8/TOOLCHAIN_GCC_ARM/stm32wle4x8.ld b/targets/TARGET_STM/TARGET_STM32WL/TARGET_STM32WLE4x8/TOOLCHAIN_GCC_ARM/stm32wle4x8.ld
new file mode 100644
index 0000000..5f47993
--- /dev/null
+++ b/targets/TARGET_STM/TARGET_STM32WL/TARGET_STM32WLE4x8/TOOLCHAIN_GCC_ARM/stm32wle4x8.ld
@@ -0,0 +1,203 @@
+/* Linker script to configure memory regions. */
+/*
+ * SPDX-License-Identifier: BSD-3-Clause
+ ******************************************************************************
+ * @attention
+ *
+ * Copyright (c) 2016-2020 STMicroelectronics.
+ * All rights reserved.
+ *
+ * This software component is licensed by ST under BSD 3-Clause license,
+ * the "License"; You may not use this file except in compliance with the
+ * License. You may obtain a copy of the License at:
+ * opensource.org/licenses/BSD-3-Clause
+ *
+ ******************************************************************************
+*/
+
+#include "../cmsis_nvic.h"
+
+
+#if !defined(MBED_APP_START)
+ #define MBED_APP_START MBED_ROM_START
+#endif
+
+#if !defined(MBED_APP_SIZE)
+ #define MBED_APP_SIZE MBED_ROM_SIZE
+#endif
+
+#if !defined(MBED_CONF_TARGET_BOOT_STACK_SIZE)
+ /* This value is normally defined by the tools
+ to 0x1000 for bare metal and 0x400 for RTOS */
+ #define MBED_CONF_TARGET_BOOT_STACK_SIZE 0x400
+#endif
+
+/* Round up VECTORS_SIZE to 8 bytes */
+#define VECTORS_SIZE (((NVIC_NUM_VECTORS * 4) + 7) & 0xFFFFFFF8)
+
+MEMORY
+{
+ FLASH (rx) : ORIGIN = MBED_APP_START, LENGTH = MBED_APP_SIZE
+ RAM (rwx) : ORIGIN = MBED_RAM_START + VECTORS_SIZE, LENGTH = MBED_RAM_SIZE - VECTORS_SIZE
+}
+
+/* Linker script to place sections and symbol values. Should be used together
+ * with other linker script that defines memory regions FLASH and RAM.
+ * It references following symbols, which must be defined in code:
+ * Reset_Handler : Entry of reset handler
+ *
+ * It defines following symbols, which code can use without definition:
+ * __exidx_start
+ * __exidx_end
+ * __etext
+ * __data_start__
+ * __preinit_array_start
+ * __preinit_array_end
+ * __init_array_start
+ * __init_array_end
+ * __fini_array_start
+ * __fini_array_end
+ * __data_end__
+ * __bss_start__
+ * __bss_end__
+ * __end__
+ * end
+ * __HeapLimit
+ * __StackLimit
+ * __StackTop
+ * __stack
+ * _estack
+ */
+ENTRY(Reset_Handler)
+
+SECTIONS
+{
+ .text :
+ {
+ KEEP(*(.isr_vector))
+ *(.text*)
+
+ KEEP(*(.init))
+ KEEP(*(.fini))
+
+ /* .ctors */
+ *crtbegin.o(.ctors)
+ *crtbegin?.o(.ctors)
+ *(EXCLUDE_FILE(*crtend?.o *crtend.o) .ctors)
+ *(SORT(.ctors.*))
+ *(.ctors)
+
+ /* .dtors */
+ *crtbegin.o(.dtors)
+ *crtbegin?.o(.dtors)
+ *(EXCLUDE_FILE(*crtend?.o *crtend.o) .dtors)
+ *(SORT(.dtors.*))
+ *(.dtors)
+
+ *(.rodata*)
+
+ KEEP(*(.eh_frame*))
+ } > FLASH
+
+ .ARM.extab :
+ {
+ *(.ARM.extab* .gnu.linkonce.armextab.*)
+ } > FLASH
+
+ __exidx_start = .;
+ .ARM.exidx :
+ {
+ *(.ARM.exidx* .gnu.linkonce.armexidx.*)
+ } > FLASH
+ __exidx_end = .;
+
+ __etext = .;
+ _sidata = .;
+
+ .data : AT (__etext)
+ {
+ __data_start__ = .;
+ _sdata = .;
+ *(vtable)
+ *(.data*)
+
+ . = ALIGN(8);
+ /* preinit data */
+ PROVIDE_HIDDEN (__preinit_array_start = .);
+ KEEP(*(.preinit_array))
+ PROVIDE_HIDDEN (__preinit_array_end = .);
+
+ . = ALIGN(8);
+ /* init data */
+ PROVIDE_HIDDEN (__init_array_start = .);
+ KEEP(*(SORT(.init_array.*)))
+ KEEP(*(.init_array))
+ PROVIDE_HIDDEN (__init_array_end = .);
+
+ . = ALIGN(8);
+ /* finit data */
+ PROVIDE_HIDDEN (__fini_array_start = .);
+ KEEP(*(SORT(.fini_array.*)))
+ KEEP(*(.fini_array))
+ PROVIDE_HIDDEN (__fini_array_end = .);
+
+ KEEP(*(.jcr*))
+ . = ALIGN(8);
+ /* All data end */
+ __data_end__ = .;
+ _edata = .;
+
+ } > RAM
+
+ /* Uninitialized data section
+ * This region is not initialized by the C/C++ library and can be used to
+ * store state across soft reboots. */
+ .uninitialized (NOLOAD):
+ {
+ . = ALIGN(32);
+ __uninitialized_start = .;
+ *(.uninitialized)
+ KEEP(*(.keep.uninitialized))
+ . = ALIGN(32);
+ __uninitialized_end = .;
+ } > RAM
+
+ .bss :
+ {
+ . = ALIGN(8);
+ __bss_start__ = .;
+ _sbss = .;
+ *(.bss*)
+ *(COMMON)
+ . = ALIGN(8);
+ __bss_end__ = .;
+ _ebss = .;
+ } > RAM
+
+ .heap (COPY):
+ {
+ __end__ = .;
+ PROVIDE(end = .);
+ *(.heap*)
+ . = ORIGIN(RAM) + LENGTH(RAM) - MBED_CONF_TARGET_BOOT_STACK_SIZE;
+ __HeapLimit = .;
+ } > RAM
+
+ /* .stack_dummy section doesn't contains any symbols. It is only
+ * used for linker to calculate size of stack sections, and assign
+ * values to stack symbols later */
+ .stack_dummy (COPY):
+ {
+ *(.stack*)
+ } > RAM
+
+ /* Set stack top to end of RAM, and stack limit move down by
+ * size of stack_dummy section */
+ __StackTop = ORIGIN(RAM) + LENGTH(RAM);
+ _estack = __StackTop;
+ __StackLimit = __StackTop - MBED_CONF_TARGET_BOOT_STACK_SIZE;
+ PROVIDE(__stack = __StackTop);
+
+ /* Check if data + heap + stack exceeds RAM limit */
+ ASSERT(__StackLimit >= __HeapLimit, "region RAM overflowed with stack")
+}
diff --git a/targets/TARGET_STM/TARGET_STM32WL/TARGET_STM32WLE4x8/TOOLCHAIN_IAR/startup_stm32wle4xx.S b/targets/TARGET_STM/TARGET_STM32WL/TARGET_STM32WLE4x8/TOOLCHAIN_IAR/startup_stm32wle4xx.S
new file mode 100644
index 0000000..0072684
--- /dev/null
+++ b/targets/TARGET_STM/TARGET_STM32WL/TARGET_STM32WLE4x8/TOOLCHAIN_IAR/startup_stm32wle4xx.S
@@ -0,0 +1,494 @@
+;********************************************************************************
+;* File Name : startup_stm32wle4xx.s
+;* Author : MCD Application Team
+;* Description : M4 core vector table of the STM32WLxxxx devices for the
+;* IAR (EWARM) toolchain.
+;*
+;* This module performs:
+;* - Set the initial SP
+;* - Set the initial PC == _iar_program_start,
+;* - Set the vector table entries with the exceptions ISR
+;* address.
+;* - Branches to main in the C library (which eventually
+;* calls main()).
+;* After Reset the Cortex-M4 processor is in Thread mode,
+;* priority is Privileged, and the Stack is set to Main.
+;********************************************************************************
+;*
+;* Copyright (c) 2020 STMicroelectronics. All rights reserved.
+;*
+;* This software component is licensed by ST under Apache License, Version 2.0,
+;* the "License"; You may not use this file except in compliance with the
+;* License. You may obtain a copy of the License at:
+;* opensource.org/licenses/Apache-2.0
+;
+;*******************************************************************************
+;
+;
+; The modules in this file are included in the libraries, and may be replaced
+; by any user-defined modules that define the PUBLIC symbol _program_start or
+; a user defined start symbol.
+; To override the cstartup defined in the library, simply add your modified
+; version to the workbench project.
+;
+; The vector table is normally located at address 0.
+; When debugging in RAM, it can be located in RAM, aligned to at least 2^6.
+; The name "__vector_table" has special meaning for C-SPY:
+; it is where the SP start value is found, and the NVIC vector
+; table register (VTOR) is initialized to this address if != 0.
+;
+; Cortex-M version
+;
+
+ MODULE ?cstartup
+
+ ;; Forward declaration of sections.
+ SECTION CSTACK:DATA:NOROOT(3)
+
+ SECTION .intvec:CODE:NOROOT(2)
+
+ EXTERN __iar_program_start
+ EXTERN SystemInit
+ PUBLIC __vector_table
+
+ DATA
+__vector_table
+ DCD sfe(CSTACK)
+ DCD Reset_Handler ; Reset Handler
+
+ DCD NMI_Handler ; NMI Handler
+ DCD HardFault_Handler ; Hard Fault Handler
+ DCD MemManage_Handler ; MPU Fault Handler
+ DCD BusFault_Handler ; Bus Fault Handler
+ DCD UsageFault_Handler ; Usage Fault Handler
+ DCD 0 ; Reserved
+ DCD 0 ; Reserved
+ DCD 0 ; Reserved
+ DCD 0 ; Reserved
+ DCD SVC_Handler ; SVCall Handler
+ DCD DebugMon_Handler ; Debug Monitor Handler
+ DCD 0 ; Reserved
+ DCD PendSV_Handler ; PendSV Handler
+ DCD SysTick_Handler ; SysTick Handler
+
+ ; External Interrupts
+ DCD WWDG_IRQHandler ; Window WatchDog
+ DCD PVD_PVM_IRQHandler ; PVD and PVM Interrupt
+ DCD TAMP_STAMP_LSECSS_SSRU_IRQHandler ; RTC Tamper, RTC TimeStamp, LSECSS and RTC SSRU Interrupts
+ DCD RTC_WKUP_IRQHandler ; RTC Wakeup Interrupt
+ DCD FLASH_IRQHandler ; FLASH global Interrupt
+ DCD RCC_IRQHandler ; RCC Interrupt
+ DCD EXTI0_IRQHandler ; EXTI Line 0 Interrupt
+ DCD EXTI1_IRQHandler ; EXTI Line 1 Interrupt
+ DCD EXTI2_IRQHandler ; EXTI Line 2 Interrupt
+ DCD EXTI3_IRQHandler ; EXTI Line 3 Interrupt
+ DCD EXTI4_IRQHandler ; EXTI Line 4 Interrupt
+ DCD DMA1_Channel1_IRQHandler ; DMA1 Channel 1 Interrupt
+ DCD DMA1_Channel2_IRQHandler ; DMA1 Channel 2 Interrupt
+ DCD DMA1_Channel3_IRQHandler ; DMA1 Channel 3 Interrupt
+ DCD DMA1_Channel4_IRQHandler ; DMA1 Channel 4 Interrupt
+ DCD DMA1_Channel5_IRQHandler ; DMA1 Channel 5 Interrupt
+ DCD DMA1_Channel6_IRQHandler ; DMA1 Channel 6 Interrupt
+ DCD DMA1_Channel7_IRQHandler ; DMA1 Channel 7 Interrupt
+ DCD ADC_IRQHandler ; ADC Interrupt
+ DCD DAC_IRQHandler ; DAC Interrupt
+ DCD 0 ; Reserved
+ DCD COMP_IRQHandler ; COMP1 and COMP2 Interrupts
+ DCD EXTI9_5_IRQHandler ; EXTI Lines [9:5] Interrupt
+ DCD TIM1_BRK_IRQHandler ; TIM1 Break Interrupt
+ DCD TIM1_UP_IRQHandler ; TIM1 Update Interrupt
+ DCD TIM1_TRG_COM_IRQHandler ; TIM1 Trigger and Communication Interrupts
+ DCD TIM1_CC_IRQHandler ; TIM1 Capture Compare Interrupt
+ DCD TIM2_IRQHandler ; TIM2 Global Interrupt
+ DCD TIM16_IRQHandler ; TIM16 Global Interrupt
+ DCD TIM17_IRQHandler ; TIM17 Global Interrupt
+ DCD I2C1_EV_IRQHandler ; I2C1 Event Interrupt
+ DCD I2C1_ER_IRQHandler ; I2C1 Error Interrupt
+ DCD I2C2_EV_IRQHandler ; I2C2 Event Interrupt
+ DCD I2C2_ER_IRQHandler ; I2C2 Error Interrupt
+ DCD SPI1_IRQHandler ; SPI1 Interrupt
+ DCD SPI2_IRQHandler ; SPI2 Interrupt
+ DCD USART1_IRQHandler ; USART1 Interrupt
+ DCD USART2_IRQHandler ; USART2 Interrupt
+ DCD LPUART1_IRQHandler ; LPUART1 Interrupt
+ DCD LPTIM1_IRQHandler ; LPTIM1 Global Interrupt
+ DCD LPTIM2_IRQHandler ; LPTIM2 Global Interrupt
+ DCD EXTI15_10_IRQHandler ; EXTI Lines [15:10] Interrupt
+ DCD RTC_Alarm_IRQHandler ; RTC Alarms (A and B) Interrupt
+ DCD LPTIM3_IRQHandler ; LPTIM3 Global Interrupt
+ DCD SUBGHZSPI_IRQHandler ; SUBGHZSPI Interrupt
+ DCD 0 ; Reserved
+ DCD 0 ; Reserved
+ DCD HSEM_IRQHandler ; HSEM0 Interrupt
+ DCD I2C3_EV_IRQHandler ; I2C3 Event Interrupt
+ DCD I2C3_ER_IRQHandler ; I2C3 Error Interrupt
+ DCD SUBGHZ_Radio_IRQHandler ; SUBGHZ Radio Interrupt
+ DCD AES_IRQHandler ; AES Interrupt
+ DCD RNG_IRQHandler ; RNG1 Interrupt
+ DCD PKA_IRQHandler ; PKA Interrupt
+ DCD DMA2_Channel1_IRQHandler ; DMA2 Channel 1 Interrupt
+ DCD DMA2_Channel2_IRQHandler ; DMA2 Channel 2 Interrupt
+ DCD DMA2_Channel3_IRQHandler ; DMA2 Channel 3 Interrupt
+ DCD DMA2_Channel4_IRQHandler ; DMA2 Channel 4 Interrupt
+ DCD DMA2_Channel5_IRQHandler ; DMA2 Channel 5 Interrupt
+ DCD DMA2_Channel6_IRQHandler ; DMA2 Channel 6 Interrupt
+ DCD DMA2_Channel7_IRQHandler ; DMA2 Channel 7 Interrupt
+ DCD DMAMUX1_OVR_IRQHandler ; DMAMUX overrun Interrupt
+
+;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;
+;;
+;; Default interrupt handlers.
+;;
+ THUMB
+
+ PUBWEAK Reset_Handler
+ SECTION .text:CODE:NOROOT:REORDER(2)
+Reset_Handler
+ LDR R0, =SystemInit
+ BLX R0
+ LDR R0, =__iar_program_start
+ BX R0
+
+ PUBWEAK NMI_Handler
+ SECTION .text:CODE:NOROOT:REORDER(1)
+NMI_Handler
+ B NMI_Handler
+
+ PUBWEAK HardFault_Handler
+ SECTION .text:CODE:NOROOT:REORDER(1)
+HardFault_Handler
+ B HardFault_Handler
+
+ PUBWEAK MemManage_Handler
+ SECTION .text:CODE:NOROOT:REORDER(1)
+MemManage_Handler
+ B MemManage_Handler
+
+ PUBWEAK BusFault_Handler
+ SECTION .text:CODE:NOROOT:REORDER(1)
+BusFault_Handler
+ B BusFault_Handler
+
+ PUBWEAK UsageFault_Handler
+ SECTION .text:CODE:NOROOT:REORDER(1)
+UsageFault_Handler
+ B UsageFault_Handler
+
+ PUBWEAK SVC_Handler
+ SECTION .text:CODE:NOROOT:REORDER(1)
+SVC_Handler
+ B SVC_Handler
+
+ PUBWEAK DebugMon_Handler
+ SECTION .text:CODE:NOROOT:REORDER(1)
+DebugMon_Handler
+ B DebugMon_Handler
+
+ PUBWEAK PendSV_Handler
+ SECTION .text:CODE:NOROOT:REORDER(1)
+PendSV_Handler
+ B PendSV_Handler
+
+ PUBWEAK SysTick_Handler
+ SECTION .text:CODE:NOROOT:REORDER(1)
+SysTick_Handler
+ B SysTick_Handler
+
+ PUBWEAK WWDG_IRQHandler
+ SECTION .text:CODE:NOROOT:REORDER(1)
+WWDG_IRQHandler
+ B WWDG_IRQHandler
+
+ PUBWEAK PVD_PVM_IRQHandler
+ SECTION .text:CODE:NOROOT:REORDER(1)
+PVD_PVM_IRQHandler
+ B PVD_PVM_IRQHandler
+
+ PUBWEAK TAMP_STAMP_LSECSS_SSRU_IRQHandler
+ SECTION .text:CODE:NOROOT:REORDER(1)
+TAMP_STAMP_LSECSS_SSRU_IRQHandler
+ B TAMP_STAMP_LSECSS_SSRU_IRQHandler
+
+ PUBWEAK RTC_WKUP_IRQHandler
+ SECTION .text:CODE:NOROOT:REORDER(1)
+RTC_WKUP_IRQHandler
+ B RTC_WKUP_IRQHandler
+
+ PUBWEAK FLASH_IRQHandler
+ SECTION .text:CODE:NOROOT:REORDER(1)
+FLASH_IRQHandler
+ B FLASH_IRQHandler
+
+ PUBWEAK RCC_IRQHandler
+ SECTION .text:CODE:NOROOT:REORDER(1)
+RCC_IRQHandler
+ B RCC_IRQHandler
+
+ PUBWEAK EXTI0_IRQHandler
+ SECTION .text:CODE:NOROOT:REORDER(1)
+EXTI0_IRQHandler
+ B EXTI0_IRQHandler
+
+ PUBWEAK EXTI1_IRQHandler
+ SECTION .text:CODE:NOROOT:REORDER(1)
+EXTI1_IRQHandler
+ B EXTI1_IRQHandler
+
+ PUBWEAK EXTI2_IRQHandler
+ SECTION .text:CODE:NOROOT:REORDER(1)
+EXTI2_IRQHandler
+ B EXTI2_IRQHandler
+
+ PUBWEAK EXTI3_IRQHandler
+ SECTION .text:CODE:NOROOT:REORDER(1)
+EXTI3_IRQHandler
+ B EXTI3_IRQHandler
+
+ PUBWEAK EXTI4_IRQHandler
+ SECTION .text:CODE:NOROOT:REORDER(1)
+EXTI4_IRQHandler
+ B EXTI4_IRQHandler
+
+ PUBWEAK DMA1_Channel1_IRQHandler
+ SECTION .text:CODE:NOROOT:REORDER(1)
+DMA1_Channel1_IRQHandler
+ B DMA1_Channel1_IRQHandler
+
+ PUBWEAK DMA1_Channel2_IRQHandler
+ SECTION .text:CODE:NOROOT:REORDER(1)
+DMA1_Channel2_IRQHandler
+ B DMA1_Channel2_IRQHandler
+
+ PUBWEAK DMA1_Channel3_IRQHandler
+ SECTION .text:CODE:NOROOT:REORDER(1)
+DMA1_Channel3_IRQHandler
+ B DMA1_Channel3_IRQHandler
+
+ PUBWEAK DMA1_Channel4_IRQHandler
+ SECTION .text:CODE:NOROOT:REORDER(1)
+DMA1_Channel4_IRQHandler
+ B DMA1_Channel4_IRQHandler
+
+ PUBWEAK DMA1_Channel5_IRQHandler
+ SECTION .text:CODE:NOROOT:REORDER(1)
+DMA1_Channel5_IRQHandler
+ B DMA1_Channel5_IRQHandler
+
+ PUBWEAK DMA1_Channel6_IRQHandler
+ SECTION .text:CODE:NOROOT:REORDER(1)
+DMA1_Channel6_IRQHandler
+ B DMA1_Channel6_IRQHandler
+
+ PUBWEAK DMA1_Channel7_IRQHandler
+ SECTION .text:CODE:NOROOT:REORDER(1)
+DMA1_Channel7_IRQHandler
+ B DMA1_Channel7_IRQHandler
+
+ PUBWEAK ADC_IRQHandler
+ SECTION .text:CODE:NOROOT:REORDER(1)
+ADC_IRQHandler
+ B ADC_IRQHandler
+
+ PUBWEAK DAC_IRQHandler
+ SECTION .text:CODE:NOROOT:REORDER(1)
+DAC_IRQHandler
+ B DAC_IRQHandler
+
+ PUBWEAK COMP_IRQHandler
+ SECTION .text:CODE:NOROOT:REORDER(1)
+COMP_IRQHandler
+ B COMP_IRQHandler
+
+ PUBWEAK EXTI9_5_IRQHandler
+ SECTION .text:CODE:NOROOT:REORDER(1)
+EXTI9_5_IRQHandler
+ B EXTI9_5_IRQHandler
+
+ PUBWEAK TIM1_BRK_IRQHandler
+ SECTION .text:CODE:NOROOT:REORDER(1)
+TIM1_BRK_IRQHandler
+ B TIM1_BRK_IRQHandler
+
+ PUBWEAK TIM1_UP_IRQHandler
+ SECTION .text:CODE:NOROOT:REORDER(1)
+TIM1_UP_IRQHandler
+ B TIM1_UP_IRQHandler
+
+ PUBWEAK TIM1_TRG_COM_IRQHandler
+ SECTION .text:CODE:NOROOT:REORDER(1)
+TIM1_TRG_COM_IRQHandler
+ B TIM1_TRG_COM_IRQHandler
+
+ PUBWEAK TIM1_CC_IRQHandler
+ SECTION .text:CODE:NOROOT:REORDER(1)
+TIM1_CC_IRQHandler
+ B TIM1_CC_IRQHandler
+
+ PUBWEAK TIM2_IRQHandler
+ SECTION .text:CODE:NOROOT:REORDER(1)
+TIM2_IRQHandler
+ B TIM2_IRQHandler
+
+ PUBWEAK TIM16_IRQHandler
+ SECTION .text:CODE:NOROOT:REORDER(1)
+TIM16_IRQHandler
+ B TIM16_IRQHandler
+
+ PUBWEAK TIM17_IRQHandler
+ SECTION .text:CODE:NOROOT:REORDER(1)
+TIM17_IRQHandler
+ B TIM17_IRQHandler
+
+ PUBWEAK I2C1_EV_IRQHandler
+ SECTION .text:CODE:NOROOT:REORDER(1)
+I2C1_EV_IRQHandler
+ B I2C1_EV_IRQHandler
+
+ PUBWEAK I2C1_ER_IRQHandler
+ SECTION .text:CODE:NOROOT:REORDER(1)
+I2C1_ER_IRQHandler
+ B I2C1_ER_IRQHandler
+
+ PUBWEAK I2C2_EV_IRQHandler
+ SECTION .text:CODE:NOROOT:REORDER(1)
+I2C2_EV_IRQHandler
+ B I2C2_EV_IRQHandler
+
+ PUBWEAK I2C2_ER_IRQHandler
+ SECTION .text:CODE:NOROOT:REORDER(1)
+I2C2_ER_IRQHandler
+ B I2C2_ER_IRQHandler
+
+ PUBWEAK SPI1_IRQHandler
+ SECTION .text:CODE:NOROOT:REORDER(1)
+SPI1_IRQHandler
+ B SPI1_IRQHandler
+
+ PUBWEAK SPI2_IRQHandler
+ SECTION .text:CODE:NOROOT:REORDER(1)
+SPI2_IRQHandler
+ B SPI2_IRQHandler
+
+ PUBWEAK USART1_IRQHandler
+ SECTION .text:CODE:NOROOT:REORDER(1)
+USART1_IRQHandler
+ B USART1_IRQHandler
+
+ PUBWEAK USART2_IRQHandler
+ SECTION .text:CODE:NOROOT:REORDER(1)
+USART2_IRQHandler
+ B USART2_IRQHandler
+
+ PUBWEAK LPUART1_IRQHandler
+ SECTION .text:CODE:NOROOT:REORDER(1)
+LPUART1_IRQHandler
+ B LPUART1_IRQHandler
+
+ PUBWEAK LPTIM1_IRQHandler
+ SECTION .text:CODE:NOROOT:REORDER(1)
+LPTIM1_IRQHandler
+ B LPTIM1_IRQHandler
+
+ PUBWEAK LPTIM2_IRQHandler
+ SECTION .text:CODE:NOROOT:REORDER(1)
+LPTIM2_IRQHandler
+ B LPTIM2_IRQHandler
+
+ PUBWEAK EXTI15_10_IRQHandler
+ SECTION .text:CODE:NOROOT:REORDER(1)
+EXTI15_10_IRQHandler
+ B EXTI15_10_IRQHandler
+
+ PUBWEAK RTC_Alarm_IRQHandler
+ SECTION .text:CODE:NOROOT:REORDER(1)
+RTC_Alarm_IRQHandler
+ B RTC_Alarm_IRQHandler
+
+ PUBWEAK LPTIM3_IRQHandler
+ SECTION .text:CODE:NOROOT:REORDER(1)
+LPTIM3_IRQHandler
+ B LPTIM3_IRQHandler
+
+ PUBWEAK SUBGHZSPI_IRQHandler
+ SECTION .text:CODE:NOROOT:REORDER(1)
+SUBGHZSPI_IRQHandler
+ B SUBGHZSPI_IRQHandler
+
+ PUBWEAK HSEM_IRQHandler
+ SECTION .text:CODE:NOROOT:REORDER(1)
+HSEM_IRQHandler
+ B HSEM_IRQHandler
+
+ PUBWEAK I2C3_EV_IRQHandler
+ SECTION .text:CODE:NOROOT:REORDER(1)
+I2C3_EV_IRQHandler
+ B I2C3_EV_IRQHandler
+
+ PUBWEAK I2C3_ER_IRQHandler
+ SECTION .text:CODE:NOROOT:REORDER(1)
+I2C3_ER_IRQHandler
+ B I2C3_ER_IRQHandler
+
+ PUBWEAK SUBGHZ_Radio_IRQHandler
+ SECTION .text:CODE:NOROOT:REORDER(1)
+SUBGHZ_Radio_IRQHandler
+ B SUBGHZ_Radio_IRQHandler
+
+ PUBWEAK AES_IRQHandler
+ SECTION .text:CODE:NOROOT:REORDER(1)
+AES_IRQHandler
+ B AES_IRQHandler
+
+ PUBWEAK RNG_IRQHandler
+ SECTION .text:CODE:NOROOT:REORDER(1)
+RNG_IRQHandler
+ B RNG_IRQHandler
+
+ PUBWEAK PKA_IRQHandler
+ SECTION .text:CODE:NOROOT:REORDER(1)
+PKA_IRQHandler
+ B PKA_IRQHandler
+
+ PUBWEAK DMA2_Channel1_IRQHandler
+ SECTION .text:CODE:NOROOT:REORDER(1)
+DMA2_Channel1_IRQHandler
+ B DMA2_Channel1_IRQHandler
+
+ PUBWEAK DMA2_Channel2_IRQHandler
+ SECTION .text:CODE:NOROOT:REORDER(1)
+DMA2_Channel2_IRQHandler
+ B DMA2_Channel2_IRQHandler
+
+ PUBWEAK DMA2_Channel3_IRQHandler
+ SECTION .text:CODE:NOROOT:REORDER(1)
+DMA2_Channel3_IRQHandler
+ B DMA2_Channel3_IRQHandler
+
+ PUBWEAK DMA2_Channel4_IRQHandler
+ SECTION .text:CODE:NOROOT:REORDER(1)
+DMA2_Channel4_IRQHandler
+ B DMA2_Channel4_IRQHandler
+
+ PUBWEAK DMA2_Channel5_IRQHandler
+ SECTION .text:CODE:NOROOT:REORDER(1)
+DMA2_Channel5_IRQHandler
+ B DMA2_Channel5_IRQHandler
+
+ PUBWEAK DMA2_Channel6_IRQHandler
+ SECTION .text:CODE:NOROOT:REORDER(1)
+DMA2_Channel6_IRQHandler
+ B DMA2_Channel6_IRQHandler
+
+ PUBWEAK DMA2_Channel7_IRQHandler
+ SECTION .text:CODE:NOROOT:REORDER(1)
+DMA2_Channel7_IRQHandler
+ B DMA2_Channel7_IRQHandler
+
+ PUBWEAK DMAMUX1_OVR_IRQHandler
+ SECTION .text:CODE:NOROOT:REORDER(1)
+DMAMUX1_OVR_IRQHandler
+ B DMAMUX1_OVR_IRQHandler
+
+ END
+
+;************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE*****
diff --git a/targets/TARGET_STM/TARGET_STM32WL/TARGET_STM32WLE4x8/TOOLCHAIN_IAR/stm32wle4x8.icf b/targets/TARGET_STM/TARGET_STM32WL/TARGET_STM32WLE4x8/TOOLCHAIN_IAR/stm32wle4x8.icf
new file mode 100644
index 0000000..7fb4af2
--- /dev/null
+++ b/targets/TARGET_STM/TARGET_STM32WL/TARGET_STM32WLE4x8/TOOLCHAIN_IAR/stm32wle4x8.icf
@@ -0,0 +1,59 @@
+/* Linker script to configure memory regions.
+ *
+ * SPDX-License-Identifier: BSD-3-Clause
+ ******************************************************************************
+ * @attention
+ *
+ * Copyright (c) 2016-2020 STMicroelectronics.
+ * All rights reserved.
+ *
+ * This software component is licensed by ST under BSD 3-Clause license,
+ * the "License"; You may not use this file except in compliance with the
+ * License. You may obtain a copy of the License at:
+ * opensource.org/licenses/BSD-3-Clause
+ *
+ ******************************************************************************
+*/
+/* Device specific values */
+
+/* Tools provide -DMBED_ROM_START=xxx -DMBED_ROM_SIZE=xxx -DMBED_RAM_START=xxx -DMBED_RAM_SIZE=xxx */
+
+define symbol VECTORS = 78; /* This value must match NVIC_NUM_VECTORS in cmsis_nvic.h */
+define symbol HEAP_SIZE = 0x1000;
+
+/* Common - Do not change */
+
+if (!isdefinedsymbol(MBED_APP_START)) {
+ define symbol MBED_APP_START = MBED_ROM_START;
+}
+
+if (!isdefinedsymbol(MBED_APP_SIZE)) {
+ define symbol MBED_APP_SIZE = MBED_ROM_SIZE;
+}
+
+if (!isdefinedsymbol(MBED_CONF_TARGET_BOOT_STACK_SIZE)) {
+ /* This value is normally defined by the tools
+ to 0x1000 for bare metal and 0x400 for RTOS */
+ define symbol MBED_CONF_TARGET_BOOT_STACK_SIZE = 0x400;
+}
+
+/* Round up VECTORS_SIZE to 8 bytes */
+define symbol VECTORS_SIZE = ((VECTORS * 4) + 7) & ~7;
+define symbol RAM_REGION_START = MBED_RAM_START + VECTORS_SIZE;
+define symbol RAM_REGION_SIZE = MBED_RAM_SIZE - VECTORS_SIZE;
+
+define memory mem with size = 4G;
+define region ROM_region = mem:[from MBED_APP_START size MBED_APP_SIZE];
+define region RAM_region = mem:[from RAM_REGION_START size RAM_REGION_SIZE];
+
+define block CSTACK with alignment = 8, size = MBED_CONF_TARGET_BOOT_STACK_SIZE { };
+define block HEAP with alignment = 8, size = HEAP_SIZE { };
+
+initialize by copy { readwrite };
+do not initialize { section .noinit };
+
+place at address mem: MBED_APP_START { readonly section .intvec };
+
+place in ROM_region { readonly };
+place in RAM_region { readwrite,
+ block CSTACK, block HEAP };
diff --git a/targets/TARGET_STM/TARGET_STM32WL/TARGET_STM32WLE4x8/cmsis_nvic.h b/targets/TARGET_STM/TARGET_STM32WL/TARGET_STM32WLE4x8/cmsis_nvic.h
new file mode 100644
index 0000000..a18342e
--- /dev/null
+++ b/targets/TARGET_STM/TARGET_STM32WL/TARGET_STM32WLE4x8/cmsis_nvic.h
@@ -0,0 +1,39 @@
+/* mbed Microcontroller Library
+ * SPDX-License-Identifier: BSD-3-Clause
+ ******************************************************************************
+ * @attention
+ *
+ * © Copyright (c) 2016-2020 STMicroelectronics.
+ * All rights reserved.
+ *
+ * This software component is licensed by ST under BSD 3-Clause license,
+ * the "License"; You may not use this file except in compliance with the
+ * License. You may obtain a copy of the License at:
+ * opensource.org/licenses/BSD-3-Clause
+ *
+ ******************************************************************************
+*/
+
+#ifndef MBED_CMSIS_NVIC_H
+#define MBED_CMSIS_NVIC_H
+
+#if !defined(MBED_ROM_START)
+#define MBED_ROM_START 0x8000000
+#endif
+
+#if !defined(MBED_ROM_SIZE)
+#define MBED_ROM_SIZE 0x0 // 0 B
+#endif
+
+#if !defined(MBED_RAM_START)
+#define MBED_RAM_START 0x20000000
+#endif
+
+#if !defined(MBED_RAM_SIZE)
+#define MBED_RAM_SIZE 0x0 // 0 B
+#endif
+
+#define NVIC_NUM_VECTORS 78
+#define NVIC_RAM_VECTOR_ADDRESS MBED_RAM_START
+
+#endif
diff --git a/targets/TARGET_STM/TARGET_STM32WL/TARGET_STM32WLE4xB/TOOLCHAIN_ARM/startup_stm32wle4xx.S b/targets/TARGET_STM/TARGET_STM32WL/TARGET_STM32WLE4xB/TOOLCHAIN_ARM/startup_stm32wle4xx.S
new file mode 100644
index 0000000..002a574
--- /dev/null
+++ b/targets/TARGET_STM/TARGET_STM32WL/TARGET_STM32WLE4xB/TOOLCHAIN_ARM/startup_stm32wle4xx.S
@@ -0,0 +1,314 @@
+;******************************************************************************
+;* File Name : startup_stm32wle4xx.s
+;* Author : MCD Application Team
+;* Description : STM32WLE4xx devices vector table for MDK-ARM toolchain.
+;* This module performs:
+;* - Set the initial SP
+;* - Set the initial PC == Reset_Handler
+;* - Set the vector table entries with the exceptions ISR address
+;* - Branches to __main in the C library (which eventually
+;* calls main()).
+;* After Reset the CortexM4 processor is in Thread mode,
+;* priority is Privileged, and the Stack is set to Main.
+;* <<< Use Configuration Wizard in Context Menu >>>
+;******************************************************************************
+;* @attention
+;*
+;* Copyright (c) 2020 STMicroelectronics. All rights reserved.
+;*
+;* This software component is licensed by ST under Apache License, Version 2.0,
+;* the "License"; You may not use this file except in compliance with the
+;* License. You may obtain a copy of the License at:
+;* opensource.org/licenses/Apache-2.0
+;*
+;******************************************************************************
+
+ PRESERVE8
+ THUMB
+
+
+; Vector Table Mapped to Address 0 at Reset
+ AREA RESET, DATA, READONLY
+ EXPORT __Vectors
+ EXPORT __Vectors_End
+ EXPORT __Vectors_Size
+
+ IMPORT |Image$$ARM_LIB_STACK$$ZI$$Limit|
+__Vectors DCD |Image$$ARM_LIB_STACK$$ZI$$Limit| ; Top of Stack
+ DCD Reset_Handler ; Reset Handler
+ DCD NMI_Handler ; NMI Handler
+ DCD HardFault_Handler ; Hard Fault Handler
+ DCD MemManage_Handler ; MPU Fault Handler
+ DCD BusFault_Handler ; Bus Fault Handler
+ DCD UsageFault_Handler ; Usage Fault Handler
+ DCD 0 ; Reserved
+ DCD 0 ; Reserved
+ DCD 0 ; Reserved
+ DCD 0 ; Reserved
+ DCD SVC_Handler ; SVCall Handler
+ DCD DebugMon_Handler ; Debug Monitor Handler
+ DCD 0 ; Reserved
+ DCD PendSV_Handler ; PendSV Handler
+ DCD SysTick_Handler ; SysTick Handler
+
+ ; External Interrupts
+ DCD WWDG_IRQHandler ; Window WatchDog
+ DCD PVD_PVM_IRQHandler ; PVD and PVM detector
+ DCD TAMP_STAMP_LSECSS_SSRU_IRQHandler ; RTC Tamper, RTC TimeStamp, LSECSS and RTC SSR Underflow Interrupts
+ DCD RTC_WKUP_IRQHandler ; RTC Wakeup Interrupt
+ DCD FLASH_IRQHandler ; FLASH global Interrupt
+ DCD RCC_IRQHandler ; RCC Interrupt
+ DCD EXTI0_IRQHandler ; EXTI Line 0 Interrupt
+ DCD EXTI1_IRQHandler ; EXTI Line 1 Interrupt
+ DCD EXTI2_IRQHandler ; EXTI Line 2 Interrupt
+ DCD EXTI3_IRQHandler ; EXTI Line 3 Interrup
+ DCD EXTI4_IRQHandler ; EXTI Line 4 Interrupt
+ DCD DMA1_Channel1_IRQHandler ; DMA1 Channel 1 Interrupt
+ DCD DMA1_Channel2_IRQHandler ; DMA1 Channel 2 Interrupt
+ DCD DMA1_Channel3_IRQHandler ; DMA1 Channel 3 Interrupt
+ DCD DMA1_Channel4_IRQHandler ; DMA1 Channel 4 Interrupt
+ DCD DMA1_Channel5_IRQHandler ; DMA1 Channel 5 Interrupt
+ DCD DMA1_Channel6_IRQHandler ; DMA1 Channel 6 Interrupt
+ DCD DMA1_Channel7_IRQHandler ; DMA1 Channel 7 Interrupt
+ DCD ADC_IRQHandler ; ADC Interrupt
+ DCD DAC_IRQHandler ; DAC Interrupt
+ DCD 0 ; Reserved
+ DCD COMP_IRQHandler ; COMP1 and COMP2 Interrupts
+ DCD EXTI9_5_IRQHandler ; EXTI Lines [9:5] Interrupt
+ DCD TIM1_BRK_IRQHandler ; TIM1 Break Interrupt
+ DCD TIM1_UP_IRQHandler ; TIM1 Update Interrupts
+ DCD TIM1_TRG_COM_IRQHandler ; TIM1 Trigger and Communication Interrupts
+ DCD TIM1_CC_IRQHandler ; TIM1 Capture Compare Interrupt
+ DCD TIM2_IRQHandler ; TIM2 Global Interrupt
+ DCD TIM16_IRQHandler ; TIM16 Global Interrupt
+ DCD TIM17_IRQHandler ; TIM17 Global Interrupt
+ DCD I2C1_EV_IRQHandler ; I2C1 Event Interrupt
+ DCD I2C1_ER_IRQHandler ; I2C1 Error Interrupt
+ DCD I2C2_EV_IRQHandler ; I2C2 Event Interrupt
+ DCD I2C2_ER_IRQHandler ; I2C2 Error Interrupt
+ DCD SPI1_IRQHandler ; SPI1 Interrupt
+ DCD SPI2_IRQHandler ; SPI2 Interrupt
+ DCD USART1_IRQHandler ; USART1 Interrupt
+ DCD USART2_IRQHandler ; USART2 Interrupt
+ DCD LPUART1_IRQHandler ; LPUART1 Interrupt
+ DCD LPTIM1_IRQHandler ; LPTIM1 Interrupt
+ DCD LPTIM2_IRQHandler ; LPTIM2 Interrupt
+ DCD EXTI15_10_IRQHandler ; EXTI Lines1[15:10 ]Interrupts
+ DCD RTC_Alarm_IRQHandler ; RTC Alarms (A and B) Interrupt
+ DCD LPTIM3_IRQHandler ; LPTIM3 Interrupt
+ DCD SUBGHZSPI_IRQHandler ; SUBGHZSPI Interrupt
+ DCD 0 ; Reserved
+ DCD 0 ; Reserved
+ DCD HSEM_IRQHandler ; HSEM0 Interrupt
+ DCD I2C3_EV_IRQHandler ; I2C3 Event Interrupt
+ DCD I2C3_ER_IRQHandler ; I2C3 Error Interrupt
+ DCD SUBGHZ_Radio_IRQHandler ; SUBGHZ Radio Interrupt
+ DCD AES_IRQHandler ; AES Interrupt
+ DCD RNG_IRQHandler ; RNG1 Interrupt
+ DCD PKA_IRQHandler ; PKA Interrupt
+ DCD DMA2_Channel1_IRQHandler ; DMA2 Channel 1 Interrupt
+ DCD DMA2_Channel2_IRQHandler ; DMA2 Channel 2 Interrupt
+ DCD DMA2_Channel3_IRQHandler ; DMA2 Channel 3 Interrupt
+ DCD DMA2_Channel4_IRQHandler ; DMA2 Channel 4 Interrupt
+ DCD DMA2_Channel5_IRQHandler ; DMA2 Channel 5 Interrupt
+ DCD DMA2_Channel6_IRQHandler ; DMA2 Channel 6 Interrupt
+ DCD DMA2_Channel7_IRQHandler ; DMA2 Channel 7 Interrupt
+ DCD DMAMUX1_OVR_IRQHandler ; DMAMUX overrun Interrupt
+
+__Vectors_End
+
+__Vectors_Size EQU __Vectors_End - __Vectors
+
+ AREA |.text|, CODE, READONLY
+
+; Reset handler
+Reset_Handler PROC
+ EXPORT Reset_Handler [WEAK]
+ IMPORT SystemInit
+ IMPORT __main
+
+ LDR R0, =SystemInit
+ BLX R0
+ LDR R0, =__main
+ BX R0
+ ENDP
+
+; Dummy Exception Handlers (infinite loops which can be modified)
+
+NMI_Handler PROC
+ EXPORT NMI_Handler [WEAK]
+ B .
+ ENDP
+HardFault_Handler\
+ PROC
+ EXPORT HardFault_Handler [WEAK]
+ B .
+ ENDP
+MemManage_Handler\
+ PROC
+ EXPORT MemManage_Handler [WEAK]
+ B .
+ ENDP
+BusFault_Handler\
+ PROC
+ EXPORT BusFault_Handler [WEAK]
+ B .
+ ENDP
+UsageFault_Handler\
+ PROC
+ EXPORT UsageFault_Handler [WEAK]
+ B .
+ ENDP
+SVC_Handler PROC
+ EXPORT SVC_Handler [WEAK]
+ B .
+ ENDP
+DebugMon_Handler\
+ PROC
+ EXPORT DebugMon_Handler [WEAK]
+ B .
+ ENDP
+PendSV_Handler PROC
+ EXPORT PendSV_Handler [WEAK]
+ B .
+ ENDP
+SysTick_Handler PROC
+ EXPORT SysTick_Handler [WEAK]
+ B .
+ ENDP
+
+Default_Handler PROC
+
+ EXPORT WWDG_IRQHandler [WEAK]
+ EXPORT PVD_PVM_IRQHandler [WEAK]
+ EXPORT TAMP_STAMP_LSECSS_SSRU_IRQHandler [WEAK]
+ EXPORT RTC_WKUP_IRQHandler [WEAK]
+ EXPORT FLASH_IRQHandler [WEAK]
+ EXPORT RCC_IRQHandler [WEAK]
+ EXPORT EXTI0_IRQHandler [WEAK]
+ EXPORT EXTI1_IRQHandler [WEAK]
+ EXPORT EXTI2_IRQHandler [WEAK]
+ EXPORT EXTI3_IRQHandler [WEAK]
+ EXPORT EXTI4_IRQHandler [WEAK]
+ EXPORT DMA1_Channel1_IRQHandler [WEAK]
+ EXPORT DMA1_Channel2_IRQHandler [WEAK]
+ EXPORT DMA1_Channel3_IRQHandler [WEAK]
+ EXPORT DMA1_Channel4_IRQHandler [WEAK]
+ EXPORT DMA1_Channel5_IRQHandler [WEAK]
+ EXPORT DMA1_Channel6_IRQHandler [WEAK]
+ EXPORT DMA1_Channel7_IRQHandler [WEAK]
+ EXPORT ADC_IRQHandler [WEAK]
+ EXPORT DAC_IRQHandler [WEAK]
+ EXPORT COMP_IRQHandler [WEAK]
+ EXPORT EXTI9_5_IRQHandler [WEAK]
+ EXPORT TIM1_BRK_IRQHandler [WEAK]
+ EXPORT TIM1_UP_IRQHandler [WEAK]
+ EXPORT TIM1_TRG_COM_IRQHandler [WEAK]
+ EXPORT TIM1_CC_IRQHandler [WEAK]
+ EXPORT TIM2_IRQHandler [WEAK]
+ EXPORT TIM16_IRQHandler [WEAK]
+ EXPORT TIM17_IRQHandler [WEAK]
+ EXPORT I2C1_EV_IRQHandler [WEAK]
+ EXPORT I2C1_ER_IRQHandler [WEAK]
+ EXPORT I2C2_EV_IRQHandler [WEAK]
+ EXPORT I2C2_ER_IRQHandler [WEAK]
+ EXPORT SPI1_IRQHandler [WEAK]
+ EXPORT SPI2_IRQHandler [WEAK]
+ EXPORT USART1_IRQHandler [WEAK]
+ EXPORT USART2_IRQHandler [WEAK]
+ EXPORT LPUART1_IRQHandler [WEAK]
+ EXPORT LPTIM1_IRQHandler [WEAK]
+ EXPORT LPTIM2_IRQHandler [WEAK]
+ EXPORT EXTI15_10_IRQHandler [WEAK]
+ EXPORT RTC_Alarm_IRQHandler [WEAK]
+ EXPORT LPTIM3_IRQHandler [WEAK]
+ EXPORT SUBGHZSPI_IRQHandler [WEAK]
+ EXPORT HSEM_IRQHandler [WEAK]
+ EXPORT I2C3_EV_IRQHandler [WEAK]
+ EXPORT I2C3_ER_IRQHandler [WEAK]
+ EXPORT SUBGHZ_Radio_IRQHandler [WEAK]
+ EXPORT AES_IRQHandler [WEAK]
+ EXPORT RNG_IRQHandler [WEAK]
+ EXPORT PKA_IRQHandler [WEAK]
+ EXPORT DMA2_Channel1_IRQHandler [WEAK]
+ EXPORT DMA2_Channel2_IRQHandler [WEAK]
+ EXPORT DMA2_Channel3_IRQHandler [WEAK]
+ EXPORT DMA2_Channel4_IRQHandler [WEAK]
+ EXPORT DMA2_Channel5_IRQHandler [WEAK]
+ EXPORT DMA2_Channel6_IRQHandler [WEAK]
+ EXPORT DMA2_Channel7_IRQHandler [WEAK]
+ EXPORT DMAMUX1_OVR_IRQHandler [WEAK]
+
+WWDG_IRQHandler
+PVD_PVM_IRQHandler
+TAMP_STAMP_LSECSS_SSRU_IRQHandler
+RTC_WKUP_IRQHandler
+FLASH_IRQHandler
+RCC_IRQHandler
+EXTI0_IRQHandler
+EXTI1_IRQHandler
+EXTI2_IRQHandler
+EXTI3_IRQHandler
+EXTI4_IRQHandler
+DMA1_Channel1_IRQHandler
+DMA1_Channel2_IRQHandler
+DMA1_Channel3_IRQHandler
+DMA1_Channel4_IRQHandler
+DMA1_Channel5_IRQHandler
+DMA1_Channel6_IRQHandler
+DMA1_Channel7_IRQHandler
+ADC_IRQHandler
+DAC_IRQHandler
+COMP_IRQHandler
+EXTI9_5_IRQHandler
+TIM1_BRK_IRQHandler
+TIM1_UP_IRQHandler
+TIM1_TRG_COM_IRQHandler
+TIM1_CC_IRQHandler
+TIM2_IRQHandler
+TIM16_IRQHandler
+TIM17_IRQHandler
+I2C1_EV_IRQHandler
+I2C1_ER_IRQHandler
+I2C2_EV_IRQHandler
+I2C2_ER_IRQHandler
+SPI1_IRQHandler
+SPI2_IRQHandler
+USART1_IRQHandler
+USART2_IRQHandler
+LPUART1_IRQHandler
+LPTIM1_IRQHandler
+LPTIM2_IRQHandler
+EXTI15_10_IRQHandler
+RTC_Alarm_IRQHandler
+LPTIM3_IRQHandler
+SUBGHZSPI_IRQHandler
+HSEM_IRQHandler
+I2C3_EV_IRQHandler
+I2C3_ER_IRQHandler
+SUBGHZ_Radio_IRQHandler
+AES_IRQHandler
+RNG_IRQHandler
+PKA_IRQHandler
+DMA2_Channel1_IRQHandler
+DMA2_Channel2_IRQHandler
+DMA2_Channel3_IRQHandler
+DMA2_Channel4_IRQHandler
+DMA2_Channel5_IRQHandler
+DMA2_Channel6_IRQHandler
+DMA2_Channel7_IRQHandler
+DMAMUX1_OVR_IRQHandler
+
+ B .
+
+ ENDP
+
+ ALIGN
+
+;*******************************************************************************
+; User Stack and Heap initialization
+;*******************************************************************************
+
+ END
+
+;************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE*****
diff --git a/targets/TARGET_STM/TARGET_STM32WL/TARGET_STM32WLE4xB/TOOLCHAIN_ARM/stm32wle4xb.sct b/targets/TARGET_STM/TARGET_STM32WL/TARGET_STM32WLE4xB/TOOLCHAIN_ARM/stm32wle4xb.sct
new file mode 100644
index 0000000..9258e6a
--- /dev/null
+++ b/targets/TARGET_STM/TARGET_STM32WL/TARGET_STM32WLE4xB/TOOLCHAIN_ARM/stm32wle4xb.sct
@@ -0,0 +1,57 @@
+#! armclang -E --target=arm-arm-none-eabi -x c -mcpu=cortex-M4
+; Scatter-Loading Description File
+;
+; SPDX-License-Identifier: BSD-3-Clause
+;******************************************************************************
+;* @attention
+;*
+;* Copyright (c) 2016-2020 STMicroelectronics.
+;* All rights reserved.
+;*
+;* This software component is licensed by ST under BSD 3-Clause license,
+;* the "License"; You may not use this file except in compliance with the
+;* License. You may obtain a copy of the License at:
+;* opensource.org/licenses/BSD-3-Clause
+;*
+;******************************************************************************
+
+#include "../cmsis_nvic.h"
+
+#if !defined(MBED_APP_START)
+ #define MBED_APP_START MBED_ROM_START
+#endif
+
+#if !defined(MBED_APP_SIZE)
+ #define MBED_APP_SIZE MBED_ROM_SIZE
+#endif
+
+#if !defined(MBED_CONF_TARGET_BOOT_STACK_SIZE)
+/* This value is normally defined by the tools to 0x1000 for bare metal and 0x400 for RTOS */
+#if defined(MBED_BOOT_STACK_SIZE)
+#define MBED_CONF_TARGET_BOOT_STACK_SIZE MBED_BOOT_STACK_SIZE
+#else
+#define MBED_CONF_TARGET_BOOT_STACK_SIZE 0x400
+#endif
+#endif
+
+/* Round up VECTORS_SIZE to 8 bytes */
+#define VECTORS_SIZE (((NVIC_NUM_VECTORS * 4) + 7) AND ~7)
+
+LR_IROM1 MBED_APP_START MBED_APP_SIZE {
+
+ ER_IROM1 MBED_APP_START MBED_APP_SIZE {
+ *.o (RESET, +First)
+ *(InRoot$$Sections)
+ .ANY (+RO)
+ }
+
+ RW_IRAM1 (MBED_RAM_START + VECTORS_SIZE) { ; RW data
+ .ANY (+RW +ZI)
+ }
+
+ ARM_LIB_HEAP AlignExpr(+0, 16) EMPTY (MBED_RAM_START + MBED_RAM_SIZE - MBED_CONF_TARGET_BOOT_STACK_SIZE - AlignExpr(ImageLimit(RW_IRAM1), 16)) { ; Heap growing up
+ }
+
+ ARM_LIB_STACK (MBED_RAM_START + MBED_RAM_SIZE) EMPTY -MBED_CONF_TARGET_BOOT_STACK_SIZE { ; Stack region growing down
+ }
+}
diff --git a/targets/TARGET_STM/TARGET_STM32WL/TARGET_STM32WLE4xB/TOOLCHAIN_GCC_ARM/startup_stm32wle4xx.S b/targets/TARGET_STM/TARGET_STM32WL/TARGET_STM32WLE4xB/TOOLCHAIN_GCC_ARM/startup_stm32wle4xx.S
new file mode 100644
index 0000000..c919abb
--- /dev/null
+++ b/targets/TARGET_STM/TARGET_STM32WL/TARGET_STM32WLE4xB/TOOLCHAIN_GCC_ARM/startup_stm32wle4xx.S
@@ -0,0 +1,425 @@
+/**
+ ******************************************************************************
+ * @file startup_stm32wle4xx.s
+ * @author MCD Application Team
+ * @brief STM32WLE4xx devices vector table for GCC toolchain.
+ * This module performs:
+ * - Set the initial SP
+ * - Set the initial PC == Reset_Handler,
+ * - Set the vector table entries with the exceptions ISR address,
+ * - Branches to main in the C library (which eventually
+ * calls main()).
+ * After Reset the Cortex-M4 processor is in Thread mode,
+ * priority is Privileged, and the Stack is set to Main.
+ ******************************************************************************
+ * @attention
+ *
+ * © Copyright (c) 2020 STMicroelectronics.
+ * All rights reserved.
+ *
+ * This software component is licensed by ST under Apache License, Version 2.0,
+ * the "License"; You may not use this file except in compliance with the
+ * License. You may obtain a copy of the License at:
+ * opensource.org/licenses/Apache-2.0
+ *
+ ******************************************************************************
+ */
+
+.syntax unified
+.cpu cortex-m4
+.fpu softvfp
+.thumb
+
+.global g_pfnVectors
+.global Default_Handler
+
+/* start address for the initialization values of the .data section.
+defined in linker script */
+.word _sidata
+/* start address for the .data section. defined in linker script */
+.word _sdata
+/* end address for the .data section. defined in linker script */
+.word _edata
+/* start address for the .bss section. defined in linker script */
+.word _sbss
+/* end address for the .bss section. defined in linker script */
+.word _ebss
+
+/**
+ * @brief This is the code that gets called when the processor first
+ * starts execution following a reset event. Only the absolutely
+ * necessary set is performed, after which the application
+ * supplied main() routine is called.
+ * @param None
+ * @retval : None
+*/
+
+ .section .text.Reset_Handler
+ .weak Reset_Handler
+ .type Reset_Handler, %function
+Reset_Handler:
+ ldr r0, =_estack
+ mov sp, r0 /* set stack pointer */
+
+/* Call the clock system initialization function.*/
+ bl SystemInit
+
+/* Copy the data segment initializers from flash to SRAM */
+ ldr r0, =_sdata
+ ldr r1, =_edata
+ ldr r2, =_sidata
+ movs r3, #0
+ b LoopCopyDataInit
+
+CopyDataInit:
+ ldr r4, [r2, r3]
+ str r4, [r0, r3]
+ adds r3, r3, #4
+
+LoopCopyDataInit:
+ adds r4, r0, r3
+ cmp r4, r1
+ bcc CopyDataInit
+
+/* Zero fill the bss segment. */
+ ldr r2, =_sbss
+ ldr r4, =_ebss
+ movs r3, #0
+ b LoopFillZerobss
+
+FillZerobss:
+ str r3, [r2]
+ adds r2, r2, #4
+
+LoopFillZerobss:
+ cmp r2, r4
+ bcc FillZerobss
+
+ bl _start
+ bx lr
+
+LoopForever:
+ b LoopForever
+
+ .size Reset_Handler, .-Reset_Handler
+
+/**
+ * @brief This is the code that gets called when the processor receives an
+ * unexpected interrupt. This simply enters an infinite loop, preserving
+ * the system state for examination by a debugger.
+ *
+ * @param None
+ * @retval : None
+*/
+ .section .text.Default_Handler,"ax",%progbits
+Default_Handler:
+Infinite_Loop:
+ b Infinite_Loop
+ .size Default_Handler, .-Default_Handler
+
+/******************************************************************************
+*
+* The STM32WLE4xx vector table. Note that the proper constructs
+* must be placed on this to ensure that it ends up at physical address
+* 0x0000.0000.
+*
+******************************************************************************/
+ .section .isr_vector,"a",%progbits
+ .type g_pfnVectors, %object
+ .size g_pfnVectors, .-g_pfnVectors
+
+g_pfnVectors:
+ .word _estack
+ .word Reset_Handler
+ .word NMI_Handler
+ .word HardFault_Handler
+ .word MemManage_Handler
+ .word BusFault_Handler
+ .word UsageFault_Handler
+ .word 0
+ .word 0
+ .word 0
+ .word 0
+ .word SVC_Handler
+ .word DebugMon_Handler
+ .word 0
+ .word PendSV_Handler
+ .word SysTick_Handler
+ .word WWDG_IRQHandler /* Window Watchdog interrupt */
+ .word PVD_PVM_IRQHandler /* PVD and PVM interrupt through EXTI */
+ .word TAMP_STAMP_LSECSS_SSRU_IRQHandler /* RTC Tamper, RTC TimeStamp, LSECSS and RTC SSRU int.*/
+ .word RTC_WKUP_IRQHandler /* RTC wakeup interrupt through EXTI[19] */
+ .word FLASH_IRQHandler /* Flash memory global interrupt and Flash memory ECC */
+ .word RCC_IRQHandler /* RCC global interrupt */
+ .word EXTI0_IRQHandler /* EXTI line 0 interrupt */
+ .word EXTI1_IRQHandler /* EXTI line 1 interrupt */
+ .word EXTI2_IRQHandler /* EXTI line 2 interrupt */
+ .word EXTI3_IRQHandler /* EXTI line 3 interrupt */
+ .word EXTI4_IRQHandler /* EXTI line 4 interrupt */
+ .word DMA1_Channel1_IRQHandler /* DMA1 channel 1 interrupt */
+ .word DMA1_Channel2_IRQHandler /* DMA1 channel 2 interrupt */
+ .word DMA1_Channel3_IRQHandler /* DMA1 channel 3 interrupt */
+ .word DMA1_Channel4_IRQHandler /* DMA1 channel 4 interrupt */
+ .word DMA1_Channel5_IRQHandler /* DMA1 channel 5 interrupt */
+ .word DMA1_Channel6_IRQHandler /* DMA1 channel 6 interrupt */
+ .word DMA1_Channel7_IRQHandler /* DMA1 channel 7 interrupt */
+ .word ADC_IRQHandler /* ADC interrupt */
+ .word DAC_IRQHandler /* DAC interrupt */
+ .word 0 /* Reserved */
+ .word COMP_IRQHandler /* COMP1 and COMP2 interrupt through EXTI */
+ .word EXTI9_5_IRQHandler /* EXTI line 9_5 interrupt */
+ .word TIM1_BRK_IRQHandler /* Timer 1 break interrupt */
+ .word TIM1_UP_IRQHandler /* Timer 1 Update */
+ .word TIM1_TRG_COM_IRQHandler /* Timer 1 trigger and communication */
+ .word TIM1_CC_IRQHandler /* Timer 1 capture compare interrupt */
+ .word TIM2_IRQHandler /* TIM2 global interrupt */
+ .word TIM16_IRQHandler /* Timer 16 global interrupt */
+ .word TIM17_IRQHandler /* Timer 17 global interrupt */
+ .word I2C1_EV_IRQHandler /* I2C1 event interrupt */
+ .word I2C1_ER_IRQHandler /* I2C1 event interrupt */
+ .word I2C2_EV_IRQHandler /* I2C2 error interrupt */
+ .word I2C2_ER_IRQHandler /* I2C2 error interrupt */
+ .word SPI1_IRQHandler /* SPI1 global interrupt */
+ .word SPI2_IRQHandler /* SPI2 global interrupt */
+ .word USART1_IRQHandler /* USART1 global interrupt */
+ .word USART2_IRQHandler /* USART2 global interrupt */
+ .word LPUART1_IRQHandler /* LPUART1 global interrupt */
+ .word LPTIM1_IRQHandler /* LPtimer 1 global interrupt */
+ .word LPTIM2_IRQHandler /* LPtimer 2 global interrupt */
+ .word EXTI15_10_IRQHandler /* EXTI line 15_10] interrupt through EXTI */
+ .word RTC_Alarm_IRQHandler /* RTC Alarms A & B interrupt */
+ .word LPTIM3_IRQHandler /* LPtimer 3 global interrupt */
+ .word SUBGHZSPI_IRQHandler /* SUBGHZSPI global interrupt */
+ .word 0 /* Reserved */
+ .word 0 /* Reserved */
+ .word HSEM_IRQHandler /* Semaphore interrupt 0 to CPU1 */
+ .word I2C3_EV_IRQHandler /* I2C3 event interrupt */
+ .word I2C3_ER_IRQHandler /* I2C3 error interrupt */
+ .word SUBGHZ_Radio_IRQHandler /* Radio IRQs RFBUSY interrupt through EXTI */
+ .word AES_IRQHandler /* AES global interrupt */
+ .word RNG_IRQHandler /* RNG interrupt */
+ .word PKA_IRQHandler /* PKA interrupt */
+ .word DMA2_Channel1_IRQHandler /* DMA2 channel 1 interrupt */
+ .word DMA2_Channel2_IRQHandler /* DMA2 channel 2 interrupt */
+ .word DMA2_Channel3_IRQHandler /* DMA2 channel 3 interrupt */
+ .word DMA2_Channel4_IRQHandler /* DMA2 channel 4 interrupt */
+ .word DMA2_Channel5_IRQHandler /* DMA2 channel 5 interrupt */
+ .word DMA2_Channel6_IRQHandler /* DMA2 channel 6 interrupt */
+ .word DMA2_Channel7_IRQHandler /* DMA2 channel 7 interrupt */
+ .word DMAMUX1_OVR_IRQHandler /* DMAMUX overrun interrupt */
+
+/*******************************************************************************
+*
+* Provide weak aliases for each Exception handler to the Default_Handler.
+* As they are weak aliases, any function with the same name will override
+* this definition.
+*
+*******************************************************************************/
+
+ .weak NMI_Handler
+ .thumb_set NMI_Handler,Default_Handler
+
+ .weak HardFault_Handler
+ .thumb_set HardFault_Handler,Default_Handler
+
+ .weak MemManage_Handler
+ .thumb_set MemManage_Handler,Default_Handler
+
+ .weak BusFault_Handler
+ .thumb_set BusFault_Handler,Default_Handler
+
+ .weak UsageFault_Handler
+ .thumb_set UsageFault_Handler,Default_Handler
+
+ .weak SVC_Handler
+ .thumb_set SVC_Handler,Default_Handler
+
+ .weak DebugMon_Handler
+ .thumb_set DebugMon_Handler,Default_Handler
+
+ .weak PendSV_Handler
+ .thumb_set PendSV_Handler,Default_Handler
+
+ .weak SysTick_Handler
+ .thumb_set SysTick_Handler,Default_Handler
+
+ .weak WWDG_IRQHandler
+ .thumb_set WWDG_IRQHandler,Default_Handler
+
+ .weak PVD_PVM_IRQHandler
+ .thumb_set PVD_PVM_IRQHandler,Default_Handler
+
+ .weak TAMP_STAMP_LSECSS_SSRU_IRQHandler
+ .thumb_set TAMP_STAMP_LSECSS_SSRU_IRQHandler,Default_Handler
+
+ .weak RTC_WKUP_IRQHandler
+ .thumb_set RTC_WKUP_IRQHandler,Default_Handler
+
+ .weak FLASH_IRQHandler
+ .thumb_set FLASH_IRQHandler,Default_Handler
+
+ .weak RCC_IRQHandler
+ .thumb_set RCC_IRQHandler,Default_Handler
+
+ .weak EXTI0_IRQHandler
+ .thumb_set EXTI0_IRQHandler,Default_Handler
+
+ .weak EXTI1_IRQHandler
+ .thumb_set EXTI1_IRQHandler,Default_Handler
+
+ .weak EXTI2_IRQHandler
+ .thumb_set EXTI2_IRQHandler,Default_Handler
+
+ .weak EXTI3_IRQHandler
+ .thumb_set EXTI3_IRQHandler,Default_Handler
+
+ .weak EXTI4_IRQHandler
+ .thumb_set EXTI4_IRQHandler,Default_Handler
+
+ .weak DMA1_Channel1_IRQHandler
+ .thumb_set DMA1_Channel1_IRQHandler,Default_Handler
+
+ .weak DMA1_Channel2_IRQHandler
+ .thumb_set DMA1_Channel2_IRQHandler,Default_Handler
+
+ .weak DMA1_Channel3_IRQHandler
+ .thumb_set DMA1_Channel3_IRQHandler,Default_Handler
+
+ .weak DMA1_Channel4_IRQHandler
+ .thumb_set DMA1_Channel4_IRQHandler,Default_Handler
+
+ .weak DMA1_Channel5_IRQHandler
+ .thumb_set DMA1_Channel5_IRQHandler,Default_Handler
+
+ .weak DMA1_Channel6_IRQHandler
+ .thumb_set DMA1_Channel6_IRQHandler,Default_Handler
+
+ .weak DMA1_Channel7_IRQHandler
+ .thumb_set DMA1_Channel7_IRQHandler,Default_Handler
+
+ .weak ADC_IRQHandler
+ .thumb_set ADC_IRQHandler,Default_Handler
+
+ .weak DAC_IRQHandler
+ .thumb_set DAC_IRQHandler,Default_Handler
+
+ .weak COMP_IRQHandler
+ .thumb_set COMP_IRQHandler,Default_Handler
+
+ .weak EXTI9_5_IRQHandler
+ .thumb_set EXTI9_5_IRQHandler,Default_Handler
+
+ .weak TIM1_BRK_IRQHandler
+ .thumb_set TIM1_BRK_IRQHandler,Default_Handler
+
+ .weak TIM1_UP_IRQHandler
+ .thumb_set TIM1_UP_IRQHandler,Default_Handler
+
+ .weak TIM1_TRG_COM_IRQHandler
+ .thumb_set TIM1_TRG_COM_IRQHandler,Default_Handler
+
+ .weak TIM1_CC_IRQHandler
+ .thumb_set TIM1_CC_IRQHandler,Default_Handler
+
+ .weak TIM2_IRQHandler
+ .thumb_set TIM2_IRQHandler,Default_Handler
+
+ .weak TIM16_IRQHandler
+ .thumb_set TIM16_IRQHandler,Default_Handler
+
+ .weak TIM17_IRQHandler
+ .thumb_set TIM17_IRQHandler,Default_Handler
+
+ .weak I2C1_EV_IRQHandler
+ .thumb_set I2C1_EV_IRQHandler,Default_Handler
+
+ .weak I2C1_ER_IRQHandler
+ .thumb_set I2C1_ER_IRQHandler,Default_Handler
+
+ .weak I2C2_EV_IRQHandler
+ .thumb_set I2C2_EV_IRQHandler,Default_Handler
+
+ .weak I2C2_ER_IRQHandler
+ .thumb_set I2C2_ER_IRQHandler,Default_Handler
+
+ .weak SPI1_IRQHandler
+ .thumb_set SPI1_IRQHandler,Default_Handler
+
+ .weak SPI2_IRQHandler
+ .thumb_set SPI2_IRQHandler,Default_Handler
+
+ .weak USART1_IRQHandler
+ .thumb_set USART1_IRQHandler,Default_Handler
+
+ .weak USART2_IRQHandler
+ .thumb_set USART2_IRQHandler,Default_Handler
+
+ .weak LPUART1_IRQHandler
+ .thumb_set LPUART1_IRQHandler,Default_Handler
+
+ .weak LPTIM1_IRQHandler
+ .thumb_set LPTIM1_IRQHandler,Default_Handler
+
+ .weak LPTIM2_IRQHandler
+ .thumb_set LPTIM2_IRQHandler,Default_Handler
+
+ .weak EXTI15_10_IRQHandler
+ .thumb_set EXTI15_10_IRQHandler,Default_Handler
+
+ .weak RTC_Alarm_IRQHandler
+ .thumb_set RTC_Alarm_IRQHandler,Default_Handler
+
+ .weak LPTIM3_IRQHandler
+ .thumb_set LPTIM3_IRQHandler,Default_Handler
+
+ .weak SUBGHZSPI_IRQHandler
+ .thumb_set SUBGHZSPI_IRQHandler,Default_Handler
+
+ .weak HSEM_IRQHandler
+ .thumb_set HSEM_IRQHandler,Default_Handler
+
+ .weak I2C3_EV_IRQHandler
+ .thumb_set I2C3_EV_IRQHandler,Default_Handler
+
+ .weak I2C3_ER_IRQHandler
+ .thumb_set I2C3_ER_IRQHandler,Default_Handler
+
+ .weak SUBGHZ_Radio_IRQHandler
+ .thumb_set SUBGHZ_Radio_IRQHandler,Default_Handler
+
+ .weak AES_IRQHandler
+ .thumb_set AES_IRQHandler,Default_Handler
+
+ .weak RNG_IRQHandler
+ .thumb_set RNG_IRQHandler,Default_Handler
+
+ .weak PKA_IRQHandler
+ .thumb_set PKA_IRQHandler,Default_Handler
+
+ .weak DMA2_Channel1_IRQHandler
+ .thumb_set DMA2_Channel1_IRQHandler,Default_Handler
+
+ .weak DMA2_Channel2_IRQHandler
+ .thumb_set DMA2_Channel2_IRQHandler,Default_Handler
+
+ .weak DMA2_Channel3_IRQHandler
+ .thumb_set DMA2_Channel3_IRQHandler,Default_Handler
+
+ .weak DMA2_Channel4_IRQHandler
+ .thumb_set DMA2_Channel4_IRQHandler,Default_Handler
+
+ .weak DMA2_Channel5_IRQHandler
+ .thumb_set DMA2_Channel5_IRQHandler,Default_Handler
+
+ .weak DMA2_Channel6_IRQHandler
+ .thumb_set DMA2_Channel6_IRQHandler,Default_Handler
+
+ .weak DMA2_Channel7_IRQHandler
+ .thumb_set DMA2_Channel7_IRQHandler,Default_Handler
+
+ .weak DMAMUX1_OVR_IRQHandler
+ .thumb_set DMAMUX1_OVR_IRQHandler,Default_Handler
+
+ .weak SystemInit
+
+/************************ (C) COPYRIGHT STMicroelectonics *****END OF FILE****/
diff --git a/targets/TARGET_STM/TARGET_STM32WL/TARGET_STM32WLE4xB/TOOLCHAIN_GCC_ARM/stm32wle4xb.ld b/targets/TARGET_STM/TARGET_STM32WL/TARGET_STM32WLE4xB/TOOLCHAIN_GCC_ARM/stm32wle4xb.ld
new file mode 100644
index 0000000..5f47993
--- /dev/null
+++ b/targets/TARGET_STM/TARGET_STM32WL/TARGET_STM32WLE4xB/TOOLCHAIN_GCC_ARM/stm32wle4xb.ld
@@ -0,0 +1,203 @@
+/* Linker script to configure memory regions. */
+/*
+ * SPDX-License-Identifier: BSD-3-Clause
+ ******************************************************************************
+ * @attention
+ *
+ * Copyright (c) 2016-2020 STMicroelectronics.
+ * All rights reserved.
+ *
+ * This software component is licensed by ST under BSD 3-Clause license,
+ * the "License"; You may not use this file except in compliance with the
+ * License. You may obtain a copy of the License at:
+ * opensource.org/licenses/BSD-3-Clause
+ *
+ ******************************************************************************
+*/
+
+#include "../cmsis_nvic.h"
+
+
+#if !defined(MBED_APP_START)
+ #define MBED_APP_START MBED_ROM_START
+#endif
+
+#if !defined(MBED_APP_SIZE)
+ #define MBED_APP_SIZE MBED_ROM_SIZE
+#endif
+
+#if !defined(MBED_CONF_TARGET_BOOT_STACK_SIZE)
+ /* This value is normally defined by the tools
+ to 0x1000 for bare metal and 0x400 for RTOS */
+ #define MBED_CONF_TARGET_BOOT_STACK_SIZE 0x400
+#endif
+
+/* Round up VECTORS_SIZE to 8 bytes */
+#define VECTORS_SIZE (((NVIC_NUM_VECTORS * 4) + 7) & 0xFFFFFFF8)
+
+MEMORY
+{
+ FLASH (rx) : ORIGIN = MBED_APP_START, LENGTH = MBED_APP_SIZE
+ RAM (rwx) : ORIGIN = MBED_RAM_START + VECTORS_SIZE, LENGTH = MBED_RAM_SIZE - VECTORS_SIZE
+}
+
+/* Linker script to place sections and symbol values. Should be used together
+ * with other linker script that defines memory regions FLASH and RAM.
+ * It references following symbols, which must be defined in code:
+ * Reset_Handler : Entry of reset handler
+ *
+ * It defines following symbols, which code can use without definition:
+ * __exidx_start
+ * __exidx_end
+ * __etext
+ * __data_start__
+ * __preinit_array_start
+ * __preinit_array_end
+ * __init_array_start
+ * __init_array_end
+ * __fini_array_start
+ * __fini_array_end
+ * __data_end__
+ * __bss_start__
+ * __bss_end__
+ * __end__
+ * end
+ * __HeapLimit
+ * __StackLimit
+ * __StackTop
+ * __stack
+ * _estack
+ */
+ENTRY(Reset_Handler)
+
+SECTIONS
+{
+ .text :
+ {
+ KEEP(*(.isr_vector))
+ *(.text*)
+
+ KEEP(*(.init))
+ KEEP(*(.fini))
+
+ /* .ctors */
+ *crtbegin.o(.ctors)
+ *crtbegin?.o(.ctors)
+ *(EXCLUDE_FILE(*crtend?.o *crtend.o) .ctors)
+ *(SORT(.ctors.*))
+ *(.ctors)
+
+ /* .dtors */
+ *crtbegin.o(.dtors)
+ *crtbegin?.o(.dtors)
+ *(EXCLUDE_FILE(*crtend?.o *crtend.o) .dtors)
+ *(SORT(.dtors.*))
+ *(.dtors)
+
+ *(.rodata*)
+
+ KEEP(*(.eh_frame*))
+ } > FLASH
+
+ .ARM.extab :
+ {
+ *(.ARM.extab* .gnu.linkonce.armextab.*)
+ } > FLASH
+
+ __exidx_start = .;
+ .ARM.exidx :
+ {
+ *(.ARM.exidx* .gnu.linkonce.armexidx.*)
+ } > FLASH
+ __exidx_end = .;
+
+ __etext = .;
+ _sidata = .;
+
+ .data : AT (__etext)
+ {
+ __data_start__ = .;
+ _sdata = .;
+ *(vtable)
+ *(.data*)
+
+ . = ALIGN(8);
+ /* preinit data */
+ PROVIDE_HIDDEN (__preinit_array_start = .);
+ KEEP(*(.preinit_array))
+ PROVIDE_HIDDEN (__preinit_array_end = .);
+
+ . = ALIGN(8);
+ /* init data */
+ PROVIDE_HIDDEN (__init_array_start = .);
+ KEEP(*(SORT(.init_array.*)))
+ KEEP(*(.init_array))
+ PROVIDE_HIDDEN (__init_array_end = .);
+
+ . = ALIGN(8);
+ /* finit data */
+ PROVIDE_HIDDEN (__fini_array_start = .);
+ KEEP(*(SORT(.fini_array.*)))
+ KEEP(*(.fini_array))
+ PROVIDE_HIDDEN (__fini_array_end = .);
+
+ KEEP(*(.jcr*))
+ . = ALIGN(8);
+ /* All data end */
+ __data_end__ = .;
+ _edata = .;
+
+ } > RAM
+
+ /* Uninitialized data section
+ * This region is not initialized by the C/C++ library and can be used to
+ * store state across soft reboots. */
+ .uninitialized (NOLOAD):
+ {
+ . = ALIGN(32);
+ __uninitialized_start = .;
+ *(.uninitialized)
+ KEEP(*(.keep.uninitialized))
+ . = ALIGN(32);
+ __uninitialized_end = .;
+ } > RAM
+
+ .bss :
+ {
+ . = ALIGN(8);
+ __bss_start__ = .;
+ _sbss = .;
+ *(.bss*)
+ *(COMMON)
+ . = ALIGN(8);
+ __bss_end__ = .;
+ _ebss = .;
+ } > RAM
+
+ .heap (COPY):
+ {
+ __end__ = .;
+ PROVIDE(end = .);
+ *(.heap*)
+ . = ORIGIN(RAM) + LENGTH(RAM) - MBED_CONF_TARGET_BOOT_STACK_SIZE;
+ __HeapLimit = .;
+ } > RAM
+
+ /* .stack_dummy section doesn't contains any symbols. It is only
+ * used for linker to calculate size of stack sections, and assign
+ * values to stack symbols later */
+ .stack_dummy (COPY):
+ {
+ *(.stack*)
+ } > RAM
+
+ /* Set stack top to end of RAM, and stack limit move down by
+ * size of stack_dummy section */
+ __StackTop = ORIGIN(RAM) + LENGTH(RAM);
+ _estack = __StackTop;
+ __StackLimit = __StackTop - MBED_CONF_TARGET_BOOT_STACK_SIZE;
+ PROVIDE(__stack = __StackTop);
+
+ /* Check if data + heap + stack exceeds RAM limit */
+ ASSERT(__StackLimit >= __HeapLimit, "region RAM overflowed with stack")
+}
diff --git a/targets/TARGET_STM/TARGET_STM32WL/TARGET_STM32WLE4xB/TOOLCHAIN_IAR/startup_stm32wle4xx.S b/targets/TARGET_STM/TARGET_STM32WL/TARGET_STM32WLE4xB/TOOLCHAIN_IAR/startup_stm32wle4xx.S
new file mode 100644
index 0000000..0072684
--- /dev/null
+++ b/targets/TARGET_STM/TARGET_STM32WL/TARGET_STM32WLE4xB/TOOLCHAIN_IAR/startup_stm32wle4xx.S
@@ -0,0 +1,494 @@
+;********************************************************************************
+;* File Name : startup_stm32wle4xx.s
+;* Author : MCD Application Team
+;* Description : M4 core vector table of the STM32WLxxxx devices for the
+;* IAR (EWARM) toolchain.
+;*
+;* This module performs:
+;* - Set the initial SP
+;* - Set the initial PC == _iar_program_start,
+;* - Set the vector table entries with the exceptions ISR
+;* address.
+;* - Branches to main in the C library (which eventually
+;* calls main()).
+;* After Reset the Cortex-M4 processor is in Thread mode,
+;* priority is Privileged, and the Stack is set to Main.
+;********************************************************************************
+;*
+;* Copyright (c) 2020 STMicroelectronics. All rights reserved.
+;*
+;* This software component is licensed by ST under Apache License, Version 2.0,
+;* the "License"; You may not use this file except in compliance with the
+;* License. You may obtain a copy of the License at:
+;* opensource.org/licenses/Apache-2.0
+;
+;*******************************************************************************
+;
+;
+; The modules in this file are included in the libraries, and may be replaced
+; by any user-defined modules that define the PUBLIC symbol _program_start or
+; a user defined start symbol.
+; To override the cstartup defined in the library, simply add your modified
+; version to the workbench project.
+;
+; The vector table is normally located at address 0.
+; When debugging in RAM, it can be located in RAM, aligned to at least 2^6.
+; The name "__vector_table" has special meaning for C-SPY:
+; it is where the SP start value is found, and the NVIC vector
+; table register (VTOR) is initialized to this address if != 0.
+;
+; Cortex-M version
+;
+
+ MODULE ?cstartup
+
+ ;; Forward declaration of sections.
+ SECTION CSTACK:DATA:NOROOT(3)
+
+ SECTION .intvec:CODE:NOROOT(2)
+
+ EXTERN __iar_program_start
+ EXTERN SystemInit
+ PUBLIC __vector_table
+
+ DATA
+__vector_table
+ DCD sfe(CSTACK)
+ DCD Reset_Handler ; Reset Handler
+
+ DCD NMI_Handler ; NMI Handler
+ DCD HardFault_Handler ; Hard Fault Handler
+ DCD MemManage_Handler ; MPU Fault Handler
+ DCD BusFault_Handler ; Bus Fault Handler
+ DCD UsageFault_Handler ; Usage Fault Handler
+ DCD 0 ; Reserved
+ DCD 0 ; Reserved
+ DCD 0 ; Reserved
+ DCD 0 ; Reserved
+ DCD SVC_Handler ; SVCall Handler
+ DCD DebugMon_Handler ; Debug Monitor Handler
+ DCD 0 ; Reserved
+ DCD PendSV_Handler ; PendSV Handler
+ DCD SysTick_Handler ; SysTick Handler
+
+ ; External Interrupts
+ DCD WWDG_IRQHandler ; Window WatchDog
+ DCD PVD_PVM_IRQHandler ; PVD and PVM Interrupt
+ DCD TAMP_STAMP_LSECSS_SSRU_IRQHandler ; RTC Tamper, RTC TimeStamp, LSECSS and RTC SSRU Interrupts
+ DCD RTC_WKUP_IRQHandler ; RTC Wakeup Interrupt
+ DCD FLASH_IRQHandler ; FLASH global Interrupt
+ DCD RCC_IRQHandler ; RCC Interrupt
+ DCD EXTI0_IRQHandler ; EXTI Line 0 Interrupt
+ DCD EXTI1_IRQHandler ; EXTI Line 1 Interrupt
+ DCD EXTI2_IRQHandler ; EXTI Line 2 Interrupt
+ DCD EXTI3_IRQHandler ; EXTI Line 3 Interrupt
+ DCD EXTI4_IRQHandler ; EXTI Line 4 Interrupt
+ DCD DMA1_Channel1_IRQHandler ; DMA1 Channel 1 Interrupt
+ DCD DMA1_Channel2_IRQHandler ; DMA1 Channel 2 Interrupt
+ DCD DMA1_Channel3_IRQHandler ; DMA1 Channel 3 Interrupt
+ DCD DMA1_Channel4_IRQHandler ; DMA1 Channel 4 Interrupt
+ DCD DMA1_Channel5_IRQHandler ; DMA1 Channel 5 Interrupt
+ DCD DMA1_Channel6_IRQHandler ; DMA1 Channel 6 Interrupt
+ DCD DMA1_Channel7_IRQHandler ; DMA1 Channel 7 Interrupt
+ DCD ADC_IRQHandler ; ADC Interrupt
+ DCD DAC_IRQHandler ; DAC Interrupt
+ DCD 0 ; Reserved
+ DCD COMP_IRQHandler ; COMP1 and COMP2 Interrupts
+ DCD EXTI9_5_IRQHandler ; EXTI Lines [9:5] Interrupt
+ DCD TIM1_BRK_IRQHandler ; TIM1 Break Interrupt
+ DCD TIM1_UP_IRQHandler ; TIM1 Update Interrupt
+ DCD TIM1_TRG_COM_IRQHandler ; TIM1 Trigger and Communication Interrupts
+ DCD TIM1_CC_IRQHandler ; TIM1 Capture Compare Interrupt
+ DCD TIM2_IRQHandler ; TIM2 Global Interrupt
+ DCD TIM16_IRQHandler ; TIM16 Global Interrupt
+ DCD TIM17_IRQHandler ; TIM17 Global Interrupt
+ DCD I2C1_EV_IRQHandler ; I2C1 Event Interrupt
+ DCD I2C1_ER_IRQHandler ; I2C1 Error Interrupt
+ DCD I2C2_EV_IRQHandler ; I2C2 Event Interrupt
+ DCD I2C2_ER_IRQHandler ; I2C2 Error Interrupt
+ DCD SPI1_IRQHandler ; SPI1 Interrupt
+ DCD SPI2_IRQHandler ; SPI2 Interrupt
+ DCD USART1_IRQHandler ; USART1 Interrupt
+ DCD USART2_IRQHandler ; USART2 Interrupt
+ DCD LPUART1_IRQHandler ; LPUART1 Interrupt
+ DCD LPTIM1_IRQHandler ; LPTIM1 Global Interrupt
+ DCD LPTIM2_IRQHandler ; LPTIM2 Global Interrupt
+ DCD EXTI15_10_IRQHandler ; EXTI Lines [15:10] Interrupt
+ DCD RTC_Alarm_IRQHandler ; RTC Alarms (A and B) Interrupt
+ DCD LPTIM3_IRQHandler ; LPTIM3 Global Interrupt
+ DCD SUBGHZSPI_IRQHandler ; SUBGHZSPI Interrupt
+ DCD 0 ; Reserved
+ DCD 0 ; Reserved
+ DCD HSEM_IRQHandler ; HSEM0 Interrupt
+ DCD I2C3_EV_IRQHandler ; I2C3 Event Interrupt
+ DCD I2C3_ER_IRQHandler ; I2C3 Error Interrupt
+ DCD SUBGHZ_Radio_IRQHandler ; SUBGHZ Radio Interrupt
+ DCD AES_IRQHandler ; AES Interrupt
+ DCD RNG_IRQHandler ; RNG1 Interrupt
+ DCD PKA_IRQHandler ; PKA Interrupt
+ DCD DMA2_Channel1_IRQHandler ; DMA2 Channel 1 Interrupt
+ DCD DMA2_Channel2_IRQHandler ; DMA2 Channel 2 Interrupt
+ DCD DMA2_Channel3_IRQHandler ; DMA2 Channel 3 Interrupt
+ DCD DMA2_Channel4_IRQHandler ; DMA2 Channel 4 Interrupt
+ DCD DMA2_Channel5_IRQHandler ; DMA2 Channel 5 Interrupt
+ DCD DMA2_Channel6_IRQHandler ; DMA2 Channel 6 Interrupt
+ DCD DMA2_Channel7_IRQHandler ; DMA2 Channel 7 Interrupt
+ DCD DMAMUX1_OVR_IRQHandler ; DMAMUX overrun Interrupt
+
+;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;
+;;
+;; Default interrupt handlers.
+;;
+ THUMB
+
+ PUBWEAK Reset_Handler
+ SECTION .text:CODE:NOROOT:REORDER(2)
+Reset_Handler
+ LDR R0, =SystemInit
+ BLX R0
+ LDR R0, =__iar_program_start
+ BX R0
+
+ PUBWEAK NMI_Handler
+ SECTION .text:CODE:NOROOT:REORDER(1)
+NMI_Handler
+ B NMI_Handler
+
+ PUBWEAK HardFault_Handler
+ SECTION .text:CODE:NOROOT:REORDER(1)
+HardFault_Handler
+ B HardFault_Handler
+
+ PUBWEAK MemManage_Handler
+ SECTION .text:CODE:NOROOT:REORDER(1)
+MemManage_Handler
+ B MemManage_Handler
+
+ PUBWEAK BusFault_Handler
+ SECTION .text:CODE:NOROOT:REORDER(1)
+BusFault_Handler
+ B BusFault_Handler
+
+ PUBWEAK UsageFault_Handler
+ SECTION .text:CODE:NOROOT:REORDER(1)
+UsageFault_Handler
+ B UsageFault_Handler
+
+ PUBWEAK SVC_Handler
+ SECTION .text:CODE:NOROOT:REORDER(1)
+SVC_Handler
+ B SVC_Handler
+
+ PUBWEAK DebugMon_Handler
+ SECTION .text:CODE:NOROOT:REORDER(1)
+DebugMon_Handler
+ B DebugMon_Handler
+
+ PUBWEAK PendSV_Handler
+ SECTION .text:CODE:NOROOT:REORDER(1)
+PendSV_Handler
+ B PendSV_Handler
+
+ PUBWEAK SysTick_Handler
+ SECTION .text:CODE:NOROOT:REORDER(1)
+SysTick_Handler
+ B SysTick_Handler
+
+ PUBWEAK WWDG_IRQHandler
+ SECTION .text:CODE:NOROOT:REORDER(1)
+WWDG_IRQHandler
+ B WWDG_IRQHandler
+
+ PUBWEAK PVD_PVM_IRQHandler
+ SECTION .text:CODE:NOROOT:REORDER(1)
+PVD_PVM_IRQHandler
+ B PVD_PVM_IRQHandler
+
+ PUBWEAK TAMP_STAMP_LSECSS_SSRU_IRQHandler
+ SECTION .text:CODE:NOROOT:REORDER(1)
+TAMP_STAMP_LSECSS_SSRU_IRQHandler
+ B TAMP_STAMP_LSECSS_SSRU_IRQHandler
+
+ PUBWEAK RTC_WKUP_IRQHandler
+ SECTION .text:CODE:NOROOT:REORDER(1)
+RTC_WKUP_IRQHandler
+ B RTC_WKUP_IRQHandler
+
+ PUBWEAK FLASH_IRQHandler
+ SECTION .text:CODE:NOROOT:REORDER(1)
+FLASH_IRQHandler
+ B FLASH_IRQHandler
+
+ PUBWEAK RCC_IRQHandler
+ SECTION .text:CODE:NOROOT:REORDER(1)
+RCC_IRQHandler
+ B RCC_IRQHandler
+
+ PUBWEAK EXTI0_IRQHandler
+ SECTION .text:CODE:NOROOT:REORDER(1)
+EXTI0_IRQHandler
+ B EXTI0_IRQHandler
+
+ PUBWEAK EXTI1_IRQHandler
+ SECTION .text:CODE:NOROOT:REORDER(1)
+EXTI1_IRQHandler
+ B EXTI1_IRQHandler
+
+ PUBWEAK EXTI2_IRQHandler
+ SECTION .text:CODE:NOROOT:REORDER(1)
+EXTI2_IRQHandler
+ B EXTI2_IRQHandler
+
+ PUBWEAK EXTI3_IRQHandler
+ SECTION .text:CODE:NOROOT:REORDER(1)
+EXTI3_IRQHandler
+ B EXTI3_IRQHandler
+
+ PUBWEAK EXTI4_IRQHandler
+ SECTION .text:CODE:NOROOT:REORDER(1)
+EXTI4_IRQHandler
+ B EXTI4_IRQHandler
+
+ PUBWEAK DMA1_Channel1_IRQHandler
+ SECTION .text:CODE:NOROOT:REORDER(1)
+DMA1_Channel1_IRQHandler
+ B DMA1_Channel1_IRQHandler
+
+ PUBWEAK DMA1_Channel2_IRQHandler
+ SECTION .text:CODE:NOROOT:REORDER(1)
+DMA1_Channel2_IRQHandler
+ B DMA1_Channel2_IRQHandler
+
+ PUBWEAK DMA1_Channel3_IRQHandler
+ SECTION .text:CODE:NOROOT:REORDER(1)
+DMA1_Channel3_IRQHandler
+ B DMA1_Channel3_IRQHandler
+
+ PUBWEAK DMA1_Channel4_IRQHandler
+ SECTION .text:CODE:NOROOT:REORDER(1)
+DMA1_Channel4_IRQHandler
+ B DMA1_Channel4_IRQHandler
+
+ PUBWEAK DMA1_Channel5_IRQHandler
+ SECTION .text:CODE:NOROOT:REORDER(1)
+DMA1_Channel5_IRQHandler
+ B DMA1_Channel5_IRQHandler
+
+ PUBWEAK DMA1_Channel6_IRQHandler
+ SECTION .text:CODE:NOROOT:REORDER(1)
+DMA1_Channel6_IRQHandler
+ B DMA1_Channel6_IRQHandler
+
+ PUBWEAK DMA1_Channel7_IRQHandler
+ SECTION .text:CODE:NOROOT:REORDER(1)
+DMA1_Channel7_IRQHandler
+ B DMA1_Channel7_IRQHandler
+
+ PUBWEAK ADC_IRQHandler
+ SECTION .text:CODE:NOROOT:REORDER(1)
+ADC_IRQHandler
+ B ADC_IRQHandler
+
+ PUBWEAK DAC_IRQHandler
+ SECTION .text:CODE:NOROOT:REORDER(1)
+DAC_IRQHandler
+ B DAC_IRQHandler
+
+ PUBWEAK COMP_IRQHandler
+ SECTION .text:CODE:NOROOT:REORDER(1)
+COMP_IRQHandler
+ B COMP_IRQHandler
+
+ PUBWEAK EXTI9_5_IRQHandler
+ SECTION .text:CODE:NOROOT:REORDER(1)
+EXTI9_5_IRQHandler
+ B EXTI9_5_IRQHandler
+
+ PUBWEAK TIM1_BRK_IRQHandler
+ SECTION .text:CODE:NOROOT:REORDER(1)
+TIM1_BRK_IRQHandler
+ B TIM1_BRK_IRQHandler
+
+ PUBWEAK TIM1_UP_IRQHandler
+ SECTION .text:CODE:NOROOT:REORDER(1)
+TIM1_UP_IRQHandler
+ B TIM1_UP_IRQHandler
+
+ PUBWEAK TIM1_TRG_COM_IRQHandler
+ SECTION .text:CODE:NOROOT:REORDER(1)
+TIM1_TRG_COM_IRQHandler
+ B TIM1_TRG_COM_IRQHandler
+
+ PUBWEAK TIM1_CC_IRQHandler
+ SECTION .text:CODE:NOROOT:REORDER(1)
+TIM1_CC_IRQHandler
+ B TIM1_CC_IRQHandler
+
+ PUBWEAK TIM2_IRQHandler
+ SECTION .text:CODE:NOROOT:REORDER(1)
+TIM2_IRQHandler
+ B TIM2_IRQHandler
+
+ PUBWEAK TIM16_IRQHandler
+ SECTION .text:CODE:NOROOT:REORDER(1)
+TIM16_IRQHandler
+ B TIM16_IRQHandler
+
+ PUBWEAK TIM17_IRQHandler
+ SECTION .text:CODE:NOROOT:REORDER(1)
+TIM17_IRQHandler
+ B TIM17_IRQHandler
+
+ PUBWEAK I2C1_EV_IRQHandler
+ SECTION .text:CODE:NOROOT:REORDER(1)
+I2C1_EV_IRQHandler
+ B I2C1_EV_IRQHandler
+
+ PUBWEAK I2C1_ER_IRQHandler
+ SECTION .text:CODE:NOROOT:REORDER(1)
+I2C1_ER_IRQHandler
+ B I2C1_ER_IRQHandler
+
+ PUBWEAK I2C2_EV_IRQHandler
+ SECTION .text:CODE:NOROOT:REORDER(1)
+I2C2_EV_IRQHandler
+ B I2C2_EV_IRQHandler
+
+ PUBWEAK I2C2_ER_IRQHandler
+ SECTION .text:CODE:NOROOT:REORDER(1)
+I2C2_ER_IRQHandler
+ B I2C2_ER_IRQHandler
+
+ PUBWEAK SPI1_IRQHandler
+ SECTION .text:CODE:NOROOT:REORDER(1)
+SPI1_IRQHandler
+ B SPI1_IRQHandler
+
+ PUBWEAK SPI2_IRQHandler
+ SECTION .text:CODE:NOROOT:REORDER(1)
+SPI2_IRQHandler
+ B SPI2_IRQHandler
+
+ PUBWEAK USART1_IRQHandler
+ SECTION .text:CODE:NOROOT:REORDER(1)
+USART1_IRQHandler
+ B USART1_IRQHandler
+
+ PUBWEAK USART2_IRQHandler
+ SECTION .text:CODE:NOROOT:REORDER(1)
+USART2_IRQHandler
+ B USART2_IRQHandler
+
+ PUBWEAK LPUART1_IRQHandler
+ SECTION .text:CODE:NOROOT:REORDER(1)
+LPUART1_IRQHandler
+ B LPUART1_IRQHandler
+
+ PUBWEAK LPTIM1_IRQHandler
+ SECTION .text:CODE:NOROOT:REORDER(1)
+LPTIM1_IRQHandler
+ B LPTIM1_IRQHandler
+
+ PUBWEAK LPTIM2_IRQHandler
+ SECTION .text:CODE:NOROOT:REORDER(1)
+LPTIM2_IRQHandler
+ B LPTIM2_IRQHandler
+
+ PUBWEAK EXTI15_10_IRQHandler
+ SECTION .text:CODE:NOROOT:REORDER(1)
+EXTI15_10_IRQHandler
+ B EXTI15_10_IRQHandler
+
+ PUBWEAK RTC_Alarm_IRQHandler
+ SECTION .text:CODE:NOROOT:REORDER(1)
+RTC_Alarm_IRQHandler
+ B RTC_Alarm_IRQHandler
+
+ PUBWEAK LPTIM3_IRQHandler
+ SECTION .text:CODE:NOROOT:REORDER(1)
+LPTIM3_IRQHandler
+ B LPTIM3_IRQHandler
+
+ PUBWEAK SUBGHZSPI_IRQHandler
+ SECTION .text:CODE:NOROOT:REORDER(1)
+SUBGHZSPI_IRQHandler
+ B SUBGHZSPI_IRQHandler
+
+ PUBWEAK HSEM_IRQHandler
+ SECTION .text:CODE:NOROOT:REORDER(1)
+HSEM_IRQHandler
+ B HSEM_IRQHandler
+
+ PUBWEAK I2C3_EV_IRQHandler
+ SECTION .text:CODE:NOROOT:REORDER(1)
+I2C3_EV_IRQHandler
+ B I2C3_EV_IRQHandler
+
+ PUBWEAK I2C3_ER_IRQHandler
+ SECTION .text:CODE:NOROOT:REORDER(1)
+I2C3_ER_IRQHandler
+ B I2C3_ER_IRQHandler
+
+ PUBWEAK SUBGHZ_Radio_IRQHandler
+ SECTION .text:CODE:NOROOT:REORDER(1)
+SUBGHZ_Radio_IRQHandler
+ B SUBGHZ_Radio_IRQHandler
+
+ PUBWEAK AES_IRQHandler
+ SECTION .text:CODE:NOROOT:REORDER(1)
+AES_IRQHandler
+ B AES_IRQHandler
+
+ PUBWEAK RNG_IRQHandler
+ SECTION .text:CODE:NOROOT:REORDER(1)
+RNG_IRQHandler
+ B RNG_IRQHandler
+
+ PUBWEAK PKA_IRQHandler
+ SECTION .text:CODE:NOROOT:REORDER(1)
+PKA_IRQHandler
+ B PKA_IRQHandler
+
+ PUBWEAK DMA2_Channel1_IRQHandler
+ SECTION .text:CODE:NOROOT:REORDER(1)
+DMA2_Channel1_IRQHandler
+ B DMA2_Channel1_IRQHandler
+
+ PUBWEAK DMA2_Channel2_IRQHandler
+ SECTION .text:CODE:NOROOT:REORDER(1)
+DMA2_Channel2_IRQHandler
+ B DMA2_Channel2_IRQHandler
+
+ PUBWEAK DMA2_Channel3_IRQHandler
+ SECTION .text:CODE:NOROOT:REORDER(1)
+DMA2_Channel3_IRQHandler
+ B DMA2_Channel3_IRQHandler
+
+ PUBWEAK DMA2_Channel4_IRQHandler
+ SECTION .text:CODE:NOROOT:REORDER(1)
+DMA2_Channel4_IRQHandler
+ B DMA2_Channel4_IRQHandler
+
+ PUBWEAK DMA2_Channel5_IRQHandler
+ SECTION .text:CODE:NOROOT:REORDER(1)
+DMA2_Channel5_IRQHandler
+ B DMA2_Channel5_IRQHandler
+
+ PUBWEAK DMA2_Channel6_IRQHandler
+ SECTION .text:CODE:NOROOT:REORDER(1)
+DMA2_Channel6_IRQHandler
+ B DMA2_Channel6_IRQHandler
+
+ PUBWEAK DMA2_Channel7_IRQHandler
+ SECTION .text:CODE:NOROOT:REORDER(1)
+DMA2_Channel7_IRQHandler
+ B DMA2_Channel7_IRQHandler
+
+ PUBWEAK DMAMUX1_OVR_IRQHandler
+ SECTION .text:CODE:NOROOT:REORDER(1)
+DMAMUX1_OVR_IRQHandler
+ B DMAMUX1_OVR_IRQHandler
+
+ END
+
+;************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE*****
diff --git a/targets/TARGET_STM/TARGET_STM32WL/TARGET_STM32WLE4xB/TOOLCHAIN_IAR/stm32wle4xb.icf b/targets/TARGET_STM/TARGET_STM32WL/TARGET_STM32WLE4xB/TOOLCHAIN_IAR/stm32wle4xb.icf
new file mode 100644
index 0000000..7fb4af2
--- /dev/null
+++ b/targets/TARGET_STM/TARGET_STM32WL/TARGET_STM32WLE4xB/TOOLCHAIN_IAR/stm32wle4xb.icf
@@ -0,0 +1,59 @@
+/* Linker script to configure memory regions.
+ *
+ * SPDX-License-Identifier: BSD-3-Clause
+ ******************************************************************************
+ * @attention
+ *
+ * Copyright (c) 2016-2020 STMicroelectronics.
+ * All rights reserved.
+ *
+ * This software component is licensed by ST under BSD 3-Clause license,
+ * the "License"; You may not use this file except in compliance with the
+ * License. You may obtain a copy of the License at:
+ * opensource.org/licenses/BSD-3-Clause
+ *
+ ******************************************************************************
+*/
+/* Device specific values */
+
+/* Tools provide -DMBED_ROM_START=xxx -DMBED_ROM_SIZE=xxx -DMBED_RAM_START=xxx -DMBED_RAM_SIZE=xxx */
+
+define symbol VECTORS = 78; /* This value must match NVIC_NUM_VECTORS in cmsis_nvic.h */
+define symbol HEAP_SIZE = 0x1000;
+
+/* Common - Do not change */
+
+if (!isdefinedsymbol(MBED_APP_START)) {
+ define symbol MBED_APP_START = MBED_ROM_START;
+}
+
+if (!isdefinedsymbol(MBED_APP_SIZE)) {
+ define symbol MBED_APP_SIZE = MBED_ROM_SIZE;
+}
+
+if (!isdefinedsymbol(MBED_CONF_TARGET_BOOT_STACK_SIZE)) {
+ /* This value is normally defined by the tools
+ to 0x1000 for bare metal and 0x400 for RTOS */
+ define symbol MBED_CONF_TARGET_BOOT_STACK_SIZE = 0x400;
+}
+
+/* Round up VECTORS_SIZE to 8 bytes */
+define symbol VECTORS_SIZE = ((VECTORS * 4) + 7) & ~7;
+define symbol RAM_REGION_START = MBED_RAM_START + VECTORS_SIZE;
+define symbol RAM_REGION_SIZE = MBED_RAM_SIZE - VECTORS_SIZE;
+
+define memory mem with size = 4G;
+define region ROM_region = mem:[from MBED_APP_START size MBED_APP_SIZE];
+define region RAM_region = mem:[from RAM_REGION_START size RAM_REGION_SIZE];
+
+define block CSTACK with alignment = 8, size = MBED_CONF_TARGET_BOOT_STACK_SIZE { };
+define block HEAP with alignment = 8, size = HEAP_SIZE { };
+
+initialize by copy { readwrite };
+do not initialize { section .noinit };
+
+place at address mem: MBED_APP_START { readonly section .intvec };
+
+place in ROM_region { readonly };
+place in RAM_region { readwrite,
+ block CSTACK, block HEAP };
diff --git a/targets/TARGET_STM/TARGET_STM32WL/TARGET_STM32WLE4xB/cmsis_nvic.h b/targets/TARGET_STM/TARGET_STM32WL/TARGET_STM32WLE4xB/cmsis_nvic.h
new file mode 100644
index 0000000..a18342e
--- /dev/null
+++ b/targets/TARGET_STM/TARGET_STM32WL/TARGET_STM32WLE4xB/cmsis_nvic.h
@@ -0,0 +1,39 @@
+/* mbed Microcontroller Library
+ * SPDX-License-Identifier: BSD-3-Clause
+ ******************************************************************************
+ * @attention
+ *
+ * © Copyright (c) 2016-2020 STMicroelectronics.
+ * All rights reserved.
+ *
+ * This software component is licensed by ST under BSD 3-Clause license,
+ * the "License"; You may not use this file except in compliance with the
+ * License. You may obtain a copy of the License at:
+ * opensource.org/licenses/BSD-3-Clause
+ *
+ ******************************************************************************
+*/
+
+#ifndef MBED_CMSIS_NVIC_H
+#define MBED_CMSIS_NVIC_H
+
+#if !defined(MBED_ROM_START)
+#define MBED_ROM_START 0x8000000
+#endif
+
+#if !defined(MBED_ROM_SIZE)
+#define MBED_ROM_SIZE 0x0 // 0 B
+#endif
+
+#if !defined(MBED_RAM_START)
+#define MBED_RAM_START 0x20000000
+#endif
+
+#if !defined(MBED_RAM_SIZE)
+#define MBED_RAM_SIZE 0x0 // 0 B
+#endif
+
+#define NVIC_NUM_VECTORS 78
+#define NVIC_RAM_VECTOR_ADDRESS MBED_RAM_START
+
+#endif
diff --git a/targets/TARGET_STM/TARGET_STM32WL/TARGET_STM32WLE4xC/TOOLCHAIN_ARM/startup_stm32wle4xx.S b/targets/TARGET_STM/TARGET_STM32WL/TARGET_STM32WLE4xC/TOOLCHAIN_ARM/startup_stm32wle4xx.S
new file mode 100644
index 0000000..002a574
--- /dev/null
+++ b/targets/TARGET_STM/TARGET_STM32WL/TARGET_STM32WLE4xC/TOOLCHAIN_ARM/startup_stm32wle4xx.S
@@ -0,0 +1,314 @@
+;******************************************************************************
+;* File Name : startup_stm32wle4xx.s
+;* Author : MCD Application Team
+;* Description : STM32WLE4xx devices vector table for MDK-ARM toolchain.
+;* This module performs:
+;* - Set the initial SP
+;* - Set the initial PC == Reset_Handler
+;* - Set the vector table entries with the exceptions ISR address
+;* - Branches to __main in the C library (which eventually
+;* calls main()).
+;* After Reset the CortexM4 processor is in Thread mode,
+;* priority is Privileged, and the Stack is set to Main.
+;* <<< Use Configuration Wizard in Context Menu >>>
+;******************************************************************************
+;* @attention
+;*
+;* Copyright (c) 2020 STMicroelectronics. All rights reserved.
+;*
+;* This software component is licensed by ST under Apache License, Version 2.0,
+;* the "License"; You may not use this file except in compliance with the
+;* License. You may obtain a copy of the License at:
+;* opensource.org/licenses/Apache-2.0
+;*
+;******************************************************************************
+
+ PRESERVE8
+ THUMB
+
+
+; Vector Table Mapped to Address 0 at Reset
+ AREA RESET, DATA, READONLY
+ EXPORT __Vectors
+ EXPORT __Vectors_End
+ EXPORT __Vectors_Size
+
+ IMPORT |Image$$ARM_LIB_STACK$$ZI$$Limit|
+__Vectors DCD |Image$$ARM_LIB_STACK$$ZI$$Limit| ; Top of Stack
+ DCD Reset_Handler ; Reset Handler
+ DCD NMI_Handler ; NMI Handler
+ DCD HardFault_Handler ; Hard Fault Handler
+ DCD MemManage_Handler ; MPU Fault Handler
+ DCD BusFault_Handler ; Bus Fault Handler
+ DCD UsageFault_Handler ; Usage Fault Handler
+ DCD 0 ; Reserved
+ DCD 0 ; Reserved
+ DCD 0 ; Reserved
+ DCD 0 ; Reserved
+ DCD SVC_Handler ; SVCall Handler
+ DCD DebugMon_Handler ; Debug Monitor Handler
+ DCD 0 ; Reserved
+ DCD PendSV_Handler ; PendSV Handler
+ DCD SysTick_Handler ; SysTick Handler
+
+ ; External Interrupts
+ DCD WWDG_IRQHandler ; Window WatchDog
+ DCD PVD_PVM_IRQHandler ; PVD and PVM detector
+ DCD TAMP_STAMP_LSECSS_SSRU_IRQHandler ; RTC Tamper, RTC TimeStamp, LSECSS and RTC SSR Underflow Interrupts
+ DCD RTC_WKUP_IRQHandler ; RTC Wakeup Interrupt
+ DCD FLASH_IRQHandler ; FLASH global Interrupt
+ DCD RCC_IRQHandler ; RCC Interrupt
+ DCD EXTI0_IRQHandler ; EXTI Line 0 Interrupt
+ DCD EXTI1_IRQHandler ; EXTI Line 1 Interrupt
+ DCD EXTI2_IRQHandler ; EXTI Line 2 Interrupt
+ DCD EXTI3_IRQHandler ; EXTI Line 3 Interrup
+ DCD EXTI4_IRQHandler ; EXTI Line 4 Interrupt
+ DCD DMA1_Channel1_IRQHandler ; DMA1 Channel 1 Interrupt
+ DCD DMA1_Channel2_IRQHandler ; DMA1 Channel 2 Interrupt
+ DCD DMA1_Channel3_IRQHandler ; DMA1 Channel 3 Interrupt
+ DCD DMA1_Channel4_IRQHandler ; DMA1 Channel 4 Interrupt
+ DCD DMA1_Channel5_IRQHandler ; DMA1 Channel 5 Interrupt
+ DCD DMA1_Channel6_IRQHandler ; DMA1 Channel 6 Interrupt
+ DCD DMA1_Channel7_IRQHandler ; DMA1 Channel 7 Interrupt
+ DCD ADC_IRQHandler ; ADC Interrupt
+ DCD DAC_IRQHandler ; DAC Interrupt
+ DCD 0 ; Reserved
+ DCD COMP_IRQHandler ; COMP1 and COMP2 Interrupts
+ DCD EXTI9_5_IRQHandler ; EXTI Lines [9:5] Interrupt
+ DCD TIM1_BRK_IRQHandler ; TIM1 Break Interrupt
+ DCD TIM1_UP_IRQHandler ; TIM1 Update Interrupts
+ DCD TIM1_TRG_COM_IRQHandler ; TIM1 Trigger and Communication Interrupts
+ DCD TIM1_CC_IRQHandler ; TIM1 Capture Compare Interrupt
+ DCD TIM2_IRQHandler ; TIM2 Global Interrupt
+ DCD TIM16_IRQHandler ; TIM16 Global Interrupt
+ DCD TIM17_IRQHandler ; TIM17 Global Interrupt
+ DCD I2C1_EV_IRQHandler ; I2C1 Event Interrupt
+ DCD I2C1_ER_IRQHandler ; I2C1 Error Interrupt
+ DCD I2C2_EV_IRQHandler ; I2C2 Event Interrupt
+ DCD I2C2_ER_IRQHandler ; I2C2 Error Interrupt
+ DCD SPI1_IRQHandler ; SPI1 Interrupt
+ DCD SPI2_IRQHandler ; SPI2 Interrupt
+ DCD USART1_IRQHandler ; USART1 Interrupt
+ DCD USART2_IRQHandler ; USART2 Interrupt
+ DCD LPUART1_IRQHandler ; LPUART1 Interrupt
+ DCD LPTIM1_IRQHandler ; LPTIM1 Interrupt
+ DCD LPTIM2_IRQHandler ; LPTIM2 Interrupt
+ DCD EXTI15_10_IRQHandler ; EXTI Lines1[15:10 ]Interrupts
+ DCD RTC_Alarm_IRQHandler ; RTC Alarms (A and B) Interrupt
+ DCD LPTIM3_IRQHandler ; LPTIM3 Interrupt
+ DCD SUBGHZSPI_IRQHandler ; SUBGHZSPI Interrupt
+ DCD 0 ; Reserved
+ DCD 0 ; Reserved
+ DCD HSEM_IRQHandler ; HSEM0 Interrupt
+ DCD I2C3_EV_IRQHandler ; I2C3 Event Interrupt
+ DCD I2C3_ER_IRQHandler ; I2C3 Error Interrupt
+ DCD SUBGHZ_Radio_IRQHandler ; SUBGHZ Radio Interrupt
+ DCD AES_IRQHandler ; AES Interrupt
+ DCD RNG_IRQHandler ; RNG1 Interrupt
+ DCD PKA_IRQHandler ; PKA Interrupt
+ DCD DMA2_Channel1_IRQHandler ; DMA2 Channel 1 Interrupt
+ DCD DMA2_Channel2_IRQHandler ; DMA2 Channel 2 Interrupt
+ DCD DMA2_Channel3_IRQHandler ; DMA2 Channel 3 Interrupt
+ DCD DMA2_Channel4_IRQHandler ; DMA2 Channel 4 Interrupt
+ DCD DMA2_Channel5_IRQHandler ; DMA2 Channel 5 Interrupt
+ DCD DMA2_Channel6_IRQHandler ; DMA2 Channel 6 Interrupt
+ DCD DMA2_Channel7_IRQHandler ; DMA2 Channel 7 Interrupt
+ DCD DMAMUX1_OVR_IRQHandler ; DMAMUX overrun Interrupt
+
+__Vectors_End
+
+__Vectors_Size EQU __Vectors_End - __Vectors
+
+ AREA |.text|, CODE, READONLY
+
+; Reset handler
+Reset_Handler PROC
+ EXPORT Reset_Handler [WEAK]
+ IMPORT SystemInit
+ IMPORT __main
+
+ LDR R0, =SystemInit
+ BLX R0
+ LDR R0, =__main
+ BX R0
+ ENDP
+
+; Dummy Exception Handlers (infinite loops which can be modified)
+
+NMI_Handler PROC
+ EXPORT NMI_Handler [WEAK]
+ B .
+ ENDP
+HardFault_Handler\
+ PROC
+ EXPORT HardFault_Handler [WEAK]
+ B .
+ ENDP
+MemManage_Handler\
+ PROC
+ EXPORT MemManage_Handler [WEAK]
+ B .
+ ENDP
+BusFault_Handler\
+ PROC
+ EXPORT BusFault_Handler [WEAK]
+ B .
+ ENDP
+UsageFault_Handler\
+ PROC
+ EXPORT UsageFault_Handler [WEAK]
+ B .
+ ENDP
+SVC_Handler PROC
+ EXPORT SVC_Handler [WEAK]
+ B .
+ ENDP
+DebugMon_Handler\
+ PROC
+ EXPORT DebugMon_Handler [WEAK]
+ B .
+ ENDP
+PendSV_Handler PROC
+ EXPORT PendSV_Handler [WEAK]
+ B .
+ ENDP
+SysTick_Handler PROC
+ EXPORT SysTick_Handler [WEAK]
+ B .
+ ENDP
+
+Default_Handler PROC
+
+ EXPORT WWDG_IRQHandler [WEAK]
+ EXPORT PVD_PVM_IRQHandler [WEAK]
+ EXPORT TAMP_STAMP_LSECSS_SSRU_IRQHandler [WEAK]
+ EXPORT RTC_WKUP_IRQHandler [WEAK]
+ EXPORT FLASH_IRQHandler [WEAK]
+ EXPORT RCC_IRQHandler [WEAK]
+ EXPORT EXTI0_IRQHandler [WEAK]
+ EXPORT EXTI1_IRQHandler [WEAK]
+ EXPORT EXTI2_IRQHandler [WEAK]
+ EXPORT EXTI3_IRQHandler [WEAK]
+ EXPORT EXTI4_IRQHandler [WEAK]
+ EXPORT DMA1_Channel1_IRQHandler [WEAK]
+ EXPORT DMA1_Channel2_IRQHandler [WEAK]
+ EXPORT DMA1_Channel3_IRQHandler [WEAK]
+ EXPORT DMA1_Channel4_IRQHandler [WEAK]
+ EXPORT DMA1_Channel5_IRQHandler [WEAK]
+ EXPORT DMA1_Channel6_IRQHandler [WEAK]
+ EXPORT DMA1_Channel7_IRQHandler [WEAK]
+ EXPORT ADC_IRQHandler [WEAK]
+ EXPORT DAC_IRQHandler [WEAK]
+ EXPORT COMP_IRQHandler [WEAK]
+ EXPORT EXTI9_5_IRQHandler [WEAK]
+ EXPORT TIM1_BRK_IRQHandler [WEAK]
+ EXPORT TIM1_UP_IRQHandler [WEAK]
+ EXPORT TIM1_TRG_COM_IRQHandler [WEAK]
+ EXPORT TIM1_CC_IRQHandler [WEAK]
+ EXPORT TIM2_IRQHandler [WEAK]
+ EXPORT TIM16_IRQHandler [WEAK]
+ EXPORT TIM17_IRQHandler [WEAK]
+ EXPORT I2C1_EV_IRQHandler [WEAK]
+ EXPORT I2C1_ER_IRQHandler [WEAK]
+ EXPORT I2C2_EV_IRQHandler [WEAK]
+ EXPORT I2C2_ER_IRQHandler [WEAK]
+ EXPORT SPI1_IRQHandler [WEAK]
+ EXPORT SPI2_IRQHandler [WEAK]
+ EXPORT USART1_IRQHandler [WEAK]
+ EXPORT USART2_IRQHandler [WEAK]
+ EXPORT LPUART1_IRQHandler [WEAK]
+ EXPORT LPTIM1_IRQHandler [WEAK]
+ EXPORT LPTIM2_IRQHandler [WEAK]
+ EXPORT EXTI15_10_IRQHandler [WEAK]
+ EXPORT RTC_Alarm_IRQHandler [WEAK]
+ EXPORT LPTIM3_IRQHandler [WEAK]
+ EXPORT SUBGHZSPI_IRQHandler [WEAK]
+ EXPORT HSEM_IRQHandler [WEAK]
+ EXPORT I2C3_EV_IRQHandler [WEAK]
+ EXPORT I2C3_ER_IRQHandler [WEAK]
+ EXPORT SUBGHZ_Radio_IRQHandler [WEAK]
+ EXPORT AES_IRQHandler [WEAK]
+ EXPORT RNG_IRQHandler [WEAK]
+ EXPORT PKA_IRQHandler [WEAK]
+ EXPORT DMA2_Channel1_IRQHandler [WEAK]
+ EXPORT DMA2_Channel2_IRQHandler [WEAK]
+ EXPORT DMA2_Channel3_IRQHandler [WEAK]
+ EXPORT DMA2_Channel4_IRQHandler [WEAK]
+ EXPORT DMA2_Channel5_IRQHandler [WEAK]
+ EXPORT DMA2_Channel6_IRQHandler [WEAK]
+ EXPORT DMA2_Channel7_IRQHandler [WEAK]
+ EXPORT DMAMUX1_OVR_IRQHandler [WEAK]
+
+WWDG_IRQHandler
+PVD_PVM_IRQHandler
+TAMP_STAMP_LSECSS_SSRU_IRQHandler
+RTC_WKUP_IRQHandler
+FLASH_IRQHandler
+RCC_IRQHandler
+EXTI0_IRQHandler
+EXTI1_IRQHandler
+EXTI2_IRQHandler
+EXTI3_IRQHandler
+EXTI4_IRQHandler
+DMA1_Channel1_IRQHandler
+DMA1_Channel2_IRQHandler
+DMA1_Channel3_IRQHandler
+DMA1_Channel4_IRQHandler
+DMA1_Channel5_IRQHandler
+DMA1_Channel6_IRQHandler
+DMA1_Channel7_IRQHandler
+ADC_IRQHandler
+DAC_IRQHandler
+COMP_IRQHandler
+EXTI9_5_IRQHandler
+TIM1_BRK_IRQHandler
+TIM1_UP_IRQHandler
+TIM1_TRG_COM_IRQHandler
+TIM1_CC_IRQHandler
+TIM2_IRQHandler
+TIM16_IRQHandler
+TIM17_IRQHandler
+I2C1_EV_IRQHandler
+I2C1_ER_IRQHandler
+I2C2_EV_IRQHandler
+I2C2_ER_IRQHandler
+SPI1_IRQHandler
+SPI2_IRQHandler
+USART1_IRQHandler
+USART2_IRQHandler
+LPUART1_IRQHandler
+LPTIM1_IRQHandler
+LPTIM2_IRQHandler
+EXTI15_10_IRQHandler
+RTC_Alarm_IRQHandler
+LPTIM3_IRQHandler
+SUBGHZSPI_IRQHandler
+HSEM_IRQHandler
+I2C3_EV_IRQHandler
+I2C3_ER_IRQHandler
+SUBGHZ_Radio_IRQHandler
+AES_IRQHandler
+RNG_IRQHandler
+PKA_IRQHandler
+DMA2_Channel1_IRQHandler
+DMA2_Channel2_IRQHandler
+DMA2_Channel3_IRQHandler
+DMA2_Channel4_IRQHandler
+DMA2_Channel5_IRQHandler
+DMA2_Channel6_IRQHandler
+DMA2_Channel7_IRQHandler
+DMAMUX1_OVR_IRQHandler
+
+ B .
+
+ ENDP
+
+ ALIGN
+
+;*******************************************************************************
+; User Stack and Heap initialization
+;*******************************************************************************
+
+ END
+
+;************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE*****
diff --git a/targets/TARGET_STM/TARGET_STM32WL/TARGET_STM32WLE4xC/TOOLCHAIN_ARM/stm32wle4xc.sct b/targets/TARGET_STM/TARGET_STM32WL/TARGET_STM32WLE4xC/TOOLCHAIN_ARM/stm32wle4xc.sct
new file mode 100644
index 0000000..9258e6a
--- /dev/null
+++ b/targets/TARGET_STM/TARGET_STM32WL/TARGET_STM32WLE4xC/TOOLCHAIN_ARM/stm32wle4xc.sct
@@ -0,0 +1,57 @@
+#! armclang -E --target=arm-arm-none-eabi -x c -mcpu=cortex-M4
+; Scatter-Loading Description File
+;
+; SPDX-License-Identifier: BSD-3-Clause
+;******************************************************************************
+;* @attention
+;*
+;* Copyright (c) 2016-2020 STMicroelectronics.
+;* All rights reserved.
+;*
+;* This software component is licensed by ST under BSD 3-Clause license,
+;* the "License"; You may not use this file except in compliance with the
+;* License. You may obtain a copy of the License at:
+;* opensource.org/licenses/BSD-3-Clause
+;*
+;******************************************************************************
+
+#include "../cmsis_nvic.h"
+
+#if !defined(MBED_APP_START)
+ #define MBED_APP_START MBED_ROM_START
+#endif
+
+#if !defined(MBED_APP_SIZE)
+ #define MBED_APP_SIZE MBED_ROM_SIZE
+#endif
+
+#if !defined(MBED_CONF_TARGET_BOOT_STACK_SIZE)
+/* This value is normally defined by the tools to 0x1000 for bare metal and 0x400 for RTOS */
+#if defined(MBED_BOOT_STACK_SIZE)
+#define MBED_CONF_TARGET_BOOT_STACK_SIZE MBED_BOOT_STACK_SIZE
+#else
+#define MBED_CONF_TARGET_BOOT_STACK_SIZE 0x400
+#endif
+#endif
+
+/* Round up VECTORS_SIZE to 8 bytes */
+#define VECTORS_SIZE (((NVIC_NUM_VECTORS * 4) + 7) AND ~7)
+
+LR_IROM1 MBED_APP_START MBED_APP_SIZE {
+
+ ER_IROM1 MBED_APP_START MBED_APP_SIZE {
+ *.o (RESET, +First)
+ *(InRoot$$Sections)
+ .ANY (+RO)
+ }
+
+ RW_IRAM1 (MBED_RAM_START + VECTORS_SIZE) { ; RW data
+ .ANY (+RW +ZI)
+ }
+
+ ARM_LIB_HEAP AlignExpr(+0, 16) EMPTY (MBED_RAM_START + MBED_RAM_SIZE - MBED_CONF_TARGET_BOOT_STACK_SIZE - AlignExpr(ImageLimit(RW_IRAM1), 16)) { ; Heap growing up
+ }
+
+ ARM_LIB_STACK (MBED_RAM_START + MBED_RAM_SIZE) EMPTY -MBED_CONF_TARGET_BOOT_STACK_SIZE { ; Stack region growing down
+ }
+}
diff --git a/targets/TARGET_STM/TARGET_STM32WL/TARGET_STM32WLE4xC/TOOLCHAIN_GCC_ARM/startup_stm32wle4xx.S b/targets/TARGET_STM/TARGET_STM32WL/TARGET_STM32WLE4xC/TOOLCHAIN_GCC_ARM/startup_stm32wle4xx.S
new file mode 100644
index 0000000..c919abb
--- /dev/null
+++ b/targets/TARGET_STM/TARGET_STM32WL/TARGET_STM32WLE4xC/TOOLCHAIN_GCC_ARM/startup_stm32wle4xx.S
@@ -0,0 +1,425 @@
+/**
+ ******************************************************************************
+ * @file startup_stm32wle4xx.s
+ * @author MCD Application Team
+ * @brief STM32WLE4xx devices vector table for GCC toolchain.
+ * This module performs:
+ * - Set the initial SP
+ * - Set the initial PC == Reset_Handler,
+ * - Set the vector table entries with the exceptions ISR address,
+ * - Branches to main in the C library (which eventually
+ * calls main()).
+ * After Reset the Cortex-M4 processor is in Thread mode,
+ * priority is Privileged, and the Stack is set to Main.
+ ******************************************************************************
+ * @attention
+ *
+ * © Copyright (c) 2020 STMicroelectronics.
+ * All rights reserved.
+ *
+ * This software component is licensed by ST under Apache License, Version 2.0,
+ * the "License"; You may not use this file except in compliance with the
+ * License. You may obtain a copy of the License at:
+ * opensource.org/licenses/Apache-2.0
+ *
+ ******************************************************************************
+ */
+
+.syntax unified
+.cpu cortex-m4
+.fpu softvfp
+.thumb
+
+.global g_pfnVectors
+.global Default_Handler
+
+/* start address for the initialization values of the .data section.
+defined in linker script */
+.word _sidata
+/* start address for the .data section. defined in linker script */
+.word _sdata
+/* end address for the .data section. defined in linker script */
+.word _edata
+/* start address for the .bss section. defined in linker script */
+.word _sbss
+/* end address for the .bss section. defined in linker script */
+.word _ebss
+
+/**
+ * @brief This is the code that gets called when the processor first
+ * starts execution following a reset event. Only the absolutely
+ * necessary set is performed, after which the application
+ * supplied main() routine is called.
+ * @param None
+ * @retval : None
+*/
+
+ .section .text.Reset_Handler
+ .weak Reset_Handler
+ .type Reset_Handler, %function
+Reset_Handler:
+ ldr r0, =_estack
+ mov sp, r0 /* set stack pointer */
+
+/* Call the clock system initialization function.*/
+ bl SystemInit
+
+/* Copy the data segment initializers from flash to SRAM */
+ ldr r0, =_sdata
+ ldr r1, =_edata
+ ldr r2, =_sidata
+ movs r3, #0
+ b LoopCopyDataInit
+
+CopyDataInit:
+ ldr r4, [r2, r3]
+ str r4, [r0, r3]
+ adds r3, r3, #4
+
+LoopCopyDataInit:
+ adds r4, r0, r3
+ cmp r4, r1
+ bcc CopyDataInit
+
+/* Zero fill the bss segment. */
+ ldr r2, =_sbss
+ ldr r4, =_ebss
+ movs r3, #0
+ b LoopFillZerobss
+
+FillZerobss:
+ str r3, [r2]
+ adds r2, r2, #4
+
+LoopFillZerobss:
+ cmp r2, r4
+ bcc FillZerobss
+
+ bl _start
+ bx lr
+
+LoopForever:
+ b LoopForever
+
+ .size Reset_Handler, .-Reset_Handler
+
+/**
+ * @brief This is the code that gets called when the processor receives an
+ * unexpected interrupt. This simply enters an infinite loop, preserving
+ * the system state for examination by a debugger.
+ *
+ * @param None
+ * @retval : None
+*/
+ .section .text.Default_Handler,"ax",%progbits
+Default_Handler:
+Infinite_Loop:
+ b Infinite_Loop
+ .size Default_Handler, .-Default_Handler
+
+/******************************************************************************
+*
+* The STM32WLE4xx vector table. Note that the proper constructs
+* must be placed on this to ensure that it ends up at physical address
+* 0x0000.0000.
+*
+******************************************************************************/
+ .section .isr_vector,"a",%progbits
+ .type g_pfnVectors, %object
+ .size g_pfnVectors, .-g_pfnVectors
+
+g_pfnVectors:
+ .word _estack
+ .word Reset_Handler
+ .word NMI_Handler
+ .word HardFault_Handler
+ .word MemManage_Handler
+ .word BusFault_Handler
+ .word UsageFault_Handler
+ .word 0
+ .word 0
+ .word 0
+ .word 0
+ .word SVC_Handler
+ .word DebugMon_Handler
+ .word 0
+ .word PendSV_Handler
+ .word SysTick_Handler
+ .word WWDG_IRQHandler /* Window Watchdog interrupt */
+ .word PVD_PVM_IRQHandler /* PVD and PVM interrupt through EXTI */
+ .word TAMP_STAMP_LSECSS_SSRU_IRQHandler /* RTC Tamper, RTC TimeStamp, LSECSS and RTC SSRU int.*/
+ .word RTC_WKUP_IRQHandler /* RTC wakeup interrupt through EXTI[19] */
+ .word FLASH_IRQHandler /* Flash memory global interrupt and Flash memory ECC */
+ .word RCC_IRQHandler /* RCC global interrupt */
+ .word EXTI0_IRQHandler /* EXTI line 0 interrupt */
+ .word EXTI1_IRQHandler /* EXTI line 1 interrupt */
+ .word EXTI2_IRQHandler /* EXTI line 2 interrupt */
+ .word EXTI3_IRQHandler /* EXTI line 3 interrupt */
+ .word EXTI4_IRQHandler /* EXTI line 4 interrupt */
+ .word DMA1_Channel1_IRQHandler /* DMA1 channel 1 interrupt */
+ .word DMA1_Channel2_IRQHandler /* DMA1 channel 2 interrupt */
+ .word DMA1_Channel3_IRQHandler /* DMA1 channel 3 interrupt */
+ .word DMA1_Channel4_IRQHandler /* DMA1 channel 4 interrupt */
+ .word DMA1_Channel5_IRQHandler /* DMA1 channel 5 interrupt */
+ .word DMA1_Channel6_IRQHandler /* DMA1 channel 6 interrupt */
+ .word DMA1_Channel7_IRQHandler /* DMA1 channel 7 interrupt */
+ .word ADC_IRQHandler /* ADC interrupt */
+ .word DAC_IRQHandler /* DAC interrupt */
+ .word 0 /* Reserved */
+ .word COMP_IRQHandler /* COMP1 and COMP2 interrupt through EXTI */
+ .word EXTI9_5_IRQHandler /* EXTI line 9_5 interrupt */
+ .word TIM1_BRK_IRQHandler /* Timer 1 break interrupt */
+ .word TIM1_UP_IRQHandler /* Timer 1 Update */
+ .word TIM1_TRG_COM_IRQHandler /* Timer 1 trigger and communication */
+ .word TIM1_CC_IRQHandler /* Timer 1 capture compare interrupt */
+ .word TIM2_IRQHandler /* TIM2 global interrupt */
+ .word TIM16_IRQHandler /* Timer 16 global interrupt */
+ .word TIM17_IRQHandler /* Timer 17 global interrupt */
+ .word I2C1_EV_IRQHandler /* I2C1 event interrupt */
+ .word I2C1_ER_IRQHandler /* I2C1 event interrupt */
+ .word I2C2_EV_IRQHandler /* I2C2 error interrupt */
+ .word I2C2_ER_IRQHandler /* I2C2 error interrupt */
+ .word SPI1_IRQHandler /* SPI1 global interrupt */
+ .word SPI2_IRQHandler /* SPI2 global interrupt */
+ .word USART1_IRQHandler /* USART1 global interrupt */
+ .word USART2_IRQHandler /* USART2 global interrupt */
+ .word LPUART1_IRQHandler /* LPUART1 global interrupt */
+ .word LPTIM1_IRQHandler /* LPtimer 1 global interrupt */
+ .word LPTIM2_IRQHandler /* LPtimer 2 global interrupt */
+ .word EXTI15_10_IRQHandler /* EXTI line 15_10] interrupt through EXTI */
+ .word RTC_Alarm_IRQHandler /* RTC Alarms A & B interrupt */
+ .word LPTIM3_IRQHandler /* LPtimer 3 global interrupt */
+ .word SUBGHZSPI_IRQHandler /* SUBGHZSPI global interrupt */
+ .word 0 /* Reserved */
+ .word 0 /* Reserved */
+ .word HSEM_IRQHandler /* Semaphore interrupt 0 to CPU1 */
+ .word I2C3_EV_IRQHandler /* I2C3 event interrupt */
+ .word I2C3_ER_IRQHandler /* I2C3 error interrupt */
+ .word SUBGHZ_Radio_IRQHandler /* Radio IRQs RFBUSY interrupt through EXTI */
+ .word AES_IRQHandler /* AES global interrupt */
+ .word RNG_IRQHandler /* RNG interrupt */
+ .word PKA_IRQHandler /* PKA interrupt */
+ .word DMA2_Channel1_IRQHandler /* DMA2 channel 1 interrupt */
+ .word DMA2_Channel2_IRQHandler /* DMA2 channel 2 interrupt */
+ .word DMA2_Channel3_IRQHandler /* DMA2 channel 3 interrupt */
+ .word DMA2_Channel4_IRQHandler /* DMA2 channel 4 interrupt */
+ .word DMA2_Channel5_IRQHandler /* DMA2 channel 5 interrupt */
+ .word DMA2_Channel6_IRQHandler /* DMA2 channel 6 interrupt */
+ .word DMA2_Channel7_IRQHandler /* DMA2 channel 7 interrupt */
+ .word DMAMUX1_OVR_IRQHandler /* DMAMUX overrun interrupt */
+
+/*******************************************************************************
+*
+* Provide weak aliases for each Exception handler to the Default_Handler.
+* As they are weak aliases, any function with the same name will override
+* this definition.
+*
+*******************************************************************************/
+
+ .weak NMI_Handler
+ .thumb_set NMI_Handler,Default_Handler
+
+ .weak HardFault_Handler
+ .thumb_set HardFault_Handler,Default_Handler
+
+ .weak MemManage_Handler
+ .thumb_set MemManage_Handler,Default_Handler
+
+ .weak BusFault_Handler
+ .thumb_set BusFault_Handler,Default_Handler
+
+ .weak UsageFault_Handler
+ .thumb_set UsageFault_Handler,Default_Handler
+
+ .weak SVC_Handler
+ .thumb_set SVC_Handler,Default_Handler
+
+ .weak DebugMon_Handler
+ .thumb_set DebugMon_Handler,Default_Handler
+
+ .weak PendSV_Handler
+ .thumb_set PendSV_Handler,Default_Handler
+
+ .weak SysTick_Handler
+ .thumb_set SysTick_Handler,Default_Handler
+
+ .weak WWDG_IRQHandler
+ .thumb_set WWDG_IRQHandler,Default_Handler
+
+ .weak PVD_PVM_IRQHandler
+ .thumb_set PVD_PVM_IRQHandler,Default_Handler
+
+ .weak TAMP_STAMP_LSECSS_SSRU_IRQHandler
+ .thumb_set TAMP_STAMP_LSECSS_SSRU_IRQHandler,Default_Handler
+
+ .weak RTC_WKUP_IRQHandler
+ .thumb_set RTC_WKUP_IRQHandler,Default_Handler
+
+ .weak FLASH_IRQHandler
+ .thumb_set FLASH_IRQHandler,Default_Handler
+
+ .weak RCC_IRQHandler
+ .thumb_set RCC_IRQHandler,Default_Handler
+
+ .weak EXTI0_IRQHandler
+ .thumb_set EXTI0_IRQHandler,Default_Handler
+
+ .weak EXTI1_IRQHandler
+ .thumb_set EXTI1_IRQHandler,Default_Handler
+
+ .weak EXTI2_IRQHandler
+ .thumb_set EXTI2_IRQHandler,Default_Handler
+
+ .weak EXTI3_IRQHandler
+ .thumb_set EXTI3_IRQHandler,Default_Handler
+
+ .weak EXTI4_IRQHandler
+ .thumb_set EXTI4_IRQHandler,Default_Handler
+
+ .weak DMA1_Channel1_IRQHandler
+ .thumb_set DMA1_Channel1_IRQHandler,Default_Handler
+
+ .weak DMA1_Channel2_IRQHandler
+ .thumb_set DMA1_Channel2_IRQHandler,Default_Handler
+
+ .weak DMA1_Channel3_IRQHandler
+ .thumb_set DMA1_Channel3_IRQHandler,Default_Handler
+
+ .weak DMA1_Channel4_IRQHandler
+ .thumb_set DMA1_Channel4_IRQHandler,Default_Handler
+
+ .weak DMA1_Channel5_IRQHandler
+ .thumb_set DMA1_Channel5_IRQHandler,Default_Handler
+
+ .weak DMA1_Channel6_IRQHandler
+ .thumb_set DMA1_Channel6_IRQHandler,Default_Handler
+
+ .weak DMA1_Channel7_IRQHandler
+ .thumb_set DMA1_Channel7_IRQHandler,Default_Handler
+
+ .weak ADC_IRQHandler
+ .thumb_set ADC_IRQHandler,Default_Handler
+
+ .weak DAC_IRQHandler
+ .thumb_set DAC_IRQHandler,Default_Handler
+
+ .weak COMP_IRQHandler
+ .thumb_set COMP_IRQHandler,Default_Handler
+
+ .weak EXTI9_5_IRQHandler
+ .thumb_set EXTI9_5_IRQHandler,Default_Handler
+
+ .weak TIM1_BRK_IRQHandler
+ .thumb_set TIM1_BRK_IRQHandler,Default_Handler
+
+ .weak TIM1_UP_IRQHandler
+ .thumb_set TIM1_UP_IRQHandler,Default_Handler
+
+ .weak TIM1_TRG_COM_IRQHandler
+ .thumb_set TIM1_TRG_COM_IRQHandler,Default_Handler
+
+ .weak TIM1_CC_IRQHandler
+ .thumb_set TIM1_CC_IRQHandler,Default_Handler
+
+ .weak TIM2_IRQHandler
+ .thumb_set TIM2_IRQHandler,Default_Handler
+
+ .weak TIM16_IRQHandler
+ .thumb_set TIM16_IRQHandler,Default_Handler
+
+ .weak TIM17_IRQHandler
+ .thumb_set TIM17_IRQHandler,Default_Handler
+
+ .weak I2C1_EV_IRQHandler
+ .thumb_set I2C1_EV_IRQHandler,Default_Handler
+
+ .weak I2C1_ER_IRQHandler
+ .thumb_set I2C1_ER_IRQHandler,Default_Handler
+
+ .weak I2C2_EV_IRQHandler
+ .thumb_set I2C2_EV_IRQHandler,Default_Handler
+
+ .weak I2C2_ER_IRQHandler
+ .thumb_set I2C2_ER_IRQHandler,Default_Handler
+
+ .weak SPI1_IRQHandler
+ .thumb_set SPI1_IRQHandler,Default_Handler
+
+ .weak SPI2_IRQHandler
+ .thumb_set SPI2_IRQHandler,Default_Handler
+
+ .weak USART1_IRQHandler
+ .thumb_set USART1_IRQHandler,Default_Handler
+
+ .weak USART2_IRQHandler
+ .thumb_set USART2_IRQHandler,Default_Handler
+
+ .weak LPUART1_IRQHandler
+ .thumb_set LPUART1_IRQHandler,Default_Handler
+
+ .weak LPTIM1_IRQHandler
+ .thumb_set LPTIM1_IRQHandler,Default_Handler
+
+ .weak LPTIM2_IRQHandler
+ .thumb_set LPTIM2_IRQHandler,Default_Handler
+
+ .weak EXTI15_10_IRQHandler
+ .thumb_set EXTI15_10_IRQHandler,Default_Handler
+
+ .weak RTC_Alarm_IRQHandler
+ .thumb_set RTC_Alarm_IRQHandler,Default_Handler
+
+ .weak LPTIM3_IRQHandler
+ .thumb_set LPTIM3_IRQHandler,Default_Handler
+
+ .weak SUBGHZSPI_IRQHandler
+ .thumb_set SUBGHZSPI_IRQHandler,Default_Handler
+
+ .weak HSEM_IRQHandler
+ .thumb_set HSEM_IRQHandler,Default_Handler
+
+ .weak I2C3_EV_IRQHandler
+ .thumb_set I2C3_EV_IRQHandler,Default_Handler
+
+ .weak I2C3_ER_IRQHandler
+ .thumb_set I2C3_ER_IRQHandler,Default_Handler
+
+ .weak SUBGHZ_Radio_IRQHandler
+ .thumb_set SUBGHZ_Radio_IRQHandler,Default_Handler
+
+ .weak AES_IRQHandler
+ .thumb_set AES_IRQHandler,Default_Handler
+
+ .weak RNG_IRQHandler
+ .thumb_set RNG_IRQHandler,Default_Handler
+
+ .weak PKA_IRQHandler
+ .thumb_set PKA_IRQHandler,Default_Handler
+
+ .weak DMA2_Channel1_IRQHandler
+ .thumb_set DMA2_Channel1_IRQHandler,Default_Handler
+
+ .weak DMA2_Channel2_IRQHandler
+ .thumb_set DMA2_Channel2_IRQHandler,Default_Handler
+
+ .weak DMA2_Channel3_IRQHandler
+ .thumb_set DMA2_Channel3_IRQHandler,Default_Handler
+
+ .weak DMA2_Channel4_IRQHandler
+ .thumb_set DMA2_Channel4_IRQHandler,Default_Handler
+
+ .weak DMA2_Channel5_IRQHandler
+ .thumb_set DMA2_Channel5_IRQHandler,Default_Handler
+
+ .weak DMA2_Channel6_IRQHandler
+ .thumb_set DMA2_Channel6_IRQHandler,Default_Handler
+
+ .weak DMA2_Channel7_IRQHandler
+ .thumb_set DMA2_Channel7_IRQHandler,Default_Handler
+
+ .weak DMAMUX1_OVR_IRQHandler
+ .thumb_set DMAMUX1_OVR_IRQHandler,Default_Handler
+
+ .weak SystemInit
+
+/************************ (C) COPYRIGHT STMicroelectonics *****END OF FILE****/
diff --git a/targets/TARGET_STM/TARGET_STM32WL/TARGET_STM32WLE4xC/TOOLCHAIN_GCC_ARM/stm32wle4xc.ld b/targets/TARGET_STM/TARGET_STM32WL/TARGET_STM32WLE4xC/TOOLCHAIN_GCC_ARM/stm32wle4xc.ld
new file mode 100644
index 0000000..5f47993
--- /dev/null
+++ b/targets/TARGET_STM/TARGET_STM32WL/TARGET_STM32WLE4xC/TOOLCHAIN_GCC_ARM/stm32wle4xc.ld
@@ -0,0 +1,203 @@
+/* Linker script to configure memory regions. */
+/*
+ * SPDX-License-Identifier: BSD-3-Clause
+ ******************************************************************************
+ * @attention
+ *
+ * Copyright (c) 2016-2020 STMicroelectronics.
+ * All rights reserved.
+ *
+ * This software component is licensed by ST under BSD 3-Clause license,
+ * the "License"; You may not use this file except in compliance with the
+ * License. You may obtain a copy of the License at:
+ * opensource.org/licenses/BSD-3-Clause
+ *
+ ******************************************************************************
+*/
+
+#include "../cmsis_nvic.h"
+
+
+#if !defined(MBED_APP_START)
+ #define MBED_APP_START MBED_ROM_START
+#endif
+
+#if !defined(MBED_APP_SIZE)
+ #define MBED_APP_SIZE MBED_ROM_SIZE
+#endif
+
+#if !defined(MBED_CONF_TARGET_BOOT_STACK_SIZE)
+ /* This value is normally defined by the tools
+ to 0x1000 for bare metal and 0x400 for RTOS */
+ #define MBED_CONF_TARGET_BOOT_STACK_SIZE 0x400
+#endif
+
+/* Round up VECTORS_SIZE to 8 bytes */
+#define VECTORS_SIZE (((NVIC_NUM_VECTORS * 4) + 7) & 0xFFFFFFF8)
+
+MEMORY
+{
+ FLASH (rx) : ORIGIN = MBED_APP_START, LENGTH = MBED_APP_SIZE
+ RAM (rwx) : ORIGIN = MBED_RAM_START + VECTORS_SIZE, LENGTH = MBED_RAM_SIZE - VECTORS_SIZE
+}
+
+/* Linker script to place sections and symbol values. Should be used together
+ * with other linker script that defines memory regions FLASH and RAM.
+ * It references following symbols, which must be defined in code:
+ * Reset_Handler : Entry of reset handler
+ *
+ * It defines following symbols, which code can use without definition:
+ * __exidx_start
+ * __exidx_end
+ * __etext
+ * __data_start__
+ * __preinit_array_start
+ * __preinit_array_end
+ * __init_array_start
+ * __init_array_end
+ * __fini_array_start
+ * __fini_array_end
+ * __data_end__
+ * __bss_start__
+ * __bss_end__
+ * __end__
+ * end
+ * __HeapLimit
+ * __StackLimit
+ * __StackTop
+ * __stack
+ * _estack
+ */
+ENTRY(Reset_Handler)
+
+SECTIONS
+{
+ .text :
+ {
+ KEEP(*(.isr_vector))
+ *(.text*)
+
+ KEEP(*(.init))
+ KEEP(*(.fini))
+
+ /* .ctors */
+ *crtbegin.o(.ctors)
+ *crtbegin?.o(.ctors)
+ *(EXCLUDE_FILE(*crtend?.o *crtend.o) .ctors)
+ *(SORT(.ctors.*))
+ *(.ctors)
+
+ /* .dtors */
+ *crtbegin.o(.dtors)
+ *crtbegin?.o(.dtors)
+ *(EXCLUDE_FILE(*crtend?.o *crtend.o) .dtors)
+ *(SORT(.dtors.*))
+ *(.dtors)
+
+ *(.rodata*)
+
+ KEEP(*(.eh_frame*))
+ } > FLASH
+
+ .ARM.extab :
+ {
+ *(.ARM.extab* .gnu.linkonce.armextab.*)
+ } > FLASH
+
+ __exidx_start = .;
+ .ARM.exidx :
+ {
+ *(.ARM.exidx* .gnu.linkonce.armexidx.*)
+ } > FLASH
+ __exidx_end = .;
+
+ __etext = .;
+ _sidata = .;
+
+ .data : AT (__etext)
+ {
+ __data_start__ = .;
+ _sdata = .;
+ *(vtable)
+ *(.data*)
+
+ . = ALIGN(8);
+ /* preinit data */
+ PROVIDE_HIDDEN (__preinit_array_start = .);
+ KEEP(*(.preinit_array))
+ PROVIDE_HIDDEN (__preinit_array_end = .);
+
+ . = ALIGN(8);
+ /* init data */
+ PROVIDE_HIDDEN (__init_array_start = .);
+ KEEP(*(SORT(.init_array.*)))
+ KEEP(*(.init_array))
+ PROVIDE_HIDDEN (__init_array_end = .);
+
+ . = ALIGN(8);
+ /* finit data */
+ PROVIDE_HIDDEN (__fini_array_start = .);
+ KEEP(*(SORT(.fini_array.*)))
+ KEEP(*(.fini_array))
+ PROVIDE_HIDDEN (__fini_array_end = .);
+
+ KEEP(*(.jcr*))
+ . = ALIGN(8);
+ /* All data end */
+ __data_end__ = .;
+ _edata = .;
+
+ } > RAM
+
+ /* Uninitialized data section
+ * This region is not initialized by the C/C++ library and can be used to
+ * store state across soft reboots. */
+ .uninitialized (NOLOAD):
+ {
+ . = ALIGN(32);
+ __uninitialized_start = .;
+ *(.uninitialized)
+ KEEP(*(.keep.uninitialized))
+ . = ALIGN(32);
+ __uninitialized_end = .;
+ } > RAM
+
+ .bss :
+ {
+ . = ALIGN(8);
+ __bss_start__ = .;
+ _sbss = .;
+ *(.bss*)
+ *(COMMON)
+ . = ALIGN(8);
+ __bss_end__ = .;
+ _ebss = .;
+ } > RAM
+
+ .heap (COPY):
+ {
+ __end__ = .;
+ PROVIDE(end = .);
+ *(.heap*)
+ . = ORIGIN(RAM) + LENGTH(RAM) - MBED_CONF_TARGET_BOOT_STACK_SIZE;
+ __HeapLimit = .;
+ } > RAM
+
+ /* .stack_dummy section doesn't contains any symbols. It is only
+ * used for linker to calculate size of stack sections, and assign
+ * values to stack symbols later */
+ .stack_dummy (COPY):
+ {
+ *(.stack*)
+ } > RAM
+
+ /* Set stack top to end of RAM, and stack limit move down by
+ * size of stack_dummy section */
+ __StackTop = ORIGIN(RAM) + LENGTH(RAM);
+ _estack = __StackTop;
+ __StackLimit = __StackTop - MBED_CONF_TARGET_BOOT_STACK_SIZE;
+ PROVIDE(__stack = __StackTop);
+
+ /* Check if data + heap + stack exceeds RAM limit */
+ ASSERT(__StackLimit >= __HeapLimit, "region RAM overflowed with stack")
+}
diff --git a/targets/TARGET_STM/TARGET_STM32WL/TARGET_STM32WLE4xC/TOOLCHAIN_IAR/startup_stm32wle4xx.S b/targets/TARGET_STM/TARGET_STM32WL/TARGET_STM32WLE4xC/TOOLCHAIN_IAR/startup_stm32wle4xx.S
new file mode 100644
index 0000000..0072684
--- /dev/null
+++ b/targets/TARGET_STM/TARGET_STM32WL/TARGET_STM32WLE4xC/TOOLCHAIN_IAR/startup_stm32wle4xx.S
@@ -0,0 +1,494 @@
+;********************************************************************************
+;* File Name : startup_stm32wle4xx.s
+;* Author : MCD Application Team
+;* Description : M4 core vector table of the STM32WLxxxx devices for the
+;* IAR (EWARM) toolchain.
+;*
+;* This module performs:
+;* - Set the initial SP
+;* - Set the initial PC == _iar_program_start,
+;* - Set the vector table entries with the exceptions ISR
+;* address.
+;* - Branches to main in the C library (which eventually
+;* calls main()).
+;* After Reset the Cortex-M4 processor is in Thread mode,
+;* priority is Privileged, and the Stack is set to Main.
+;********************************************************************************
+;*
+;* Copyright (c) 2020 STMicroelectronics. All rights reserved.
+;*
+;* This software component is licensed by ST under Apache License, Version 2.0,
+;* the "License"; You may not use this file except in compliance with the
+;* License. You may obtain a copy of the License at:
+;* opensource.org/licenses/Apache-2.0
+;
+;*******************************************************************************
+;
+;
+; The modules in this file are included in the libraries, and may be replaced
+; by any user-defined modules that define the PUBLIC symbol _program_start or
+; a user defined start symbol.
+; To override the cstartup defined in the library, simply add your modified
+; version to the workbench project.
+;
+; The vector table is normally located at address 0.
+; When debugging in RAM, it can be located in RAM, aligned to at least 2^6.
+; The name "__vector_table" has special meaning for C-SPY:
+; it is where the SP start value is found, and the NVIC vector
+; table register (VTOR) is initialized to this address if != 0.
+;
+; Cortex-M version
+;
+
+ MODULE ?cstartup
+
+ ;; Forward declaration of sections.
+ SECTION CSTACK:DATA:NOROOT(3)
+
+ SECTION .intvec:CODE:NOROOT(2)
+
+ EXTERN __iar_program_start
+ EXTERN SystemInit
+ PUBLIC __vector_table
+
+ DATA
+__vector_table
+ DCD sfe(CSTACK)
+ DCD Reset_Handler ; Reset Handler
+
+ DCD NMI_Handler ; NMI Handler
+ DCD HardFault_Handler ; Hard Fault Handler
+ DCD MemManage_Handler ; MPU Fault Handler
+ DCD BusFault_Handler ; Bus Fault Handler
+ DCD UsageFault_Handler ; Usage Fault Handler
+ DCD 0 ; Reserved
+ DCD 0 ; Reserved
+ DCD 0 ; Reserved
+ DCD 0 ; Reserved
+ DCD SVC_Handler ; SVCall Handler
+ DCD DebugMon_Handler ; Debug Monitor Handler
+ DCD 0 ; Reserved
+ DCD PendSV_Handler ; PendSV Handler
+ DCD SysTick_Handler ; SysTick Handler
+
+ ; External Interrupts
+ DCD WWDG_IRQHandler ; Window WatchDog
+ DCD PVD_PVM_IRQHandler ; PVD and PVM Interrupt
+ DCD TAMP_STAMP_LSECSS_SSRU_IRQHandler ; RTC Tamper, RTC TimeStamp, LSECSS and RTC SSRU Interrupts
+ DCD RTC_WKUP_IRQHandler ; RTC Wakeup Interrupt
+ DCD FLASH_IRQHandler ; FLASH global Interrupt
+ DCD RCC_IRQHandler ; RCC Interrupt
+ DCD EXTI0_IRQHandler ; EXTI Line 0 Interrupt
+ DCD EXTI1_IRQHandler ; EXTI Line 1 Interrupt
+ DCD EXTI2_IRQHandler ; EXTI Line 2 Interrupt
+ DCD EXTI3_IRQHandler ; EXTI Line 3 Interrupt
+ DCD EXTI4_IRQHandler ; EXTI Line 4 Interrupt
+ DCD DMA1_Channel1_IRQHandler ; DMA1 Channel 1 Interrupt
+ DCD DMA1_Channel2_IRQHandler ; DMA1 Channel 2 Interrupt
+ DCD DMA1_Channel3_IRQHandler ; DMA1 Channel 3 Interrupt
+ DCD DMA1_Channel4_IRQHandler ; DMA1 Channel 4 Interrupt
+ DCD DMA1_Channel5_IRQHandler ; DMA1 Channel 5 Interrupt
+ DCD DMA1_Channel6_IRQHandler ; DMA1 Channel 6 Interrupt
+ DCD DMA1_Channel7_IRQHandler ; DMA1 Channel 7 Interrupt
+ DCD ADC_IRQHandler ; ADC Interrupt
+ DCD DAC_IRQHandler ; DAC Interrupt
+ DCD 0 ; Reserved
+ DCD COMP_IRQHandler ; COMP1 and COMP2 Interrupts
+ DCD EXTI9_5_IRQHandler ; EXTI Lines [9:5] Interrupt
+ DCD TIM1_BRK_IRQHandler ; TIM1 Break Interrupt
+ DCD TIM1_UP_IRQHandler ; TIM1 Update Interrupt
+ DCD TIM1_TRG_COM_IRQHandler ; TIM1 Trigger and Communication Interrupts
+ DCD TIM1_CC_IRQHandler ; TIM1 Capture Compare Interrupt
+ DCD TIM2_IRQHandler ; TIM2 Global Interrupt
+ DCD TIM16_IRQHandler ; TIM16 Global Interrupt
+ DCD TIM17_IRQHandler ; TIM17 Global Interrupt
+ DCD I2C1_EV_IRQHandler ; I2C1 Event Interrupt
+ DCD I2C1_ER_IRQHandler ; I2C1 Error Interrupt
+ DCD I2C2_EV_IRQHandler ; I2C2 Event Interrupt
+ DCD I2C2_ER_IRQHandler ; I2C2 Error Interrupt
+ DCD SPI1_IRQHandler ; SPI1 Interrupt
+ DCD SPI2_IRQHandler ; SPI2 Interrupt
+ DCD USART1_IRQHandler ; USART1 Interrupt
+ DCD USART2_IRQHandler ; USART2 Interrupt
+ DCD LPUART1_IRQHandler ; LPUART1 Interrupt
+ DCD LPTIM1_IRQHandler ; LPTIM1 Global Interrupt
+ DCD LPTIM2_IRQHandler ; LPTIM2 Global Interrupt
+ DCD EXTI15_10_IRQHandler ; EXTI Lines [15:10] Interrupt
+ DCD RTC_Alarm_IRQHandler ; RTC Alarms (A and B) Interrupt
+ DCD LPTIM3_IRQHandler ; LPTIM3 Global Interrupt
+ DCD SUBGHZSPI_IRQHandler ; SUBGHZSPI Interrupt
+ DCD 0 ; Reserved
+ DCD 0 ; Reserved
+ DCD HSEM_IRQHandler ; HSEM0 Interrupt
+ DCD I2C3_EV_IRQHandler ; I2C3 Event Interrupt
+ DCD I2C3_ER_IRQHandler ; I2C3 Error Interrupt
+ DCD SUBGHZ_Radio_IRQHandler ; SUBGHZ Radio Interrupt
+ DCD AES_IRQHandler ; AES Interrupt
+ DCD RNG_IRQHandler ; RNG1 Interrupt
+ DCD PKA_IRQHandler ; PKA Interrupt
+ DCD DMA2_Channel1_IRQHandler ; DMA2 Channel 1 Interrupt
+ DCD DMA2_Channel2_IRQHandler ; DMA2 Channel 2 Interrupt
+ DCD DMA2_Channel3_IRQHandler ; DMA2 Channel 3 Interrupt
+ DCD DMA2_Channel4_IRQHandler ; DMA2 Channel 4 Interrupt
+ DCD DMA2_Channel5_IRQHandler ; DMA2 Channel 5 Interrupt
+ DCD DMA2_Channel6_IRQHandler ; DMA2 Channel 6 Interrupt
+ DCD DMA2_Channel7_IRQHandler ; DMA2 Channel 7 Interrupt
+ DCD DMAMUX1_OVR_IRQHandler ; DMAMUX overrun Interrupt
+
+;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;
+;;
+;; Default interrupt handlers.
+;;
+ THUMB
+
+ PUBWEAK Reset_Handler
+ SECTION .text:CODE:NOROOT:REORDER(2)
+Reset_Handler
+ LDR R0, =SystemInit
+ BLX R0
+ LDR R0, =__iar_program_start
+ BX R0
+
+ PUBWEAK NMI_Handler
+ SECTION .text:CODE:NOROOT:REORDER(1)
+NMI_Handler
+ B NMI_Handler
+
+ PUBWEAK HardFault_Handler
+ SECTION .text:CODE:NOROOT:REORDER(1)
+HardFault_Handler
+ B HardFault_Handler
+
+ PUBWEAK MemManage_Handler
+ SECTION .text:CODE:NOROOT:REORDER(1)
+MemManage_Handler
+ B MemManage_Handler
+
+ PUBWEAK BusFault_Handler
+ SECTION .text:CODE:NOROOT:REORDER(1)
+BusFault_Handler
+ B BusFault_Handler
+
+ PUBWEAK UsageFault_Handler
+ SECTION .text:CODE:NOROOT:REORDER(1)
+UsageFault_Handler
+ B UsageFault_Handler
+
+ PUBWEAK SVC_Handler
+ SECTION .text:CODE:NOROOT:REORDER(1)
+SVC_Handler
+ B SVC_Handler
+
+ PUBWEAK DebugMon_Handler
+ SECTION .text:CODE:NOROOT:REORDER(1)
+DebugMon_Handler
+ B DebugMon_Handler
+
+ PUBWEAK PendSV_Handler
+ SECTION .text:CODE:NOROOT:REORDER(1)
+PendSV_Handler
+ B PendSV_Handler
+
+ PUBWEAK SysTick_Handler
+ SECTION .text:CODE:NOROOT:REORDER(1)
+SysTick_Handler
+ B SysTick_Handler
+
+ PUBWEAK WWDG_IRQHandler
+ SECTION .text:CODE:NOROOT:REORDER(1)
+WWDG_IRQHandler
+ B WWDG_IRQHandler
+
+ PUBWEAK PVD_PVM_IRQHandler
+ SECTION .text:CODE:NOROOT:REORDER(1)
+PVD_PVM_IRQHandler
+ B PVD_PVM_IRQHandler
+
+ PUBWEAK TAMP_STAMP_LSECSS_SSRU_IRQHandler
+ SECTION .text:CODE:NOROOT:REORDER(1)
+TAMP_STAMP_LSECSS_SSRU_IRQHandler
+ B TAMP_STAMP_LSECSS_SSRU_IRQHandler
+
+ PUBWEAK RTC_WKUP_IRQHandler
+ SECTION .text:CODE:NOROOT:REORDER(1)
+RTC_WKUP_IRQHandler
+ B RTC_WKUP_IRQHandler
+
+ PUBWEAK FLASH_IRQHandler
+ SECTION .text:CODE:NOROOT:REORDER(1)
+FLASH_IRQHandler
+ B FLASH_IRQHandler
+
+ PUBWEAK RCC_IRQHandler
+ SECTION .text:CODE:NOROOT:REORDER(1)
+RCC_IRQHandler
+ B RCC_IRQHandler
+
+ PUBWEAK EXTI0_IRQHandler
+ SECTION .text:CODE:NOROOT:REORDER(1)
+EXTI0_IRQHandler
+ B EXTI0_IRQHandler
+
+ PUBWEAK EXTI1_IRQHandler
+ SECTION .text:CODE:NOROOT:REORDER(1)
+EXTI1_IRQHandler
+ B EXTI1_IRQHandler
+
+ PUBWEAK EXTI2_IRQHandler
+ SECTION .text:CODE:NOROOT:REORDER(1)
+EXTI2_IRQHandler
+ B EXTI2_IRQHandler
+
+ PUBWEAK EXTI3_IRQHandler
+ SECTION .text:CODE:NOROOT:REORDER(1)
+EXTI3_IRQHandler
+ B EXTI3_IRQHandler
+
+ PUBWEAK EXTI4_IRQHandler
+ SECTION .text:CODE:NOROOT:REORDER(1)
+EXTI4_IRQHandler
+ B EXTI4_IRQHandler
+
+ PUBWEAK DMA1_Channel1_IRQHandler
+ SECTION .text:CODE:NOROOT:REORDER(1)
+DMA1_Channel1_IRQHandler
+ B DMA1_Channel1_IRQHandler
+
+ PUBWEAK DMA1_Channel2_IRQHandler
+ SECTION .text:CODE:NOROOT:REORDER(1)
+DMA1_Channel2_IRQHandler
+ B DMA1_Channel2_IRQHandler
+
+ PUBWEAK DMA1_Channel3_IRQHandler
+ SECTION .text:CODE:NOROOT:REORDER(1)
+DMA1_Channel3_IRQHandler
+ B DMA1_Channel3_IRQHandler
+
+ PUBWEAK DMA1_Channel4_IRQHandler
+ SECTION .text:CODE:NOROOT:REORDER(1)
+DMA1_Channel4_IRQHandler
+ B DMA1_Channel4_IRQHandler
+
+ PUBWEAK DMA1_Channel5_IRQHandler
+ SECTION .text:CODE:NOROOT:REORDER(1)
+DMA1_Channel5_IRQHandler
+ B DMA1_Channel5_IRQHandler
+
+ PUBWEAK DMA1_Channel6_IRQHandler
+ SECTION .text:CODE:NOROOT:REORDER(1)
+DMA1_Channel6_IRQHandler
+ B DMA1_Channel6_IRQHandler
+
+ PUBWEAK DMA1_Channel7_IRQHandler
+ SECTION .text:CODE:NOROOT:REORDER(1)
+DMA1_Channel7_IRQHandler
+ B DMA1_Channel7_IRQHandler
+
+ PUBWEAK ADC_IRQHandler
+ SECTION .text:CODE:NOROOT:REORDER(1)
+ADC_IRQHandler
+ B ADC_IRQHandler
+
+ PUBWEAK DAC_IRQHandler
+ SECTION .text:CODE:NOROOT:REORDER(1)
+DAC_IRQHandler
+ B DAC_IRQHandler
+
+ PUBWEAK COMP_IRQHandler
+ SECTION .text:CODE:NOROOT:REORDER(1)
+COMP_IRQHandler
+ B COMP_IRQHandler
+
+ PUBWEAK EXTI9_5_IRQHandler
+ SECTION .text:CODE:NOROOT:REORDER(1)
+EXTI9_5_IRQHandler
+ B EXTI9_5_IRQHandler
+
+ PUBWEAK TIM1_BRK_IRQHandler
+ SECTION .text:CODE:NOROOT:REORDER(1)
+TIM1_BRK_IRQHandler
+ B TIM1_BRK_IRQHandler
+
+ PUBWEAK TIM1_UP_IRQHandler
+ SECTION .text:CODE:NOROOT:REORDER(1)
+TIM1_UP_IRQHandler
+ B TIM1_UP_IRQHandler
+
+ PUBWEAK TIM1_TRG_COM_IRQHandler
+ SECTION .text:CODE:NOROOT:REORDER(1)
+TIM1_TRG_COM_IRQHandler
+ B TIM1_TRG_COM_IRQHandler
+
+ PUBWEAK TIM1_CC_IRQHandler
+ SECTION .text:CODE:NOROOT:REORDER(1)
+TIM1_CC_IRQHandler
+ B TIM1_CC_IRQHandler
+
+ PUBWEAK TIM2_IRQHandler
+ SECTION .text:CODE:NOROOT:REORDER(1)
+TIM2_IRQHandler
+ B TIM2_IRQHandler
+
+ PUBWEAK TIM16_IRQHandler
+ SECTION .text:CODE:NOROOT:REORDER(1)
+TIM16_IRQHandler
+ B TIM16_IRQHandler
+
+ PUBWEAK TIM17_IRQHandler
+ SECTION .text:CODE:NOROOT:REORDER(1)
+TIM17_IRQHandler
+ B TIM17_IRQHandler
+
+ PUBWEAK I2C1_EV_IRQHandler
+ SECTION .text:CODE:NOROOT:REORDER(1)
+I2C1_EV_IRQHandler
+ B I2C1_EV_IRQHandler
+
+ PUBWEAK I2C1_ER_IRQHandler
+ SECTION .text:CODE:NOROOT:REORDER(1)
+I2C1_ER_IRQHandler
+ B I2C1_ER_IRQHandler
+
+ PUBWEAK I2C2_EV_IRQHandler
+ SECTION .text:CODE:NOROOT:REORDER(1)
+I2C2_EV_IRQHandler
+ B I2C2_EV_IRQHandler
+
+ PUBWEAK I2C2_ER_IRQHandler
+ SECTION .text:CODE:NOROOT:REORDER(1)
+I2C2_ER_IRQHandler
+ B I2C2_ER_IRQHandler
+
+ PUBWEAK SPI1_IRQHandler
+ SECTION .text:CODE:NOROOT:REORDER(1)
+SPI1_IRQHandler
+ B SPI1_IRQHandler
+
+ PUBWEAK SPI2_IRQHandler
+ SECTION .text:CODE:NOROOT:REORDER(1)
+SPI2_IRQHandler
+ B SPI2_IRQHandler
+
+ PUBWEAK USART1_IRQHandler
+ SECTION .text:CODE:NOROOT:REORDER(1)
+USART1_IRQHandler
+ B USART1_IRQHandler
+
+ PUBWEAK USART2_IRQHandler
+ SECTION .text:CODE:NOROOT:REORDER(1)
+USART2_IRQHandler
+ B USART2_IRQHandler
+
+ PUBWEAK LPUART1_IRQHandler
+ SECTION .text:CODE:NOROOT:REORDER(1)
+LPUART1_IRQHandler
+ B LPUART1_IRQHandler
+
+ PUBWEAK LPTIM1_IRQHandler
+ SECTION .text:CODE:NOROOT:REORDER(1)
+LPTIM1_IRQHandler
+ B LPTIM1_IRQHandler
+
+ PUBWEAK LPTIM2_IRQHandler
+ SECTION .text:CODE:NOROOT:REORDER(1)
+LPTIM2_IRQHandler
+ B LPTIM2_IRQHandler
+
+ PUBWEAK EXTI15_10_IRQHandler
+ SECTION .text:CODE:NOROOT:REORDER(1)
+EXTI15_10_IRQHandler
+ B EXTI15_10_IRQHandler
+
+ PUBWEAK RTC_Alarm_IRQHandler
+ SECTION .text:CODE:NOROOT:REORDER(1)
+RTC_Alarm_IRQHandler
+ B RTC_Alarm_IRQHandler
+
+ PUBWEAK LPTIM3_IRQHandler
+ SECTION .text:CODE:NOROOT:REORDER(1)
+LPTIM3_IRQHandler
+ B LPTIM3_IRQHandler
+
+ PUBWEAK SUBGHZSPI_IRQHandler
+ SECTION .text:CODE:NOROOT:REORDER(1)
+SUBGHZSPI_IRQHandler
+ B SUBGHZSPI_IRQHandler
+
+ PUBWEAK HSEM_IRQHandler
+ SECTION .text:CODE:NOROOT:REORDER(1)
+HSEM_IRQHandler
+ B HSEM_IRQHandler
+
+ PUBWEAK I2C3_EV_IRQHandler
+ SECTION .text:CODE:NOROOT:REORDER(1)
+I2C3_EV_IRQHandler
+ B I2C3_EV_IRQHandler
+
+ PUBWEAK I2C3_ER_IRQHandler
+ SECTION .text:CODE:NOROOT:REORDER(1)
+I2C3_ER_IRQHandler
+ B I2C3_ER_IRQHandler
+
+ PUBWEAK SUBGHZ_Radio_IRQHandler
+ SECTION .text:CODE:NOROOT:REORDER(1)
+SUBGHZ_Radio_IRQHandler
+ B SUBGHZ_Radio_IRQHandler
+
+ PUBWEAK AES_IRQHandler
+ SECTION .text:CODE:NOROOT:REORDER(1)
+AES_IRQHandler
+ B AES_IRQHandler
+
+ PUBWEAK RNG_IRQHandler
+ SECTION .text:CODE:NOROOT:REORDER(1)
+RNG_IRQHandler
+ B RNG_IRQHandler
+
+ PUBWEAK PKA_IRQHandler
+ SECTION .text:CODE:NOROOT:REORDER(1)
+PKA_IRQHandler
+ B PKA_IRQHandler
+
+ PUBWEAK DMA2_Channel1_IRQHandler
+ SECTION .text:CODE:NOROOT:REORDER(1)
+DMA2_Channel1_IRQHandler
+ B DMA2_Channel1_IRQHandler
+
+ PUBWEAK DMA2_Channel2_IRQHandler
+ SECTION .text:CODE:NOROOT:REORDER(1)
+DMA2_Channel2_IRQHandler
+ B DMA2_Channel2_IRQHandler
+
+ PUBWEAK DMA2_Channel3_IRQHandler
+ SECTION .text:CODE:NOROOT:REORDER(1)
+DMA2_Channel3_IRQHandler
+ B DMA2_Channel3_IRQHandler
+
+ PUBWEAK DMA2_Channel4_IRQHandler
+ SECTION .text:CODE:NOROOT:REORDER(1)
+DMA2_Channel4_IRQHandler
+ B DMA2_Channel4_IRQHandler
+
+ PUBWEAK DMA2_Channel5_IRQHandler
+ SECTION .text:CODE:NOROOT:REORDER(1)
+DMA2_Channel5_IRQHandler
+ B DMA2_Channel5_IRQHandler
+
+ PUBWEAK DMA2_Channel6_IRQHandler
+ SECTION .text:CODE:NOROOT:REORDER(1)
+DMA2_Channel6_IRQHandler
+ B DMA2_Channel6_IRQHandler
+
+ PUBWEAK DMA2_Channel7_IRQHandler
+ SECTION .text:CODE:NOROOT:REORDER(1)
+DMA2_Channel7_IRQHandler
+ B DMA2_Channel7_IRQHandler
+
+ PUBWEAK DMAMUX1_OVR_IRQHandler
+ SECTION .text:CODE:NOROOT:REORDER(1)
+DMAMUX1_OVR_IRQHandler
+ B DMAMUX1_OVR_IRQHandler
+
+ END
+
+;************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE*****
diff --git a/targets/TARGET_STM/TARGET_STM32WL/TARGET_STM32WLE4xC/TOOLCHAIN_IAR/stm32wle4xc.icf b/targets/TARGET_STM/TARGET_STM32WL/TARGET_STM32WLE4xC/TOOLCHAIN_IAR/stm32wle4xc.icf
new file mode 100644
index 0000000..7fb4af2
--- /dev/null
+++ b/targets/TARGET_STM/TARGET_STM32WL/TARGET_STM32WLE4xC/TOOLCHAIN_IAR/stm32wle4xc.icf
@@ -0,0 +1,59 @@
+/* Linker script to configure memory regions.
+ *
+ * SPDX-License-Identifier: BSD-3-Clause
+ ******************************************************************************
+ * @attention
+ *
+ * Copyright (c) 2016-2020 STMicroelectronics.
+ * All rights reserved.
+ *
+ * This software component is licensed by ST under BSD 3-Clause license,
+ * the "License"; You may not use this file except in compliance with the
+ * License. You may obtain a copy of the License at:
+ * opensource.org/licenses/BSD-3-Clause
+ *
+ ******************************************************************************
+*/
+/* Device specific values */
+
+/* Tools provide -DMBED_ROM_START=xxx -DMBED_ROM_SIZE=xxx -DMBED_RAM_START=xxx -DMBED_RAM_SIZE=xxx */
+
+define symbol VECTORS = 78; /* This value must match NVIC_NUM_VECTORS in cmsis_nvic.h */
+define symbol HEAP_SIZE = 0x1000;
+
+/* Common - Do not change */
+
+if (!isdefinedsymbol(MBED_APP_START)) {
+ define symbol MBED_APP_START = MBED_ROM_START;
+}
+
+if (!isdefinedsymbol(MBED_APP_SIZE)) {
+ define symbol MBED_APP_SIZE = MBED_ROM_SIZE;
+}
+
+if (!isdefinedsymbol(MBED_CONF_TARGET_BOOT_STACK_SIZE)) {
+ /* This value is normally defined by the tools
+ to 0x1000 for bare metal and 0x400 for RTOS */
+ define symbol MBED_CONF_TARGET_BOOT_STACK_SIZE = 0x400;
+}
+
+/* Round up VECTORS_SIZE to 8 bytes */
+define symbol VECTORS_SIZE = ((VECTORS * 4) + 7) & ~7;
+define symbol RAM_REGION_START = MBED_RAM_START + VECTORS_SIZE;
+define symbol RAM_REGION_SIZE = MBED_RAM_SIZE - VECTORS_SIZE;
+
+define memory mem with size = 4G;
+define region ROM_region = mem:[from MBED_APP_START size MBED_APP_SIZE];
+define region RAM_region = mem:[from RAM_REGION_START size RAM_REGION_SIZE];
+
+define block CSTACK with alignment = 8, size = MBED_CONF_TARGET_BOOT_STACK_SIZE { };
+define block HEAP with alignment = 8, size = HEAP_SIZE { };
+
+initialize by copy { readwrite };
+do not initialize { section .noinit };
+
+place at address mem: MBED_APP_START { readonly section .intvec };
+
+place in ROM_region { readonly };
+place in RAM_region { readwrite,
+ block CSTACK, block HEAP };
diff --git a/targets/TARGET_STM/TARGET_STM32WL/TARGET_STM32WLE4xC/cmsis_nvic.h b/targets/TARGET_STM/TARGET_STM32WL/TARGET_STM32WLE4xC/cmsis_nvic.h
new file mode 100644
index 0000000..a18342e
--- /dev/null
+++ b/targets/TARGET_STM/TARGET_STM32WL/TARGET_STM32WLE4xC/cmsis_nvic.h
@@ -0,0 +1,39 @@
+/* mbed Microcontroller Library
+ * SPDX-License-Identifier: BSD-3-Clause
+ ******************************************************************************
+ * @attention
+ *
+ * © Copyright (c) 2016-2020 STMicroelectronics.
+ * All rights reserved.
+ *
+ * This software component is licensed by ST under BSD 3-Clause license,
+ * the "License"; You may not use this file except in compliance with the
+ * License. You may obtain a copy of the License at:
+ * opensource.org/licenses/BSD-3-Clause
+ *
+ ******************************************************************************
+*/
+
+#ifndef MBED_CMSIS_NVIC_H
+#define MBED_CMSIS_NVIC_H
+
+#if !defined(MBED_ROM_START)
+#define MBED_ROM_START 0x8000000
+#endif
+
+#if !defined(MBED_ROM_SIZE)
+#define MBED_ROM_SIZE 0x0 // 0 B
+#endif
+
+#if !defined(MBED_RAM_START)
+#define MBED_RAM_START 0x20000000
+#endif
+
+#if !defined(MBED_RAM_SIZE)
+#define MBED_RAM_SIZE 0x0 // 0 B
+#endif
+
+#define NVIC_NUM_VECTORS 78
+#define NVIC_RAM_VECTOR_ADDRESS MBED_RAM_START
+
+#endif
diff --git a/targets/TARGET_STM/TARGET_STM32WL/TARGET_STM32WLE5x8/TOOLCHAIN_ARM/startup_stm32wle5xx.S b/targets/TARGET_STM/TARGET_STM32WL/TARGET_STM32WLE5x8/TOOLCHAIN_ARM/startup_stm32wle5xx.S
new file mode 100644
index 0000000..29f645e
--- /dev/null
+++ b/targets/TARGET_STM/TARGET_STM32WL/TARGET_STM32WLE5x8/TOOLCHAIN_ARM/startup_stm32wle5xx.S
@@ -0,0 +1,314 @@
+;******************************************************************************
+;* File Name : startup_stm32wle5xx.s
+;* Author : MCD Application Team
+;* Description : STM32WLE5xx devices vector table for MDK-ARM toolchain.
+;* This module performs:
+;* - Set the initial SP
+;* - Set the initial PC == Reset_Handler
+;* - Set the vector table entries with the exceptions ISR address
+;* - Branches to __main in the C library (which eventually
+;* calls main()).
+;* After Reset the CortexM4 processor is in Thread mode,
+;* priority is Privileged, and the Stack is set to Main.
+;* <<< Use Configuration Wizard in Context Menu >>>
+;******************************************************************************
+;* @attention
+;*
+;* Copyright (c) 2020 STMicroelectronics. All rights reserved.
+;*
+;* This software component is licensed by ST under Apache License, Version 2.0,
+;* the "License"; You may not use this file except in compliance with the
+;* License. You may obtain a copy of the License at:
+;* opensource.org/licenses/Apache-2.0
+;*
+;******************************************************************************
+
+ PRESERVE8
+ THUMB
+
+
+; Vector Table Mapped to Address 0 at Reset
+ AREA RESET, DATA, READONLY
+ EXPORT __Vectors
+ EXPORT __Vectors_End
+ EXPORT __Vectors_Size
+
+ IMPORT |Image$$ARM_LIB_STACK$$ZI$$Limit|
+__Vectors DCD |Image$$ARM_LIB_STACK$$ZI$$Limit| ; Top of Stack
+ DCD Reset_Handler ; Reset Handler
+ DCD NMI_Handler ; NMI Handler
+ DCD HardFault_Handler ; Hard Fault Handler
+ DCD MemManage_Handler ; MPU Fault Handler
+ DCD BusFault_Handler ; Bus Fault Handler
+ DCD UsageFault_Handler ; Usage Fault Handler
+ DCD 0 ; Reserved
+ DCD 0 ; Reserved
+ DCD 0 ; Reserved
+ DCD 0 ; Reserved
+ DCD SVC_Handler ; SVCall Handler
+ DCD DebugMon_Handler ; Debug Monitor Handler
+ DCD 0 ; Reserved
+ DCD PendSV_Handler ; PendSV Handler
+ DCD SysTick_Handler ; SysTick Handler
+
+ ; External Interrupts
+ DCD WWDG_IRQHandler ; Window WatchDog
+ DCD PVD_PVM_IRQHandler ; PVD and PVM detector
+ DCD TAMP_STAMP_LSECSS_SSRU_IRQHandler ; RTC Tamper, RTC TimeStamp, LSECSS and RTC SSR Underflow Interrupts
+ DCD RTC_WKUP_IRQHandler ; RTC Wakeup Interrupt
+ DCD FLASH_IRQHandler ; FLASH global Interrupt
+ DCD RCC_IRQHandler ; RCC Interrupt
+ DCD EXTI0_IRQHandler ; EXTI Line 0 Interrupt
+ DCD EXTI1_IRQHandler ; EXTI Line 1 Interrupt
+ DCD EXTI2_IRQHandler ; EXTI Line 2 Interrupt
+ DCD EXTI3_IRQHandler ; EXTI Line 3 Interrup
+ DCD EXTI4_IRQHandler ; EXTI Line 4 Interrupt
+ DCD DMA1_Channel1_IRQHandler ; DMA1 Channel 1 Interrupt
+ DCD DMA1_Channel2_IRQHandler ; DMA1 Channel 2 Interrupt
+ DCD DMA1_Channel3_IRQHandler ; DMA1 Channel 3 Interrupt
+ DCD DMA1_Channel4_IRQHandler ; DMA1 Channel 4 Interrupt
+ DCD DMA1_Channel5_IRQHandler ; DMA1 Channel 5 Interrupt
+ DCD DMA1_Channel6_IRQHandler ; DMA1 Channel 6 Interrupt
+ DCD DMA1_Channel7_IRQHandler ; DMA1 Channel 7 Interrupt
+ DCD ADC_IRQHandler ; ADC Interrupt
+ DCD DAC_IRQHandler ; DAC Interrupt
+ DCD 0 ; Reserved
+ DCD COMP_IRQHandler ; COMP1 and COMP2 Interrupts
+ DCD EXTI9_5_IRQHandler ; EXTI Lines [9:5] Interrupt
+ DCD TIM1_BRK_IRQHandler ; TIM1 Break Interrupt
+ DCD TIM1_UP_IRQHandler ; TIM1 Update Interrupts
+ DCD TIM1_TRG_COM_IRQHandler ; TIM1 Trigger and Communication Interrupts
+ DCD TIM1_CC_IRQHandler ; TIM1 Capture Compare Interrupt
+ DCD TIM2_IRQHandler ; TIM2 Global Interrupt
+ DCD TIM16_IRQHandler ; TIM16 Global Interrupt
+ DCD TIM17_IRQHandler ; TIM17 Global Interrupt
+ DCD I2C1_EV_IRQHandler ; I2C1 Event Interrupt
+ DCD I2C1_ER_IRQHandler ; I2C1 Error Interrupt
+ DCD I2C2_EV_IRQHandler ; I2C2 Event Interrupt
+ DCD I2C2_ER_IRQHandler ; I2C2 Error Interrupt
+ DCD SPI1_IRQHandler ; SPI1 Interrupt
+ DCD SPI2_IRQHandler ; SPI2 Interrupt
+ DCD USART1_IRQHandler ; USART1 Interrupt
+ DCD USART2_IRQHandler ; USART2 Interrupt
+ DCD LPUART1_IRQHandler ; LPUART1 Interrupt
+ DCD LPTIM1_IRQHandler ; LPTIM1 Interrupt
+ DCD LPTIM2_IRQHandler ; LPTIM2 Interrupt
+ DCD EXTI15_10_IRQHandler ; EXTI Lines1[15:10 ]Interrupts
+ DCD RTC_Alarm_IRQHandler ; RTC Alarms (A and B) Interrupt
+ DCD LPTIM3_IRQHandler ; LPTIM3 Interrupt
+ DCD SUBGHZSPI_IRQHandler ; SUBGHZSPI Interrupt
+ DCD 0 ; Reserved
+ DCD 0 ; Reserved
+ DCD HSEM_IRQHandler ; HSEM0 Interrupt
+ DCD I2C3_EV_IRQHandler ; I2C3 Event Interrupt
+ DCD I2C3_ER_IRQHandler ; I2C3 Error Interrupt
+ DCD SUBGHZ_Radio_IRQHandler ; SUBGHZ Radio Interrupt
+ DCD AES_IRQHandler ; AES Interrupt
+ DCD RNG_IRQHandler ; RNG1 Interrupt
+ DCD PKA_IRQHandler ; PKA Interrupt
+ DCD DMA2_Channel1_IRQHandler ; DMA2 Channel 1 Interrupt
+ DCD DMA2_Channel2_IRQHandler ; DMA2 Channel 2 Interrupt
+ DCD DMA2_Channel3_IRQHandler ; DMA2 Channel 3 Interrupt
+ DCD DMA2_Channel4_IRQHandler ; DMA2 Channel 4 Interrupt
+ DCD DMA2_Channel5_IRQHandler ; DMA2 Channel 5 Interrupt
+ DCD DMA2_Channel6_IRQHandler ; DMA2 Channel 6 Interrupt
+ DCD DMA2_Channel7_IRQHandler ; DMA2 Channel 7 Interrupt
+ DCD DMAMUX1_OVR_IRQHandler ; DMAMUX overrun Interrupt
+
+__Vectors_End
+
+__Vectors_Size EQU __Vectors_End - __Vectors
+
+ AREA |.text|, CODE, READONLY
+
+; Reset handler
+Reset_Handler PROC
+ EXPORT Reset_Handler [WEAK]
+ IMPORT SystemInit
+ IMPORT __main
+
+ LDR R0, =SystemInit
+ BLX R0
+ LDR R0, =__main
+ BX R0
+ ENDP
+
+; Dummy Exception Handlers (infinite loops which can be modified)
+
+NMI_Handler PROC
+ EXPORT NMI_Handler [WEAK]
+ B .
+ ENDP
+HardFault_Handler\
+ PROC
+ EXPORT HardFault_Handler [WEAK]
+ B .
+ ENDP
+MemManage_Handler\
+ PROC
+ EXPORT MemManage_Handler [WEAK]
+ B .
+ ENDP
+BusFault_Handler\
+ PROC
+ EXPORT BusFault_Handler [WEAK]
+ B .
+ ENDP
+UsageFault_Handler\
+ PROC
+ EXPORT UsageFault_Handler [WEAK]
+ B .
+ ENDP
+SVC_Handler PROC
+ EXPORT SVC_Handler [WEAK]
+ B .
+ ENDP
+DebugMon_Handler\
+ PROC
+ EXPORT DebugMon_Handler [WEAK]
+ B .
+ ENDP
+PendSV_Handler PROC
+ EXPORT PendSV_Handler [WEAK]
+ B .
+ ENDP
+SysTick_Handler PROC
+ EXPORT SysTick_Handler [WEAK]
+ B .
+ ENDP
+
+Default_Handler PROC
+
+ EXPORT WWDG_IRQHandler [WEAK]
+ EXPORT PVD_PVM_IRQHandler [WEAK]
+ EXPORT TAMP_STAMP_LSECSS_SSRU_IRQHandler [WEAK]
+ EXPORT RTC_WKUP_IRQHandler [WEAK]
+ EXPORT FLASH_IRQHandler [WEAK]
+ EXPORT RCC_IRQHandler [WEAK]
+ EXPORT EXTI0_IRQHandler [WEAK]
+ EXPORT EXTI1_IRQHandler [WEAK]
+ EXPORT EXTI2_IRQHandler [WEAK]
+ EXPORT EXTI3_IRQHandler [WEAK]
+ EXPORT EXTI4_IRQHandler [WEAK]
+ EXPORT DMA1_Channel1_IRQHandler [WEAK]
+ EXPORT DMA1_Channel2_IRQHandler [WEAK]
+ EXPORT DMA1_Channel3_IRQHandler [WEAK]
+ EXPORT DMA1_Channel4_IRQHandler [WEAK]
+ EXPORT DMA1_Channel5_IRQHandler [WEAK]
+ EXPORT DMA1_Channel6_IRQHandler [WEAK]
+ EXPORT DMA1_Channel7_IRQHandler [WEAK]
+ EXPORT ADC_IRQHandler [WEAK]
+ EXPORT DAC_IRQHandler [WEAK]
+ EXPORT COMP_IRQHandler [WEAK]
+ EXPORT EXTI9_5_IRQHandler [WEAK]
+ EXPORT TIM1_BRK_IRQHandler [WEAK]
+ EXPORT TIM1_UP_IRQHandler [WEAK]
+ EXPORT TIM1_TRG_COM_IRQHandler [WEAK]
+ EXPORT TIM1_CC_IRQHandler [WEAK]
+ EXPORT TIM2_IRQHandler [WEAK]
+ EXPORT TIM16_IRQHandler [WEAK]
+ EXPORT TIM17_IRQHandler [WEAK]
+ EXPORT I2C1_EV_IRQHandler [WEAK]
+ EXPORT I2C1_ER_IRQHandler [WEAK]
+ EXPORT I2C2_EV_IRQHandler [WEAK]
+ EXPORT I2C2_ER_IRQHandler [WEAK]
+ EXPORT SPI1_IRQHandler [WEAK]
+ EXPORT SPI2_IRQHandler [WEAK]
+ EXPORT USART1_IRQHandler [WEAK]
+ EXPORT USART2_IRQHandler [WEAK]
+ EXPORT LPUART1_IRQHandler [WEAK]
+ EXPORT LPTIM1_IRQHandler [WEAK]
+ EXPORT LPTIM2_IRQHandler [WEAK]
+ EXPORT EXTI15_10_IRQHandler [WEAK]
+ EXPORT RTC_Alarm_IRQHandler [WEAK]
+ EXPORT LPTIM3_IRQHandler [WEAK]
+ EXPORT SUBGHZSPI_IRQHandler [WEAK]
+ EXPORT HSEM_IRQHandler [WEAK]
+ EXPORT I2C3_EV_IRQHandler [WEAK]
+ EXPORT I2C3_ER_IRQHandler [WEAK]
+ EXPORT SUBGHZ_Radio_IRQHandler [WEAK]
+ EXPORT AES_IRQHandler [WEAK]
+ EXPORT RNG_IRQHandler [WEAK]
+ EXPORT PKA_IRQHandler [WEAK]
+ EXPORT DMA2_Channel1_IRQHandler [WEAK]
+ EXPORT DMA2_Channel2_IRQHandler [WEAK]
+ EXPORT DMA2_Channel3_IRQHandler [WEAK]
+ EXPORT DMA2_Channel4_IRQHandler [WEAK]
+ EXPORT DMA2_Channel5_IRQHandler [WEAK]
+ EXPORT DMA2_Channel6_IRQHandler [WEAK]
+ EXPORT DMA2_Channel7_IRQHandler [WEAK]
+ EXPORT DMAMUX1_OVR_IRQHandler [WEAK]
+
+WWDG_IRQHandler
+PVD_PVM_IRQHandler
+TAMP_STAMP_LSECSS_SSRU_IRQHandler
+RTC_WKUP_IRQHandler
+FLASH_IRQHandler
+RCC_IRQHandler
+EXTI0_IRQHandler
+EXTI1_IRQHandler
+EXTI2_IRQHandler
+EXTI3_IRQHandler
+EXTI4_IRQHandler
+DMA1_Channel1_IRQHandler
+DMA1_Channel2_IRQHandler
+DMA1_Channel3_IRQHandler
+DMA1_Channel4_IRQHandler
+DMA1_Channel5_IRQHandler
+DMA1_Channel6_IRQHandler
+DMA1_Channel7_IRQHandler
+ADC_IRQHandler
+DAC_IRQHandler
+COMP_IRQHandler
+EXTI9_5_IRQHandler
+TIM1_BRK_IRQHandler
+TIM1_UP_IRQHandler
+TIM1_TRG_COM_IRQHandler
+TIM1_CC_IRQHandler
+TIM2_IRQHandler
+TIM16_IRQHandler
+TIM17_IRQHandler
+I2C1_EV_IRQHandler
+I2C1_ER_IRQHandler
+I2C2_EV_IRQHandler
+I2C2_ER_IRQHandler
+SPI1_IRQHandler
+SPI2_IRQHandler
+USART1_IRQHandler
+USART2_IRQHandler
+LPUART1_IRQHandler
+LPTIM1_IRQHandler
+LPTIM2_IRQHandler
+EXTI15_10_IRQHandler
+RTC_Alarm_IRQHandler
+LPTIM3_IRQHandler
+SUBGHZSPI_IRQHandler
+HSEM_IRQHandler
+I2C3_EV_IRQHandler
+I2C3_ER_IRQHandler
+SUBGHZ_Radio_IRQHandler
+AES_IRQHandler
+RNG_IRQHandler
+PKA_IRQHandler
+DMA2_Channel1_IRQHandler
+DMA2_Channel2_IRQHandler
+DMA2_Channel3_IRQHandler
+DMA2_Channel4_IRQHandler
+DMA2_Channel5_IRQHandler
+DMA2_Channel6_IRQHandler
+DMA2_Channel7_IRQHandler
+DMAMUX1_OVR_IRQHandler
+
+ B .
+
+ ENDP
+
+ ALIGN
+
+;*******************************************************************************
+; User Stack and Heap initialization
+;*******************************************************************************
+
+ END
+
+;************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE*****
diff --git a/targets/TARGET_STM/TARGET_STM32WL/TARGET_STM32WLE5x8/TOOLCHAIN_ARM/stm32wle5x8.sct b/targets/TARGET_STM/TARGET_STM32WL/TARGET_STM32WLE5x8/TOOLCHAIN_ARM/stm32wle5x8.sct
new file mode 100644
index 0000000..9258e6a
--- /dev/null
+++ b/targets/TARGET_STM/TARGET_STM32WL/TARGET_STM32WLE5x8/TOOLCHAIN_ARM/stm32wle5x8.sct
@@ -0,0 +1,57 @@
+#! armclang -E --target=arm-arm-none-eabi -x c -mcpu=cortex-M4
+; Scatter-Loading Description File
+;
+; SPDX-License-Identifier: BSD-3-Clause
+;******************************************************************************
+;* @attention
+;*
+;* Copyright (c) 2016-2020 STMicroelectronics.
+;* All rights reserved.
+;*
+;* This software component is licensed by ST under BSD 3-Clause license,
+;* the "License"; You may not use this file except in compliance with the
+;* License. You may obtain a copy of the License at:
+;* opensource.org/licenses/BSD-3-Clause
+;*
+;******************************************************************************
+
+#include "../cmsis_nvic.h"
+
+#if !defined(MBED_APP_START)
+ #define MBED_APP_START MBED_ROM_START
+#endif
+
+#if !defined(MBED_APP_SIZE)
+ #define MBED_APP_SIZE MBED_ROM_SIZE
+#endif
+
+#if !defined(MBED_CONF_TARGET_BOOT_STACK_SIZE)
+/* This value is normally defined by the tools to 0x1000 for bare metal and 0x400 for RTOS */
+#if defined(MBED_BOOT_STACK_SIZE)
+#define MBED_CONF_TARGET_BOOT_STACK_SIZE MBED_BOOT_STACK_SIZE
+#else
+#define MBED_CONF_TARGET_BOOT_STACK_SIZE 0x400
+#endif
+#endif
+
+/* Round up VECTORS_SIZE to 8 bytes */
+#define VECTORS_SIZE (((NVIC_NUM_VECTORS * 4) + 7) AND ~7)
+
+LR_IROM1 MBED_APP_START MBED_APP_SIZE {
+
+ ER_IROM1 MBED_APP_START MBED_APP_SIZE {
+ *.o (RESET, +First)
+ *(InRoot$$Sections)
+ .ANY (+RO)
+ }
+
+ RW_IRAM1 (MBED_RAM_START + VECTORS_SIZE) { ; RW data
+ .ANY (+RW +ZI)
+ }
+
+ ARM_LIB_HEAP AlignExpr(+0, 16) EMPTY (MBED_RAM_START + MBED_RAM_SIZE - MBED_CONF_TARGET_BOOT_STACK_SIZE - AlignExpr(ImageLimit(RW_IRAM1), 16)) { ; Heap growing up
+ }
+
+ ARM_LIB_STACK (MBED_RAM_START + MBED_RAM_SIZE) EMPTY -MBED_CONF_TARGET_BOOT_STACK_SIZE { ; Stack region growing down
+ }
+}
diff --git a/targets/TARGET_STM/TARGET_STM32WL/TARGET_STM32WLE5x8/TOOLCHAIN_GCC_ARM/startup_stm32wle5xx.S b/targets/TARGET_STM/TARGET_STM32WL/TARGET_STM32WLE5x8/TOOLCHAIN_GCC_ARM/startup_stm32wle5xx.S
new file mode 100644
index 0000000..69a5b33
--- /dev/null
+++ b/targets/TARGET_STM/TARGET_STM32WL/TARGET_STM32WLE5x8/TOOLCHAIN_GCC_ARM/startup_stm32wle5xx.S
@@ -0,0 +1,425 @@
+/**
+ ******************************************************************************
+ * @file startup_stm32wle5xx.s
+ * @author MCD Application Team
+ * @brief STM32WLE5xx devices vector table for GCC toolchain.
+ * This module performs:
+ * - Set the initial SP
+ * - Set the initial PC == Reset_Handler,
+ * - Set the vector table entries with the exceptions ISR address,
+ * - Branches to main in the C library (which eventually
+ * calls main()).
+ * After Reset the Cortex-M4 processor is in Thread mode,
+ * priority is Privileged, and the Stack is set to Main.
+ ******************************************************************************
+ * @attention
+ *
+ * © Copyright (c) 2020 STMicroelectronics.
+ * All rights reserved.
+ *
+ * This software component is licensed by ST under Apache License, Version 2.0,
+ * the "License"; You may not use this file except in compliance with the
+ * License. You may obtain a copy of the License at:
+ * opensource.org/licenses/Apache-2.0
+ *
+ ******************************************************************************
+ */
+
+.syntax unified
+.cpu cortex-m4
+.fpu softvfp
+.thumb
+
+.global g_pfnVectors
+.global Default_Handler
+
+/* start address for the initialization values of the .data section.
+defined in linker script */
+.word _sidata
+/* start address for the .data section. defined in linker script */
+.word _sdata
+/* end address for the .data section. defined in linker script */
+.word _edata
+/* start address for the .bss section. defined in linker script */
+.word _sbss
+/* end address for the .bss section. defined in linker script */
+.word _ebss
+
+/**
+ * @brief This is the code that gets called when the processor first
+ * starts execution following a reset event. Only the absolutely
+ * necessary set is performed, after which the application
+ * supplied main() routine is called.
+ * @param None
+ * @retval : None
+*/
+
+ .section .text.Reset_Handler
+ .weak Reset_Handler
+ .type Reset_Handler, %function
+Reset_Handler:
+ ldr r0, =_estack
+ mov sp, r0 /* set stack pointer */
+
+/* Call the clock system initialization function.*/
+ bl SystemInit
+
+/* Copy the data segment initializers from flash to SRAM */
+ ldr r0, =_sdata
+ ldr r1, =_edata
+ ldr r2, =_sidata
+ movs r3, #0
+ b LoopCopyDataInit
+
+CopyDataInit:
+ ldr r4, [r2, r3]
+ str r4, [r0, r3]
+ adds r3, r3, #4
+
+LoopCopyDataInit:
+ adds r4, r0, r3
+ cmp r4, r1
+ bcc CopyDataInit
+
+/* Zero fill the bss segment. */
+ ldr r2, =_sbss
+ ldr r4, =_ebss
+ movs r3, #0
+ b LoopFillZerobss
+
+FillZerobss:
+ str r3, [r2]
+ adds r2, r2, #4
+
+LoopFillZerobss:
+ cmp r2, r4
+ bcc FillZerobss
+
+ bl _start
+ bx lr
+
+LoopForever:
+ b LoopForever
+
+ .size Reset_Handler, .-Reset_Handler
+
+/**
+ * @brief This is the code that gets called when the processor receives an
+ * unexpected interrupt. This simply enters an infinite loop, preserving
+ * the system state for examination by a debugger.
+ *
+ * @param None
+ * @retval : None
+*/
+ .section .text.Default_Handler,"ax",%progbits
+Default_Handler:
+Infinite_Loop:
+ b Infinite_Loop
+ .size Default_Handler, .-Default_Handler
+
+/******************************************************************************
+*
+* The STM32WLE5xx vector table. Note that the proper constructs
+* must be placed on this to ensure that it ends up at physical address
+* 0x0000.0000.
+*
+******************************************************************************/
+ .section .isr_vector,"a",%progbits
+ .type g_pfnVectors, %object
+ .size g_pfnVectors, .-g_pfnVectors
+
+g_pfnVectors:
+ .word _estack
+ .word Reset_Handler
+ .word NMI_Handler
+ .word HardFault_Handler
+ .word MemManage_Handler
+ .word BusFault_Handler
+ .word UsageFault_Handler
+ .word 0
+ .word 0
+ .word 0
+ .word 0
+ .word SVC_Handler
+ .word DebugMon_Handler
+ .word 0
+ .word PendSV_Handler
+ .word SysTick_Handler
+ .word WWDG_IRQHandler /* Window Watchdog interrupt */
+ .word PVD_PVM_IRQHandler /* PVD and PVM interrupt through EXTI */
+ .word TAMP_STAMP_LSECSS_SSRU_IRQHandler /* RTC Tamper, RTC TimeStamp, LSECSS and RTC SSRU int.*/
+ .word RTC_WKUP_IRQHandler /* RTC wakeup interrupt through EXTI[19] */
+ .word FLASH_IRQHandler /* Flash memory global interrupt and Flash memory ECC */
+ .word RCC_IRQHandler /* RCC global interrupt */
+ .word EXTI0_IRQHandler /* EXTI line 0 interrupt */
+ .word EXTI1_IRQHandler /* EXTI line 1 interrupt */
+ .word EXTI2_IRQHandler /* EXTI line 2 interrupt */
+ .word EXTI3_IRQHandler /* EXTI line 3 interrupt */
+ .word EXTI4_IRQHandler /* EXTI line 4 interrupt */
+ .word DMA1_Channel1_IRQHandler /* DMA1 channel 1 interrupt */
+ .word DMA1_Channel2_IRQHandler /* DMA1 channel 2 interrupt */
+ .word DMA1_Channel3_IRQHandler /* DMA1 channel 3 interrupt */
+ .word DMA1_Channel4_IRQHandler /* DMA1 channel 4 interrupt */
+ .word DMA1_Channel5_IRQHandler /* DMA1 channel 5 interrupt */
+ .word DMA1_Channel6_IRQHandler /* DMA1 channel 6 interrupt */
+ .word DMA1_Channel7_IRQHandler /* DMA1 channel 7 interrupt */
+ .word ADC_IRQHandler /* ADC interrupt */
+ .word DAC_IRQHandler /* DAC interrupt */
+ .word 0 /* Reserved */
+ .word COMP_IRQHandler /* COMP1 and COMP2 interrupt through EXTI */
+ .word EXTI9_5_IRQHandler /* EXTI line 9_5 interrupt */
+ .word TIM1_BRK_IRQHandler /* Timer 1 break interrupt */
+ .word TIM1_UP_IRQHandler /* Timer 1 Update */
+ .word TIM1_TRG_COM_IRQHandler /* Timer 1 trigger and communication */
+ .word TIM1_CC_IRQHandler /* Timer 1 capture compare interrupt */
+ .word TIM2_IRQHandler /* TIM2 global interrupt */
+ .word TIM16_IRQHandler /* Timer 16 global interrupt */
+ .word TIM17_IRQHandler /* Timer 17 global interrupt */
+ .word I2C1_EV_IRQHandler /* I2C1 event interrupt */
+ .word I2C1_ER_IRQHandler /* I2C1 event interrupt */
+ .word I2C2_EV_IRQHandler /* I2C2 error interrupt */
+ .word I2C2_ER_IRQHandler /* I2C2 error interrupt */
+ .word SPI1_IRQHandler /* SPI1 global interrupt */
+ .word SPI2_IRQHandler /* SPI2 global interrupt */
+ .word USART1_IRQHandler /* USART1 global interrupt */
+ .word USART2_IRQHandler /* USART2 global interrupt */
+ .word LPUART1_IRQHandler /* LPUART1 global interrupt */
+ .word LPTIM1_IRQHandler /* LPtimer 1 global interrupt */
+ .word LPTIM2_IRQHandler /* LPtimer 2 global interrupt */
+ .word EXTI15_10_IRQHandler /* EXTI line 15_10] interrupt through EXTI */
+ .word RTC_Alarm_IRQHandler /* RTC Alarms A & B interrupt */
+ .word LPTIM3_IRQHandler /* LPtimer 3 global interrupt */
+ .word SUBGHZSPI_IRQHandler /* SUBGHZSPI global interrupt */
+ .word 0 /* Reserved */
+ .word 0 /* Reserved */
+ .word HSEM_IRQHandler /* Semaphore interrupt 0 to CPU1 */
+ .word I2C3_EV_IRQHandler /* I2C3 event interrupt */
+ .word I2C3_ER_IRQHandler /* I2C3 error interrupt */
+ .word SUBGHZ_Radio_IRQHandler /* Radio IRQs RFBUSY interrupt through EXTI */
+ .word AES_IRQHandler /* AES global interrupt */
+ .word RNG_IRQHandler /* RNG interrupt */
+ .word PKA_IRQHandler /* PKA interrupt */
+ .word DMA2_Channel1_IRQHandler /* DMA2 channel 1 interrupt */
+ .word DMA2_Channel2_IRQHandler /* DMA2 channel 2 interrupt */
+ .word DMA2_Channel3_IRQHandler /* DMA2 channel 3 interrupt */
+ .word DMA2_Channel4_IRQHandler /* DMA2 channel 4 interrupt */
+ .word DMA2_Channel5_IRQHandler /* DMA2 channel 5 interrupt */
+ .word DMA2_Channel6_IRQHandler /* DMA2 channel 6 interrupt */
+ .word DMA2_Channel7_IRQHandler /* DMA2 channel 7 interrupt */
+ .word DMAMUX1_OVR_IRQHandler /* DMAMUX overrun interrupt */
+
+/*******************************************************************************
+*
+* Provide weak aliases for each Exception handler to the Default_Handler.
+* As they are weak aliases, any function with the same name will override
+* this definition.
+*
+*******************************************************************************/
+
+ .weak NMI_Handler
+ .thumb_set NMI_Handler,Default_Handler
+
+ .weak HardFault_Handler
+ .thumb_set HardFault_Handler,Default_Handler
+
+ .weak MemManage_Handler
+ .thumb_set MemManage_Handler,Default_Handler
+
+ .weak BusFault_Handler
+ .thumb_set BusFault_Handler,Default_Handler
+
+ .weak UsageFault_Handler
+ .thumb_set UsageFault_Handler,Default_Handler
+
+ .weak SVC_Handler
+ .thumb_set SVC_Handler,Default_Handler
+
+ .weak DebugMon_Handler
+ .thumb_set DebugMon_Handler,Default_Handler
+
+ .weak PendSV_Handler
+ .thumb_set PendSV_Handler,Default_Handler
+
+ .weak SysTick_Handler
+ .thumb_set SysTick_Handler,Default_Handler
+
+ .weak WWDG_IRQHandler
+ .thumb_set WWDG_IRQHandler,Default_Handler
+
+ .weak PVD_PVM_IRQHandler
+ .thumb_set PVD_PVM_IRQHandler,Default_Handler
+
+ .weak TAMP_STAMP_LSECSS_SSRU_IRQHandler
+ .thumb_set TAMP_STAMP_LSECSS_SSRU_IRQHandler,Default_Handler
+
+ .weak RTC_WKUP_IRQHandler
+ .thumb_set RTC_WKUP_IRQHandler,Default_Handler
+
+ .weak FLASH_IRQHandler
+ .thumb_set FLASH_IRQHandler,Default_Handler
+
+ .weak RCC_IRQHandler
+ .thumb_set RCC_IRQHandler,Default_Handler
+
+ .weak EXTI0_IRQHandler
+ .thumb_set EXTI0_IRQHandler,Default_Handler
+
+ .weak EXTI1_IRQHandler
+ .thumb_set EXTI1_IRQHandler,Default_Handler
+
+ .weak EXTI2_IRQHandler
+ .thumb_set EXTI2_IRQHandler,Default_Handler
+
+ .weak EXTI3_IRQHandler
+ .thumb_set EXTI3_IRQHandler,Default_Handler
+
+ .weak EXTI4_IRQHandler
+ .thumb_set EXTI4_IRQHandler,Default_Handler
+
+ .weak DMA1_Channel1_IRQHandler
+ .thumb_set DMA1_Channel1_IRQHandler,Default_Handler
+
+ .weak DMA1_Channel2_IRQHandler
+ .thumb_set DMA1_Channel2_IRQHandler,Default_Handler
+
+ .weak DMA1_Channel3_IRQHandler
+ .thumb_set DMA1_Channel3_IRQHandler,Default_Handler
+
+ .weak DMA1_Channel4_IRQHandler
+ .thumb_set DMA1_Channel4_IRQHandler,Default_Handler
+
+ .weak DMA1_Channel5_IRQHandler
+ .thumb_set DMA1_Channel5_IRQHandler,Default_Handler
+
+ .weak DMA1_Channel6_IRQHandler
+ .thumb_set DMA1_Channel6_IRQHandler,Default_Handler
+
+ .weak DMA1_Channel7_IRQHandler
+ .thumb_set DMA1_Channel7_IRQHandler,Default_Handler
+
+ .weak ADC_IRQHandler
+ .thumb_set ADC_IRQHandler,Default_Handler
+
+ .weak DAC_IRQHandler
+ .thumb_set DAC_IRQHandler,Default_Handler
+
+ .weak COMP_IRQHandler
+ .thumb_set COMP_IRQHandler,Default_Handler
+
+ .weak EXTI9_5_IRQHandler
+ .thumb_set EXTI9_5_IRQHandler,Default_Handler
+
+ .weak TIM1_BRK_IRQHandler
+ .thumb_set TIM1_BRK_IRQHandler,Default_Handler
+
+ .weak TIM1_UP_IRQHandler
+ .thumb_set TIM1_UP_IRQHandler,Default_Handler
+
+ .weak TIM1_TRG_COM_IRQHandler
+ .thumb_set TIM1_TRG_COM_IRQHandler,Default_Handler
+
+ .weak TIM1_CC_IRQHandler
+ .thumb_set TIM1_CC_IRQHandler,Default_Handler
+
+ .weak TIM2_IRQHandler
+ .thumb_set TIM2_IRQHandler,Default_Handler
+
+ .weak TIM16_IRQHandler
+ .thumb_set TIM16_IRQHandler,Default_Handler
+
+ .weak TIM17_IRQHandler
+ .thumb_set TIM17_IRQHandler,Default_Handler
+
+ .weak I2C1_EV_IRQHandler
+ .thumb_set I2C1_EV_IRQHandler,Default_Handler
+
+ .weak I2C1_ER_IRQHandler
+ .thumb_set I2C1_ER_IRQHandler,Default_Handler
+
+ .weak I2C2_EV_IRQHandler
+ .thumb_set I2C2_EV_IRQHandler,Default_Handler
+
+ .weak I2C2_ER_IRQHandler
+ .thumb_set I2C2_ER_IRQHandler,Default_Handler
+
+ .weak SPI1_IRQHandler
+ .thumb_set SPI1_IRQHandler,Default_Handler
+
+ .weak SPI2_IRQHandler
+ .thumb_set SPI2_IRQHandler,Default_Handler
+
+ .weak USART1_IRQHandler
+ .thumb_set USART1_IRQHandler,Default_Handler
+
+ .weak USART2_IRQHandler
+ .thumb_set USART2_IRQHandler,Default_Handler
+
+ .weak LPUART1_IRQHandler
+ .thumb_set LPUART1_IRQHandler,Default_Handler
+
+ .weak LPTIM1_IRQHandler
+ .thumb_set LPTIM1_IRQHandler,Default_Handler
+
+ .weak LPTIM2_IRQHandler
+ .thumb_set LPTIM2_IRQHandler,Default_Handler
+
+ .weak EXTI15_10_IRQHandler
+ .thumb_set EXTI15_10_IRQHandler,Default_Handler
+
+ .weak RTC_Alarm_IRQHandler
+ .thumb_set RTC_Alarm_IRQHandler,Default_Handler
+
+ .weak LPTIM3_IRQHandler
+ .thumb_set LPTIM3_IRQHandler,Default_Handler
+
+ .weak SUBGHZSPI_IRQHandler
+ .thumb_set SUBGHZSPI_IRQHandler,Default_Handler
+
+ .weak HSEM_IRQHandler
+ .thumb_set HSEM_IRQHandler,Default_Handler
+
+ .weak I2C3_EV_IRQHandler
+ .thumb_set I2C3_EV_IRQHandler,Default_Handler
+
+ .weak I2C3_ER_IRQHandler
+ .thumb_set I2C3_ER_IRQHandler,Default_Handler
+
+ .weak SUBGHZ_Radio_IRQHandler
+ .thumb_set SUBGHZ_Radio_IRQHandler,Default_Handler
+
+ .weak AES_IRQHandler
+ .thumb_set AES_IRQHandler,Default_Handler
+
+ .weak RNG_IRQHandler
+ .thumb_set RNG_IRQHandler,Default_Handler
+
+ .weak PKA_IRQHandler
+ .thumb_set PKA_IRQHandler,Default_Handler
+
+ .weak DMA2_Channel1_IRQHandler
+ .thumb_set DMA2_Channel1_IRQHandler,Default_Handler
+
+ .weak DMA2_Channel2_IRQHandler
+ .thumb_set DMA2_Channel2_IRQHandler,Default_Handler
+
+ .weak DMA2_Channel3_IRQHandler
+ .thumb_set DMA2_Channel3_IRQHandler,Default_Handler
+
+ .weak DMA2_Channel4_IRQHandler
+ .thumb_set DMA2_Channel4_IRQHandler,Default_Handler
+
+ .weak DMA2_Channel5_IRQHandler
+ .thumb_set DMA2_Channel5_IRQHandler,Default_Handler
+
+ .weak DMA2_Channel6_IRQHandler
+ .thumb_set DMA2_Channel6_IRQHandler,Default_Handler
+
+ .weak DMA2_Channel7_IRQHandler
+ .thumb_set DMA2_Channel7_IRQHandler,Default_Handler
+
+ .weak DMAMUX1_OVR_IRQHandler
+ .thumb_set DMAMUX1_OVR_IRQHandler,Default_Handler
+
+ .weak SystemInit
+
+/************************ (C) COPYRIGHT STMicroelectonics *****END OF FILE****/
diff --git a/targets/TARGET_STM/TARGET_STM32WL/TARGET_STM32WLE5x8/TOOLCHAIN_GCC_ARM/stm32wle5x8.ld b/targets/TARGET_STM/TARGET_STM32WL/TARGET_STM32WLE5x8/TOOLCHAIN_GCC_ARM/stm32wle5x8.ld
new file mode 100644
index 0000000..5f47993
--- /dev/null
+++ b/targets/TARGET_STM/TARGET_STM32WL/TARGET_STM32WLE5x8/TOOLCHAIN_GCC_ARM/stm32wle5x8.ld
@@ -0,0 +1,203 @@
+/* Linker script to configure memory regions. */
+/*
+ * SPDX-License-Identifier: BSD-3-Clause
+ ******************************************************************************
+ * @attention
+ *
+ * Copyright (c) 2016-2020 STMicroelectronics.
+ * All rights reserved.
+ *
+ * This software component is licensed by ST under BSD 3-Clause license,
+ * the "License"; You may not use this file except in compliance with the
+ * License. You may obtain a copy of the License at:
+ * opensource.org/licenses/BSD-3-Clause
+ *
+ ******************************************************************************
+*/
+
+#include "../cmsis_nvic.h"
+
+
+#if !defined(MBED_APP_START)
+ #define MBED_APP_START MBED_ROM_START
+#endif
+
+#if !defined(MBED_APP_SIZE)
+ #define MBED_APP_SIZE MBED_ROM_SIZE
+#endif
+
+#if !defined(MBED_CONF_TARGET_BOOT_STACK_SIZE)
+ /* This value is normally defined by the tools
+ to 0x1000 for bare metal and 0x400 for RTOS */
+ #define MBED_CONF_TARGET_BOOT_STACK_SIZE 0x400
+#endif
+
+/* Round up VECTORS_SIZE to 8 bytes */
+#define VECTORS_SIZE (((NVIC_NUM_VECTORS * 4) + 7) & 0xFFFFFFF8)
+
+MEMORY
+{
+ FLASH (rx) : ORIGIN = MBED_APP_START, LENGTH = MBED_APP_SIZE
+ RAM (rwx) : ORIGIN = MBED_RAM_START + VECTORS_SIZE, LENGTH = MBED_RAM_SIZE - VECTORS_SIZE
+}
+
+/* Linker script to place sections and symbol values. Should be used together
+ * with other linker script that defines memory regions FLASH and RAM.
+ * It references following symbols, which must be defined in code:
+ * Reset_Handler : Entry of reset handler
+ *
+ * It defines following symbols, which code can use without definition:
+ * __exidx_start
+ * __exidx_end
+ * __etext
+ * __data_start__
+ * __preinit_array_start
+ * __preinit_array_end
+ * __init_array_start
+ * __init_array_end
+ * __fini_array_start
+ * __fini_array_end
+ * __data_end__
+ * __bss_start__
+ * __bss_end__
+ * __end__
+ * end
+ * __HeapLimit
+ * __StackLimit
+ * __StackTop
+ * __stack
+ * _estack
+ */
+ENTRY(Reset_Handler)
+
+SECTIONS
+{
+ .text :
+ {
+ KEEP(*(.isr_vector))
+ *(.text*)
+
+ KEEP(*(.init))
+ KEEP(*(.fini))
+
+ /* .ctors */
+ *crtbegin.o(.ctors)
+ *crtbegin?.o(.ctors)
+ *(EXCLUDE_FILE(*crtend?.o *crtend.o) .ctors)
+ *(SORT(.ctors.*))
+ *(.ctors)
+
+ /* .dtors */
+ *crtbegin.o(.dtors)
+ *crtbegin?.o(.dtors)
+ *(EXCLUDE_FILE(*crtend?.o *crtend.o) .dtors)
+ *(SORT(.dtors.*))
+ *(.dtors)
+
+ *(.rodata*)
+
+ KEEP(*(.eh_frame*))
+ } > FLASH
+
+ .ARM.extab :
+ {
+ *(.ARM.extab* .gnu.linkonce.armextab.*)
+ } > FLASH
+
+ __exidx_start = .;
+ .ARM.exidx :
+ {
+ *(.ARM.exidx* .gnu.linkonce.armexidx.*)
+ } > FLASH
+ __exidx_end = .;
+
+ __etext = .;
+ _sidata = .;
+
+ .data : AT (__etext)
+ {
+ __data_start__ = .;
+ _sdata = .;
+ *(vtable)
+ *(.data*)
+
+ . = ALIGN(8);
+ /* preinit data */
+ PROVIDE_HIDDEN (__preinit_array_start = .);
+ KEEP(*(.preinit_array))
+ PROVIDE_HIDDEN (__preinit_array_end = .);
+
+ . = ALIGN(8);
+ /* init data */
+ PROVIDE_HIDDEN (__init_array_start = .);
+ KEEP(*(SORT(.init_array.*)))
+ KEEP(*(.init_array))
+ PROVIDE_HIDDEN (__init_array_end = .);
+
+ . = ALIGN(8);
+ /* finit data */
+ PROVIDE_HIDDEN (__fini_array_start = .);
+ KEEP(*(SORT(.fini_array.*)))
+ KEEP(*(.fini_array))
+ PROVIDE_HIDDEN (__fini_array_end = .);
+
+ KEEP(*(.jcr*))
+ . = ALIGN(8);
+ /* All data end */
+ __data_end__ = .;
+ _edata = .;
+
+ } > RAM
+
+ /* Uninitialized data section
+ * This region is not initialized by the C/C++ library and can be used to
+ * store state across soft reboots. */
+ .uninitialized (NOLOAD):
+ {
+ . = ALIGN(32);
+ __uninitialized_start = .;
+ *(.uninitialized)
+ KEEP(*(.keep.uninitialized))
+ . = ALIGN(32);
+ __uninitialized_end = .;
+ } > RAM
+
+ .bss :
+ {
+ . = ALIGN(8);
+ __bss_start__ = .;
+ _sbss = .;
+ *(.bss*)
+ *(COMMON)
+ . = ALIGN(8);
+ __bss_end__ = .;
+ _ebss = .;
+ } > RAM
+
+ .heap (COPY):
+ {
+ __end__ = .;
+ PROVIDE(end = .);
+ *(.heap*)
+ . = ORIGIN(RAM) + LENGTH(RAM) - MBED_CONF_TARGET_BOOT_STACK_SIZE;
+ __HeapLimit = .;
+ } > RAM
+
+ /* .stack_dummy section doesn't contains any symbols. It is only
+ * used for linker to calculate size of stack sections, and assign
+ * values to stack symbols later */
+ .stack_dummy (COPY):
+ {
+ *(.stack*)
+ } > RAM
+
+ /* Set stack top to end of RAM, and stack limit move down by
+ * size of stack_dummy section */
+ __StackTop = ORIGIN(RAM) + LENGTH(RAM);
+ _estack = __StackTop;
+ __StackLimit = __StackTop - MBED_CONF_TARGET_BOOT_STACK_SIZE;
+ PROVIDE(__stack = __StackTop);
+
+ /* Check if data + heap + stack exceeds RAM limit */
+ ASSERT(__StackLimit >= __HeapLimit, "region RAM overflowed with stack")
+}
diff --git a/targets/TARGET_STM/TARGET_STM32WL/TARGET_STM32WLE5x8/TOOLCHAIN_IAR/startup_stm32wle5xx.S b/targets/TARGET_STM/TARGET_STM32WL/TARGET_STM32WLE5x8/TOOLCHAIN_IAR/startup_stm32wle5xx.S
new file mode 100644
index 0000000..341ee9e
--- /dev/null
+++ b/targets/TARGET_STM/TARGET_STM32WL/TARGET_STM32WLE5x8/TOOLCHAIN_IAR/startup_stm32wle5xx.S
@@ -0,0 +1,494 @@
+;********************************************************************************
+;* File Name : startup_stm32wle5xx.s
+;* Author : MCD Application Team
+;* Description : M4 core vector table of the STM32WLxxxx devices for the
+;* IAR (EWARM) toolchain.
+;*
+;* This module performs:
+;* - Set the initial SP
+;* - Set the initial PC == _iar_program_start,
+;* - Set the vector table entries with the exceptions ISR
+;* address.
+;* - Branches to main in the C library (which eventually
+;* calls main()).
+;* After Reset the Cortex-M4 processor is in Thread mode,
+;* priority is Privileged, and the Stack is set to Main.
+;********************************************************************************
+;*
+;* Copyright (c) 2020 STMicroelectronics. All rights reserved.
+;*
+;* This software component is licensed by ST under Apache License, Version 2.0,
+;* the "License"; You may not use this file except in compliance with the
+;* License. You may obtain a copy of the License at:
+;* opensource.org/licenses/Apache-2.0
+;
+;*******************************************************************************
+;
+;
+; The modules in this file are included in the libraries, and may be replaced
+; by any user-defined modules that define the PUBLIC symbol _program_start or
+; a user defined start symbol.
+; To override the cstartup defined in the library, simply add your modified
+; version to the workbench project.
+;
+; The vector table is normally located at address 0.
+; When debugging in RAM, it can be located in RAM, aligned to at least 2^6.
+; The name "__vector_table" has special meaning for C-SPY:
+; it is where the SP start value is found, and the NVIC vector
+; table register (VTOR) is initialized to this address if != 0.
+;
+; Cortex-M version
+;
+
+ MODULE ?cstartup
+
+ ;; Forward declaration of sections.
+ SECTION CSTACK:DATA:NOROOT(3)
+
+ SECTION .intvec:CODE:NOROOT(2)
+
+ EXTERN __iar_program_start
+ EXTERN SystemInit
+ PUBLIC __vector_table
+
+ DATA
+__vector_table
+ DCD sfe(CSTACK)
+ DCD Reset_Handler ; Reset Handler
+
+ DCD NMI_Handler ; NMI Handler
+ DCD HardFault_Handler ; Hard Fault Handler
+ DCD MemManage_Handler ; MPU Fault Handler
+ DCD BusFault_Handler ; Bus Fault Handler
+ DCD UsageFault_Handler ; Usage Fault Handler
+ DCD 0 ; Reserved
+ DCD 0 ; Reserved
+ DCD 0 ; Reserved
+ DCD 0 ; Reserved
+ DCD SVC_Handler ; SVCall Handler
+ DCD DebugMon_Handler ; Debug Monitor Handler
+ DCD 0 ; Reserved
+ DCD PendSV_Handler ; PendSV Handler
+ DCD SysTick_Handler ; SysTick Handler
+
+ ; External Interrupts
+ DCD WWDG_IRQHandler ; Window WatchDog
+ DCD PVD_PVM_IRQHandler ; PVD and PVM Interrupt
+ DCD TAMP_STAMP_LSECSS_SSRU_IRQHandler ; RTC Tamper, RTC TimeStamp, LSECSS and RTC SSRU Interrupts
+ DCD RTC_WKUP_IRQHandler ; RTC Wakeup Interrupt
+ DCD FLASH_IRQHandler ; FLASH global Interrupt
+ DCD RCC_IRQHandler ; RCC Interrupt
+ DCD EXTI0_IRQHandler ; EXTI Line 0 Interrupt
+ DCD EXTI1_IRQHandler ; EXTI Line 1 Interrupt
+ DCD EXTI2_IRQHandler ; EXTI Line 2 Interrupt
+ DCD EXTI3_IRQHandler ; EXTI Line 3 Interrupt
+ DCD EXTI4_IRQHandler ; EXTI Line 4 Interrupt
+ DCD DMA1_Channel1_IRQHandler ; DMA1 Channel 1 Interrupt
+ DCD DMA1_Channel2_IRQHandler ; DMA1 Channel 2 Interrupt
+ DCD DMA1_Channel3_IRQHandler ; DMA1 Channel 3 Interrupt
+ DCD DMA1_Channel4_IRQHandler ; DMA1 Channel 4 Interrupt
+ DCD DMA1_Channel5_IRQHandler ; DMA1 Channel 5 Interrupt
+ DCD DMA1_Channel6_IRQHandler ; DMA1 Channel 6 Interrupt
+ DCD DMA1_Channel7_IRQHandler ; DMA1 Channel 7 Interrupt
+ DCD ADC_IRQHandler ; ADC Interrupt
+ DCD DAC_IRQHandler ; DAC Interrupt
+ DCD 0 ; Reserved
+ DCD COMP_IRQHandler ; COMP1 and COMP2 Interrupts
+ DCD EXTI9_5_IRQHandler ; EXTI Lines [9:5] Interrupt
+ DCD TIM1_BRK_IRQHandler ; TIM1 Break Interrupt
+ DCD TIM1_UP_IRQHandler ; TIM1 Update Interrupt
+ DCD TIM1_TRG_COM_IRQHandler ; TIM1 Trigger and Communication Interrupts
+ DCD TIM1_CC_IRQHandler ; TIM1 Capture Compare Interrupt
+ DCD TIM2_IRQHandler ; TIM2 Global Interrupt
+ DCD TIM16_IRQHandler ; TIM16 Global Interrupt
+ DCD TIM17_IRQHandler ; TIM17 Global Interrupt
+ DCD I2C1_EV_IRQHandler ; I2C1 Event Interrupt
+ DCD I2C1_ER_IRQHandler ; I2C1 Error Interrupt
+ DCD I2C2_EV_IRQHandler ; I2C2 Event Interrupt
+ DCD I2C2_ER_IRQHandler ; I2C2 Error Interrupt
+ DCD SPI1_IRQHandler ; SPI1 Interrupt
+ DCD SPI2_IRQHandler ; SPI2 Interrupt
+ DCD USART1_IRQHandler ; USART1 Interrupt
+ DCD USART2_IRQHandler ; USART2 Interrupt
+ DCD LPUART1_IRQHandler ; LPUART1 Interrupt
+ DCD LPTIM1_IRQHandler ; LPTIM1 Global Interrupt
+ DCD LPTIM2_IRQHandler ; LPTIM2 Global Interrupt
+ DCD EXTI15_10_IRQHandler ; EXTI Lines [15:10] Interrupt
+ DCD RTC_Alarm_IRQHandler ; RTC Alarms (A and B) Interrupt
+ DCD LPTIM3_IRQHandler ; LPTIM3 Global Interrupt
+ DCD SUBGHZSPI_IRQHandler ; SUBGHZSPI Interrupt
+ DCD 0 ; Reserved
+ DCD 0 ; Reserved
+ DCD HSEM_IRQHandler ; HSEM0 Interrupt
+ DCD I2C3_EV_IRQHandler ; I2C3 Event Interrupt
+ DCD I2C3_ER_IRQHandler ; I2C3 Error Interrupt
+ DCD SUBGHZ_Radio_IRQHandler ; SUBGHZ Radio Interrupt
+ DCD AES_IRQHandler ; AES Interrupt
+ DCD RNG_IRQHandler ; RNG1 Interrupt
+ DCD PKA_IRQHandler ; PKA Interrupt
+ DCD DMA2_Channel1_IRQHandler ; DMA2 Channel 1 Interrupt
+ DCD DMA2_Channel2_IRQHandler ; DMA2 Channel 2 Interrupt
+ DCD DMA2_Channel3_IRQHandler ; DMA2 Channel 3 Interrupt
+ DCD DMA2_Channel4_IRQHandler ; DMA2 Channel 4 Interrupt
+ DCD DMA2_Channel5_IRQHandler ; DMA2 Channel 5 Interrupt
+ DCD DMA2_Channel6_IRQHandler ; DMA2 Channel 6 Interrupt
+ DCD DMA2_Channel7_IRQHandler ; DMA2 Channel 7 Interrupt
+ DCD DMAMUX1_OVR_IRQHandler ; DMAMUX overrun Interrupt
+
+;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;
+;;
+;; Default interrupt handlers.
+;;
+ THUMB
+
+ PUBWEAK Reset_Handler
+ SECTION .text:CODE:NOROOT:REORDER(2)
+Reset_Handler
+ LDR R0, =SystemInit
+ BLX R0
+ LDR R0, =__iar_program_start
+ BX R0
+
+ PUBWEAK NMI_Handler
+ SECTION .text:CODE:NOROOT:REORDER(1)
+NMI_Handler
+ B NMI_Handler
+
+ PUBWEAK HardFault_Handler
+ SECTION .text:CODE:NOROOT:REORDER(1)
+HardFault_Handler
+ B HardFault_Handler
+
+ PUBWEAK MemManage_Handler
+ SECTION .text:CODE:NOROOT:REORDER(1)
+MemManage_Handler
+ B MemManage_Handler
+
+ PUBWEAK BusFault_Handler
+ SECTION .text:CODE:NOROOT:REORDER(1)
+BusFault_Handler
+ B BusFault_Handler
+
+ PUBWEAK UsageFault_Handler
+ SECTION .text:CODE:NOROOT:REORDER(1)
+UsageFault_Handler
+ B UsageFault_Handler
+
+ PUBWEAK SVC_Handler
+ SECTION .text:CODE:NOROOT:REORDER(1)
+SVC_Handler
+ B SVC_Handler
+
+ PUBWEAK DebugMon_Handler
+ SECTION .text:CODE:NOROOT:REORDER(1)
+DebugMon_Handler
+ B DebugMon_Handler
+
+ PUBWEAK PendSV_Handler
+ SECTION .text:CODE:NOROOT:REORDER(1)
+PendSV_Handler
+ B PendSV_Handler
+
+ PUBWEAK SysTick_Handler
+ SECTION .text:CODE:NOROOT:REORDER(1)
+SysTick_Handler
+ B SysTick_Handler
+
+ PUBWEAK WWDG_IRQHandler
+ SECTION .text:CODE:NOROOT:REORDER(1)
+WWDG_IRQHandler
+ B WWDG_IRQHandler
+
+ PUBWEAK PVD_PVM_IRQHandler
+ SECTION .text:CODE:NOROOT:REORDER(1)
+PVD_PVM_IRQHandler
+ B PVD_PVM_IRQHandler
+
+ PUBWEAK TAMP_STAMP_LSECSS_SSRU_IRQHandler
+ SECTION .text:CODE:NOROOT:REORDER(1)
+TAMP_STAMP_LSECSS_SSRU_IRQHandler
+ B TAMP_STAMP_LSECSS_SSRU_IRQHandler
+
+ PUBWEAK RTC_WKUP_IRQHandler
+ SECTION .text:CODE:NOROOT:REORDER(1)
+RTC_WKUP_IRQHandler
+ B RTC_WKUP_IRQHandler
+
+ PUBWEAK FLASH_IRQHandler
+ SECTION .text:CODE:NOROOT:REORDER(1)
+FLASH_IRQHandler
+ B FLASH_IRQHandler
+
+ PUBWEAK RCC_IRQHandler
+ SECTION .text:CODE:NOROOT:REORDER(1)
+RCC_IRQHandler
+ B RCC_IRQHandler
+
+ PUBWEAK EXTI0_IRQHandler
+ SECTION .text:CODE:NOROOT:REORDER(1)
+EXTI0_IRQHandler
+ B EXTI0_IRQHandler
+
+ PUBWEAK EXTI1_IRQHandler
+ SECTION .text:CODE:NOROOT:REORDER(1)
+EXTI1_IRQHandler
+ B EXTI1_IRQHandler
+
+ PUBWEAK EXTI2_IRQHandler
+ SECTION .text:CODE:NOROOT:REORDER(1)
+EXTI2_IRQHandler
+ B EXTI2_IRQHandler
+
+ PUBWEAK EXTI3_IRQHandler
+ SECTION .text:CODE:NOROOT:REORDER(1)
+EXTI3_IRQHandler
+ B EXTI3_IRQHandler
+
+ PUBWEAK EXTI4_IRQHandler
+ SECTION .text:CODE:NOROOT:REORDER(1)
+EXTI4_IRQHandler
+ B EXTI4_IRQHandler
+
+ PUBWEAK DMA1_Channel1_IRQHandler
+ SECTION .text:CODE:NOROOT:REORDER(1)
+DMA1_Channel1_IRQHandler
+ B DMA1_Channel1_IRQHandler
+
+ PUBWEAK DMA1_Channel2_IRQHandler
+ SECTION .text:CODE:NOROOT:REORDER(1)
+DMA1_Channel2_IRQHandler
+ B DMA1_Channel2_IRQHandler
+
+ PUBWEAK DMA1_Channel3_IRQHandler
+ SECTION .text:CODE:NOROOT:REORDER(1)
+DMA1_Channel3_IRQHandler
+ B DMA1_Channel3_IRQHandler
+
+ PUBWEAK DMA1_Channel4_IRQHandler
+ SECTION .text:CODE:NOROOT:REORDER(1)
+DMA1_Channel4_IRQHandler
+ B DMA1_Channel4_IRQHandler
+
+ PUBWEAK DMA1_Channel5_IRQHandler
+ SECTION .text:CODE:NOROOT:REORDER(1)
+DMA1_Channel5_IRQHandler
+ B DMA1_Channel5_IRQHandler
+
+ PUBWEAK DMA1_Channel6_IRQHandler
+ SECTION .text:CODE:NOROOT:REORDER(1)
+DMA1_Channel6_IRQHandler
+ B DMA1_Channel6_IRQHandler
+
+ PUBWEAK DMA1_Channel7_IRQHandler
+ SECTION .text:CODE:NOROOT:REORDER(1)
+DMA1_Channel7_IRQHandler
+ B DMA1_Channel7_IRQHandler
+
+ PUBWEAK ADC_IRQHandler
+ SECTION .text:CODE:NOROOT:REORDER(1)
+ADC_IRQHandler
+ B ADC_IRQHandler
+
+ PUBWEAK DAC_IRQHandler
+ SECTION .text:CODE:NOROOT:REORDER(1)
+DAC_IRQHandler
+ B DAC_IRQHandler
+
+ PUBWEAK COMP_IRQHandler
+ SECTION .text:CODE:NOROOT:REORDER(1)
+COMP_IRQHandler
+ B COMP_IRQHandler
+
+ PUBWEAK EXTI9_5_IRQHandler
+ SECTION .text:CODE:NOROOT:REORDER(1)
+EXTI9_5_IRQHandler
+ B EXTI9_5_IRQHandler
+
+ PUBWEAK TIM1_BRK_IRQHandler
+ SECTION .text:CODE:NOROOT:REORDER(1)
+TIM1_BRK_IRQHandler
+ B TIM1_BRK_IRQHandler
+
+ PUBWEAK TIM1_UP_IRQHandler
+ SECTION .text:CODE:NOROOT:REORDER(1)
+TIM1_UP_IRQHandler
+ B TIM1_UP_IRQHandler
+
+ PUBWEAK TIM1_TRG_COM_IRQHandler
+ SECTION .text:CODE:NOROOT:REORDER(1)
+TIM1_TRG_COM_IRQHandler
+ B TIM1_TRG_COM_IRQHandler
+
+ PUBWEAK TIM1_CC_IRQHandler
+ SECTION .text:CODE:NOROOT:REORDER(1)
+TIM1_CC_IRQHandler
+ B TIM1_CC_IRQHandler
+
+ PUBWEAK TIM2_IRQHandler
+ SECTION .text:CODE:NOROOT:REORDER(1)
+TIM2_IRQHandler
+ B TIM2_IRQHandler
+
+ PUBWEAK TIM16_IRQHandler
+ SECTION .text:CODE:NOROOT:REORDER(1)
+TIM16_IRQHandler
+ B TIM16_IRQHandler
+
+ PUBWEAK TIM17_IRQHandler
+ SECTION .text:CODE:NOROOT:REORDER(1)
+TIM17_IRQHandler
+ B TIM17_IRQHandler
+
+ PUBWEAK I2C1_EV_IRQHandler
+ SECTION .text:CODE:NOROOT:REORDER(1)
+I2C1_EV_IRQHandler
+ B I2C1_EV_IRQHandler
+
+ PUBWEAK I2C1_ER_IRQHandler
+ SECTION .text:CODE:NOROOT:REORDER(1)
+I2C1_ER_IRQHandler
+ B I2C1_ER_IRQHandler
+
+ PUBWEAK I2C2_EV_IRQHandler
+ SECTION .text:CODE:NOROOT:REORDER(1)
+I2C2_EV_IRQHandler
+ B I2C2_EV_IRQHandler
+
+ PUBWEAK I2C2_ER_IRQHandler
+ SECTION .text:CODE:NOROOT:REORDER(1)
+I2C2_ER_IRQHandler
+ B I2C2_ER_IRQHandler
+
+ PUBWEAK SPI1_IRQHandler
+ SECTION .text:CODE:NOROOT:REORDER(1)
+SPI1_IRQHandler
+ B SPI1_IRQHandler
+
+ PUBWEAK SPI2_IRQHandler
+ SECTION .text:CODE:NOROOT:REORDER(1)
+SPI2_IRQHandler
+ B SPI2_IRQHandler
+
+ PUBWEAK USART1_IRQHandler
+ SECTION .text:CODE:NOROOT:REORDER(1)
+USART1_IRQHandler
+ B USART1_IRQHandler
+
+ PUBWEAK USART2_IRQHandler
+ SECTION .text:CODE:NOROOT:REORDER(1)
+USART2_IRQHandler
+ B USART2_IRQHandler
+
+ PUBWEAK LPUART1_IRQHandler
+ SECTION .text:CODE:NOROOT:REORDER(1)
+LPUART1_IRQHandler
+ B LPUART1_IRQHandler
+
+ PUBWEAK LPTIM1_IRQHandler
+ SECTION .text:CODE:NOROOT:REORDER(1)
+LPTIM1_IRQHandler
+ B LPTIM1_IRQHandler
+
+ PUBWEAK LPTIM2_IRQHandler
+ SECTION .text:CODE:NOROOT:REORDER(1)
+LPTIM2_IRQHandler
+ B LPTIM2_IRQHandler
+
+ PUBWEAK EXTI15_10_IRQHandler
+ SECTION .text:CODE:NOROOT:REORDER(1)
+EXTI15_10_IRQHandler
+ B EXTI15_10_IRQHandler
+
+ PUBWEAK RTC_Alarm_IRQHandler
+ SECTION .text:CODE:NOROOT:REORDER(1)
+RTC_Alarm_IRQHandler
+ B RTC_Alarm_IRQHandler
+
+ PUBWEAK LPTIM3_IRQHandler
+ SECTION .text:CODE:NOROOT:REORDER(1)
+LPTIM3_IRQHandler
+ B LPTIM3_IRQHandler
+
+ PUBWEAK SUBGHZSPI_IRQHandler
+ SECTION .text:CODE:NOROOT:REORDER(1)
+SUBGHZSPI_IRQHandler
+ B SUBGHZSPI_IRQHandler
+
+ PUBWEAK HSEM_IRQHandler
+ SECTION .text:CODE:NOROOT:REORDER(1)
+HSEM_IRQHandler
+ B HSEM_IRQHandler
+
+ PUBWEAK I2C3_EV_IRQHandler
+ SECTION .text:CODE:NOROOT:REORDER(1)
+I2C3_EV_IRQHandler
+ B I2C3_EV_IRQHandler
+
+ PUBWEAK I2C3_ER_IRQHandler
+ SECTION .text:CODE:NOROOT:REORDER(1)
+I2C3_ER_IRQHandler
+ B I2C3_ER_IRQHandler
+
+ PUBWEAK SUBGHZ_Radio_IRQHandler
+ SECTION .text:CODE:NOROOT:REORDER(1)
+SUBGHZ_Radio_IRQHandler
+ B SUBGHZ_Radio_IRQHandler
+
+ PUBWEAK AES_IRQHandler
+ SECTION .text:CODE:NOROOT:REORDER(1)
+AES_IRQHandler
+ B AES_IRQHandler
+
+ PUBWEAK RNG_IRQHandler
+ SECTION .text:CODE:NOROOT:REORDER(1)
+RNG_IRQHandler
+ B RNG_IRQHandler
+
+ PUBWEAK PKA_IRQHandler
+ SECTION .text:CODE:NOROOT:REORDER(1)
+PKA_IRQHandler
+ B PKA_IRQHandler
+
+ PUBWEAK DMA2_Channel1_IRQHandler
+ SECTION .text:CODE:NOROOT:REORDER(1)
+DMA2_Channel1_IRQHandler
+ B DMA2_Channel1_IRQHandler
+
+ PUBWEAK DMA2_Channel2_IRQHandler
+ SECTION .text:CODE:NOROOT:REORDER(1)
+DMA2_Channel2_IRQHandler
+ B DMA2_Channel2_IRQHandler
+
+ PUBWEAK DMA2_Channel3_IRQHandler
+ SECTION .text:CODE:NOROOT:REORDER(1)
+DMA2_Channel3_IRQHandler
+ B DMA2_Channel3_IRQHandler
+
+ PUBWEAK DMA2_Channel4_IRQHandler
+ SECTION .text:CODE:NOROOT:REORDER(1)
+DMA2_Channel4_IRQHandler
+ B DMA2_Channel4_IRQHandler
+
+ PUBWEAK DMA2_Channel5_IRQHandler
+ SECTION .text:CODE:NOROOT:REORDER(1)
+DMA2_Channel5_IRQHandler
+ B DMA2_Channel5_IRQHandler
+
+ PUBWEAK DMA2_Channel6_IRQHandler
+ SECTION .text:CODE:NOROOT:REORDER(1)
+DMA2_Channel6_IRQHandler
+ B DMA2_Channel6_IRQHandler
+
+ PUBWEAK DMA2_Channel7_IRQHandler
+ SECTION .text:CODE:NOROOT:REORDER(1)
+DMA2_Channel7_IRQHandler
+ B DMA2_Channel7_IRQHandler
+
+ PUBWEAK DMAMUX1_OVR_IRQHandler
+ SECTION .text:CODE:NOROOT:REORDER(1)
+DMAMUX1_OVR_IRQHandler
+ B DMAMUX1_OVR_IRQHandler
+
+ END
+
+;************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE*****
diff --git a/targets/TARGET_STM/TARGET_STM32WL/TARGET_STM32WLE5x8/TOOLCHAIN_IAR/stm32wle5x8.icf b/targets/TARGET_STM/TARGET_STM32WL/TARGET_STM32WLE5x8/TOOLCHAIN_IAR/stm32wle5x8.icf
new file mode 100644
index 0000000..7fb4af2
--- /dev/null
+++ b/targets/TARGET_STM/TARGET_STM32WL/TARGET_STM32WLE5x8/TOOLCHAIN_IAR/stm32wle5x8.icf
@@ -0,0 +1,59 @@
+/* Linker script to configure memory regions.
+ *
+ * SPDX-License-Identifier: BSD-3-Clause
+ ******************************************************************************
+ * @attention
+ *
+ * Copyright (c) 2016-2020 STMicroelectronics.
+ * All rights reserved.
+ *
+ * This software component is licensed by ST under BSD 3-Clause license,
+ * the "License"; You may not use this file except in compliance with the
+ * License. You may obtain a copy of the License at:
+ * opensource.org/licenses/BSD-3-Clause
+ *
+ ******************************************************************************
+*/
+/* Device specific values */
+
+/* Tools provide -DMBED_ROM_START=xxx -DMBED_ROM_SIZE=xxx -DMBED_RAM_START=xxx -DMBED_RAM_SIZE=xxx */
+
+define symbol VECTORS = 78; /* This value must match NVIC_NUM_VECTORS in cmsis_nvic.h */
+define symbol HEAP_SIZE = 0x1000;
+
+/* Common - Do not change */
+
+if (!isdefinedsymbol(MBED_APP_START)) {
+ define symbol MBED_APP_START = MBED_ROM_START;
+}
+
+if (!isdefinedsymbol(MBED_APP_SIZE)) {
+ define symbol MBED_APP_SIZE = MBED_ROM_SIZE;
+}
+
+if (!isdefinedsymbol(MBED_CONF_TARGET_BOOT_STACK_SIZE)) {
+ /* This value is normally defined by the tools
+ to 0x1000 for bare metal and 0x400 for RTOS */
+ define symbol MBED_CONF_TARGET_BOOT_STACK_SIZE = 0x400;
+}
+
+/* Round up VECTORS_SIZE to 8 bytes */
+define symbol VECTORS_SIZE = ((VECTORS * 4) + 7) & ~7;
+define symbol RAM_REGION_START = MBED_RAM_START + VECTORS_SIZE;
+define symbol RAM_REGION_SIZE = MBED_RAM_SIZE - VECTORS_SIZE;
+
+define memory mem with size = 4G;
+define region ROM_region = mem:[from MBED_APP_START size MBED_APP_SIZE];
+define region RAM_region = mem:[from RAM_REGION_START size RAM_REGION_SIZE];
+
+define block CSTACK with alignment = 8, size = MBED_CONF_TARGET_BOOT_STACK_SIZE { };
+define block HEAP with alignment = 8, size = HEAP_SIZE { };
+
+initialize by copy { readwrite };
+do not initialize { section .noinit };
+
+place at address mem: MBED_APP_START { readonly section .intvec };
+
+place in ROM_region { readonly };
+place in RAM_region { readwrite,
+ block CSTACK, block HEAP };
diff --git a/targets/TARGET_STM/TARGET_STM32WL/TARGET_STM32WLE5x8/cmsis_nvic.h b/targets/TARGET_STM/TARGET_STM32WL/TARGET_STM32WLE5x8/cmsis_nvic.h
new file mode 100644
index 0000000..a18342e
--- /dev/null
+++ b/targets/TARGET_STM/TARGET_STM32WL/TARGET_STM32WLE5x8/cmsis_nvic.h
@@ -0,0 +1,39 @@
+/* mbed Microcontroller Library
+ * SPDX-License-Identifier: BSD-3-Clause
+ ******************************************************************************
+ * @attention
+ *
+ * © Copyright (c) 2016-2020 STMicroelectronics.
+ * All rights reserved.
+ *
+ * This software component is licensed by ST under BSD 3-Clause license,
+ * the "License"; You may not use this file except in compliance with the
+ * License. You may obtain a copy of the License at:
+ * opensource.org/licenses/BSD-3-Clause
+ *
+ ******************************************************************************
+*/
+
+#ifndef MBED_CMSIS_NVIC_H
+#define MBED_CMSIS_NVIC_H
+
+#if !defined(MBED_ROM_START)
+#define MBED_ROM_START 0x8000000
+#endif
+
+#if !defined(MBED_ROM_SIZE)
+#define MBED_ROM_SIZE 0x0 // 0 B
+#endif
+
+#if !defined(MBED_RAM_START)
+#define MBED_RAM_START 0x20000000
+#endif
+
+#if !defined(MBED_RAM_SIZE)
+#define MBED_RAM_SIZE 0x0 // 0 B
+#endif
+
+#define NVIC_NUM_VECTORS 78
+#define NVIC_RAM_VECTOR_ADDRESS MBED_RAM_START
+
+#endif
diff --git a/targets/TARGET_STM/TARGET_STM32WL/TARGET_STM32WLE5xB/TOOLCHAIN_ARM/startup_stm32wle5xx.S b/targets/TARGET_STM/TARGET_STM32WL/TARGET_STM32WLE5xB/TOOLCHAIN_ARM/startup_stm32wle5xx.S
new file mode 100644
index 0000000..29f645e
--- /dev/null
+++ b/targets/TARGET_STM/TARGET_STM32WL/TARGET_STM32WLE5xB/TOOLCHAIN_ARM/startup_stm32wle5xx.S
@@ -0,0 +1,314 @@
+;******************************************************************************
+;* File Name : startup_stm32wle5xx.s
+;* Author : MCD Application Team
+;* Description : STM32WLE5xx devices vector table for MDK-ARM toolchain.
+;* This module performs:
+;* - Set the initial SP
+;* - Set the initial PC == Reset_Handler
+;* - Set the vector table entries with the exceptions ISR address
+;* - Branches to __main in the C library (which eventually
+;* calls main()).
+;* After Reset the CortexM4 processor is in Thread mode,
+;* priority is Privileged, and the Stack is set to Main.
+;* <<< Use Configuration Wizard in Context Menu >>>
+;******************************************************************************
+;* @attention
+;*
+;* Copyright (c) 2020 STMicroelectronics. All rights reserved.
+;*
+;* This software component is licensed by ST under Apache License, Version 2.0,
+;* the "License"; You may not use this file except in compliance with the
+;* License. You may obtain a copy of the License at:
+;* opensource.org/licenses/Apache-2.0
+;*
+;******************************************************************************
+
+ PRESERVE8
+ THUMB
+
+
+; Vector Table Mapped to Address 0 at Reset
+ AREA RESET, DATA, READONLY
+ EXPORT __Vectors
+ EXPORT __Vectors_End
+ EXPORT __Vectors_Size
+
+ IMPORT |Image$$ARM_LIB_STACK$$ZI$$Limit|
+__Vectors DCD |Image$$ARM_LIB_STACK$$ZI$$Limit| ; Top of Stack
+ DCD Reset_Handler ; Reset Handler
+ DCD NMI_Handler ; NMI Handler
+ DCD HardFault_Handler ; Hard Fault Handler
+ DCD MemManage_Handler ; MPU Fault Handler
+ DCD BusFault_Handler ; Bus Fault Handler
+ DCD UsageFault_Handler ; Usage Fault Handler
+ DCD 0 ; Reserved
+ DCD 0 ; Reserved
+ DCD 0 ; Reserved
+ DCD 0 ; Reserved
+ DCD SVC_Handler ; SVCall Handler
+ DCD DebugMon_Handler ; Debug Monitor Handler
+ DCD 0 ; Reserved
+ DCD PendSV_Handler ; PendSV Handler
+ DCD SysTick_Handler ; SysTick Handler
+
+ ; External Interrupts
+ DCD WWDG_IRQHandler ; Window WatchDog
+ DCD PVD_PVM_IRQHandler ; PVD and PVM detector
+ DCD TAMP_STAMP_LSECSS_SSRU_IRQHandler ; RTC Tamper, RTC TimeStamp, LSECSS and RTC SSR Underflow Interrupts
+ DCD RTC_WKUP_IRQHandler ; RTC Wakeup Interrupt
+ DCD FLASH_IRQHandler ; FLASH global Interrupt
+ DCD RCC_IRQHandler ; RCC Interrupt
+ DCD EXTI0_IRQHandler ; EXTI Line 0 Interrupt
+ DCD EXTI1_IRQHandler ; EXTI Line 1 Interrupt
+ DCD EXTI2_IRQHandler ; EXTI Line 2 Interrupt
+ DCD EXTI3_IRQHandler ; EXTI Line 3 Interrup
+ DCD EXTI4_IRQHandler ; EXTI Line 4 Interrupt
+ DCD DMA1_Channel1_IRQHandler ; DMA1 Channel 1 Interrupt
+ DCD DMA1_Channel2_IRQHandler ; DMA1 Channel 2 Interrupt
+ DCD DMA1_Channel3_IRQHandler ; DMA1 Channel 3 Interrupt
+ DCD DMA1_Channel4_IRQHandler ; DMA1 Channel 4 Interrupt
+ DCD DMA1_Channel5_IRQHandler ; DMA1 Channel 5 Interrupt
+ DCD DMA1_Channel6_IRQHandler ; DMA1 Channel 6 Interrupt
+ DCD DMA1_Channel7_IRQHandler ; DMA1 Channel 7 Interrupt
+ DCD ADC_IRQHandler ; ADC Interrupt
+ DCD DAC_IRQHandler ; DAC Interrupt
+ DCD 0 ; Reserved
+ DCD COMP_IRQHandler ; COMP1 and COMP2 Interrupts
+ DCD EXTI9_5_IRQHandler ; EXTI Lines [9:5] Interrupt
+ DCD TIM1_BRK_IRQHandler ; TIM1 Break Interrupt
+ DCD TIM1_UP_IRQHandler ; TIM1 Update Interrupts
+ DCD TIM1_TRG_COM_IRQHandler ; TIM1 Trigger and Communication Interrupts
+ DCD TIM1_CC_IRQHandler ; TIM1 Capture Compare Interrupt
+ DCD TIM2_IRQHandler ; TIM2 Global Interrupt
+ DCD TIM16_IRQHandler ; TIM16 Global Interrupt
+ DCD TIM17_IRQHandler ; TIM17 Global Interrupt
+ DCD I2C1_EV_IRQHandler ; I2C1 Event Interrupt
+ DCD I2C1_ER_IRQHandler ; I2C1 Error Interrupt
+ DCD I2C2_EV_IRQHandler ; I2C2 Event Interrupt
+ DCD I2C2_ER_IRQHandler ; I2C2 Error Interrupt
+ DCD SPI1_IRQHandler ; SPI1 Interrupt
+ DCD SPI2_IRQHandler ; SPI2 Interrupt
+ DCD USART1_IRQHandler ; USART1 Interrupt
+ DCD USART2_IRQHandler ; USART2 Interrupt
+ DCD LPUART1_IRQHandler ; LPUART1 Interrupt
+ DCD LPTIM1_IRQHandler ; LPTIM1 Interrupt
+ DCD LPTIM2_IRQHandler ; LPTIM2 Interrupt
+ DCD EXTI15_10_IRQHandler ; EXTI Lines1[15:10 ]Interrupts
+ DCD RTC_Alarm_IRQHandler ; RTC Alarms (A and B) Interrupt
+ DCD LPTIM3_IRQHandler ; LPTIM3 Interrupt
+ DCD SUBGHZSPI_IRQHandler ; SUBGHZSPI Interrupt
+ DCD 0 ; Reserved
+ DCD 0 ; Reserved
+ DCD HSEM_IRQHandler ; HSEM0 Interrupt
+ DCD I2C3_EV_IRQHandler ; I2C3 Event Interrupt
+ DCD I2C3_ER_IRQHandler ; I2C3 Error Interrupt
+ DCD SUBGHZ_Radio_IRQHandler ; SUBGHZ Radio Interrupt
+ DCD AES_IRQHandler ; AES Interrupt
+ DCD RNG_IRQHandler ; RNG1 Interrupt
+ DCD PKA_IRQHandler ; PKA Interrupt
+ DCD DMA2_Channel1_IRQHandler ; DMA2 Channel 1 Interrupt
+ DCD DMA2_Channel2_IRQHandler ; DMA2 Channel 2 Interrupt
+ DCD DMA2_Channel3_IRQHandler ; DMA2 Channel 3 Interrupt
+ DCD DMA2_Channel4_IRQHandler ; DMA2 Channel 4 Interrupt
+ DCD DMA2_Channel5_IRQHandler ; DMA2 Channel 5 Interrupt
+ DCD DMA2_Channel6_IRQHandler ; DMA2 Channel 6 Interrupt
+ DCD DMA2_Channel7_IRQHandler ; DMA2 Channel 7 Interrupt
+ DCD DMAMUX1_OVR_IRQHandler ; DMAMUX overrun Interrupt
+
+__Vectors_End
+
+__Vectors_Size EQU __Vectors_End - __Vectors
+
+ AREA |.text|, CODE, READONLY
+
+; Reset handler
+Reset_Handler PROC
+ EXPORT Reset_Handler [WEAK]
+ IMPORT SystemInit
+ IMPORT __main
+
+ LDR R0, =SystemInit
+ BLX R0
+ LDR R0, =__main
+ BX R0
+ ENDP
+
+; Dummy Exception Handlers (infinite loops which can be modified)
+
+NMI_Handler PROC
+ EXPORT NMI_Handler [WEAK]
+ B .
+ ENDP
+HardFault_Handler\
+ PROC
+ EXPORT HardFault_Handler [WEAK]
+ B .
+ ENDP
+MemManage_Handler\
+ PROC
+ EXPORT MemManage_Handler [WEAK]
+ B .
+ ENDP
+BusFault_Handler\
+ PROC
+ EXPORT BusFault_Handler [WEAK]
+ B .
+ ENDP
+UsageFault_Handler\
+ PROC
+ EXPORT UsageFault_Handler [WEAK]
+ B .
+ ENDP
+SVC_Handler PROC
+ EXPORT SVC_Handler [WEAK]
+ B .
+ ENDP
+DebugMon_Handler\
+ PROC
+ EXPORT DebugMon_Handler [WEAK]
+ B .
+ ENDP
+PendSV_Handler PROC
+ EXPORT PendSV_Handler [WEAK]
+ B .
+ ENDP
+SysTick_Handler PROC
+ EXPORT SysTick_Handler [WEAK]
+ B .
+ ENDP
+
+Default_Handler PROC
+
+ EXPORT WWDG_IRQHandler [WEAK]
+ EXPORT PVD_PVM_IRQHandler [WEAK]
+ EXPORT TAMP_STAMP_LSECSS_SSRU_IRQHandler [WEAK]
+ EXPORT RTC_WKUP_IRQHandler [WEAK]
+ EXPORT FLASH_IRQHandler [WEAK]
+ EXPORT RCC_IRQHandler [WEAK]
+ EXPORT EXTI0_IRQHandler [WEAK]
+ EXPORT EXTI1_IRQHandler [WEAK]
+ EXPORT EXTI2_IRQHandler [WEAK]
+ EXPORT EXTI3_IRQHandler [WEAK]
+ EXPORT EXTI4_IRQHandler [WEAK]
+ EXPORT DMA1_Channel1_IRQHandler [WEAK]
+ EXPORT DMA1_Channel2_IRQHandler [WEAK]
+ EXPORT DMA1_Channel3_IRQHandler [WEAK]
+ EXPORT DMA1_Channel4_IRQHandler [WEAK]
+ EXPORT DMA1_Channel5_IRQHandler [WEAK]
+ EXPORT DMA1_Channel6_IRQHandler [WEAK]
+ EXPORT DMA1_Channel7_IRQHandler [WEAK]
+ EXPORT ADC_IRQHandler [WEAK]
+ EXPORT DAC_IRQHandler [WEAK]
+ EXPORT COMP_IRQHandler [WEAK]
+ EXPORT EXTI9_5_IRQHandler [WEAK]
+ EXPORT TIM1_BRK_IRQHandler [WEAK]
+ EXPORT TIM1_UP_IRQHandler [WEAK]
+ EXPORT TIM1_TRG_COM_IRQHandler [WEAK]
+ EXPORT TIM1_CC_IRQHandler [WEAK]
+ EXPORT TIM2_IRQHandler [WEAK]
+ EXPORT TIM16_IRQHandler [WEAK]
+ EXPORT TIM17_IRQHandler [WEAK]
+ EXPORT I2C1_EV_IRQHandler [WEAK]
+ EXPORT I2C1_ER_IRQHandler [WEAK]
+ EXPORT I2C2_EV_IRQHandler [WEAK]
+ EXPORT I2C2_ER_IRQHandler [WEAK]
+ EXPORT SPI1_IRQHandler [WEAK]
+ EXPORT SPI2_IRQHandler [WEAK]
+ EXPORT USART1_IRQHandler [WEAK]
+ EXPORT USART2_IRQHandler [WEAK]
+ EXPORT LPUART1_IRQHandler [WEAK]
+ EXPORT LPTIM1_IRQHandler [WEAK]
+ EXPORT LPTIM2_IRQHandler [WEAK]
+ EXPORT EXTI15_10_IRQHandler [WEAK]
+ EXPORT RTC_Alarm_IRQHandler [WEAK]
+ EXPORT LPTIM3_IRQHandler [WEAK]
+ EXPORT SUBGHZSPI_IRQHandler [WEAK]
+ EXPORT HSEM_IRQHandler [WEAK]
+ EXPORT I2C3_EV_IRQHandler [WEAK]
+ EXPORT I2C3_ER_IRQHandler [WEAK]
+ EXPORT SUBGHZ_Radio_IRQHandler [WEAK]
+ EXPORT AES_IRQHandler [WEAK]
+ EXPORT RNG_IRQHandler [WEAK]
+ EXPORT PKA_IRQHandler [WEAK]
+ EXPORT DMA2_Channel1_IRQHandler [WEAK]
+ EXPORT DMA2_Channel2_IRQHandler [WEAK]
+ EXPORT DMA2_Channel3_IRQHandler [WEAK]
+ EXPORT DMA2_Channel4_IRQHandler [WEAK]
+ EXPORT DMA2_Channel5_IRQHandler [WEAK]
+ EXPORT DMA2_Channel6_IRQHandler [WEAK]
+ EXPORT DMA2_Channel7_IRQHandler [WEAK]
+ EXPORT DMAMUX1_OVR_IRQHandler [WEAK]
+
+WWDG_IRQHandler
+PVD_PVM_IRQHandler
+TAMP_STAMP_LSECSS_SSRU_IRQHandler
+RTC_WKUP_IRQHandler
+FLASH_IRQHandler
+RCC_IRQHandler
+EXTI0_IRQHandler
+EXTI1_IRQHandler
+EXTI2_IRQHandler
+EXTI3_IRQHandler
+EXTI4_IRQHandler
+DMA1_Channel1_IRQHandler
+DMA1_Channel2_IRQHandler
+DMA1_Channel3_IRQHandler
+DMA1_Channel4_IRQHandler
+DMA1_Channel5_IRQHandler
+DMA1_Channel6_IRQHandler
+DMA1_Channel7_IRQHandler
+ADC_IRQHandler
+DAC_IRQHandler
+COMP_IRQHandler
+EXTI9_5_IRQHandler
+TIM1_BRK_IRQHandler
+TIM1_UP_IRQHandler
+TIM1_TRG_COM_IRQHandler
+TIM1_CC_IRQHandler
+TIM2_IRQHandler
+TIM16_IRQHandler
+TIM17_IRQHandler
+I2C1_EV_IRQHandler
+I2C1_ER_IRQHandler
+I2C2_EV_IRQHandler
+I2C2_ER_IRQHandler
+SPI1_IRQHandler
+SPI2_IRQHandler
+USART1_IRQHandler
+USART2_IRQHandler
+LPUART1_IRQHandler
+LPTIM1_IRQHandler
+LPTIM2_IRQHandler
+EXTI15_10_IRQHandler
+RTC_Alarm_IRQHandler
+LPTIM3_IRQHandler
+SUBGHZSPI_IRQHandler
+HSEM_IRQHandler
+I2C3_EV_IRQHandler
+I2C3_ER_IRQHandler
+SUBGHZ_Radio_IRQHandler
+AES_IRQHandler
+RNG_IRQHandler
+PKA_IRQHandler
+DMA2_Channel1_IRQHandler
+DMA2_Channel2_IRQHandler
+DMA2_Channel3_IRQHandler
+DMA2_Channel4_IRQHandler
+DMA2_Channel5_IRQHandler
+DMA2_Channel6_IRQHandler
+DMA2_Channel7_IRQHandler
+DMAMUX1_OVR_IRQHandler
+
+ B .
+
+ ENDP
+
+ ALIGN
+
+;*******************************************************************************
+; User Stack and Heap initialization
+;*******************************************************************************
+
+ END
+
+;************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE*****
diff --git a/targets/TARGET_STM/TARGET_STM32WL/TARGET_STM32WLE5xB/TOOLCHAIN_ARM/stm32wle5xb.sct b/targets/TARGET_STM/TARGET_STM32WL/TARGET_STM32WLE5xB/TOOLCHAIN_ARM/stm32wle5xb.sct
new file mode 100644
index 0000000..9258e6a
--- /dev/null
+++ b/targets/TARGET_STM/TARGET_STM32WL/TARGET_STM32WLE5xB/TOOLCHAIN_ARM/stm32wle5xb.sct
@@ -0,0 +1,57 @@
+#! armclang -E --target=arm-arm-none-eabi -x c -mcpu=cortex-M4
+; Scatter-Loading Description File
+;
+; SPDX-License-Identifier: BSD-3-Clause
+;******************************************************************************
+;* @attention
+;*
+;* Copyright (c) 2016-2020 STMicroelectronics.
+;* All rights reserved.
+;*
+;* This software component is licensed by ST under BSD 3-Clause license,
+;* the "License"; You may not use this file except in compliance with the
+;* License. You may obtain a copy of the License at:
+;* opensource.org/licenses/BSD-3-Clause
+;*
+;******************************************************************************
+
+#include "../cmsis_nvic.h"
+
+#if !defined(MBED_APP_START)
+ #define MBED_APP_START MBED_ROM_START
+#endif
+
+#if !defined(MBED_APP_SIZE)
+ #define MBED_APP_SIZE MBED_ROM_SIZE
+#endif
+
+#if !defined(MBED_CONF_TARGET_BOOT_STACK_SIZE)
+/* This value is normally defined by the tools to 0x1000 for bare metal and 0x400 for RTOS */
+#if defined(MBED_BOOT_STACK_SIZE)
+#define MBED_CONF_TARGET_BOOT_STACK_SIZE MBED_BOOT_STACK_SIZE
+#else
+#define MBED_CONF_TARGET_BOOT_STACK_SIZE 0x400
+#endif
+#endif
+
+/* Round up VECTORS_SIZE to 8 bytes */
+#define VECTORS_SIZE (((NVIC_NUM_VECTORS * 4) + 7) AND ~7)
+
+LR_IROM1 MBED_APP_START MBED_APP_SIZE {
+
+ ER_IROM1 MBED_APP_START MBED_APP_SIZE {
+ *.o (RESET, +First)
+ *(InRoot$$Sections)
+ .ANY (+RO)
+ }
+
+ RW_IRAM1 (MBED_RAM_START + VECTORS_SIZE) { ; RW data
+ .ANY (+RW +ZI)
+ }
+
+ ARM_LIB_HEAP AlignExpr(+0, 16) EMPTY (MBED_RAM_START + MBED_RAM_SIZE - MBED_CONF_TARGET_BOOT_STACK_SIZE - AlignExpr(ImageLimit(RW_IRAM1), 16)) { ; Heap growing up
+ }
+
+ ARM_LIB_STACK (MBED_RAM_START + MBED_RAM_SIZE) EMPTY -MBED_CONF_TARGET_BOOT_STACK_SIZE { ; Stack region growing down
+ }
+}
diff --git a/targets/TARGET_STM/TARGET_STM32WL/TARGET_STM32WLE5xB/TOOLCHAIN_GCC_ARM/startup_stm32wle5xx.S b/targets/TARGET_STM/TARGET_STM32WL/TARGET_STM32WLE5xB/TOOLCHAIN_GCC_ARM/startup_stm32wle5xx.S
new file mode 100644
index 0000000..69a5b33
--- /dev/null
+++ b/targets/TARGET_STM/TARGET_STM32WL/TARGET_STM32WLE5xB/TOOLCHAIN_GCC_ARM/startup_stm32wle5xx.S
@@ -0,0 +1,425 @@
+/**
+ ******************************************************************************
+ * @file startup_stm32wle5xx.s
+ * @author MCD Application Team
+ * @brief STM32WLE5xx devices vector table for GCC toolchain.
+ * This module performs:
+ * - Set the initial SP
+ * - Set the initial PC == Reset_Handler,
+ * - Set the vector table entries with the exceptions ISR address,
+ * - Branches to main in the C library (which eventually
+ * calls main()).
+ * After Reset the Cortex-M4 processor is in Thread mode,
+ * priority is Privileged, and the Stack is set to Main.
+ ******************************************************************************
+ * @attention
+ *
+ * © Copyright (c) 2020 STMicroelectronics.
+ * All rights reserved.
+ *
+ * This software component is licensed by ST under Apache License, Version 2.0,
+ * the "License"; You may not use this file except in compliance with the
+ * License. You may obtain a copy of the License at:
+ * opensource.org/licenses/Apache-2.0
+ *
+ ******************************************************************************
+ */
+
+.syntax unified
+.cpu cortex-m4
+.fpu softvfp
+.thumb
+
+.global g_pfnVectors
+.global Default_Handler
+
+/* start address for the initialization values of the .data section.
+defined in linker script */
+.word _sidata
+/* start address for the .data section. defined in linker script */
+.word _sdata
+/* end address for the .data section. defined in linker script */
+.word _edata
+/* start address for the .bss section. defined in linker script */
+.word _sbss
+/* end address for the .bss section. defined in linker script */
+.word _ebss
+
+/**
+ * @brief This is the code that gets called when the processor first
+ * starts execution following a reset event. Only the absolutely
+ * necessary set is performed, after which the application
+ * supplied main() routine is called.
+ * @param None
+ * @retval : None
+*/
+
+ .section .text.Reset_Handler
+ .weak Reset_Handler
+ .type Reset_Handler, %function
+Reset_Handler:
+ ldr r0, =_estack
+ mov sp, r0 /* set stack pointer */
+
+/* Call the clock system initialization function.*/
+ bl SystemInit
+
+/* Copy the data segment initializers from flash to SRAM */
+ ldr r0, =_sdata
+ ldr r1, =_edata
+ ldr r2, =_sidata
+ movs r3, #0
+ b LoopCopyDataInit
+
+CopyDataInit:
+ ldr r4, [r2, r3]
+ str r4, [r0, r3]
+ adds r3, r3, #4
+
+LoopCopyDataInit:
+ adds r4, r0, r3
+ cmp r4, r1
+ bcc CopyDataInit
+
+/* Zero fill the bss segment. */
+ ldr r2, =_sbss
+ ldr r4, =_ebss
+ movs r3, #0
+ b LoopFillZerobss
+
+FillZerobss:
+ str r3, [r2]
+ adds r2, r2, #4
+
+LoopFillZerobss:
+ cmp r2, r4
+ bcc FillZerobss
+
+ bl _start
+ bx lr
+
+LoopForever:
+ b LoopForever
+
+ .size Reset_Handler, .-Reset_Handler
+
+/**
+ * @brief This is the code that gets called when the processor receives an
+ * unexpected interrupt. This simply enters an infinite loop, preserving
+ * the system state for examination by a debugger.
+ *
+ * @param None
+ * @retval : None
+*/
+ .section .text.Default_Handler,"ax",%progbits
+Default_Handler:
+Infinite_Loop:
+ b Infinite_Loop
+ .size Default_Handler, .-Default_Handler
+
+/******************************************************************************
+*
+* The STM32WLE5xx vector table. Note that the proper constructs
+* must be placed on this to ensure that it ends up at physical address
+* 0x0000.0000.
+*
+******************************************************************************/
+ .section .isr_vector,"a",%progbits
+ .type g_pfnVectors, %object
+ .size g_pfnVectors, .-g_pfnVectors
+
+g_pfnVectors:
+ .word _estack
+ .word Reset_Handler
+ .word NMI_Handler
+ .word HardFault_Handler
+ .word MemManage_Handler
+ .word BusFault_Handler
+ .word UsageFault_Handler
+ .word 0
+ .word 0
+ .word 0
+ .word 0
+ .word SVC_Handler
+ .word DebugMon_Handler
+ .word 0
+ .word PendSV_Handler
+ .word SysTick_Handler
+ .word WWDG_IRQHandler /* Window Watchdog interrupt */
+ .word PVD_PVM_IRQHandler /* PVD and PVM interrupt through EXTI */
+ .word TAMP_STAMP_LSECSS_SSRU_IRQHandler /* RTC Tamper, RTC TimeStamp, LSECSS and RTC SSRU int.*/
+ .word RTC_WKUP_IRQHandler /* RTC wakeup interrupt through EXTI[19] */
+ .word FLASH_IRQHandler /* Flash memory global interrupt and Flash memory ECC */
+ .word RCC_IRQHandler /* RCC global interrupt */
+ .word EXTI0_IRQHandler /* EXTI line 0 interrupt */
+ .word EXTI1_IRQHandler /* EXTI line 1 interrupt */
+ .word EXTI2_IRQHandler /* EXTI line 2 interrupt */
+ .word EXTI3_IRQHandler /* EXTI line 3 interrupt */
+ .word EXTI4_IRQHandler /* EXTI line 4 interrupt */
+ .word DMA1_Channel1_IRQHandler /* DMA1 channel 1 interrupt */
+ .word DMA1_Channel2_IRQHandler /* DMA1 channel 2 interrupt */
+ .word DMA1_Channel3_IRQHandler /* DMA1 channel 3 interrupt */
+ .word DMA1_Channel4_IRQHandler /* DMA1 channel 4 interrupt */
+ .word DMA1_Channel5_IRQHandler /* DMA1 channel 5 interrupt */
+ .word DMA1_Channel6_IRQHandler /* DMA1 channel 6 interrupt */
+ .word DMA1_Channel7_IRQHandler /* DMA1 channel 7 interrupt */
+ .word ADC_IRQHandler /* ADC interrupt */
+ .word DAC_IRQHandler /* DAC interrupt */
+ .word 0 /* Reserved */
+ .word COMP_IRQHandler /* COMP1 and COMP2 interrupt through EXTI */
+ .word EXTI9_5_IRQHandler /* EXTI line 9_5 interrupt */
+ .word TIM1_BRK_IRQHandler /* Timer 1 break interrupt */
+ .word TIM1_UP_IRQHandler /* Timer 1 Update */
+ .word TIM1_TRG_COM_IRQHandler /* Timer 1 trigger and communication */
+ .word TIM1_CC_IRQHandler /* Timer 1 capture compare interrupt */
+ .word TIM2_IRQHandler /* TIM2 global interrupt */
+ .word TIM16_IRQHandler /* Timer 16 global interrupt */
+ .word TIM17_IRQHandler /* Timer 17 global interrupt */
+ .word I2C1_EV_IRQHandler /* I2C1 event interrupt */
+ .word I2C1_ER_IRQHandler /* I2C1 event interrupt */
+ .word I2C2_EV_IRQHandler /* I2C2 error interrupt */
+ .word I2C2_ER_IRQHandler /* I2C2 error interrupt */
+ .word SPI1_IRQHandler /* SPI1 global interrupt */
+ .word SPI2_IRQHandler /* SPI2 global interrupt */
+ .word USART1_IRQHandler /* USART1 global interrupt */
+ .word USART2_IRQHandler /* USART2 global interrupt */
+ .word LPUART1_IRQHandler /* LPUART1 global interrupt */
+ .word LPTIM1_IRQHandler /* LPtimer 1 global interrupt */
+ .word LPTIM2_IRQHandler /* LPtimer 2 global interrupt */
+ .word EXTI15_10_IRQHandler /* EXTI line 15_10] interrupt through EXTI */
+ .word RTC_Alarm_IRQHandler /* RTC Alarms A & B interrupt */
+ .word LPTIM3_IRQHandler /* LPtimer 3 global interrupt */
+ .word SUBGHZSPI_IRQHandler /* SUBGHZSPI global interrupt */
+ .word 0 /* Reserved */
+ .word 0 /* Reserved */
+ .word HSEM_IRQHandler /* Semaphore interrupt 0 to CPU1 */
+ .word I2C3_EV_IRQHandler /* I2C3 event interrupt */
+ .word I2C3_ER_IRQHandler /* I2C3 error interrupt */
+ .word SUBGHZ_Radio_IRQHandler /* Radio IRQs RFBUSY interrupt through EXTI */
+ .word AES_IRQHandler /* AES global interrupt */
+ .word RNG_IRQHandler /* RNG interrupt */
+ .word PKA_IRQHandler /* PKA interrupt */
+ .word DMA2_Channel1_IRQHandler /* DMA2 channel 1 interrupt */
+ .word DMA2_Channel2_IRQHandler /* DMA2 channel 2 interrupt */
+ .word DMA2_Channel3_IRQHandler /* DMA2 channel 3 interrupt */
+ .word DMA2_Channel4_IRQHandler /* DMA2 channel 4 interrupt */
+ .word DMA2_Channel5_IRQHandler /* DMA2 channel 5 interrupt */
+ .word DMA2_Channel6_IRQHandler /* DMA2 channel 6 interrupt */
+ .word DMA2_Channel7_IRQHandler /* DMA2 channel 7 interrupt */
+ .word DMAMUX1_OVR_IRQHandler /* DMAMUX overrun interrupt */
+
+/*******************************************************************************
+*
+* Provide weak aliases for each Exception handler to the Default_Handler.
+* As they are weak aliases, any function with the same name will override
+* this definition.
+*
+*******************************************************************************/
+
+ .weak NMI_Handler
+ .thumb_set NMI_Handler,Default_Handler
+
+ .weak HardFault_Handler
+ .thumb_set HardFault_Handler,Default_Handler
+
+ .weak MemManage_Handler
+ .thumb_set MemManage_Handler,Default_Handler
+
+ .weak BusFault_Handler
+ .thumb_set BusFault_Handler,Default_Handler
+
+ .weak UsageFault_Handler
+ .thumb_set UsageFault_Handler,Default_Handler
+
+ .weak SVC_Handler
+ .thumb_set SVC_Handler,Default_Handler
+
+ .weak DebugMon_Handler
+ .thumb_set DebugMon_Handler,Default_Handler
+
+ .weak PendSV_Handler
+ .thumb_set PendSV_Handler,Default_Handler
+
+ .weak SysTick_Handler
+ .thumb_set SysTick_Handler,Default_Handler
+
+ .weak WWDG_IRQHandler
+ .thumb_set WWDG_IRQHandler,Default_Handler
+
+ .weak PVD_PVM_IRQHandler
+ .thumb_set PVD_PVM_IRQHandler,Default_Handler
+
+ .weak TAMP_STAMP_LSECSS_SSRU_IRQHandler
+ .thumb_set TAMP_STAMP_LSECSS_SSRU_IRQHandler,Default_Handler
+
+ .weak RTC_WKUP_IRQHandler
+ .thumb_set RTC_WKUP_IRQHandler,Default_Handler
+
+ .weak FLASH_IRQHandler
+ .thumb_set FLASH_IRQHandler,Default_Handler
+
+ .weak RCC_IRQHandler
+ .thumb_set RCC_IRQHandler,Default_Handler
+
+ .weak EXTI0_IRQHandler
+ .thumb_set EXTI0_IRQHandler,Default_Handler
+
+ .weak EXTI1_IRQHandler
+ .thumb_set EXTI1_IRQHandler,Default_Handler
+
+ .weak EXTI2_IRQHandler
+ .thumb_set EXTI2_IRQHandler,Default_Handler
+
+ .weak EXTI3_IRQHandler
+ .thumb_set EXTI3_IRQHandler,Default_Handler
+
+ .weak EXTI4_IRQHandler
+ .thumb_set EXTI4_IRQHandler,Default_Handler
+
+ .weak DMA1_Channel1_IRQHandler
+ .thumb_set DMA1_Channel1_IRQHandler,Default_Handler
+
+ .weak DMA1_Channel2_IRQHandler
+ .thumb_set DMA1_Channel2_IRQHandler,Default_Handler
+
+ .weak DMA1_Channel3_IRQHandler
+ .thumb_set DMA1_Channel3_IRQHandler,Default_Handler
+
+ .weak DMA1_Channel4_IRQHandler
+ .thumb_set DMA1_Channel4_IRQHandler,Default_Handler
+
+ .weak DMA1_Channel5_IRQHandler
+ .thumb_set DMA1_Channel5_IRQHandler,Default_Handler
+
+ .weak DMA1_Channel6_IRQHandler
+ .thumb_set DMA1_Channel6_IRQHandler,Default_Handler
+
+ .weak DMA1_Channel7_IRQHandler
+ .thumb_set DMA1_Channel7_IRQHandler,Default_Handler
+
+ .weak ADC_IRQHandler
+ .thumb_set ADC_IRQHandler,Default_Handler
+
+ .weak DAC_IRQHandler
+ .thumb_set DAC_IRQHandler,Default_Handler
+
+ .weak COMP_IRQHandler
+ .thumb_set COMP_IRQHandler,Default_Handler
+
+ .weak EXTI9_5_IRQHandler
+ .thumb_set EXTI9_5_IRQHandler,Default_Handler
+
+ .weak TIM1_BRK_IRQHandler
+ .thumb_set TIM1_BRK_IRQHandler,Default_Handler
+
+ .weak TIM1_UP_IRQHandler
+ .thumb_set TIM1_UP_IRQHandler,Default_Handler
+
+ .weak TIM1_TRG_COM_IRQHandler
+ .thumb_set TIM1_TRG_COM_IRQHandler,Default_Handler
+
+ .weak TIM1_CC_IRQHandler
+ .thumb_set TIM1_CC_IRQHandler,Default_Handler
+
+ .weak TIM2_IRQHandler
+ .thumb_set TIM2_IRQHandler,Default_Handler
+
+ .weak TIM16_IRQHandler
+ .thumb_set TIM16_IRQHandler,Default_Handler
+
+ .weak TIM17_IRQHandler
+ .thumb_set TIM17_IRQHandler,Default_Handler
+
+ .weak I2C1_EV_IRQHandler
+ .thumb_set I2C1_EV_IRQHandler,Default_Handler
+
+ .weak I2C1_ER_IRQHandler
+ .thumb_set I2C1_ER_IRQHandler,Default_Handler
+
+ .weak I2C2_EV_IRQHandler
+ .thumb_set I2C2_EV_IRQHandler,Default_Handler
+
+ .weak I2C2_ER_IRQHandler
+ .thumb_set I2C2_ER_IRQHandler,Default_Handler
+
+ .weak SPI1_IRQHandler
+ .thumb_set SPI1_IRQHandler,Default_Handler
+
+ .weak SPI2_IRQHandler
+ .thumb_set SPI2_IRQHandler,Default_Handler
+
+ .weak USART1_IRQHandler
+ .thumb_set USART1_IRQHandler,Default_Handler
+
+ .weak USART2_IRQHandler
+ .thumb_set USART2_IRQHandler,Default_Handler
+
+ .weak LPUART1_IRQHandler
+ .thumb_set LPUART1_IRQHandler,Default_Handler
+
+ .weak LPTIM1_IRQHandler
+ .thumb_set LPTIM1_IRQHandler,Default_Handler
+
+ .weak LPTIM2_IRQHandler
+ .thumb_set LPTIM2_IRQHandler,Default_Handler
+
+ .weak EXTI15_10_IRQHandler
+ .thumb_set EXTI15_10_IRQHandler,Default_Handler
+
+ .weak RTC_Alarm_IRQHandler
+ .thumb_set RTC_Alarm_IRQHandler,Default_Handler
+
+ .weak LPTIM3_IRQHandler
+ .thumb_set LPTIM3_IRQHandler,Default_Handler
+
+ .weak SUBGHZSPI_IRQHandler
+ .thumb_set SUBGHZSPI_IRQHandler,Default_Handler
+
+ .weak HSEM_IRQHandler
+ .thumb_set HSEM_IRQHandler,Default_Handler
+
+ .weak I2C3_EV_IRQHandler
+ .thumb_set I2C3_EV_IRQHandler,Default_Handler
+
+ .weak I2C3_ER_IRQHandler
+ .thumb_set I2C3_ER_IRQHandler,Default_Handler
+
+ .weak SUBGHZ_Radio_IRQHandler
+ .thumb_set SUBGHZ_Radio_IRQHandler,Default_Handler
+
+ .weak AES_IRQHandler
+ .thumb_set AES_IRQHandler,Default_Handler
+
+ .weak RNG_IRQHandler
+ .thumb_set RNG_IRQHandler,Default_Handler
+
+ .weak PKA_IRQHandler
+ .thumb_set PKA_IRQHandler,Default_Handler
+
+ .weak DMA2_Channel1_IRQHandler
+ .thumb_set DMA2_Channel1_IRQHandler,Default_Handler
+
+ .weak DMA2_Channel2_IRQHandler
+ .thumb_set DMA2_Channel2_IRQHandler,Default_Handler
+
+ .weak DMA2_Channel3_IRQHandler
+ .thumb_set DMA2_Channel3_IRQHandler,Default_Handler
+
+ .weak DMA2_Channel4_IRQHandler
+ .thumb_set DMA2_Channel4_IRQHandler,Default_Handler
+
+ .weak DMA2_Channel5_IRQHandler
+ .thumb_set DMA2_Channel5_IRQHandler,Default_Handler
+
+ .weak DMA2_Channel6_IRQHandler
+ .thumb_set DMA2_Channel6_IRQHandler,Default_Handler
+
+ .weak DMA2_Channel7_IRQHandler
+ .thumb_set DMA2_Channel7_IRQHandler,Default_Handler
+
+ .weak DMAMUX1_OVR_IRQHandler
+ .thumb_set DMAMUX1_OVR_IRQHandler,Default_Handler
+
+ .weak SystemInit
+
+/************************ (C) COPYRIGHT STMicroelectonics *****END OF FILE****/
diff --git a/targets/TARGET_STM/TARGET_STM32WL/TARGET_STM32WLE5xB/TOOLCHAIN_GCC_ARM/stm32wle5xb.ld b/targets/TARGET_STM/TARGET_STM32WL/TARGET_STM32WLE5xB/TOOLCHAIN_GCC_ARM/stm32wle5xb.ld
new file mode 100644
index 0000000..5f47993
--- /dev/null
+++ b/targets/TARGET_STM/TARGET_STM32WL/TARGET_STM32WLE5xB/TOOLCHAIN_GCC_ARM/stm32wle5xb.ld
@@ -0,0 +1,203 @@
+/* Linker script to configure memory regions. */
+/*
+ * SPDX-License-Identifier: BSD-3-Clause
+ ******************************************************************************
+ * @attention
+ *
+ * Copyright (c) 2016-2020 STMicroelectronics.
+ * All rights reserved.
+ *
+ * This software component is licensed by ST under BSD 3-Clause license,
+ * the "License"; You may not use this file except in compliance with the
+ * License. You may obtain a copy of the License at:
+ * opensource.org/licenses/BSD-3-Clause
+ *
+ ******************************************************************************
+*/
+
+#include "../cmsis_nvic.h"
+
+
+#if !defined(MBED_APP_START)
+ #define MBED_APP_START MBED_ROM_START
+#endif
+
+#if !defined(MBED_APP_SIZE)
+ #define MBED_APP_SIZE MBED_ROM_SIZE
+#endif
+
+#if !defined(MBED_CONF_TARGET_BOOT_STACK_SIZE)
+ /* This value is normally defined by the tools
+ to 0x1000 for bare metal and 0x400 for RTOS */
+ #define MBED_CONF_TARGET_BOOT_STACK_SIZE 0x400
+#endif
+
+/* Round up VECTORS_SIZE to 8 bytes */
+#define VECTORS_SIZE (((NVIC_NUM_VECTORS * 4) + 7) & 0xFFFFFFF8)
+
+MEMORY
+{
+ FLASH (rx) : ORIGIN = MBED_APP_START, LENGTH = MBED_APP_SIZE
+ RAM (rwx) : ORIGIN = MBED_RAM_START + VECTORS_SIZE, LENGTH = MBED_RAM_SIZE - VECTORS_SIZE
+}
+
+/* Linker script to place sections and symbol values. Should be used together
+ * with other linker script that defines memory regions FLASH and RAM.
+ * It references following symbols, which must be defined in code:
+ * Reset_Handler : Entry of reset handler
+ *
+ * It defines following symbols, which code can use without definition:
+ * __exidx_start
+ * __exidx_end
+ * __etext
+ * __data_start__
+ * __preinit_array_start
+ * __preinit_array_end
+ * __init_array_start
+ * __init_array_end
+ * __fini_array_start
+ * __fini_array_end
+ * __data_end__
+ * __bss_start__
+ * __bss_end__
+ * __end__
+ * end
+ * __HeapLimit
+ * __StackLimit
+ * __StackTop
+ * __stack
+ * _estack
+ */
+ENTRY(Reset_Handler)
+
+SECTIONS
+{
+ .text :
+ {
+ KEEP(*(.isr_vector))
+ *(.text*)
+
+ KEEP(*(.init))
+ KEEP(*(.fini))
+
+ /* .ctors */
+ *crtbegin.o(.ctors)
+ *crtbegin?.o(.ctors)
+ *(EXCLUDE_FILE(*crtend?.o *crtend.o) .ctors)
+ *(SORT(.ctors.*))
+ *(.ctors)
+
+ /* .dtors */
+ *crtbegin.o(.dtors)
+ *crtbegin?.o(.dtors)
+ *(EXCLUDE_FILE(*crtend?.o *crtend.o) .dtors)
+ *(SORT(.dtors.*))
+ *(.dtors)
+
+ *(.rodata*)
+
+ KEEP(*(.eh_frame*))
+ } > FLASH
+
+ .ARM.extab :
+ {
+ *(.ARM.extab* .gnu.linkonce.armextab.*)
+ } > FLASH
+
+ __exidx_start = .;
+ .ARM.exidx :
+ {
+ *(.ARM.exidx* .gnu.linkonce.armexidx.*)
+ } > FLASH
+ __exidx_end = .;
+
+ __etext = .;
+ _sidata = .;
+
+ .data : AT (__etext)
+ {
+ __data_start__ = .;
+ _sdata = .;
+ *(vtable)
+ *(.data*)
+
+ . = ALIGN(8);
+ /* preinit data */
+ PROVIDE_HIDDEN (__preinit_array_start = .);
+ KEEP(*(.preinit_array))
+ PROVIDE_HIDDEN (__preinit_array_end = .);
+
+ . = ALIGN(8);
+ /* init data */
+ PROVIDE_HIDDEN (__init_array_start = .);
+ KEEP(*(SORT(.init_array.*)))
+ KEEP(*(.init_array))
+ PROVIDE_HIDDEN (__init_array_end = .);
+
+ . = ALIGN(8);
+ /* finit data */
+ PROVIDE_HIDDEN (__fini_array_start = .);
+ KEEP(*(SORT(.fini_array.*)))
+ KEEP(*(.fini_array))
+ PROVIDE_HIDDEN (__fini_array_end = .);
+
+ KEEP(*(.jcr*))
+ . = ALIGN(8);
+ /* All data end */
+ __data_end__ = .;
+ _edata = .;
+
+ } > RAM
+
+ /* Uninitialized data section
+ * This region is not initialized by the C/C++ library and can be used to
+ * store state across soft reboots. */
+ .uninitialized (NOLOAD):
+ {
+ . = ALIGN(32);
+ __uninitialized_start = .;
+ *(.uninitialized)
+ KEEP(*(.keep.uninitialized))
+ . = ALIGN(32);
+ __uninitialized_end = .;
+ } > RAM
+
+ .bss :
+ {
+ . = ALIGN(8);
+ __bss_start__ = .;
+ _sbss = .;
+ *(.bss*)
+ *(COMMON)
+ . = ALIGN(8);
+ __bss_end__ = .;
+ _ebss = .;
+ } > RAM
+
+ .heap (COPY):
+ {
+ __end__ = .;
+ PROVIDE(end = .);
+ *(.heap*)
+ . = ORIGIN(RAM) + LENGTH(RAM) - MBED_CONF_TARGET_BOOT_STACK_SIZE;
+ __HeapLimit = .;
+ } > RAM
+
+ /* .stack_dummy section doesn't contains any symbols. It is only
+ * used for linker to calculate size of stack sections, and assign
+ * values to stack symbols later */
+ .stack_dummy (COPY):
+ {
+ *(.stack*)
+ } > RAM
+
+ /* Set stack top to end of RAM, and stack limit move down by
+ * size of stack_dummy section */
+ __StackTop = ORIGIN(RAM) + LENGTH(RAM);
+ _estack = __StackTop;
+ __StackLimit = __StackTop - MBED_CONF_TARGET_BOOT_STACK_SIZE;
+ PROVIDE(__stack = __StackTop);
+
+ /* Check if data + heap + stack exceeds RAM limit */
+ ASSERT(__StackLimit >= __HeapLimit, "region RAM overflowed with stack")
+}
diff --git a/targets/TARGET_STM/TARGET_STM32WL/TARGET_STM32WLE5xB/TOOLCHAIN_IAR/startup_stm32wle5xx.S b/targets/TARGET_STM/TARGET_STM32WL/TARGET_STM32WLE5xB/TOOLCHAIN_IAR/startup_stm32wle5xx.S
new file mode 100644
index 0000000..341ee9e
--- /dev/null
+++ b/targets/TARGET_STM/TARGET_STM32WL/TARGET_STM32WLE5xB/TOOLCHAIN_IAR/startup_stm32wle5xx.S
@@ -0,0 +1,494 @@
+;********************************************************************************
+;* File Name : startup_stm32wle5xx.s
+;* Author : MCD Application Team
+;* Description : M4 core vector table of the STM32WLxxxx devices for the
+;* IAR (EWARM) toolchain.
+;*
+;* This module performs:
+;* - Set the initial SP
+;* - Set the initial PC == _iar_program_start,
+;* - Set the vector table entries with the exceptions ISR
+;* address.
+;* - Branches to main in the C library (which eventually
+;* calls main()).
+;* After Reset the Cortex-M4 processor is in Thread mode,
+;* priority is Privileged, and the Stack is set to Main.
+;********************************************************************************
+;*
+;* Copyright (c) 2020 STMicroelectronics. All rights reserved.
+;*
+;* This software component is licensed by ST under Apache License, Version 2.0,
+;* the "License"; You may not use this file except in compliance with the
+;* License. You may obtain a copy of the License at:
+;* opensource.org/licenses/Apache-2.0
+;
+;*******************************************************************************
+;
+;
+; The modules in this file are included in the libraries, and may be replaced
+; by any user-defined modules that define the PUBLIC symbol _program_start or
+; a user defined start symbol.
+; To override the cstartup defined in the library, simply add your modified
+; version to the workbench project.
+;
+; The vector table is normally located at address 0.
+; When debugging in RAM, it can be located in RAM, aligned to at least 2^6.
+; The name "__vector_table" has special meaning for C-SPY:
+; it is where the SP start value is found, and the NVIC vector
+; table register (VTOR) is initialized to this address if != 0.
+;
+; Cortex-M version
+;
+
+ MODULE ?cstartup
+
+ ;; Forward declaration of sections.
+ SECTION CSTACK:DATA:NOROOT(3)
+
+ SECTION .intvec:CODE:NOROOT(2)
+
+ EXTERN __iar_program_start
+ EXTERN SystemInit
+ PUBLIC __vector_table
+
+ DATA
+__vector_table
+ DCD sfe(CSTACK)
+ DCD Reset_Handler ; Reset Handler
+
+ DCD NMI_Handler ; NMI Handler
+ DCD HardFault_Handler ; Hard Fault Handler
+ DCD MemManage_Handler ; MPU Fault Handler
+ DCD BusFault_Handler ; Bus Fault Handler
+ DCD UsageFault_Handler ; Usage Fault Handler
+ DCD 0 ; Reserved
+ DCD 0 ; Reserved
+ DCD 0 ; Reserved
+ DCD 0 ; Reserved
+ DCD SVC_Handler ; SVCall Handler
+ DCD DebugMon_Handler ; Debug Monitor Handler
+ DCD 0 ; Reserved
+ DCD PendSV_Handler ; PendSV Handler
+ DCD SysTick_Handler ; SysTick Handler
+
+ ; External Interrupts
+ DCD WWDG_IRQHandler ; Window WatchDog
+ DCD PVD_PVM_IRQHandler ; PVD and PVM Interrupt
+ DCD TAMP_STAMP_LSECSS_SSRU_IRQHandler ; RTC Tamper, RTC TimeStamp, LSECSS and RTC SSRU Interrupts
+ DCD RTC_WKUP_IRQHandler ; RTC Wakeup Interrupt
+ DCD FLASH_IRQHandler ; FLASH global Interrupt
+ DCD RCC_IRQHandler ; RCC Interrupt
+ DCD EXTI0_IRQHandler ; EXTI Line 0 Interrupt
+ DCD EXTI1_IRQHandler ; EXTI Line 1 Interrupt
+ DCD EXTI2_IRQHandler ; EXTI Line 2 Interrupt
+ DCD EXTI3_IRQHandler ; EXTI Line 3 Interrupt
+ DCD EXTI4_IRQHandler ; EXTI Line 4 Interrupt
+ DCD DMA1_Channel1_IRQHandler ; DMA1 Channel 1 Interrupt
+ DCD DMA1_Channel2_IRQHandler ; DMA1 Channel 2 Interrupt
+ DCD DMA1_Channel3_IRQHandler ; DMA1 Channel 3 Interrupt
+ DCD DMA1_Channel4_IRQHandler ; DMA1 Channel 4 Interrupt
+ DCD DMA1_Channel5_IRQHandler ; DMA1 Channel 5 Interrupt
+ DCD DMA1_Channel6_IRQHandler ; DMA1 Channel 6 Interrupt
+ DCD DMA1_Channel7_IRQHandler ; DMA1 Channel 7 Interrupt
+ DCD ADC_IRQHandler ; ADC Interrupt
+ DCD DAC_IRQHandler ; DAC Interrupt
+ DCD 0 ; Reserved
+ DCD COMP_IRQHandler ; COMP1 and COMP2 Interrupts
+ DCD EXTI9_5_IRQHandler ; EXTI Lines [9:5] Interrupt
+ DCD TIM1_BRK_IRQHandler ; TIM1 Break Interrupt
+ DCD TIM1_UP_IRQHandler ; TIM1 Update Interrupt
+ DCD TIM1_TRG_COM_IRQHandler ; TIM1 Trigger and Communication Interrupts
+ DCD TIM1_CC_IRQHandler ; TIM1 Capture Compare Interrupt
+ DCD TIM2_IRQHandler ; TIM2 Global Interrupt
+ DCD TIM16_IRQHandler ; TIM16 Global Interrupt
+ DCD TIM17_IRQHandler ; TIM17 Global Interrupt
+ DCD I2C1_EV_IRQHandler ; I2C1 Event Interrupt
+ DCD I2C1_ER_IRQHandler ; I2C1 Error Interrupt
+ DCD I2C2_EV_IRQHandler ; I2C2 Event Interrupt
+ DCD I2C2_ER_IRQHandler ; I2C2 Error Interrupt
+ DCD SPI1_IRQHandler ; SPI1 Interrupt
+ DCD SPI2_IRQHandler ; SPI2 Interrupt
+ DCD USART1_IRQHandler ; USART1 Interrupt
+ DCD USART2_IRQHandler ; USART2 Interrupt
+ DCD LPUART1_IRQHandler ; LPUART1 Interrupt
+ DCD LPTIM1_IRQHandler ; LPTIM1 Global Interrupt
+ DCD LPTIM2_IRQHandler ; LPTIM2 Global Interrupt
+ DCD EXTI15_10_IRQHandler ; EXTI Lines [15:10] Interrupt
+ DCD RTC_Alarm_IRQHandler ; RTC Alarms (A and B) Interrupt
+ DCD LPTIM3_IRQHandler ; LPTIM3 Global Interrupt
+ DCD SUBGHZSPI_IRQHandler ; SUBGHZSPI Interrupt
+ DCD 0 ; Reserved
+ DCD 0 ; Reserved
+ DCD HSEM_IRQHandler ; HSEM0 Interrupt
+ DCD I2C3_EV_IRQHandler ; I2C3 Event Interrupt
+ DCD I2C3_ER_IRQHandler ; I2C3 Error Interrupt
+ DCD SUBGHZ_Radio_IRQHandler ; SUBGHZ Radio Interrupt
+ DCD AES_IRQHandler ; AES Interrupt
+ DCD RNG_IRQHandler ; RNG1 Interrupt
+ DCD PKA_IRQHandler ; PKA Interrupt
+ DCD DMA2_Channel1_IRQHandler ; DMA2 Channel 1 Interrupt
+ DCD DMA2_Channel2_IRQHandler ; DMA2 Channel 2 Interrupt
+ DCD DMA2_Channel3_IRQHandler ; DMA2 Channel 3 Interrupt
+ DCD DMA2_Channel4_IRQHandler ; DMA2 Channel 4 Interrupt
+ DCD DMA2_Channel5_IRQHandler ; DMA2 Channel 5 Interrupt
+ DCD DMA2_Channel6_IRQHandler ; DMA2 Channel 6 Interrupt
+ DCD DMA2_Channel7_IRQHandler ; DMA2 Channel 7 Interrupt
+ DCD DMAMUX1_OVR_IRQHandler ; DMAMUX overrun Interrupt
+
+;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;
+;;
+;; Default interrupt handlers.
+;;
+ THUMB
+
+ PUBWEAK Reset_Handler
+ SECTION .text:CODE:NOROOT:REORDER(2)
+Reset_Handler
+ LDR R0, =SystemInit
+ BLX R0
+ LDR R0, =__iar_program_start
+ BX R0
+
+ PUBWEAK NMI_Handler
+ SECTION .text:CODE:NOROOT:REORDER(1)
+NMI_Handler
+ B NMI_Handler
+
+ PUBWEAK HardFault_Handler
+ SECTION .text:CODE:NOROOT:REORDER(1)
+HardFault_Handler
+ B HardFault_Handler
+
+ PUBWEAK MemManage_Handler
+ SECTION .text:CODE:NOROOT:REORDER(1)
+MemManage_Handler
+ B MemManage_Handler
+
+ PUBWEAK BusFault_Handler
+ SECTION .text:CODE:NOROOT:REORDER(1)
+BusFault_Handler
+ B BusFault_Handler
+
+ PUBWEAK UsageFault_Handler
+ SECTION .text:CODE:NOROOT:REORDER(1)
+UsageFault_Handler
+ B UsageFault_Handler
+
+ PUBWEAK SVC_Handler
+ SECTION .text:CODE:NOROOT:REORDER(1)
+SVC_Handler
+ B SVC_Handler
+
+ PUBWEAK DebugMon_Handler
+ SECTION .text:CODE:NOROOT:REORDER(1)
+DebugMon_Handler
+ B DebugMon_Handler
+
+ PUBWEAK PendSV_Handler
+ SECTION .text:CODE:NOROOT:REORDER(1)
+PendSV_Handler
+ B PendSV_Handler
+
+ PUBWEAK SysTick_Handler
+ SECTION .text:CODE:NOROOT:REORDER(1)
+SysTick_Handler
+ B SysTick_Handler
+
+ PUBWEAK WWDG_IRQHandler
+ SECTION .text:CODE:NOROOT:REORDER(1)
+WWDG_IRQHandler
+ B WWDG_IRQHandler
+
+ PUBWEAK PVD_PVM_IRQHandler
+ SECTION .text:CODE:NOROOT:REORDER(1)
+PVD_PVM_IRQHandler
+ B PVD_PVM_IRQHandler
+
+ PUBWEAK TAMP_STAMP_LSECSS_SSRU_IRQHandler
+ SECTION .text:CODE:NOROOT:REORDER(1)
+TAMP_STAMP_LSECSS_SSRU_IRQHandler
+ B TAMP_STAMP_LSECSS_SSRU_IRQHandler
+
+ PUBWEAK RTC_WKUP_IRQHandler
+ SECTION .text:CODE:NOROOT:REORDER(1)
+RTC_WKUP_IRQHandler
+ B RTC_WKUP_IRQHandler
+
+ PUBWEAK FLASH_IRQHandler
+ SECTION .text:CODE:NOROOT:REORDER(1)
+FLASH_IRQHandler
+ B FLASH_IRQHandler
+
+ PUBWEAK RCC_IRQHandler
+ SECTION .text:CODE:NOROOT:REORDER(1)
+RCC_IRQHandler
+ B RCC_IRQHandler
+
+ PUBWEAK EXTI0_IRQHandler
+ SECTION .text:CODE:NOROOT:REORDER(1)
+EXTI0_IRQHandler
+ B EXTI0_IRQHandler
+
+ PUBWEAK EXTI1_IRQHandler
+ SECTION .text:CODE:NOROOT:REORDER(1)
+EXTI1_IRQHandler
+ B EXTI1_IRQHandler
+
+ PUBWEAK EXTI2_IRQHandler
+ SECTION .text:CODE:NOROOT:REORDER(1)
+EXTI2_IRQHandler
+ B EXTI2_IRQHandler
+
+ PUBWEAK EXTI3_IRQHandler
+ SECTION .text:CODE:NOROOT:REORDER(1)
+EXTI3_IRQHandler
+ B EXTI3_IRQHandler
+
+ PUBWEAK EXTI4_IRQHandler
+ SECTION .text:CODE:NOROOT:REORDER(1)
+EXTI4_IRQHandler
+ B EXTI4_IRQHandler
+
+ PUBWEAK DMA1_Channel1_IRQHandler
+ SECTION .text:CODE:NOROOT:REORDER(1)
+DMA1_Channel1_IRQHandler
+ B DMA1_Channel1_IRQHandler
+
+ PUBWEAK DMA1_Channel2_IRQHandler
+ SECTION .text:CODE:NOROOT:REORDER(1)
+DMA1_Channel2_IRQHandler
+ B DMA1_Channel2_IRQHandler
+
+ PUBWEAK DMA1_Channel3_IRQHandler
+ SECTION .text:CODE:NOROOT:REORDER(1)
+DMA1_Channel3_IRQHandler
+ B DMA1_Channel3_IRQHandler
+
+ PUBWEAK DMA1_Channel4_IRQHandler
+ SECTION .text:CODE:NOROOT:REORDER(1)
+DMA1_Channel4_IRQHandler
+ B DMA1_Channel4_IRQHandler
+
+ PUBWEAK DMA1_Channel5_IRQHandler
+ SECTION .text:CODE:NOROOT:REORDER(1)
+DMA1_Channel5_IRQHandler
+ B DMA1_Channel5_IRQHandler
+
+ PUBWEAK DMA1_Channel6_IRQHandler
+ SECTION .text:CODE:NOROOT:REORDER(1)
+DMA1_Channel6_IRQHandler
+ B DMA1_Channel6_IRQHandler
+
+ PUBWEAK DMA1_Channel7_IRQHandler
+ SECTION .text:CODE:NOROOT:REORDER(1)
+DMA1_Channel7_IRQHandler
+ B DMA1_Channel7_IRQHandler
+
+ PUBWEAK ADC_IRQHandler
+ SECTION .text:CODE:NOROOT:REORDER(1)
+ADC_IRQHandler
+ B ADC_IRQHandler
+
+ PUBWEAK DAC_IRQHandler
+ SECTION .text:CODE:NOROOT:REORDER(1)
+DAC_IRQHandler
+ B DAC_IRQHandler
+
+ PUBWEAK COMP_IRQHandler
+ SECTION .text:CODE:NOROOT:REORDER(1)
+COMP_IRQHandler
+ B COMP_IRQHandler
+
+ PUBWEAK EXTI9_5_IRQHandler
+ SECTION .text:CODE:NOROOT:REORDER(1)
+EXTI9_5_IRQHandler
+ B EXTI9_5_IRQHandler
+
+ PUBWEAK TIM1_BRK_IRQHandler
+ SECTION .text:CODE:NOROOT:REORDER(1)
+TIM1_BRK_IRQHandler
+ B TIM1_BRK_IRQHandler
+
+ PUBWEAK TIM1_UP_IRQHandler
+ SECTION .text:CODE:NOROOT:REORDER(1)
+TIM1_UP_IRQHandler
+ B TIM1_UP_IRQHandler
+
+ PUBWEAK TIM1_TRG_COM_IRQHandler
+ SECTION .text:CODE:NOROOT:REORDER(1)
+TIM1_TRG_COM_IRQHandler
+ B TIM1_TRG_COM_IRQHandler
+
+ PUBWEAK TIM1_CC_IRQHandler
+ SECTION .text:CODE:NOROOT:REORDER(1)
+TIM1_CC_IRQHandler
+ B TIM1_CC_IRQHandler
+
+ PUBWEAK TIM2_IRQHandler
+ SECTION .text:CODE:NOROOT:REORDER(1)
+TIM2_IRQHandler
+ B TIM2_IRQHandler
+
+ PUBWEAK TIM16_IRQHandler
+ SECTION .text:CODE:NOROOT:REORDER(1)
+TIM16_IRQHandler
+ B TIM16_IRQHandler
+
+ PUBWEAK TIM17_IRQHandler
+ SECTION .text:CODE:NOROOT:REORDER(1)
+TIM17_IRQHandler
+ B TIM17_IRQHandler
+
+ PUBWEAK I2C1_EV_IRQHandler
+ SECTION .text:CODE:NOROOT:REORDER(1)
+I2C1_EV_IRQHandler
+ B I2C1_EV_IRQHandler
+
+ PUBWEAK I2C1_ER_IRQHandler
+ SECTION .text:CODE:NOROOT:REORDER(1)
+I2C1_ER_IRQHandler
+ B I2C1_ER_IRQHandler
+
+ PUBWEAK I2C2_EV_IRQHandler
+ SECTION .text:CODE:NOROOT:REORDER(1)
+I2C2_EV_IRQHandler
+ B I2C2_EV_IRQHandler
+
+ PUBWEAK I2C2_ER_IRQHandler
+ SECTION .text:CODE:NOROOT:REORDER(1)
+I2C2_ER_IRQHandler
+ B I2C2_ER_IRQHandler
+
+ PUBWEAK SPI1_IRQHandler
+ SECTION .text:CODE:NOROOT:REORDER(1)
+SPI1_IRQHandler
+ B SPI1_IRQHandler
+
+ PUBWEAK SPI2_IRQHandler
+ SECTION .text:CODE:NOROOT:REORDER(1)
+SPI2_IRQHandler
+ B SPI2_IRQHandler
+
+ PUBWEAK USART1_IRQHandler
+ SECTION .text:CODE:NOROOT:REORDER(1)
+USART1_IRQHandler
+ B USART1_IRQHandler
+
+ PUBWEAK USART2_IRQHandler
+ SECTION .text:CODE:NOROOT:REORDER(1)
+USART2_IRQHandler
+ B USART2_IRQHandler
+
+ PUBWEAK LPUART1_IRQHandler
+ SECTION .text:CODE:NOROOT:REORDER(1)
+LPUART1_IRQHandler
+ B LPUART1_IRQHandler
+
+ PUBWEAK LPTIM1_IRQHandler
+ SECTION .text:CODE:NOROOT:REORDER(1)
+LPTIM1_IRQHandler
+ B LPTIM1_IRQHandler
+
+ PUBWEAK LPTIM2_IRQHandler
+ SECTION .text:CODE:NOROOT:REORDER(1)
+LPTIM2_IRQHandler
+ B LPTIM2_IRQHandler
+
+ PUBWEAK EXTI15_10_IRQHandler
+ SECTION .text:CODE:NOROOT:REORDER(1)
+EXTI15_10_IRQHandler
+ B EXTI15_10_IRQHandler
+
+ PUBWEAK RTC_Alarm_IRQHandler
+ SECTION .text:CODE:NOROOT:REORDER(1)
+RTC_Alarm_IRQHandler
+ B RTC_Alarm_IRQHandler
+
+ PUBWEAK LPTIM3_IRQHandler
+ SECTION .text:CODE:NOROOT:REORDER(1)
+LPTIM3_IRQHandler
+ B LPTIM3_IRQHandler
+
+ PUBWEAK SUBGHZSPI_IRQHandler
+ SECTION .text:CODE:NOROOT:REORDER(1)
+SUBGHZSPI_IRQHandler
+ B SUBGHZSPI_IRQHandler
+
+ PUBWEAK HSEM_IRQHandler
+ SECTION .text:CODE:NOROOT:REORDER(1)
+HSEM_IRQHandler
+ B HSEM_IRQHandler
+
+ PUBWEAK I2C3_EV_IRQHandler
+ SECTION .text:CODE:NOROOT:REORDER(1)
+I2C3_EV_IRQHandler
+ B I2C3_EV_IRQHandler
+
+ PUBWEAK I2C3_ER_IRQHandler
+ SECTION .text:CODE:NOROOT:REORDER(1)
+I2C3_ER_IRQHandler
+ B I2C3_ER_IRQHandler
+
+ PUBWEAK SUBGHZ_Radio_IRQHandler
+ SECTION .text:CODE:NOROOT:REORDER(1)
+SUBGHZ_Radio_IRQHandler
+ B SUBGHZ_Radio_IRQHandler
+
+ PUBWEAK AES_IRQHandler
+ SECTION .text:CODE:NOROOT:REORDER(1)
+AES_IRQHandler
+ B AES_IRQHandler
+
+ PUBWEAK RNG_IRQHandler
+ SECTION .text:CODE:NOROOT:REORDER(1)
+RNG_IRQHandler
+ B RNG_IRQHandler
+
+ PUBWEAK PKA_IRQHandler
+ SECTION .text:CODE:NOROOT:REORDER(1)
+PKA_IRQHandler
+ B PKA_IRQHandler
+
+ PUBWEAK DMA2_Channel1_IRQHandler
+ SECTION .text:CODE:NOROOT:REORDER(1)
+DMA2_Channel1_IRQHandler
+ B DMA2_Channel1_IRQHandler
+
+ PUBWEAK DMA2_Channel2_IRQHandler
+ SECTION .text:CODE:NOROOT:REORDER(1)
+DMA2_Channel2_IRQHandler
+ B DMA2_Channel2_IRQHandler
+
+ PUBWEAK DMA2_Channel3_IRQHandler
+ SECTION .text:CODE:NOROOT:REORDER(1)
+DMA2_Channel3_IRQHandler
+ B DMA2_Channel3_IRQHandler
+
+ PUBWEAK DMA2_Channel4_IRQHandler
+ SECTION .text:CODE:NOROOT:REORDER(1)
+DMA2_Channel4_IRQHandler
+ B DMA2_Channel4_IRQHandler
+
+ PUBWEAK DMA2_Channel5_IRQHandler
+ SECTION .text:CODE:NOROOT:REORDER(1)
+DMA2_Channel5_IRQHandler
+ B DMA2_Channel5_IRQHandler
+
+ PUBWEAK DMA2_Channel6_IRQHandler
+ SECTION .text:CODE:NOROOT:REORDER(1)
+DMA2_Channel6_IRQHandler
+ B DMA2_Channel6_IRQHandler
+
+ PUBWEAK DMA2_Channel7_IRQHandler
+ SECTION .text:CODE:NOROOT:REORDER(1)
+DMA2_Channel7_IRQHandler
+ B DMA2_Channel7_IRQHandler
+
+ PUBWEAK DMAMUX1_OVR_IRQHandler
+ SECTION .text:CODE:NOROOT:REORDER(1)
+DMAMUX1_OVR_IRQHandler
+ B DMAMUX1_OVR_IRQHandler
+
+ END
+
+;************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE*****
diff --git a/targets/TARGET_STM/TARGET_STM32WL/TARGET_STM32WLE5xB/TOOLCHAIN_IAR/stm32wle5xb.icf b/targets/TARGET_STM/TARGET_STM32WL/TARGET_STM32WLE5xB/TOOLCHAIN_IAR/stm32wle5xb.icf
new file mode 100644
index 0000000..7fb4af2
--- /dev/null
+++ b/targets/TARGET_STM/TARGET_STM32WL/TARGET_STM32WLE5xB/TOOLCHAIN_IAR/stm32wle5xb.icf
@@ -0,0 +1,59 @@
+/* Linker script to configure memory regions.
+ *
+ * SPDX-License-Identifier: BSD-3-Clause
+ ******************************************************************************
+ * @attention
+ *
+ * Copyright (c) 2016-2020 STMicroelectronics.
+ * All rights reserved.
+ *
+ * This software component is licensed by ST under BSD 3-Clause license,
+ * the "License"; You may not use this file except in compliance with the
+ * License. You may obtain a copy of the License at:
+ * opensource.org/licenses/BSD-3-Clause
+ *
+ ******************************************************************************
+*/
+/* Device specific values */
+
+/* Tools provide -DMBED_ROM_START=xxx -DMBED_ROM_SIZE=xxx -DMBED_RAM_START=xxx -DMBED_RAM_SIZE=xxx */
+
+define symbol VECTORS = 78; /* This value must match NVIC_NUM_VECTORS in cmsis_nvic.h */
+define symbol HEAP_SIZE = 0x1000;
+
+/* Common - Do not change */
+
+if (!isdefinedsymbol(MBED_APP_START)) {
+ define symbol MBED_APP_START = MBED_ROM_START;
+}
+
+if (!isdefinedsymbol(MBED_APP_SIZE)) {
+ define symbol MBED_APP_SIZE = MBED_ROM_SIZE;
+}
+
+if (!isdefinedsymbol(MBED_CONF_TARGET_BOOT_STACK_SIZE)) {
+ /* This value is normally defined by the tools
+ to 0x1000 for bare metal and 0x400 for RTOS */
+ define symbol MBED_CONF_TARGET_BOOT_STACK_SIZE = 0x400;
+}
+
+/* Round up VECTORS_SIZE to 8 bytes */
+define symbol VECTORS_SIZE = ((VECTORS * 4) + 7) & ~7;
+define symbol RAM_REGION_START = MBED_RAM_START + VECTORS_SIZE;
+define symbol RAM_REGION_SIZE = MBED_RAM_SIZE - VECTORS_SIZE;
+
+define memory mem with size = 4G;
+define region ROM_region = mem:[from MBED_APP_START size MBED_APP_SIZE];
+define region RAM_region = mem:[from RAM_REGION_START size RAM_REGION_SIZE];
+
+define block CSTACK with alignment = 8, size = MBED_CONF_TARGET_BOOT_STACK_SIZE { };
+define block HEAP with alignment = 8, size = HEAP_SIZE { };
+
+initialize by copy { readwrite };
+do not initialize { section .noinit };
+
+place at address mem: MBED_APP_START { readonly section .intvec };
+
+place in ROM_region { readonly };
+place in RAM_region { readwrite,
+ block CSTACK, block HEAP };
diff --git a/targets/TARGET_STM/TARGET_STM32WL/TARGET_STM32WLE5xB/cmsis_nvic.h b/targets/TARGET_STM/TARGET_STM32WL/TARGET_STM32WLE5xB/cmsis_nvic.h
new file mode 100644
index 0000000..a18342e
--- /dev/null
+++ b/targets/TARGET_STM/TARGET_STM32WL/TARGET_STM32WLE5xB/cmsis_nvic.h
@@ -0,0 +1,39 @@
+/* mbed Microcontroller Library
+ * SPDX-License-Identifier: BSD-3-Clause
+ ******************************************************************************
+ * @attention
+ *
+ * © Copyright (c) 2016-2020 STMicroelectronics.
+ * All rights reserved.
+ *
+ * This software component is licensed by ST under BSD 3-Clause license,
+ * the "License"; You may not use this file except in compliance with the
+ * License. You may obtain a copy of the License at:
+ * opensource.org/licenses/BSD-3-Clause
+ *
+ ******************************************************************************
+*/
+
+#ifndef MBED_CMSIS_NVIC_H
+#define MBED_CMSIS_NVIC_H
+
+#if !defined(MBED_ROM_START)
+#define MBED_ROM_START 0x8000000
+#endif
+
+#if !defined(MBED_ROM_SIZE)
+#define MBED_ROM_SIZE 0x0 // 0 B
+#endif
+
+#if !defined(MBED_RAM_START)
+#define MBED_RAM_START 0x20000000
+#endif
+
+#if !defined(MBED_RAM_SIZE)
+#define MBED_RAM_SIZE 0x0 // 0 B
+#endif
+
+#define NVIC_NUM_VECTORS 78
+#define NVIC_RAM_VECTOR_ADDRESS MBED_RAM_START
+
+#endif
diff --git a/targets/TARGET_STM/TARGET_STM32WL/TARGET_STM32WLE5xC/TOOLCHAIN_ARM/startup_stm32wle5xx.S b/targets/TARGET_STM/TARGET_STM32WL/TARGET_STM32WLE5xC/TOOLCHAIN_ARM/startup_stm32wle5xx.S
new file mode 100644
index 0000000..29f645e
--- /dev/null
+++ b/targets/TARGET_STM/TARGET_STM32WL/TARGET_STM32WLE5xC/TOOLCHAIN_ARM/startup_stm32wle5xx.S
@@ -0,0 +1,314 @@
+;******************************************************************************
+;* File Name : startup_stm32wle5xx.s
+;* Author : MCD Application Team
+;* Description : STM32WLE5xx devices vector table for MDK-ARM toolchain.
+;* This module performs:
+;* - Set the initial SP
+;* - Set the initial PC == Reset_Handler
+;* - Set the vector table entries with the exceptions ISR address
+;* - Branches to __main in the C library (which eventually
+;* calls main()).
+;* After Reset the CortexM4 processor is in Thread mode,
+;* priority is Privileged, and the Stack is set to Main.
+;* <<< Use Configuration Wizard in Context Menu >>>
+;******************************************************************************
+;* @attention
+;*
+;* Copyright (c) 2020 STMicroelectronics. All rights reserved.
+;*
+;* This software component is licensed by ST under Apache License, Version 2.0,
+;* the "License"; You may not use this file except in compliance with the
+;* License. You may obtain a copy of the License at:
+;* opensource.org/licenses/Apache-2.0
+;*
+;******************************************************************************
+
+ PRESERVE8
+ THUMB
+
+
+; Vector Table Mapped to Address 0 at Reset
+ AREA RESET, DATA, READONLY
+ EXPORT __Vectors
+ EXPORT __Vectors_End
+ EXPORT __Vectors_Size
+
+ IMPORT |Image$$ARM_LIB_STACK$$ZI$$Limit|
+__Vectors DCD |Image$$ARM_LIB_STACK$$ZI$$Limit| ; Top of Stack
+ DCD Reset_Handler ; Reset Handler
+ DCD NMI_Handler ; NMI Handler
+ DCD HardFault_Handler ; Hard Fault Handler
+ DCD MemManage_Handler ; MPU Fault Handler
+ DCD BusFault_Handler ; Bus Fault Handler
+ DCD UsageFault_Handler ; Usage Fault Handler
+ DCD 0 ; Reserved
+ DCD 0 ; Reserved
+ DCD 0 ; Reserved
+ DCD 0 ; Reserved
+ DCD SVC_Handler ; SVCall Handler
+ DCD DebugMon_Handler ; Debug Monitor Handler
+ DCD 0 ; Reserved
+ DCD PendSV_Handler ; PendSV Handler
+ DCD SysTick_Handler ; SysTick Handler
+
+ ; External Interrupts
+ DCD WWDG_IRQHandler ; Window WatchDog
+ DCD PVD_PVM_IRQHandler ; PVD and PVM detector
+ DCD TAMP_STAMP_LSECSS_SSRU_IRQHandler ; RTC Tamper, RTC TimeStamp, LSECSS and RTC SSR Underflow Interrupts
+ DCD RTC_WKUP_IRQHandler ; RTC Wakeup Interrupt
+ DCD FLASH_IRQHandler ; FLASH global Interrupt
+ DCD RCC_IRQHandler ; RCC Interrupt
+ DCD EXTI0_IRQHandler ; EXTI Line 0 Interrupt
+ DCD EXTI1_IRQHandler ; EXTI Line 1 Interrupt
+ DCD EXTI2_IRQHandler ; EXTI Line 2 Interrupt
+ DCD EXTI3_IRQHandler ; EXTI Line 3 Interrup
+ DCD EXTI4_IRQHandler ; EXTI Line 4 Interrupt
+ DCD DMA1_Channel1_IRQHandler ; DMA1 Channel 1 Interrupt
+ DCD DMA1_Channel2_IRQHandler ; DMA1 Channel 2 Interrupt
+ DCD DMA1_Channel3_IRQHandler ; DMA1 Channel 3 Interrupt
+ DCD DMA1_Channel4_IRQHandler ; DMA1 Channel 4 Interrupt
+ DCD DMA1_Channel5_IRQHandler ; DMA1 Channel 5 Interrupt
+ DCD DMA1_Channel6_IRQHandler ; DMA1 Channel 6 Interrupt
+ DCD DMA1_Channel7_IRQHandler ; DMA1 Channel 7 Interrupt
+ DCD ADC_IRQHandler ; ADC Interrupt
+ DCD DAC_IRQHandler ; DAC Interrupt
+ DCD 0 ; Reserved
+ DCD COMP_IRQHandler ; COMP1 and COMP2 Interrupts
+ DCD EXTI9_5_IRQHandler ; EXTI Lines [9:5] Interrupt
+ DCD TIM1_BRK_IRQHandler ; TIM1 Break Interrupt
+ DCD TIM1_UP_IRQHandler ; TIM1 Update Interrupts
+ DCD TIM1_TRG_COM_IRQHandler ; TIM1 Trigger and Communication Interrupts
+ DCD TIM1_CC_IRQHandler ; TIM1 Capture Compare Interrupt
+ DCD TIM2_IRQHandler ; TIM2 Global Interrupt
+ DCD TIM16_IRQHandler ; TIM16 Global Interrupt
+ DCD TIM17_IRQHandler ; TIM17 Global Interrupt
+ DCD I2C1_EV_IRQHandler ; I2C1 Event Interrupt
+ DCD I2C1_ER_IRQHandler ; I2C1 Error Interrupt
+ DCD I2C2_EV_IRQHandler ; I2C2 Event Interrupt
+ DCD I2C2_ER_IRQHandler ; I2C2 Error Interrupt
+ DCD SPI1_IRQHandler ; SPI1 Interrupt
+ DCD SPI2_IRQHandler ; SPI2 Interrupt
+ DCD USART1_IRQHandler ; USART1 Interrupt
+ DCD USART2_IRQHandler ; USART2 Interrupt
+ DCD LPUART1_IRQHandler ; LPUART1 Interrupt
+ DCD LPTIM1_IRQHandler ; LPTIM1 Interrupt
+ DCD LPTIM2_IRQHandler ; LPTIM2 Interrupt
+ DCD EXTI15_10_IRQHandler ; EXTI Lines1[15:10 ]Interrupts
+ DCD RTC_Alarm_IRQHandler ; RTC Alarms (A and B) Interrupt
+ DCD LPTIM3_IRQHandler ; LPTIM3 Interrupt
+ DCD SUBGHZSPI_IRQHandler ; SUBGHZSPI Interrupt
+ DCD 0 ; Reserved
+ DCD 0 ; Reserved
+ DCD HSEM_IRQHandler ; HSEM0 Interrupt
+ DCD I2C3_EV_IRQHandler ; I2C3 Event Interrupt
+ DCD I2C3_ER_IRQHandler ; I2C3 Error Interrupt
+ DCD SUBGHZ_Radio_IRQHandler ; SUBGHZ Radio Interrupt
+ DCD AES_IRQHandler ; AES Interrupt
+ DCD RNG_IRQHandler ; RNG1 Interrupt
+ DCD PKA_IRQHandler ; PKA Interrupt
+ DCD DMA2_Channel1_IRQHandler ; DMA2 Channel 1 Interrupt
+ DCD DMA2_Channel2_IRQHandler ; DMA2 Channel 2 Interrupt
+ DCD DMA2_Channel3_IRQHandler ; DMA2 Channel 3 Interrupt
+ DCD DMA2_Channel4_IRQHandler ; DMA2 Channel 4 Interrupt
+ DCD DMA2_Channel5_IRQHandler ; DMA2 Channel 5 Interrupt
+ DCD DMA2_Channel6_IRQHandler ; DMA2 Channel 6 Interrupt
+ DCD DMA2_Channel7_IRQHandler ; DMA2 Channel 7 Interrupt
+ DCD DMAMUX1_OVR_IRQHandler ; DMAMUX overrun Interrupt
+
+__Vectors_End
+
+__Vectors_Size EQU __Vectors_End - __Vectors
+
+ AREA |.text|, CODE, READONLY
+
+; Reset handler
+Reset_Handler PROC
+ EXPORT Reset_Handler [WEAK]
+ IMPORT SystemInit
+ IMPORT __main
+
+ LDR R0, =SystemInit
+ BLX R0
+ LDR R0, =__main
+ BX R0
+ ENDP
+
+; Dummy Exception Handlers (infinite loops which can be modified)
+
+NMI_Handler PROC
+ EXPORT NMI_Handler [WEAK]
+ B .
+ ENDP
+HardFault_Handler\
+ PROC
+ EXPORT HardFault_Handler [WEAK]
+ B .
+ ENDP
+MemManage_Handler\
+ PROC
+ EXPORT MemManage_Handler [WEAK]
+ B .
+ ENDP
+BusFault_Handler\
+ PROC
+ EXPORT BusFault_Handler [WEAK]
+ B .
+ ENDP
+UsageFault_Handler\
+ PROC
+ EXPORT UsageFault_Handler [WEAK]
+ B .
+ ENDP
+SVC_Handler PROC
+ EXPORT SVC_Handler [WEAK]
+ B .
+ ENDP
+DebugMon_Handler\
+ PROC
+ EXPORT DebugMon_Handler [WEAK]
+ B .
+ ENDP
+PendSV_Handler PROC
+ EXPORT PendSV_Handler [WEAK]
+ B .
+ ENDP
+SysTick_Handler PROC
+ EXPORT SysTick_Handler [WEAK]
+ B .
+ ENDP
+
+Default_Handler PROC
+
+ EXPORT WWDG_IRQHandler [WEAK]
+ EXPORT PVD_PVM_IRQHandler [WEAK]
+ EXPORT TAMP_STAMP_LSECSS_SSRU_IRQHandler [WEAK]
+ EXPORT RTC_WKUP_IRQHandler [WEAK]
+ EXPORT FLASH_IRQHandler [WEAK]
+ EXPORT RCC_IRQHandler [WEAK]
+ EXPORT EXTI0_IRQHandler [WEAK]
+ EXPORT EXTI1_IRQHandler [WEAK]
+ EXPORT EXTI2_IRQHandler [WEAK]
+ EXPORT EXTI3_IRQHandler [WEAK]
+ EXPORT EXTI4_IRQHandler [WEAK]
+ EXPORT DMA1_Channel1_IRQHandler [WEAK]
+ EXPORT DMA1_Channel2_IRQHandler [WEAK]
+ EXPORT DMA1_Channel3_IRQHandler [WEAK]
+ EXPORT DMA1_Channel4_IRQHandler [WEAK]
+ EXPORT DMA1_Channel5_IRQHandler [WEAK]
+ EXPORT DMA1_Channel6_IRQHandler [WEAK]
+ EXPORT DMA1_Channel7_IRQHandler [WEAK]
+ EXPORT ADC_IRQHandler [WEAK]
+ EXPORT DAC_IRQHandler [WEAK]
+ EXPORT COMP_IRQHandler [WEAK]
+ EXPORT EXTI9_5_IRQHandler [WEAK]
+ EXPORT TIM1_BRK_IRQHandler [WEAK]
+ EXPORT TIM1_UP_IRQHandler [WEAK]
+ EXPORT TIM1_TRG_COM_IRQHandler [WEAK]
+ EXPORT TIM1_CC_IRQHandler [WEAK]
+ EXPORT TIM2_IRQHandler [WEAK]
+ EXPORT TIM16_IRQHandler [WEAK]
+ EXPORT TIM17_IRQHandler [WEAK]
+ EXPORT I2C1_EV_IRQHandler [WEAK]
+ EXPORT I2C1_ER_IRQHandler [WEAK]
+ EXPORT I2C2_EV_IRQHandler [WEAK]
+ EXPORT I2C2_ER_IRQHandler [WEAK]
+ EXPORT SPI1_IRQHandler [WEAK]
+ EXPORT SPI2_IRQHandler [WEAK]
+ EXPORT USART1_IRQHandler [WEAK]
+ EXPORT USART2_IRQHandler [WEAK]
+ EXPORT LPUART1_IRQHandler [WEAK]
+ EXPORT LPTIM1_IRQHandler [WEAK]
+ EXPORT LPTIM2_IRQHandler [WEAK]
+ EXPORT EXTI15_10_IRQHandler [WEAK]
+ EXPORT RTC_Alarm_IRQHandler [WEAK]
+ EXPORT LPTIM3_IRQHandler [WEAK]
+ EXPORT SUBGHZSPI_IRQHandler [WEAK]
+ EXPORT HSEM_IRQHandler [WEAK]
+ EXPORT I2C3_EV_IRQHandler [WEAK]
+ EXPORT I2C3_ER_IRQHandler [WEAK]
+ EXPORT SUBGHZ_Radio_IRQHandler [WEAK]
+ EXPORT AES_IRQHandler [WEAK]
+ EXPORT RNG_IRQHandler [WEAK]
+ EXPORT PKA_IRQHandler [WEAK]
+ EXPORT DMA2_Channel1_IRQHandler [WEAK]
+ EXPORT DMA2_Channel2_IRQHandler [WEAK]
+ EXPORT DMA2_Channel3_IRQHandler [WEAK]
+ EXPORT DMA2_Channel4_IRQHandler [WEAK]
+ EXPORT DMA2_Channel5_IRQHandler [WEAK]
+ EXPORT DMA2_Channel6_IRQHandler [WEAK]
+ EXPORT DMA2_Channel7_IRQHandler [WEAK]
+ EXPORT DMAMUX1_OVR_IRQHandler [WEAK]
+
+WWDG_IRQHandler
+PVD_PVM_IRQHandler
+TAMP_STAMP_LSECSS_SSRU_IRQHandler
+RTC_WKUP_IRQHandler
+FLASH_IRQHandler
+RCC_IRQHandler
+EXTI0_IRQHandler
+EXTI1_IRQHandler
+EXTI2_IRQHandler
+EXTI3_IRQHandler
+EXTI4_IRQHandler
+DMA1_Channel1_IRQHandler
+DMA1_Channel2_IRQHandler
+DMA1_Channel3_IRQHandler
+DMA1_Channel4_IRQHandler
+DMA1_Channel5_IRQHandler
+DMA1_Channel6_IRQHandler
+DMA1_Channel7_IRQHandler
+ADC_IRQHandler
+DAC_IRQHandler
+COMP_IRQHandler
+EXTI9_5_IRQHandler
+TIM1_BRK_IRQHandler
+TIM1_UP_IRQHandler
+TIM1_TRG_COM_IRQHandler
+TIM1_CC_IRQHandler
+TIM2_IRQHandler
+TIM16_IRQHandler
+TIM17_IRQHandler
+I2C1_EV_IRQHandler
+I2C1_ER_IRQHandler
+I2C2_EV_IRQHandler
+I2C2_ER_IRQHandler
+SPI1_IRQHandler
+SPI2_IRQHandler
+USART1_IRQHandler
+USART2_IRQHandler
+LPUART1_IRQHandler
+LPTIM1_IRQHandler
+LPTIM2_IRQHandler
+EXTI15_10_IRQHandler
+RTC_Alarm_IRQHandler
+LPTIM3_IRQHandler
+SUBGHZSPI_IRQHandler
+HSEM_IRQHandler
+I2C3_EV_IRQHandler
+I2C3_ER_IRQHandler
+SUBGHZ_Radio_IRQHandler
+AES_IRQHandler
+RNG_IRQHandler
+PKA_IRQHandler
+DMA2_Channel1_IRQHandler
+DMA2_Channel2_IRQHandler
+DMA2_Channel3_IRQHandler
+DMA2_Channel4_IRQHandler
+DMA2_Channel5_IRQHandler
+DMA2_Channel6_IRQHandler
+DMA2_Channel7_IRQHandler
+DMAMUX1_OVR_IRQHandler
+
+ B .
+
+ ENDP
+
+ ALIGN
+
+;*******************************************************************************
+; User Stack and Heap initialization
+;*******************************************************************************
+
+ END
+
+;************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE*****
diff --git a/targets/TARGET_STM/TARGET_STM32WL/TARGET_STM32WLE5xC/TOOLCHAIN_ARM/stm32wle5xc.sct b/targets/TARGET_STM/TARGET_STM32WL/TARGET_STM32WLE5xC/TOOLCHAIN_ARM/stm32wle5xc.sct
new file mode 100644
index 0000000..9258e6a
--- /dev/null
+++ b/targets/TARGET_STM/TARGET_STM32WL/TARGET_STM32WLE5xC/TOOLCHAIN_ARM/stm32wle5xc.sct
@@ -0,0 +1,57 @@
+#! armclang -E --target=arm-arm-none-eabi -x c -mcpu=cortex-M4
+; Scatter-Loading Description File
+;
+; SPDX-License-Identifier: BSD-3-Clause
+;******************************************************************************
+;* @attention
+;*
+;* Copyright (c) 2016-2020 STMicroelectronics.
+;* All rights reserved.
+;*
+;* This software component is licensed by ST under BSD 3-Clause license,
+;* the "License"; You may not use this file except in compliance with the
+;* License. You may obtain a copy of the License at:
+;* opensource.org/licenses/BSD-3-Clause
+;*
+;******************************************************************************
+
+#include "../cmsis_nvic.h"
+
+#if !defined(MBED_APP_START)
+ #define MBED_APP_START MBED_ROM_START
+#endif
+
+#if !defined(MBED_APP_SIZE)
+ #define MBED_APP_SIZE MBED_ROM_SIZE
+#endif
+
+#if !defined(MBED_CONF_TARGET_BOOT_STACK_SIZE)
+/* This value is normally defined by the tools to 0x1000 for bare metal and 0x400 for RTOS */
+#if defined(MBED_BOOT_STACK_SIZE)
+#define MBED_CONF_TARGET_BOOT_STACK_SIZE MBED_BOOT_STACK_SIZE
+#else
+#define MBED_CONF_TARGET_BOOT_STACK_SIZE 0x400
+#endif
+#endif
+
+/* Round up VECTORS_SIZE to 8 bytes */
+#define VECTORS_SIZE (((NVIC_NUM_VECTORS * 4) + 7) AND ~7)
+
+LR_IROM1 MBED_APP_START MBED_APP_SIZE {
+
+ ER_IROM1 MBED_APP_START MBED_APP_SIZE {
+ *.o (RESET, +First)
+ *(InRoot$$Sections)
+ .ANY (+RO)
+ }
+
+ RW_IRAM1 (MBED_RAM_START + VECTORS_SIZE) { ; RW data
+ .ANY (+RW +ZI)
+ }
+
+ ARM_LIB_HEAP AlignExpr(+0, 16) EMPTY (MBED_RAM_START + MBED_RAM_SIZE - MBED_CONF_TARGET_BOOT_STACK_SIZE - AlignExpr(ImageLimit(RW_IRAM1), 16)) { ; Heap growing up
+ }
+
+ ARM_LIB_STACK (MBED_RAM_START + MBED_RAM_SIZE) EMPTY -MBED_CONF_TARGET_BOOT_STACK_SIZE { ; Stack region growing down
+ }
+}
diff --git a/targets/TARGET_STM/TARGET_STM32WL/TARGET_STM32WLE5xC/TOOLCHAIN_GCC_ARM/startup_stm32wle5xx.S b/targets/TARGET_STM/TARGET_STM32WL/TARGET_STM32WLE5xC/TOOLCHAIN_GCC_ARM/startup_stm32wle5xx.S
new file mode 100644
index 0000000..69a5b33
--- /dev/null
+++ b/targets/TARGET_STM/TARGET_STM32WL/TARGET_STM32WLE5xC/TOOLCHAIN_GCC_ARM/startup_stm32wle5xx.S
@@ -0,0 +1,425 @@
+/**
+ ******************************************************************************
+ * @file startup_stm32wle5xx.s
+ * @author MCD Application Team
+ * @brief STM32WLE5xx devices vector table for GCC toolchain.
+ * This module performs:
+ * - Set the initial SP
+ * - Set the initial PC == Reset_Handler,
+ * - Set the vector table entries with the exceptions ISR address,
+ * - Branches to main in the C library (which eventually
+ * calls main()).
+ * After Reset the Cortex-M4 processor is in Thread mode,
+ * priority is Privileged, and the Stack is set to Main.
+ ******************************************************************************
+ * @attention
+ *
+ * © Copyright (c) 2020 STMicroelectronics.
+ * All rights reserved.
+ *
+ * This software component is licensed by ST under Apache License, Version 2.0,
+ * the "License"; You may not use this file except in compliance with the
+ * License. You may obtain a copy of the License at:
+ * opensource.org/licenses/Apache-2.0
+ *
+ ******************************************************************************
+ */
+
+.syntax unified
+.cpu cortex-m4
+.fpu softvfp
+.thumb
+
+.global g_pfnVectors
+.global Default_Handler
+
+/* start address for the initialization values of the .data section.
+defined in linker script */
+.word _sidata
+/* start address for the .data section. defined in linker script */
+.word _sdata
+/* end address for the .data section. defined in linker script */
+.word _edata
+/* start address for the .bss section. defined in linker script */
+.word _sbss
+/* end address for the .bss section. defined in linker script */
+.word _ebss
+
+/**
+ * @brief This is the code that gets called when the processor first
+ * starts execution following a reset event. Only the absolutely
+ * necessary set is performed, after which the application
+ * supplied main() routine is called.
+ * @param None
+ * @retval : None
+*/
+
+ .section .text.Reset_Handler
+ .weak Reset_Handler
+ .type Reset_Handler, %function
+Reset_Handler:
+ ldr r0, =_estack
+ mov sp, r0 /* set stack pointer */
+
+/* Call the clock system initialization function.*/
+ bl SystemInit
+
+/* Copy the data segment initializers from flash to SRAM */
+ ldr r0, =_sdata
+ ldr r1, =_edata
+ ldr r2, =_sidata
+ movs r3, #0
+ b LoopCopyDataInit
+
+CopyDataInit:
+ ldr r4, [r2, r3]
+ str r4, [r0, r3]
+ adds r3, r3, #4
+
+LoopCopyDataInit:
+ adds r4, r0, r3
+ cmp r4, r1
+ bcc CopyDataInit
+
+/* Zero fill the bss segment. */
+ ldr r2, =_sbss
+ ldr r4, =_ebss
+ movs r3, #0
+ b LoopFillZerobss
+
+FillZerobss:
+ str r3, [r2]
+ adds r2, r2, #4
+
+LoopFillZerobss:
+ cmp r2, r4
+ bcc FillZerobss
+
+ bl _start
+ bx lr
+
+LoopForever:
+ b LoopForever
+
+ .size Reset_Handler, .-Reset_Handler
+
+/**
+ * @brief This is the code that gets called when the processor receives an
+ * unexpected interrupt. This simply enters an infinite loop, preserving
+ * the system state for examination by a debugger.
+ *
+ * @param None
+ * @retval : None
+*/
+ .section .text.Default_Handler,"ax",%progbits
+Default_Handler:
+Infinite_Loop:
+ b Infinite_Loop
+ .size Default_Handler, .-Default_Handler
+
+/******************************************************************************
+*
+* The STM32WLE5xx vector table. Note that the proper constructs
+* must be placed on this to ensure that it ends up at physical address
+* 0x0000.0000.
+*
+******************************************************************************/
+ .section .isr_vector,"a",%progbits
+ .type g_pfnVectors, %object
+ .size g_pfnVectors, .-g_pfnVectors
+
+g_pfnVectors:
+ .word _estack
+ .word Reset_Handler
+ .word NMI_Handler
+ .word HardFault_Handler
+ .word MemManage_Handler
+ .word BusFault_Handler
+ .word UsageFault_Handler
+ .word 0
+ .word 0
+ .word 0
+ .word 0
+ .word SVC_Handler
+ .word DebugMon_Handler
+ .word 0
+ .word PendSV_Handler
+ .word SysTick_Handler
+ .word WWDG_IRQHandler /* Window Watchdog interrupt */
+ .word PVD_PVM_IRQHandler /* PVD and PVM interrupt through EXTI */
+ .word TAMP_STAMP_LSECSS_SSRU_IRQHandler /* RTC Tamper, RTC TimeStamp, LSECSS and RTC SSRU int.*/
+ .word RTC_WKUP_IRQHandler /* RTC wakeup interrupt through EXTI[19] */
+ .word FLASH_IRQHandler /* Flash memory global interrupt and Flash memory ECC */
+ .word RCC_IRQHandler /* RCC global interrupt */
+ .word EXTI0_IRQHandler /* EXTI line 0 interrupt */
+ .word EXTI1_IRQHandler /* EXTI line 1 interrupt */
+ .word EXTI2_IRQHandler /* EXTI line 2 interrupt */
+ .word EXTI3_IRQHandler /* EXTI line 3 interrupt */
+ .word EXTI4_IRQHandler /* EXTI line 4 interrupt */
+ .word DMA1_Channel1_IRQHandler /* DMA1 channel 1 interrupt */
+ .word DMA1_Channel2_IRQHandler /* DMA1 channel 2 interrupt */
+ .word DMA1_Channel3_IRQHandler /* DMA1 channel 3 interrupt */
+ .word DMA1_Channel4_IRQHandler /* DMA1 channel 4 interrupt */
+ .word DMA1_Channel5_IRQHandler /* DMA1 channel 5 interrupt */
+ .word DMA1_Channel6_IRQHandler /* DMA1 channel 6 interrupt */
+ .word DMA1_Channel7_IRQHandler /* DMA1 channel 7 interrupt */
+ .word ADC_IRQHandler /* ADC interrupt */
+ .word DAC_IRQHandler /* DAC interrupt */
+ .word 0 /* Reserved */
+ .word COMP_IRQHandler /* COMP1 and COMP2 interrupt through EXTI */
+ .word EXTI9_5_IRQHandler /* EXTI line 9_5 interrupt */
+ .word TIM1_BRK_IRQHandler /* Timer 1 break interrupt */
+ .word TIM1_UP_IRQHandler /* Timer 1 Update */
+ .word TIM1_TRG_COM_IRQHandler /* Timer 1 trigger and communication */
+ .word TIM1_CC_IRQHandler /* Timer 1 capture compare interrupt */
+ .word TIM2_IRQHandler /* TIM2 global interrupt */
+ .word TIM16_IRQHandler /* Timer 16 global interrupt */
+ .word TIM17_IRQHandler /* Timer 17 global interrupt */
+ .word I2C1_EV_IRQHandler /* I2C1 event interrupt */
+ .word I2C1_ER_IRQHandler /* I2C1 event interrupt */
+ .word I2C2_EV_IRQHandler /* I2C2 error interrupt */
+ .word I2C2_ER_IRQHandler /* I2C2 error interrupt */
+ .word SPI1_IRQHandler /* SPI1 global interrupt */
+ .word SPI2_IRQHandler /* SPI2 global interrupt */
+ .word USART1_IRQHandler /* USART1 global interrupt */
+ .word USART2_IRQHandler /* USART2 global interrupt */
+ .word LPUART1_IRQHandler /* LPUART1 global interrupt */
+ .word LPTIM1_IRQHandler /* LPtimer 1 global interrupt */
+ .word LPTIM2_IRQHandler /* LPtimer 2 global interrupt */
+ .word EXTI15_10_IRQHandler /* EXTI line 15_10] interrupt through EXTI */
+ .word RTC_Alarm_IRQHandler /* RTC Alarms A & B interrupt */
+ .word LPTIM3_IRQHandler /* LPtimer 3 global interrupt */
+ .word SUBGHZSPI_IRQHandler /* SUBGHZSPI global interrupt */
+ .word 0 /* Reserved */
+ .word 0 /* Reserved */
+ .word HSEM_IRQHandler /* Semaphore interrupt 0 to CPU1 */
+ .word I2C3_EV_IRQHandler /* I2C3 event interrupt */
+ .word I2C3_ER_IRQHandler /* I2C3 error interrupt */
+ .word SUBGHZ_Radio_IRQHandler /* Radio IRQs RFBUSY interrupt through EXTI */
+ .word AES_IRQHandler /* AES global interrupt */
+ .word RNG_IRQHandler /* RNG interrupt */
+ .word PKA_IRQHandler /* PKA interrupt */
+ .word DMA2_Channel1_IRQHandler /* DMA2 channel 1 interrupt */
+ .word DMA2_Channel2_IRQHandler /* DMA2 channel 2 interrupt */
+ .word DMA2_Channel3_IRQHandler /* DMA2 channel 3 interrupt */
+ .word DMA2_Channel4_IRQHandler /* DMA2 channel 4 interrupt */
+ .word DMA2_Channel5_IRQHandler /* DMA2 channel 5 interrupt */
+ .word DMA2_Channel6_IRQHandler /* DMA2 channel 6 interrupt */
+ .word DMA2_Channel7_IRQHandler /* DMA2 channel 7 interrupt */
+ .word DMAMUX1_OVR_IRQHandler /* DMAMUX overrun interrupt */
+
+/*******************************************************************************
+*
+* Provide weak aliases for each Exception handler to the Default_Handler.
+* As they are weak aliases, any function with the same name will override
+* this definition.
+*
+*******************************************************************************/
+
+ .weak NMI_Handler
+ .thumb_set NMI_Handler,Default_Handler
+
+ .weak HardFault_Handler
+ .thumb_set HardFault_Handler,Default_Handler
+
+ .weak MemManage_Handler
+ .thumb_set MemManage_Handler,Default_Handler
+
+ .weak BusFault_Handler
+ .thumb_set BusFault_Handler,Default_Handler
+
+ .weak UsageFault_Handler
+ .thumb_set UsageFault_Handler,Default_Handler
+
+ .weak SVC_Handler
+ .thumb_set SVC_Handler,Default_Handler
+
+ .weak DebugMon_Handler
+ .thumb_set DebugMon_Handler,Default_Handler
+
+ .weak PendSV_Handler
+ .thumb_set PendSV_Handler,Default_Handler
+
+ .weak SysTick_Handler
+ .thumb_set SysTick_Handler,Default_Handler
+
+ .weak WWDG_IRQHandler
+ .thumb_set WWDG_IRQHandler,Default_Handler
+
+ .weak PVD_PVM_IRQHandler
+ .thumb_set PVD_PVM_IRQHandler,Default_Handler
+
+ .weak TAMP_STAMP_LSECSS_SSRU_IRQHandler
+ .thumb_set TAMP_STAMP_LSECSS_SSRU_IRQHandler,Default_Handler
+
+ .weak RTC_WKUP_IRQHandler
+ .thumb_set RTC_WKUP_IRQHandler,Default_Handler
+
+ .weak FLASH_IRQHandler
+ .thumb_set FLASH_IRQHandler,Default_Handler
+
+ .weak RCC_IRQHandler
+ .thumb_set RCC_IRQHandler,Default_Handler
+
+ .weak EXTI0_IRQHandler
+ .thumb_set EXTI0_IRQHandler,Default_Handler
+
+ .weak EXTI1_IRQHandler
+ .thumb_set EXTI1_IRQHandler,Default_Handler
+
+ .weak EXTI2_IRQHandler
+ .thumb_set EXTI2_IRQHandler,Default_Handler
+
+ .weak EXTI3_IRQHandler
+ .thumb_set EXTI3_IRQHandler,Default_Handler
+
+ .weak EXTI4_IRQHandler
+ .thumb_set EXTI4_IRQHandler,Default_Handler
+
+ .weak DMA1_Channel1_IRQHandler
+ .thumb_set DMA1_Channel1_IRQHandler,Default_Handler
+
+ .weak DMA1_Channel2_IRQHandler
+ .thumb_set DMA1_Channel2_IRQHandler,Default_Handler
+
+ .weak DMA1_Channel3_IRQHandler
+ .thumb_set DMA1_Channel3_IRQHandler,Default_Handler
+
+ .weak DMA1_Channel4_IRQHandler
+ .thumb_set DMA1_Channel4_IRQHandler,Default_Handler
+
+ .weak DMA1_Channel5_IRQHandler
+ .thumb_set DMA1_Channel5_IRQHandler,Default_Handler
+
+ .weak DMA1_Channel6_IRQHandler
+ .thumb_set DMA1_Channel6_IRQHandler,Default_Handler
+
+ .weak DMA1_Channel7_IRQHandler
+ .thumb_set DMA1_Channel7_IRQHandler,Default_Handler
+
+ .weak ADC_IRQHandler
+ .thumb_set ADC_IRQHandler,Default_Handler
+
+ .weak DAC_IRQHandler
+ .thumb_set DAC_IRQHandler,Default_Handler
+
+ .weak COMP_IRQHandler
+ .thumb_set COMP_IRQHandler,Default_Handler
+
+ .weak EXTI9_5_IRQHandler
+ .thumb_set EXTI9_5_IRQHandler,Default_Handler
+
+ .weak TIM1_BRK_IRQHandler
+ .thumb_set TIM1_BRK_IRQHandler,Default_Handler
+
+ .weak TIM1_UP_IRQHandler
+ .thumb_set TIM1_UP_IRQHandler,Default_Handler
+
+ .weak TIM1_TRG_COM_IRQHandler
+ .thumb_set TIM1_TRG_COM_IRQHandler,Default_Handler
+
+ .weak TIM1_CC_IRQHandler
+ .thumb_set TIM1_CC_IRQHandler,Default_Handler
+
+ .weak TIM2_IRQHandler
+ .thumb_set TIM2_IRQHandler,Default_Handler
+
+ .weak TIM16_IRQHandler
+ .thumb_set TIM16_IRQHandler,Default_Handler
+
+ .weak TIM17_IRQHandler
+ .thumb_set TIM17_IRQHandler,Default_Handler
+
+ .weak I2C1_EV_IRQHandler
+ .thumb_set I2C1_EV_IRQHandler,Default_Handler
+
+ .weak I2C1_ER_IRQHandler
+ .thumb_set I2C1_ER_IRQHandler,Default_Handler
+
+ .weak I2C2_EV_IRQHandler
+ .thumb_set I2C2_EV_IRQHandler,Default_Handler
+
+ .weak I2C2_ER_IRQHandler
+ .thumb_set I2C2_ER_IRQHandler,Default_Handler
+
+ .weak SPI1_IRQHandler
+ .thumb_set SPI1_IRQHandler,Default_Handler
+
+ .weak SPI2_IRQHandler
+ .thumb_set SPI2_IRQHandler,Default_Handler
+
+ .weak USART1_IRQHandler
+ .thumb_set USART1_IRQHandler,Default_Handler
+
+ .weak USART2_IRQHandler
+ .thumb_set USART2_IRQHandler,Default_Handler
+
+ .weak LPUART1_IRQHandler
+ .thumb_set LPUART1_IRQHandler,Default_Handler
+
+ .weak LPTIM1_IRQHandler
+ .thumb_set LPTIM1_IRQHandler,Default_Handler
+
+ .weak LPTIM2_IRQHandler
+ .thumb_set LPTIM2_IRQHandler,Default_Handler
+
+ .weak EXTI15_10_IRQHandler
+ .thumb_set EXTI15_10_IRQHandler,Default_Handler
+
+ .weak RTC_Alarm_IRQHandler
+ .thumb_set RTC_Alarm_IRQHandler,Default_Handler
+
+ .weak LPTIM3_IRQHandler
+ .thumb_set LPTIM3_IRQHandler,Default_Handler
+
+ .weak SUBGHZSPI_IRQHandler
+ .thumb_set SUBGHZSPI_IRQHandler,Default_Handler
+
+ .weak HSEM_IRQHandler
+ .thumb_set HSEM_IRQHandler,Default_Handler
+
+ .weak I2C3_EV_IRQHandler
+ .thumb_set I2C3_EV_IRQHandler,Default_Handler
+
+ .weak I2C3_ER_IRQHandler
+ .thumb_set I2C3_ER_IRQHandler,Default_Handler
+
+ .weak SUBGHZ_Radio_IRQHandler
+ .thumb_set SUBGHZ_Radio_IRQHandler,Default_Handler
+
+ .weak AES_IRQHandler
+ .thumb_set AES_IRQHandler,Default_Handler
+
+ .weak RNG_IRQHandler
+ .thumb_set RNG_IRQHandler,Default_Handler
+
+ .weak PKA_IRQHandler
+ .thumb_set PKA_IRQHandler,Default_Handler
+
+ .weak DMA2_Channel1_IRQHandler
+ .thumb_set DMA2_Channel1_IRQHandler,Default_Handler
+
+ .weak DMA2_Channel2_IRQHandler
+ .thumb_set DMA2_Channel2_IRQHandler,Default_Handler
+
+ .weak DMA2_Channel3_IRQHandler
+ .thumb_set DMA2_Channel3_IRQHandler,Default_Handler
+
+ .weak DMA2_Channel4_IRQHandler
+ .thumb_set DMA2_Channel4_IRQHandler,Default_Handler
+
+ .weak DMA2_Channel5_IRQHandler
+ .thumb_set DMA2_Channel5_IRQHandler,Default_Handler
+
+ .weak DMA2_Channel6_IRQHandler
+ .thumb_set DMA2_Channel6_IRQHandler,Default_Handler
+
+ .weak DMA2_Channel7_IRQHandler
+ .thumb_set DMA2_Channel7_IRQHandler,Default_Handler
+
+ .weak DMAMUX1_OVR_IRQHandler
+ .thumb_set DMAMUX1_OVR_IRQHandler,Default_Handler
+
+ .weak SystemInit
+
+/************************ (C) COPYRIGHT STMicroelectonics *****END OF FILE****/
diff --git a/targets/TARGET_STM/TARGET_STM32WL/TARGET_STM32WLE5xC/TOOLCHAIN_GCC_ARM/stm32wle5xc.ld b/targets/TARGET_STM/TARGET_STM32WL/TARGET_STM32WLE5xC/TOOLCHAIN_GCC_ARM/stm32wle5xc.ld
new file mode 100644
index 0000000..5f47993
--- /dev/null
+++ b/targets/TARGET_STM/TARGET_STM32WL/TARGET_STM32WLE5xC/TOOLCHAIN_GCC_ARM/stm32wle5xc.ld
@@ -0,0 +1,203 @@
+/* Linker script to configure memory regions. */
+/*
+ * SPDX-License-Identifier: BSD-3-Clause
+ ******************************************************************************
+ * @attention
+ *
+ * Copyright (c) 2016-2020 STMicroelectronics.
+ * All rights reserved.
+ *
+ * This software component is licensed by ST under BSD 3-Clause license,
+ * the "License"; You may not use this file except in compliance with the
+ * License. You may obtain a copy of the License at:
+ * opensource.org/licenses/BSD-3-Clause
+ *
+ ******************************************************************************
+*/
+
+#include "../cmsis_nvic.h"
+
+
+#if !defined(MBED_APP_START)
+ #define MBED_APP_START MBED_ROM_START
+#endif
+
+#if !defined(MBED_APP_SIZE)
+ #define MBED_APP_SIZE MBED_ROM_SIZE
+#endif
+
+#if !defined(MBED_CONF_TARGET_BOOT_STACK_SIZE)
+ /* This value is normally defined by the tools
+ to 0x1000 for bare metal and 0x400 for RTOS */
+ #define MBED_CONF_TARGET_BOOT_STACK_SIZE 0x400
+#endif
+
+/* Round up VECTORS_SIZE to 8 bytes */
+#define VECTORS_SIZE (((NVIC_NUM_VECTORS * 4) + 7) & 0xFFFFFFF8)
+
+MEMORY
+{
+ FLASH (rx) : ORIGIN = MBED_APP_START, LENGTH = MBED_APP_SIZE
+ RAM (rwx) : ORIGIN = MBED_RAM_START + VECTORS_SIZE, LENGTH = MBED_RAM_SIZE - VECTORS_SIZE
+}
+
+/* Linker script to place sections and symbol values. Should be used together
+ * with other linker script that defines memory regions FLASH and RAM.
+ * It references following symbols, which must be defined in code:
+ * Reset_Handler : Entry of reset handler
+ *
+ * It defines following symbols, which code can use without definition:
+ * __exidx_start
+ * __exidx_end
+ * __etext
+ * __data_start__
+ * __preinit_array_start
+ * __preinit_array_end
+ * __init_array_start
+ * __init_array_end
+ * __fini_array_start
+ * __fini_array_end
+ * __data_end__
+ * __bss_start__
+ * __bss_end__
+ * __end__
+ * end
+ * __HeapLimit
+ * __StackLimit
+ * __StackTop
+ * __stack
+ * _estack
+ */
+ENTRY(Reset_Handler)
+
+SECTIONS
+{
+ .text :
+ {
+ KEEP(*(.isr_vector))
+ *(.text*)
+
+ KEEP(*(.init))
+ KEEP(*(.fini))
+
+ /* .ctors */
+ *crtbegin.o(.ctors)
+ *crtbegin?.o(.ctors)
+ *(EXCLUDE_FILE(*crtend?.o *crtend.o) .ctors)
+ *(SORT(.ctors.*))
+ *(.ctors)
+
+ /* .dtors */
+ *crtbegin.o(.dtors)
+ *crtbegin?.o(.dtors)
+ *(EXCLUDE_FILE(*crtend?.o *crtend.o) .dtors)
+ *(SORT(.dtors.*))
+ *(.dtors)
+
+ *(.rodata*)
+
+ KEEP(*(.eh_frame*))
+ } > FLASH
+
+ .ARM.extab :
+ {
+ *(.ARM.extab* .gnu.linkonce.armextab.*)
+ } > FLASH
+
+ __exidx_start = .;
+ .ARM.exidx :
+ {
+ *(.ARM.exidx* .gnu.linkonce.armexidx.*)
+ } > FLASH
+ __exidx_end = .;
+
+ __etext = .;
+ _sidata = .;
+
+ .data : AT (__etext)
+ {
+ __data_start__ = .;
+ _sdata = .;
+ *(vtable)
+ *(.data*)
+
+ . = ALIGN(8);
+ /* preinit data */
+ PROVIDE_HIDDEN (__preinit_array_start = .);
+ KEEP(*(.preinit_array))
+ PROVIDE_HIDDEN (__preinit_array_end = .);
+
+ . = ALIGN(8);
+ /* init data */
+ PROVIDE_HIDDEN (__init_array_start = .);
+ KEEP(*(SORT(.init_array.*)))
+ KEEP(*(.init_array))
+ PROVIDE_HIDDEN (__init_array_end = .);
+
+ . = ALIGN(8);
+ /* finit data */
+ PROVIDE_HIDDEN (__fini_array_start = .);
+ KEEP(*(SORT(.fini_array.*)))
+ KEEP(*(.fini_array))
+ PROVIDE_HIDDEN (__fini_array_end = .);
+
+ KEEP(*(.jcr*))
+ . = ALIGN(8);
+ /* All data end */
+ __data_end__ = .;
+ _edata = .;
+
+ } > RAM
+
+ /* Uninitialized data section
+ * This region is not initialized by the C/C++ library and can be used to
+ * store state across soft reboots. */
+ .uninitialized (NOLOAD):
+ {
+ . = ALIGN(32);
+ __uninitialized_start = .;
+ *(.uninitialized)
+ KEEP(*(.keep.uninitialized))
+ . = ALIGN(32);
+ __uninitialized_end = .;
+ } > RAM
+
+ .bss :
+ {
+ . = ALIGN(8);
+ __bss_start__ = .;
+ _sbss = .;
+ *(.bss*)
+ *(COMMON)
+ . = ALIGN(8);
+ __bss_end__ = .;
+ _ebss = .;
+ } > RAM
+
+ .heap (COPY):
+ {
+ __end__ = .;
+ PROVIDE(end = .);
+ *(.heap*)
+ . = ORIGIN(RAM) + LENGTH(RAM) - MBED_CONF_TARGET_BOOT_STACK_SIZE;
+ __HeapLimit = .;
+ } > RAM
+
+ /* .stack_dummy section doesn't contains any symbols. It is only
+ * used for linker to calculate size of stack sections, and assign
+ * values to stack symbols later */
+ .stack_dummy (COPY):
+ {
+ *(.stack*)
+ } > RAM
+
+ /* Set stack top to end of RAM, and stack limit move down by
+ * size of stack_dummy section */
+ __StackTop = ORIGIN(RAM) + LENGTH(RAM);
+ _estack = __StackTop;
+ __StackLimit = __StackTop - MBED_CONF_TARGET_BOOT_STACK_SIZE;
+ PROVIDE(__stack = __StackTop);
+
+ /* Check if data + heap + stack exceeds RAM limit */
+ ASSERT(__StackLimit >= __HeapLimit, "region RAM overflowed with stack")
+}
diff --git a/targets/TARGET_STM/TARGET_STM32WL/TARGET_STM32WLE5xC/TOOLCHAIN_IAR/startup_stm32wle5xx.S b/targets/TARGET_STM/TARGET_STM32WL/TARGET_STM32WLE5xC/TOOLCHAIN_IAR/startup_stm32wle5xx.S
new file mode 100644
index 0000000..341ee9e
--- /dev/null
+++ b/targets/TARGET_STM/TARGET_STM32WL/TARGET_STM32WLE5xC/TOOLCHAIN_IAR/startup_stm32wle5xx.S
@@ -0,0 +1,494 @@
+;********************************************************************************
+;* File Name : startup_stm32wle5xx.s
+;* Author : MCD Application Team
+;* Description : M4 core vector table of the STM32WLxxxx devices for the
+;* IAR (EWARM) toolchain.
+;*
+;* This module performs:
+;* - Set the initial SP
+;* - Set the initial PC == _iar_program_start,
+;* - Set the vector table entries with the exceptions ISR
+;* address.
+;* - Branches to main in the C library (which eventually
+;* calls main()).
+;* After Reset the Cortex-M4 processor is in Thread mode,
+;* priority is Privileged, and the Stack is set to Main.
+;********************************************************************************
+;*
+;* Copyright (c) 2020 STMicroelectronics. All rights reserved.
+;*
+;* This software component is licensed by ST under Apache License, Version 2.0,
+;* the "License"; You may not use this file except in compliance with the
+;* License. You may obtain a copy of the License at:
+;* opensource.org/licenses/Apache-2.0
+;
+;*******************************************************************************
+;
+;
+; The modules in this file are included in the libraries, and may be replaced
+; by any user-defined modules that define the PUBLIC symbol _program_start or
+; a user defined start symbol.
+; To override the cstartup defined in the library, simply add your modified
+; version to the workbench project.
+;
+; The vector table is normally located at address 0.
+; When debugging in RAM, it can be located in RAM, aligned to at least 2^6.
+; The name "__vector_table" has special meaning for C-SPY:
+; it is where the SP start value is found, and the NVIC vector
+; table register (VTOR) is initialized to this address if != 0.
+;
+; Cortex-M version
+;
+
+ MODULE ?cstartup
+
+ ;; Forward declaration of sections.
+ SECTION CSTACK:DATA:NOROOT(3)
+
+ SECTION .intvec:CODE:NOROOT(2)
+
+ EXTERN __iar_program_start
+ EXTERN SystemInit
+ PUBLIC __vector_table
+
+ DATA
+__vector_table
+ DCD sfe(CSTACK)
+ DCD Reset_Handler ; Reset Handler
+
+ DCD NMI_Handler ; NMI Handler
+ DCD HardFault_Handler ; Hard Fault Handler
+ DCD MemManage_Handler ; MPU Fault Handler
+ DCD BusFault_Handler ; Bus Fault Handler
+ DCD UsageFault_Handler ; Usage Fault Handler
+ DCD 0 ; Reserved
+ DCD 0 ; Reserved
+ DCD 0 ; Reserved
+ DCD 0 ; Reserved
+ DCD SVC_Handler ; SVCall Handler
+ DCD DebugMon_Handler ; Debug Monitor Handler
+ DCD 0 ; Reserved
+ DCD PendSV_Handler ; PendSV Handler
+ DCD SysTick_Handler ; SysTick Handler
+
+ ; External Interrupts
+ DCD WWDG_IRQHandler ; Window WatchDog
+ DCD PVD_PVM_IRQHandler ; PVD and PVM Interrupt
+ DCD TAMP_STAMP_LSECSS_SSRU_IRQHandler ; RTC Tamper, RTC TimeStamp, LSECSS and RTC SSRU Interrupts
+ DCD RTC_WKUP_IRQHandler ; RTC Wakeup Interrupt
+ DCD FLASH_IRQHandler ; FLASH global Interrupt
+ DCD RCC_IRQHandler ; RCC Interrupt
+ DCD EXTI0_IRQHandler ; EXTI Line 0 Interrupt
+ DCD EXTI1_IRQHandler ; EXTI Line 1 Interrupt
+ DCD EXTI2_IRQHandler ; EXTI Line 2 Interrupt
+ DCD EXTI3_IRQHandler ; EXTI Line 3 Interrupt
+ DCD EXTI4_IRQHandler ; EXTI Line 4 Interrupt
+ DCD DMA1_Channel1_IRQHandler ; DMA1 Channel 1 Interrupt
+ DCD DMA1_Channel2_IRQHandler ; DMA1 Channel 2 Interrupt
+ DCD DMA1_Channel3_IRQHandler ; DMA1 Channel 3 Interrupt
+ DCD DMA1_Channel4_IRQHandler ; DMA1 Channel 4 Interrupt
+ DCD DMA1_Channel5_IRQHandler ; DMA1 Channel 5 Interrupt
+ DCD DMA1_Channel6_IRQHandler ; DMA1 Channel 6 Interrupt
+ DCD DMA1_Channel7_IRQHandler ; DMA1 Channel 7 Interrupt
+ DCD ADC_IRQHandler ; ADC Interrupt
+ DCD DAC_IRQHandler ; DAC Interrupt
+ DCD 0 ; Reserved
+ DCD COMP_IRQHandler ; COMP1 and COMP2 Interrupts
+ DCD EXTI9_5_IRQHandler ; EXTI Lines [9:5] Interrupt
+ DCD TIM1_BRK_IRQHandler ; TIM1 Break Interrupt
+ DCD TIM1_UP_IRQHandler ; TIM1 Update Interrupt
+ DCD TIM1_TRG_COM_IRQHandler ; TIM1 Trigger and Communication Interrupts
+ DCD TIM1_CC_IRQHandler ; TIM1 Capture Compare Interrupt
+ DCD TIM2_IRQHandler ; TIM2 Global Interrupt
+ DCD TIM16_IRQHandler ; TIM16 Global Interrupt
+ DCD TIM17_IRQHandler ; TIM17 Global Interrupt
+ DCD I2C1_EV_IRQHandler ; I2C1 Event Interrupt
+ DCD I2C1_ER_IRQHandler ; I2C1 Error Interrupt
+ DCD I2C2_EV_IRQHandler ; I2C2 Event Interrupt
+ DCD I2C2_ER_IRQHandler ; I2C2 Error Interrupt
+ DCD SPI1_IRQHandler ; SPI1 Interrupt
+ DCD SPI2_IRQHandler ; SPI2 Interrupt
+ DCD USART1_IRQHandler ; USART1 Interrupt
+ DCD USART2_IRQHandler ; USART2 Interrupt
+ DCD LPUART1_IRQHandler ; LPUART1 Interrupt
+ DCD LPTIM1_IRQHandler ; LPTIM1 Global Interrupt
+ DCD LPTIM2_IRQHandler ; LPTIM2 Global Interrupt
+ DCD EXTI15_10_IRQHandler ; EXTI Lines [15:10] Interrupt
+ DCD RTC_Alarm_IRQHandler ; RTC Alarms (A and B) Interrupt
+ DCD LPTIM3_IRQHandler ; LPTIM3 Global Interrupt
+ DCD SUBGHZSPI_IRQHandler ; SUBGHZSPI Interrupt
+ DCD 0 ; Reserved
+ DCD 0 ; Reserved
+ DCD HSEM_IRQHandler ; HSEM0 Interrupt
+ DCD I2C3_EV_IRQHandler ; I2C3 Event Interrupt
+ DCD I2C3_ER_IRQHandler ; I2C3 Error Interrupt
+ DCD SUBGHZ_Radio_IRQHandler ; SUBGHZ Radio Interrupt
+ DCD AES_IRQHandler ; AES Interrupt
+ DCD RNG_IRQHandler ; RNG1 Interrupt
+ DCD PKA_IRQHandler ; PKA Interrupt
+ DCD DMA2_Channel1_IRQHandler ; DMA2 Channel 1 Interrupt
+ DCD DMA2_Channel2_IRQHandler ; DMA2 Channel 2 Interrupt
+ DCD DMA2_Channel3_IRQHandler ; DMA2 Channel 3 Interrupt
+ DCD DMA2_Channel4_IRQHandler ; DMA2 Channel 4 Interrupt
+ DCD DMA2_Channel5_IRQHandler ; DMA2 Channel 5 Interrupt
+ DCD DMA2_Channel6_IRQHandler ; DMA2 Channel 6 Interrupt
+ DCD DMA2_Channel7_IRQHandler ; DMA2 Channel 7 Interrupt
+ DCD DMAMUX1_OVR_IRQHandler ; DMAMUX overrun Interrupt
+
+;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;
+;;
+;; Default interrupt handlers.
+;;
+ THUMB
+
+ PUBWEAK Reset_Handler
+ SECTION .text:CODE:NOROOT:REORDER(2)
+Reset_Handler
+ LDR R0, =SystemInit
+ BLX R0
+ LDR R0, =__iar_program_start
+ BX R0
+
+ PUBWEAK NMI_Handler
+ SECTION .text:CODE:NOROOT:REORDER(1)
+NMI_Handler
+ B NMI_Handler
+
+ PUBWEAK HardFault_Handler
+ SECTION .text:CODE:NOROOT:REORDER(1)
+HardFault_Handler
+ B HardFault_Handler
+
+ PUBWEAK MemManage_Handler
+ SECTION .text:CODE:NOROOT:REORDER(1)
+MemManage_Handler
+ B MemManage_Handler
+
+ PUBWEAK BusFault_Handler
+ SECTION .text:CODE:NOROOT:REORDER(1)
+BusFault_Handler
+ B BusFault_Handler
+
+ PUBWEAK UsageFault_Handler
+ SECTION .text:CODE:NOROOT:REORDER(1)
+UsageFault_Handler
+ B UsageFault_Handler
+
+ PUBWEAK SVC_Handler
+ SECTION .text:CODE:NOROOT:REORDER(1)
+SVC_Handler
+ B SVC_Handler
+
+ PUBWEAK DebugMon_Handler
+ SECTION .text:CODE:NOROOT:REORDER(1)
+DebugMon_Handler
+ B DebugMon_Handler
+
+ PUBWEAK PendSV_Handler
+ SECTION .text:CODE:NOROOT:REORDER(1)
+PendSV_Handler
+ B PendSV_Handler
+
+ PUBWEAK SysTick_Handler
+ SECTION .text:CODE:NOROOT:REORDER(1)
+SysTick_Handler
+ B SysTick_Handler
+
+ PUBWEAK WWDG_IRQHandler
+ SECTION .text:CODE:NOROOT:REORDER(1)
+WWDG_IRQHandler
+ B WWDG_IRQHandler
+
+ PUBWEAK PVD_PVM_IRQHandler
+ SECTION .text:CODE:NOROOT:REORDER(1)
+PVD_PVM_IRQHandler
+ B PVD_PVM_IRQHandler
+
+ PUBWEAK TAMP_STAMP_LSECSS_SSRU_IRQHandler
+ SECTION .text:CODE:NOROOT:REORDER(1)
+TAMP_STAMP_LSECSS_SSRU_IRQHandler
+ B TAMP_STAMP_LSECSS_SSRU_IRQHandler
+
+ PUBWEAK RTC_WKUP_IRQHandler
+ SECTION .text:CODE:NOROOT:REORDER(1)
+RTC_WKUP_IRQHandler
+ B RTC_WKUP_IRQHandler
+
+ PUBWEAK FLASH_IRQHandler
+ SECTION .text:CODE:NOROOT:REORDER(1)
+FLASH_IRQHandler
+ B FLASH_IRQHandler
+
+ PUBWEAK RCC_IRQHandler
+ SECTION .text:CODE:NOROOT:REORDER(1)
+RCC_IRQHandler
+ B RCC_IRQHandler
+
+ PUBWEAK EXTI0_IRQHandler
+ SECTION .text:CODE:NOROOT:REORDER(1)
+EXTI0_IRQHandler
+ B EXTI0_IRQHandler
+
+ PUBWEAK EXTI1_IRQHandler
+ SECTION .text:CODE:NOROOT:REORDER(1)
+EXTI1_IRQHandler
+ B EXTI1_IRQHandler
+
+ PUBWEAK EXTI2_IRQHandler
+ SECTION .text:CODE:NOROOT:REORDER(1)
+EXTI2_IRQHandler
+ B EXTI2_IRQHandler
+
+ PUBWEAK EXTI3_IRQHandler
+ SECTION .text:CODE:NOROOT:REORDER(1)
+EXTI3_IRQHandler
+ B EXTI3_IRQHandler
+
+ PUBWEAK EXTI4_IRQHandler
+ SECTION .text:CODE:NOROOT:REORDER(1)
+EXTI4_IRQHandler
+ B EXTI4_IRQHandler
+
+ PUBWEAK DMA1_Channel1_IRQHandler
+ SECTION .text:CODE:NOROOT:REORDER(1)
+DMA1_Channel1_IRQHandler
+ B DMA1_Channel1_IRQHandler
+
+ PUBWEAK DMA1_Channel2_IRQHandler
+ SECTION .text:CODE:NOROOT:REORDER(1)
+DMA1_Channel2_IRQHandler
+ B DMA1_Channel2_IRQHandler
+
+ PUBWEAK DMA1_Channel3_IRQHandler
+ SECTION .text:CODE:NOROOT:REORDER(1)
+DMA1_Channel3_IRQHandler
+ B DMA1_Channel3_IRQHandler
+
+ PUBWEAK DMA1_Channel4_IRQHandler
+ SECTION .text:CODE:NOROOT:REORDER(1)
+DMA1_Channel4_IRQHandler
+ B DMA1_Channel4_IRQHandler
+
+ PUBWEAK DMA1_Channel5_IRQHandler
+ SECTION .text:CODE:NOROOT:REORDER(1)
+DMA1_Channel5_IRQHandler
+ B DMA1_Channel5_IRQHandler
+
+ PUBWEAK DMA1_Channel6_IRQHandler
+ SECTION .text:CODE:NOROOT:REORDER(1)
+DMA1_Channel6_IRQHandler
+ B DMA1_Channel6_IRQHandler
+
+ PUBWEAK DMA1_Channel7_IRQHandler
+ SECTION .text:CODE:NOROOT:REORDER(1)
+DMA1_Channel7_IRQHandler
+ B DMA1_Channel7_IRQHandler
+
+ PUBWEAK ADC_IRQHandler
+ SECTION .text:CODE:NOROOT:REORDER(1)
+ADC_IRQHandler
+ B ADC_IRQHandler
+
+ PUBWEAK DAC_IRQHandler
+ SECTION .text:CODE:NOROOT:REORDER(1)
+DAC_IRQHandler
+ B DAC_IRQHandler
+
+ PUBWEAK COMP_IRQHandler
+ SECTION .text:CODE:NOROOT:REORDER(1)
+COMP_IRQHandler
+ B COMP_IRQHandler
+
+ PUBWEAK EXTI9_5_IRQHandler
+ SECTION .text:CODE:NOROOT:REORDER(1)
+EXTI9_5_IRQHandler
+ B EXTI9_5_IRQHandler
+
+ PUBWEAK TIM1_BRK_IRQHandler
+ SECTION .text:CODE:NOROOT:REORDER(1)
+TIM1_BRK_IRQHandler
+ B TIM1_BRK_IRQHandler
+
+ PUBWEAK TIM1_UP_IRQHandler
+ SECTION .text:CODE:NOROOT:REORDER(1)
+TIM1_UP_IRQHandler
+ B TIM1_UP_IRQHandler
+
+ PUBWEAK TIM1_TRG_COM_IRQHandler
+ SECTION .text:CODE:NOROOT:REORDER(1)
+TIM1_TRG_COM_IRQHandler
+ B TIM1_TRG_COM_IRQHandler
+
+ PUBWEAK TIM1_CC_IRQHandler
+ SECTION .text:CODE:NOROOT:REORDER(1)
+TIM1_CC_IRQHandler
+ B TIM1_CC_IRQHandler
+
+ PUBWEAK TIM2_IRQHandler
+ SECTION .text:CODE:NOROOT:REORDER(1)
+TIM2_IRQHandler
+ B TIM2_IRQHandler
+
+ PUBWEAK TIM16_IRQHandler
+ SECTION .text:CODE:NOROOT:REORDER(1)
+TIM16_IRQHandler
+ B TIM16_IRQHandler
+
+ PUBWEAK TIM17_IRQHandler
+ SECTION .text:CODE:NOROOT:REORDER(1)
+TIM17_IRQHandler
+ B TIM17_IRQHandler
+
+ PUBWEAK I2C1_EV_IRQHandler
+ SECTION .text:CODE:NOROOT:REORDER(1)
+I2C1_EV_IRQHandler
+ B I2C1_EV_IRQHandler
+
+ PUBWEAK I2C1_ER_IRQHandler
+ SECTION .text:CODE:NOROOT:REORDER(1)
+I2C1_ER_IRQHandler
+ B I2C1_ER_IRQHandler
+
+ PUBWEAK I2C2_EV_IRQHandler
+ SECTION .text:CODE:NOROOT:REORDER(1)
+I2C2_EV_IRQHandler
+ B I2C2_EV_IRQHandler
+
+ PUBWEAK I2C2_ER_IRQHandler
+ SECTION .text:CODE:NOROOT:REORDER(1)
+I2C2_ER_IRQHandler
+ B I2C2_ER_IRQHandler
+
+ PUBWEAK SPI1_IRQHandler
+ SECTION .text:CODE:NOROOT:REORDER(1)
+SPI1_IRQHandler
+ B SPI1_IRQHandler
+
+ PUBWEAK SPI2_IRQHandler
+ SECTION .text:CODE:NOROOT:REORDER(1)
+SPI2_IRQHandler
+ B SPI2_IRQHandler
+
+ PUBWEAK USART1_IRQHandler
+ SECTION .text:CODE:NOROOT:REORDER(1)
+USART1_IRQHandler
+ B USART1_IRQHandler
+
+ PUBWEAK USART2_IRQHandler
+ SECTION .text:CODE:NOROOT:REORDER(1)
+USART2_IRQHandler
+ B USART2_IRQHandler
+
+ PUBWEAK LPUART1_IRQHandler
+ SECTION .text:CODE:NOROOT:REORDER(1)
+LPUART1_IRQHandler
+ B LPUART1_IRQHandler
+
+ PUBWEAK LPTIM1_IRQHandler
+ SECTION .text:CODE:NOROOT:REORDER(1)
+LPTIM1_IRQHandler
+ B LPTIM1_IRQHandler
+
+ PUBWEAK LPTIM2_IRQHandler
+ SECTION .text:CODE:NOROOT:REORDER(1)
+LPTIM2_IRQHandler
+ B LPTIM2_IRQHandler
+
+ PUBWEAK EXTI15_10_IRQHandler
+ SECTION .text:CODE:NOROOT:REORDER(1)
+EXTI15_10_IRQHandler
+ B EXTI15_10_IRQHandler
+
+ PUBWEAK RTC_Alarm_IRQHandler
+ SECTION .text:CODE:NOROOT:REORDER(1)
+RTC_Alarm_IRQHandler
+ B RTC_Alarm_IRQHandler
+
+ PUBWEAK LPTIM3_IRQHandler
+ SECTION .text:CODE:NOROOT:REORDER(1)
+LPTIM3_IRQHandler
+ B LPTIM3_IRQHandler
+
+ PUBWEAK SUBGHZSPI_IRQHandler
+ SECTION .text:CODE:NOROOT:REORDER(1)
+SUBGHZSPI_IRQHandler
+ B SUBGHZSPI_IRQHandler
+
+ PUBWEAK HSEM_IRQHandler
+ SECTION .text:CODE:NOROOT:REORDER(1)
+HSEM_IRQHandler
+ B HSEM_IRQHandler
+
+ PUBWEAK I2C3_EV_IRQHandler
+ SECTION .text:CODE:NOROOT:REORDER(1)
+I2C3_EV_IRQHandler
+ B I2C3_EV_IRQHandler
+
+ PUBWEAK I2C3_ER_IRQHandler
+ SECTION .text:CODE:NOROOT:REORDER(1)
+I2C3_ER_IRQHandler
+ B I2C3_ER_IRQHandler
+
+ PUBWEAK SUBGHZ_Radio_IRQHandler
+ SECTION .text:CODE:NOROOT:REORDER(1)
+SUBGHZ_Radio_IRQHandler
+ B SUBGHZ_Radio_IRQHandler
+
+ PUBWEAK AES_IRQHandler
+ SECTION .text:CODE:NOROOT:REORDER(1)
+AES_IRQHandler
+ B AES_IRQHandler
+
+ PUBWEAK RNG_IRQHandler
+ SECTION .text:CODE:NOROOT:REORDER(1)
+RNG_IRQHandler
+ B RNG_IRQHandler
+
+ PUBWEAK PKA_IRQHandler
+ SECTION .text:CODE:NOROOT:REORDER(1)
+PKA_IRQHandler
+ B PKA_IRQHandler
+
+ PUBWEAK DMA2_Channel1_IRQHandler
+ SECTION .text:CODE:NOROOT:REORDER(1)
+DMA2_Channel1_IRQHandler
+ B DMA2_Channel1_IRQHandler
+
+ PUBWEAK DMA2_Channel2_IRQHandler
+ SECTION .text:CODE:NOROOT:REORDER(1)
+DMA2_Channel2_IRQHandler
+ B DMA2_Channel2_IRQHandler
+
+ PUBWEAK DMA2_Channel3_IRQHandler
+ SECTION .text:CODE:NOROOT:REORDER(1)
+DMA2_Channel3_IRQHandler
+ B DMA2_Channel3_IRQHandler
+
+ PUBWEAK DMA2_Channel4_IRQHandler
+ SECTION .text:CODE:NOROOT:REORDER(1)
+DMA2_Channel4_IRQHandler
+ B DMA2_Channel4_IRQHandler
+
+ PUBWEAK DMA2_Channel5_IRQHandler
+ SECTION .text:CODE:NOROOT:REORDER(1)
+DMA2_Channel5_IRQHandler
+ B DMA2_Channel5_IRQHandler
+
+ PUBWEAK DMA2_Channel6_IRQHandler
+ SECTION .text:CODE:NOROOT:REORDER(1)
+DMA2_Channel6_IRQHandler
+ B DMA2_Channel6_IRQHandler
+
+ PUBWEAK DMA2_Channel7_IRQHandler
+ SECTION .text:CODE:NOROOT:REORDER(1)
+DMA2_Channel7_IRQHandler
+ B DMA2_Channel7_IRQHandler
+
+ PUBWEAK DMAMUX1_OVR_IRQHandler
+ SECTION .text:CODE:NOROOT:REORDER(1)
+DMAMUX1_OVR_IRQHandler
+ B DMAMUX1_OVR_IRQHandler
+
+ END
+
+;************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE*****
diff --git a/targets/TARGET_STM/TARGET_STM32WL/TARGET_STM32WLE5xC/TOOLCHAIN_IAR/stm32wle5xc.icf b/targets/TARGET_STM/TARGET_STM32WL/TARGET_STM32WLE5xC/TOOLCHAIN_IAR/stm32wle5xc.icf
new file mode 100644
index 0000000..7fb4af2
--- /dev/null
+++ b/targets/TARGET_STM/TARGET_STM32WL/TARGET_STM32WLE5xC/TOOLCHAIN_IAR/stm32wle5xc.icf
@@ -0,0 +1,59 @@
+/* Linker script to configure memory regions.
+ *
+ * SPDX-License-Identifier: BSD-3-Clause
+ ******************************************************************************
+ * @attention
+ *
+ * Copyright (c) 2016-2020 STMicroelectronics.
+ * All rights reserved.
+ *
+ * This software component is licensed by ST under BSD 3-Clause license,
+ * the "License"; You may not use this file except in compliance with the
+ * License. You may obtain a copy of the License at:
+ * opensource.org/licenses/BSD-3-Clause
+ *
+ ******************************************************************************
+*/
+/* Device specific values */
+
+/* Tools provide -DMBED_ROM_START=xxx -DMBED_ROM_SIZE=xxx -DMBED_RAM_START=xxx -DMBED_RAM_SIZE=xxx */
+
+define symbol VECTORS = 78; /* This value must match NVIC_NUM_VECTORS in cmsis_nvic.h */
+define symbol HEAP_SIZE = 0x1000;
+
+/* Common - Do not change */
+
+if (!isdefinedsymbol(MBED_APP_START)) {
+ define symbol MBED_APP_START = MBED_ROM_START;
+}
+
+if (!isdefinedsymbol(MBED_APP_SIZE)) {
+ define symbol MBED_APP_SIZE = MBED_ROM_SIZE;
+}
+
+if (!isdefinedsymbol(MBED_CONF_TARGET_BOOT_STACK_SIZE)) {
+ /* This value is normally defined by the tools
+ to 0x1000 for bare metal and 0x400 for RTOS */
+ define symbol MBED_CONF_TARGET_BOOT_STACK_SIZE = 0x400;
+}
+
+/* Round up VECTORS_SIZE to 8 bytes */
+define symbol VECTORS_SIZE = ((VECTORS * 4) + 7) & ~7;
+define symbol RAM_REGION_START = MBED_RAM_START + VECTORS_SIZE;
+define symbol RAM_REGION_SIZE = MBED_RAM_SIZE - VECTORS_SIZE;
+
+define memory mem with size = 4G;
+define region ROM_region = mem:[from MBED_APP_START size MBED_APP_SIZE];
+define region RAM_region = mem:[from RAM_REGION_START size RAM_REGION_SIZE];
+
+define block CSTACK with alignment = 8, size = MBED_CONF_TARGET_BOOT_STACK_SIZE { };
+define block HEAP with alignment = 8, size = HEAP_SIZE { };
+
+initialize by copy { readwrite };
+do not initialize { section .noinit };
+
+place at address mem: MBED_APP_START { readonly section .intvec };
+
+place in ROM_region { readonly };
+place in RAM_region { readwrite,
+ block CSTACK, block HEAP };
diff --git a/targets/TARGET_STM/TARGET_STM32WL/TARGET_STM32WLE5xC/cmsis_nvic.h b/targets/TARGET_STM/TARGET_STM32WL/TARGET_STM32WLE5xC/cmsis_nvic.h
new file mode 100644
index 0000000..a18342e
--- /dev/null
+++ b/targets/TARGET_STM/TARGET_STM32WL/TARGET_STM32WLE5xC/cmsis_nvic.h
@@ -0,0 +1,39 @@
+/* mbed Microcontroller Library
+ * SPDX-License-Identifier: BSD-3-Clause
+ ******************************************************************************
+ * @attention
+ *
+ * © Copyright (c) 2016-2020 STMicroelectronics.
+ * All rights reserved.
+ *
+ * This software component is licensed by ST under BSD 3-Clause license,
+ * the "License"; You may not use this file except in compliance with the
+ * License. You may obtain a copy of the License at:
+ * opensource.org/licenses/BSD-3-Clause
+ *
+ ******************************************************************************
+*/
+
+#ifndef MBED_CMSIS_NVIC_H
+#define MBED_CMSIS_NVIC_H
+
+#if !defined(MBED_ROM_START)
+#define MBED_ROM_START 0x8000000
+#endif
+
+#if !defined(MBED_ROM_SIZE)
+#define MBED_ROM_SIZE 0x0 // 0 B
+#endif
+
+#if !defined(MBED_RAM_START)
+#define MBED_RAM_START 0x20000000
+#endif
+
+#if !defined(MBED_RAM_SIZE)
+#define MBED_RAM_SIZE 0x0 // 0 B
+#endif
+
+#define NVIC_NUM_VECTORS 78
+#define NVIC_RAM_VECTOR_ADDRESS MBED_RAM_START
+
+#endif